Errata/ARM57: Add basic constructs to handle and apply A57 specific erratas

This patch adds basic constructs in the ARMv8 u-boot code
to handle and apply Cortex-A57 specific erratas.

As and example, the framework showcases how erratas 833069, 826974
and 828024 can be handled and applied.

Later on this framework can be extended to include other
erratas.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>

diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index 4b11aa4f22272cfa1766b0482ff8b1797e15db6e..540a5db8438b782060b09005ff558046e762efcf 100644 (file)
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -67,6 +67,9 @@ reset:
        msr     cpacr_el1, x0                   /* Enable FP/SIMD */
 0:
 
+       /* Apply ARM core specific erratas */
+       bl      apply_core_errata
+
        /*
         * Cache/BPB/TLB Invalidate
         * i-cache is invalidated before enabled in icache_enable()
@@ -97,6 +100,48 @@ master_cpu:
 
 /*-----------------------------------------------------------------------*/
 
+WEAK(apply_core_errata)
+
+       mov     x29, lr                 /* Save LR */
+       /* For now, we support Cortex-A57 specific errata only */
+
+       /* Check if we are running on a Cortex-A57 core */
+       branch_if_a57_core x0, apply_a57_core_errata
+0:
+       mov     lr, x29                 /* Restore LR */
+       ret
+
+apply_a57_core_errata:
+
+#ifdef CONFIG_ARM_ERRATA_828024
+       mrs     x0, S3_1_c15_c2_0       /* cpuactlr_el1 */
+       /* Disable non-allocate hint of w-b-n-a memory type */
+       mov     x0, #0x1 << 49
+       /* Disable write streaming no L1-allocate threshold */
+       mov     x0, #0x3 << 25
+       /* Disable write streaming no-allocate threshold */
+       mov     x0, #0x3 << 27
+       msr     S3_1_c15_c2_0, x0       /* cpuactlr_el1 */
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_826974
+       mrs     x0, S3_1_c15_c2_0       /* cpuactlr_el1 */
+       /* Disable speculative load execution ahead of a DMB */
+       mov     x0, #0x1 << 59
+       msr     S3_1_c15_c2_0, x0       /* cpuactlr_el1 */
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_833069
+       mrs     x0, S3_1_c15_c2_0       /* cpuactlr_el1 */
+       /* Disable Enable Invalidates of BTB bit */
+       and     x0, x0, #0xE
+       msr     S3_1_c15_c2_0, x0       /* cpuactlr_el1 */
+#endif
+       b 0b
+ENDPROC(apply_core_errata)
+
+/*-----------------------------------------------------------------------*/
+
 WEAK(lowlevel_init)
        mov     x29, lr                 /* Save LR */
 

diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h
index 1c8c4251ee0cedde2a24d459be2109b9a1df749f..5f7c7e050145d626fc65bfb3b75f973865a3fbba 100644 (file)
--- a/arch/arm/include/asm/macro.h
+++ b/arch/arm/include/asm/macro.h
@@ -73,6 +73,28 @@ lr   .req    x30
        b.eq    \el1_label
 .endm
 
+/*
+ * Branch if current processor is a Cortex-A57 core.
+ */
+.macro branch_if_a57_core, xreg, a57_label
+       mrs     \xreg, midr_el1
+       lsr     \xreg, \xreg, #4
+       and     \xreg, \xreg, #0x00000FFF
+       cmp     \xreg, #0xD07           /* Cortex-A57 MPCore processor. */
+       b.eq    \a57_label
+.endm
+
+/*
+ * Branch if current processor is a Cortex-A53 core.
+ */
+.macro branch_if_a53_core, xreg, a53_label
+       mrs     \xreg, midr_el1
+       lsr     \xreg, \xreg, #4
+       and     \xreg, \xreg, #0x00000FFF
+       cmp     \xreg, #0xD03           /* Cortex-A53 MPCore processor. */
+       b.eq    \a53_label
+.endm
+
 /*
  * Branch if current processor is a slave,
  * choose processor with all zero affinity value as the master.