]> git.sur5r.net Git - u-boot/commitdiff
mx6q: mx6qsabrelite: Add ECSPI support to the Sabrelite platform
authorEric Nelson <eric.nelson@boundarydevices.com>
Tue, 31 Jan 2012 07:52:05 +0000 (07:52 +0000)
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>
Mon, 27 Feb 2012 20:19:23 +0000 (21:19 +0100)
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Jason Liu <jason.hui@linaro.org>
Tested-by: Jason Liu <jason.hui@linaro.org>
board/freescale/mx6qsabrelite/imximage.cfg
board/freescale/mx6qsabrelite/mx6qsabrelite.c
include/configs/mx6qsabrelite.h

index 83dee6f3b48f73ea7f936c550ad5c1a56f286eb1..c38942719190ef3e1aed4b8896253adc1ed57d96 100644 (file)
@@ -156,7 +156,7 @@ DATA 4 0x021b0404 0x00011006
 
 # set the default clock gate to save power
 DATA 4 0x020c4068 0x00C03F3F
-DATA 4 0x020c406c 0x0030FC00
+DATA 4 0x020c406c 0x0030FC03
 DATA 4 0x020c4070 0x0FFFC000
 DATA 4 0x020c4074 0x3FF00000
 DATA 4 0x020c4078 0x00FFF300
index a53b01f35c63156f6e73100751c24f4116fe74ec..97a77e841bb3ec01f3cce4687b37e21ec2ff6579 100644 (file)
@@ -46,6 +46,10 @@ DECLARE_GLOBAL_DATA_PTR;
        PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
        PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
 
+#define SPI_PAD_CTRL (PAD_CTL_HYS |                            \
+       PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED |             \
+       PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
+
 int dram_init(void)
 {
        gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
@@ -193,6 +197,23 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
+#ifdef CONFIG_MXC_SPI
+iomux_v3_cfg_t ecspi1_pads[] = {
+       /* SS1 */
+       MX6Q_PAD_EIM_D19__GPIO_3_19   | MUX_PAD_CTRL(SPI_PAD_CTRL),
+       MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+       MX6Q_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+       MX6Q_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+};
+
+void setup_spi(void)
+{
+       gpio_direction_output(GPIO_NUMBER(3, 19), 1);
+       imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
+                                        ARRAY_SIZE(ecspi1_pads));
+}
+#endif
+
 #define MII_1000BASET_CTRL             0x9
 #define MII_EXTENDED_CTRL              0xb
 #define MII_EXTENDED_DATAW             0xc
@@ -239,6 +260,10 @@ int board_eth_init(bd_t *bis)
                return ret;
        }
 
+#ifdef CONFIG_MXC_SPI
+       setup_spi();
+#endif
+
        return 0;
 }
 
index d650ee340ab25c629b5808d0e770c11b47a1ad82..bcb1a427e3225bd48eccc7581f7374cbe491ce2d 100644 (file)
 #define CONFIG_MXC_UART
 #define CONFIG_MXC_UART_BASE           UART2_BASE
 
+#define CONFIG_CMD_SF
+#ifdef CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_MXC_SPI
+#define CONFIG_SF_DEFAULT_SPEED 25000000
+#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
+#endif
+
 /* MMC Configs */
 #define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_USDHC