]> git.sur5r.net Git - u-boot/commitdiff
rockchip: rk3368: Add core start-up code for RK3368
authorAndreas Färber <afaerber@suse.de>
Mon, 15 May 2017 09:51:18 +0000 (17:51 +0800)
committerSimon Glass <sjg@chromium.org>
Wed, 7 Jun 2017 13:29:19 +0000 (07:29 -0600)
The RK3368 is an octa-core Cortex-A53 SoC from Rockchip.
This adds basic support to chain-load U-Boot from Rockchip's
miniloader.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
arch/arm/dts/rk3368.dtsi [new file with mode: 0644]
arch/arm/mach-rockchip/Kconfig
arch/arm/mach-rockchip/Makefile
arch/arm/mach-rockchip/rk3368/Kconfig [new file with mode: 0644]
arch/arm/mach-rockchip/rk3368/Makefile [new file with mode: 0644]
arch/arm/mach-rockchip/rk3368/clk_rk3368.c [new file with mode: 0644]
arch/arm/mach-rockchip/rk3368/rk3368.c [new file with mode: 0644]
arch/arm/mach-rockchip/rk3368/syscon_rk3368.c [new file with mode: 0644]
include/configs/rk3368_common.h [new file with mode: 0644]
include/dt-bindings/clock/rk3368-cru.h [new file with mode: 0644]

diff --git a/arch/arm/dts/rk3368.dtsi b/arch/arm/dts/rk3368.dtsi
new file mode 100644 (file)
index 0000000..025dc32
--- /dev/null
@@ -0,0 +1,1090 @@
+/*
+ * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/clock/rk3368-cru.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+       compatible = "rockchip,rk3368";
+       interrupt-parent = <&gic>;
+       #address-cells = <2>;
+       #size-cells = <2>;
+
+       aliases {
+               ethernet0 = &gmac;
+               i2c0 = &i2c0;
+               i2c1 = &i2c1;
+               i2c2 = &i2c2;
+               i2c3 = &i2c3;
+               i2c4 = &i2c4;
+               i2c5 = &i2c5;
+               serial0 = &uart0;
+               serial1 = &uart1;
+               serial2 = &uart2;
+               serial3 = &uart3;
+               serial4 = &uart4;
+               spi0 = &spi0;
+               spi1 = &spi1;
+               spi2 = &spi2;
+       };
+
+       cpus {
+               #address-cells = <0x2>;
+               #size-cells = <0x0>;
+
+               cpu-map {
+                       cluster0 {
+                               core0 {
+                                       cpu = <&cpu_b0>;
+                               };
+                               core1 {
+                                       cpu = <&cpu_b1>;
+                               };
+                               core2 {
+                                       cpu = <&cpu_b2>;
+                               };
+                               core3 {
+                                       cpu = <&cpu_b3>;
+                               };
+                       };
+
+                       cluster1 {
+                               core0 {
+                                       cpu = <&cpu_l0>;
+                               };
+                               core1 {
+                                       cpu = <&cpu_l1>;
+                               };
+                               core2 {
+                                       cpu = <&cpu_l2>;
+                               };
+                               core3 {
+                                       cpu = <&cpu_l3>;
+                               };
+                       };
+               };
+
+               idle-states {
+                       entry-method = "psci";
+
+                       cpu_sleep: cpu-sleep-0 {
+                               compatible = "arm,idle-state";
+                               arm,psci-suspend-param = <0x1010000>;
+                               entry-latency-us = <0x3fffffff>;
+                               exit-latency-us = <0x40000000>;
+                               min-residency-us = <0xffffffff>;
+                       };
+               };
+
+               cpu_l0: cpu@0 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a53", "arm,armv8";
+                       reg = <0x0 0x0>;
+                       cpu-idle-states = <&cpu_sleep>;
+                       enable-method = "psci";
+
+                       #cooling-cells = <2>; /* min followed by max */
+               };
+
+               cpu_l1: cpu@1 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a53", "arm,armv8";
+                       reg = <0x0 0x1>;
+                       cpu-idle-states = <&cpu_sleep>;
+                       enable-method = "psci";
+               };
+
+               cpu_l2: cpu@2 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a53", "arm,armv8";
+                       reg = <0x0 0x2>;
+                       cpu-idle-states = <&cpu_sleep>;
+                       enable-method = "psci";
+               };
+
+               cpu_l3: cpu@3 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a53", "arm,armv8";
+                       reg = <0x0 0x3>;
+                       cpu-idle-states = <&cpu_sleep>;
+                       enable-method = "psci";
+               };
+
+               cpu_b0: cpu@100 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a53", "arm,armv8";
+                       reg = <0x0 0x100>;
+                       cpu-idle-states = <&cpu_sleep>;
+                       enable-method = "psci";
+
+                       #cooling-cells = <2>; /* min followed by max */
+               };
+
+               cpu_b1: cpu@101 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a53", "arm,armv8";
+                       reg = <0x0 0x101>;
+                       cpu-idle-states = <&cpu_sleep>;
+                       enable-method = "psci";
+               };
+
+               cpu_b2: cpu@102 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a53", "arm,armv8";
+                       reg = <0x0 0x102>;
+                       cpu-idle-states = <&cpu_sleep>;
+                       enable-method = "psci";
+               };
+
+               cpu_b3: cpu@103 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a53", "arm,armv8";
+                       reg = <0x0 0x103>;
+                       cpu-idle-states = <&cpu_sleep>;
+                       enable-method = "psci";
+               };
+       };
+
+       arm-pmu {
+               compatible = "arm,armv8-pmuv3";
+               interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
+                                    <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
+                                    <&cpu_b2>, <&cpu_b3>;
+       };
+
+       psci {
+               compatible = "arm,psci-0.2";
+               method = "smc";
+       };
+
+       timer {
+               compatible = "arm,armv8-timer";
+               interrupts = <GIC_PPI 13
+                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
+                            <GIC_PPI 14
+                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
+                            <GIC_PPI 11
+                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
+                            <GIC_PPI 10
+                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
+       };
+
+       xin24m: oscillator {
+               compatible = "fixed-clock";
+               clock-frequency = <24000000>;
+               clock-output-names = "xin24m";
+               #clock-cells = <0>;
+       };
+
+       sdmmc: dwmmc@ff0c0000 {
+               compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
+               reg = <0x0 0xff0c0000 0x0 0x4000>;
+               clock-freq-min-max = <400000 150000000>;
+               clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
+                        <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
+               clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+               fifo-depth = <0x100>;
+               interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+               status = "disabled";
+       };
+
+       sdio0: dwmmc@ff0d0000 {
+               compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
+               reg = <0x0 0xff0d0000 0x0 0x4000>;
+               clock-freq-min-max = <400000 150000000>;
+               clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
+                        <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
+               clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
+               fifo-depth = <0x100>;
+               interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+               status = "disabled";
+       };
+
+       emmc: dwmmc@ff0f0000 {
+               compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
+               reg = <0x0 0xff0f0000 0x0 0x4000>;
+               clock-freq-min-max = <400000 150000000>;
+               clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
+                        <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
+               clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+               fifo-depth = <0x100>;
+               interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+               status = "disabled";
+       };
+
+       saradc: saradc@ff100000 {
+               compatible = "rockchip,saradc";
+               reg = <0x0 0xff100000 0x0 0x100>;
+               interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+               #io-channel-cells = <1>;
+               clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
+               clock-names = "saradc", "apb_pclk";
+               status = "disabled";
+       };
+
+       spi0: spi@ff110000 {
+               compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
+               reg = <0x0 0xff110000 0x0 0x1000>;
+               clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
+               clock-names = "spiclk", "apb_pclk";
+               interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+       };
+
+       spi1: spi@ff120000 {
+               compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
+               reg = <0x0 0xff120000 0x0 0x1000>;
+               clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
+               clock-names = "spiclk", "apb_pclk";
+               interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+       };
+
+       spi2: spi@ff130000 {
+               compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
+               reg = <0x0 0xff130000 0x0 0x1000>;
+               clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
+               clock-names = "spiclk", "apb_pclk";
+               interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+       };
+
+       i2c1: i2c@ff140000 {
+               compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
+               reg = <0x0 0xff140000 0x0 0x1000>;
+               interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               clock-names = "i2c";
+               clocks = <&cru PCLK_I2C1>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&i2c1_xfer>;
+               status = "disabled";
+       };
+
+       i2c3: i2c@ff150000 {
+               compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
+               reg = <0x0 0xff150000 0x0 0x1000>;
+               interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               clock-names = "i2c";
+               clocks = <&cru PCLK_I2C3>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&i2c3_xfer>;
+               status = "disabled";
+       };
+
+       i2c4: i2c@ff160000 {
+               compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
+               reg = <0x0 0xff160000 0x0 0x1000>;
+               interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               clock-names = "i2c";
+               clocks = <&cru PCLK_I2C4>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&i2c4_xfer>;
+               status = "disabled";
+       };
+
+       i2c5: i2c@ff170000 {
+               compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
+               reg = <0x0 0xff170000 0x0 0x1000>;
+               interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               clock-names = "i2c";
+               clocks = <&cru PCLK_I2C5>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&i2c5_xfer>;
+               status = "disabled";
+       };
+
+       uart0: serial@ff180000 {
+               compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
+               reg = <0x0 0xff180000 0x0 0x100>;
+               clock-frequency = <24000000>;
+               clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
+               clock-names = "baudclk", "apb_pclk";
+               interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+               reg-shift = <2>;
+               reg-io-width = <4>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&uart0_xfer>;
+               status = "disabled";
+       };
+
+       uart1: serial@ff190000 {
+               compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
+               reg = <0x0 0xff190000 0x0 0x100>;
+               clock-frequency = <24000000>;
+               clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
+               clock-names = "baudclk", "apb_pclk";
+               interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+               reg-shift = <2>;
+               reg-io-width = <4>;
+               pinctrl-names = "default";
+               pinctrl-1 = <&uart0_xfer>;
+               status = "disabled";
+       };
+
+       uart3: serial@ff1b0000 {
+               compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
+               reg = <0x0 0xff1b0000 0x0 0x100>;
+               clock-frequency = <24000000>;
+               clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
+               clock-names = "baudclk", "apb_pclk";
+               interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+               reg-shift = <2>;
+               reg-io-width = <4>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&uart3_xfer>;
+               status = "disabled";
+       };
+
+       uart4: serial@ff1c0000 {
+               compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
+               reg = <0x0 0xff1c0000 0x0 0x100>;
+               clock-frequency = <24000000>;
+               clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
+               clock-names = "baudclk", "apb_pclk";
+               interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+               reg-shift = <2>;
+               reg-io-width = <4>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&uart4_xfer>;
+               status = "disabled";
+       };
+
+       thermal-zones {
+               cpu {
+                       polling-delay-passive = <100>; /* milliseconds */
+                       polling-delay = <5000>; /* milliseconds */
+
+                       thermal-sensors = <&tsadc 0>;
+
+                       trips {
+                               cpu_alert0: cpu_alert0 {
+                                       temperature = <75000>; /* millicelsius */
+                                       hysteresis = <2000>; /* millicelsius */
+                                       type = "passive";
+                               };
+                               cpu_alert1: cpu_alert1 {
+                                       temperature = <80000>; /* millicelsius */
+                                       hysteresis = <2000>; /* millicelsius */
+                                       type = "passive";
+                               };
+                               cpu_crit: cpu_crit {
+                                       temperature = <95000>; /* millicelsius */
+                                       hysteresis = <2000>; /* millicelsius */
+                                       type = "critical";
+                               };
+                       };
+
+                       cooling-maps {
+                               map0 {
+                                       trip = <&cpu_alert0>;
+                                       cooling-device =
+                                       <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                               };
+                               map1 {
+                                       trip = <&cpu_alert1>;
+                                       cooling-device =
+                                       <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                               };
+                       };
+               };
+
+               gpu {
+                       polling-delay-passive = <100>; /* milliseconds */
+                       polling-delay = <5000>; /* milliseconds */
+
+                       thermal-sensors = <&tsadc 1>;
+
+                       trips {
+                               gpu_alert0: gpu_alert0 {
+                                       temperature = <80000>; /* millicelsius */
+                                       hysteresis = <2000>; /* millicelsius */
+                                       type = "passive";
+                               };
+                               gpu_crit: gpu_crit {
+                                       temperature = <115000>; /* millicelsius */
+                                       hysteresis = <2000>; /* millicelsius */
+                                       type = "critical";
+                               };
+                       };
+
+                       cooling-maps {
+                               map0 {
+                                       trip = <&gpu_alert0>;
+                                       cooling-device =
+                                       <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                               };
+                       };
+               };
+       };
+
+       tsadc: tsadc@ff280000 {
+               compatible = "rockchip,rk3368-tsadc";
+               reg = <0x0 0xff280000 0x0 0x100>;
+               interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
+               clock-names = "tsadc", "apb_pclk";
+               resets = <&cru SRST_TSADC>;
+               reset-names = "tsadc-apb";
+               pinctrl-names = "init", "default", "sleep";
+               pinctrl-0 = <&otp_gpio>;
+               pinctrl-1 = <&otp_out>;
+               pinctrl-2 = <&otp_gpio>;
+               #thermal-sensor-cells = <1>;
+               rockchip,hw-tshut-temp = <95000>;
+               status = "disabled";
+       };
+
+       gmac: ethernet@ff290000 {
+               compatible = "rockchip,rk3368-gmac";
+               reg = <0x0 0xff290000 0x0 0x10000>;
+               interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "macirq";
+               rockchip,grf = <&grf>;
+               clocks = <&cru SCLK_MAC>,
+                       <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
+                       <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
+                       <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
+               clock-names = "stmmaceth",
+                       "mac_clk_rx", "mac_clk_tx",
+                       "clk_mac_ref", "clk_mac_refout",
+                       "aclk_mac", "pclk_mac";
+               status = "disabled";
+       };
+
+       usb_host0_ehci: usb@ff500000 {
+               compatible = "generic-ehci";
+               reg = <0x0 0xff500000 0x0 0x100>;
+               interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru HCLK_HOST0>;
+               clock-names = "usbhost";
+               status = "disabled";
+       };
+
+       usb_otg: usb@ff580000 {
+               compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
+                               "snps,dwc2";
+               reg = <0x0 0xff580000 0x0 0x40000>;
+               interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru HCLK_OTG0>;
+               clock-names = "otg";
+               dr_mode = "otg";
+               g-np-tx-fifo-size = <16>;
+               g-rx-fifo-size = <275>;
+               g-tx-fifo-size = <256 128 128 64 64 32>;
+               g-use-dma;
+               status = "disabled";
+       };
+
+       i2c0: i2c@ff650000 {
+               compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
+               reg = <0x0 0xff650000 0x0 0x1000>;
+               clocks = <&cru PCLK_I2C0>;
+               clock-names = "i2c";
+               interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&i2c0_xfer>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+       };
+
+       i2c2: i2c@ff660000 {
+               compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
+               reg = <0x0 0xff660000 0x0 0x1000>;
+               interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               clock-names = "i2c";
+               clocks = <&cru PCLK_I2C2>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&i2c2_xfer>;
+               status = "disabled";
+       };
+
+       pwm0: pwm@ff680000 {
+               compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
+               reg = <0x0 0xff680000 0x0 0x10>;
+               #pwm-cells = <3>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pwm0_pin>;
+               clocks = <&cru PCLK_PWM1>;
+               clock-names = "pwm";
+               status = "disabled";
+       };
+
+       pwm1: pwm@ff680010 {
+               compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
+               reg = <0x0 0xff680010 0x0 0x10>;
+               #pwm-cells = <3>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pwm1_pin>;
+               clocks = <&cru PCLK_PWM1>;
+               clock-names = "pwm";
+               status = "disabled";
+       };
+
+       pwm2: pwm@ff680020 {
+               compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
+               reg = <0x0 0xff680020 0x0 0x10>;
+               #pwm-cells = <3>;
+               clocks = <&cru PCLK_PWM1>;
+               clock-names = "pwm";
+               status = "disabled";
+       };
+
+       pwm3: pwm@ff680030 {
+               compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
+               reg = <0x0 0xff680030 0x0 0x10>;
+               #pwm-cells = <3>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pwm3_pin>;
+               clocks = <&cru PCLK_PWM1>;
+               clock-names = "pwm";
+               status = "disabled";
+       };
+
+       uart2: serial@ff690000 {
+               compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
+               reg = <0x0 0xff690000 0x0 0x100>;
+               clock-frequency = <24000000>;
+               clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+               clock-names = "baudclk", "apb_pclk";
+               interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&uart2_xfer>;
+               reg-shift = <2>;
+               reg-io-width = <4>;
+               status = "disabled";
+       };
+
+       mbox: mbox@ff6b0000 {
+               compatible = "rockchip,rk3368-mailbox";
+               reg = <0x0 0xff6b0000 0x0 0x1000>;
+               interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru PCLK_MAILBOX>;
+               clock-names = "pclk_mailbox";
+               #mbox-cells = <1>;
+       };
+
+       pmugrf: syscon@ff738000 {
+               compatible = "rockchip,rk3368-pmugrf", "syscon";
+               reg = <0x0 0xff738000 0x0 0x1000>;
+       };
+
+       cru: clock-controller@ff760000 {
+               compatible = "rockchip,rk3368-cru";
+               reg = <0x0 0xff760000 0x0 0x1000>;
+               rockchip,grf = <&grf>;
+               #clock-cells = <1>;
+               #reset-cells = <1>;
+       };
+
+       grf: syscon@ff770000 {
+               compatible = "rockchip,rk3368-grf", "syscon";
+               reg = <0x0 0xff770000 0x0 0x1000>;
+       };
+
+       wdt: watchdog@ff800000 {
+               compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
+               reg = <0x0 0xff800000 0x0 0x100>;
+               clocks = <&cru PCLK_WDT>;
+               interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+               status = "disabled";
+       };
+
+       timer@ff810000 {
+               compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
+               reg = <0x0 0xff810000 0x0 0x20>;
+               interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+       };
+
+       gic: interrupt-controller@ffb71000 {
+               compatible = "arm,gic-400";
+               interrupt-controller;
+               #interrupt-cells = <3>;
+               #address-cells = <0>;
+
+               reg = <0x0 0xffb71000 0x0 0x1000>,
+                     <0x0 0xffb72000 0x0 0x1000>,
+                     <0x0 0xffb74000 0x0 0x2000>,
+                     <0x0 0xffb76000 0x0 0x2000>;
+               interrupts = <GIC_PPI 9
+                     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
+       };
+
+       pinctrl: pinctrl {
+               compatible = "rockchip,rk3368-pinctrl";
+               rockchip,grf = <&grf>;
+               rockchip,pmu = <&pmugrf>;
+               #address-cells = <0x2>;
+               #size-cells = <0x2>;
+               ranges;
+
+               gpio0: gpio0@ff750000 {
+                       compatible = "rockchip,gpio-bank";
+                       reg = <0x0 0xff750000 0x0 0x100>;
+                       clocks = <&cru PCLK_GPIO0>;
+                       interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
+
+                       gpio-controller;
+                       #gpio-cells = <0x2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <0x2>;
+               };
+
+               gpio1: gpio1@ff780000 {
+                       compatible = "rockchip,gpio-bank";
+                       reg = <0x0 0xff780000 0x0 0x100>;
+                       clocks = <&cru PCLK_GPIO1>;
+                       interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
+
+                       gpio-controller;
+                       #gpio-cells = <0x2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <0x2>;
+               };
+
+               gpio2: gpio2@ff790000 {
+                       compatible = "rockchip,gpio-bank";
+                       reg = <0x0 0xff790000 0x0 0x100>;
+                       clocks = <&cru PCLK_GPIO2>;
+                       interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
+
+                       gpio-controller;
+                       #gpio-cells = <0x2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <0x2>;
+               };
+
+               gpio3: gpio3@ff7a0000 {
+                       compatible = "rockchip,gpio-bank";
+                       reg = <0x0 0xff7a0000 0x0 0x100>;
+                       clocks = <&cru PCLK_GPIO3>;
+                       interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
+
+                       gpio-controller;
+                       #gpio-cells = <0x2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <0x2>;
+               };
+
+               pcfg_pull_up: pcfg-pull-up {
+                       bias-pull-up;
+               };
+
+               pcfg_pull_down: pcfg-pull-down {
+                       bias-pull-down;
+               };
+
+               pcfg_pull_none: pcfg-pull-none {
+                       bias-disable;
+               };
+
+               pcfg_pull_none_12ma: pcfg-pull-none-12ma {
+                       bias-disable;
+                       drive-strength = <12>;
+               };
+
+               emmc {
+                       emmc_clk: emmc-clk {
+                               rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
+                       };
+
+                       emmc_cmd: emmc-cmd {
+                               rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
+                       };
+
+                       emmc_pwr: emmc-pwr {
+                               rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
+                       };
+
+                       emmc_bus1: emmc-bus1 {
+                               rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
+                       };
+
+                       emmc_bus4: emmc-bus4 {
+                               rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
+                                               <1 19 RK_FUNC_2 &pcfg_pull_up>,
+                                               <1 20 RK_FUNC_2 &pcfg_pull_up>,
+                                               <1 21 RK_FUNC_2 &pcfg_pull_up>;
+                       };
+
+                       emmc_bus8: emmc-bus8 {
+                               rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
+                                               <1 19 RK_FUNC_2 &pcfg_pull_up>,
+                                               <1 20 RK_FUNC_2 &pcfg_pull_up>,
+                                               <1 21 RK_FUNC_2 &pcfg_pull_up>,
+                                               <1 22 RK_FUNC_2 &pcfg_pull_up>,
+                                               <1 23 RK_FUNC_2 &pcfg_pull_up>,
+                                               <1 24 RK_FUNC_2 &pcfg_pull_up>,
+                                               <1 25 RK_FUNC_2 &pcfg_pull_up>;
+                       };
+               };
+
+               gmac {
+                       rgmii_pins: rgmii-pins {
+                               rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
+                                               <3 24 RK_FUNC_1 &pcfg_pull_none>,
+                                               <3 19 RK_FUNC_1 &pcfg_pull_none>,
+                                               <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
+                                               <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
+                                               <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
+                                               <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
+                                               <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
+                                               <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
+                                               <3 15 RK_FUNC_1 &pcfg_pull_none>,
+                                               <3 16 RK_FUNC_1 &pcfg_pull_none>,
+                                               <3 17 RK_FUNC_1 &pcfg_pull_none>,
+                                               <3 18 RK_FUNC_1 &pcfg_pull_none>,
+                                               <3 25 RK_FUNC_1 &pcfg_pull_none>,
+                                               <3 20 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+
+                       rmii_pins: rmii-pins {
+                               rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
+                                               <3 24 RK_FUNC_1 &pcfg_pull_none>,
+                                               <3 19 RK_FUNC_1 &pcfg_pull_none>,
+                                               <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
+                                               <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
+                                               <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
+                                               <3 15 RK_FUNC_1 &pcfg_pull_none>,
+                                               <3 16 RK_FUNC_1 &pcfg_pull_none>,
+                                               <3 20 RK_FUNC_1 &pcfg_pull_none>,
+                                               <3 21 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+               };
+
+               i2c0 {
+                       i2c0_xfer: i2c0-xfer {
+                               rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
+                                               <0 7 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+               };
+
+               i2c1 {
+                       i2c1_xfer: i2c1-xfer {
+                               rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
+                                               <2 22 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+               };
+
+               i2c2 {
+                       i2c2_xfer: i2c2-xfer {
+                               rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
+                                               <3 31 RK_FUNC_2 &pcfg_pull_none>;
+                       };
+               };
+
+               i2c3 {
+                       i2c3_xfer: i2c3-xfer {
+                               rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
+                                               <1 17 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+               };
+
+               i2c4 {
+                       i2c4_xfer: i2c4-xfer {
+                               rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
+                                               <3 25 RK_FUNC_2 &pcfg_pull_none>;
+                       };
+               };
+
+               i2c5 {
+                       i2c5_xfer: i2c5-xfer {
+                               rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
+                                               <3 27 RK_FUNC_2 &pcfg_pull_none>;
+                       };
+               };
+
+               pwm0 {
+                       pwm0_pin: pwm0-pin {
+                               rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
+                       };
+               };
+
+               pwm1 {
+                       pwm1_pin: pwm1-pin {
+                               rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
+                       };
+               };
+
+               pwm3 {
+                       pwm3_pin: pwm3-pin {
+                               rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
+                       };
+               };
+
+               sdio0 {
+                       sdio0_bus1: sdio0-bus1 {
+                               rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
+                       };
+
+                       sdio0_bus4: sdio0-bus4 {
+                               rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
+                                               <2 29 RK_FUNC_1 &pcfg_pull_up>,
+                                               <2 30 RK_FUNC_1 &pcfg_pull_up>,
+                                               <2 31 RK_FUNC_1 &pcfg_pull_up>;
+                       };
+
+                       sdio0_cmd: sdio0-cmd {
+                               rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
+                       };
+
+                       sdio0_clk: sdio0-clk {
+                               rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+
+                       sdio0_cd: sdio0-cd {
+                               rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
+                       };
+
+                       sdio0_wp: sdio0-wp {
+                               rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
+                       };
+
+                       sdio0_pwr: sdio0-pwr {
+                               rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
+                       };
+
+                       sdio0_bkpwr: sdio0-bkpwr {
+                               rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
+                       };
+
+                       sdio0_int: sdio0-int {
+                               rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
+                       };
+               };
+
+               sdmmc {
+                       sdmmc_clk: sdmmc-clk {
+                               rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+
+                       sdmmc_cmd: sdmmc-cmd {
+                               rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
+                       };
+
+                       sdmmc_cd: sdmmc-cd {
+                               rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
+                       };
+
+                       sdmmc_bus1: sdmmc-bus1 {
+                               rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
+                       };
+
+                       sdmmc_bus4: sdmmc-bus4 {
+                               rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
+                                               <2 6 RK_FUNC_1 &pcfg_pull_up>,
+                                               <2 7 RK_FUNC_1 &pcfg_pull_up>,
+                                               <2 8 RK_FUNC_1 &pcfg_pull_up>;
+                       };
+               };
+
+               spi0 {
+                       spi0_clk: spi0-clk {
+                               rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
+                       };
+                       spi0_cs0: spi0-cs0 {
+                               rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
+                       };
+                       spi0_cs1: spi0-cs1 {
+                               rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
+                       };
+                       spi0_tx: spi0-tx {
+                               rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
+                       };
+                       spi0_rx: spi0-rx {
+                               rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
+                       };
+               };
+
+               spi1 {
+                       spi1_clk: spi1-clk {
+                               rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
+                       };
+                       spi1_cs0: spi1-cs0 {
+                               rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
+                       };
+                       spi1_cs1: spi1-cs1 {
+                               rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
+                       };
+                       spi1_rx: spi1-rx {
+                               rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
+                       };
+                       spi1_tx: spi1-tx {
+                               rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
+                       };
+               };
+
+               spi2 {
+                       spi2_clk: spi2-clk {
+                               rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
+                       };
+                       spi2_cs0: spi2-cs0 {
+                               rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
+                       };
+                       spi2_rx: spi2-rx {
+                               rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
+                       };
+                       spi2_tx: spi2-tx {
+                               rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
+                       };
+               };
+
+               tsadc {
+                       otp_gpio: otp-gpio {
+                               rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>;
+                       };
+
+                       otp_out: otp-out {
+                               rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+               };
+
+               uart0 {
+                       uart0_xfer: uart0-xfer {
+                               rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
+                                               <2 25 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+
+                       uart0_cts: uart0-cts {
+                               rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+
+                       uart0_rts: uart0-rts {
+                               rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+               };
+
+               uart1 {
+                       uart1_xfer: uart1-xfer {
+                               rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
+                                               <0 21 RK_FUNC_3 &pcfg_pull_none>;
+                       };
+
+                       uart1_cts: uart1-cts {
+                               rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
+                       };
+
+                       uart1_rts: uart1-rts {
+                               rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
+                       };
+               };
+
+               uart2 {
+                       uart2_xfer: uart2-xfer {
+                               rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
+                                               <2 5 RK_FUNC_2 &pcfg_pull_none>;
+                       };
+                       /* no rts / cts for uart2 */
+               };
+
+               uart3 {
+                       uart3_xfer: uart3-xfer {
+                               rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
+                                               <3 30 RK_FUNC_3 &pcfg_pull_none>;
+                       };
+
+                       uart3_cts: uart3-cts {
+                               rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
+                       };
+
+                       uart3_rts: uart3-rts {
+                               rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
+                       };
+               };
+
+               uart4 {
+                       uart4_xfer: uart4-xfer {
+                               rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
+                                               <0 26 RK_FUNC_3 &pcfg_pull_none>;
+                       };
+
+                       uart4_cts: uart4-cts {
+                               rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
+                       };
+
+                       uart4_rts: uart4-rts {
+                               rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
+                       };
+               };
+       };
+};
index 6be2ab5025a27ca0abe52547817bd628e44bc78d..a8d745ae8a897b68136bd9048f6902f8574a4684 100644 (file)
@@ -51,6 +51,18 @@ config ROCKCHIP_RK3328
          and video codec support. Peripherals include Gigabit Ethernet,
          USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
 
+config ROCKCHIP_RK3368
+       bool "Support Rockchip RK3368"
+       select ARM64
+       select SYS_NS16550
+       help
+         The Rockchip RK3328 is a ARM-based SoC with a octa-core Cortex-A53.
+         including NEON and GPU, 512KB L2 cache for big cluster and 256 KB
+         L2 cache for little cluser, PowerVR G6110 based graphics, one video
+         output processor supporting LVDS、HDMI、eDP, several DDR3 options
+         and video codec support. Peripherals include Gigabit Ethernet,
+         USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
+
 config ROCKCHIP_RK3399
        bool "Support Rockchip RK3399"
        select ARM64
@@ -94,5 +106,6 @@ source "arch/arm/mach-rockchip/rk3036/Kconfig"
 source "arch/arm/mach-rockchip/rk3188/Kconfig"
 source "arch/arm/mach-rockchip/rk3288/Kconfig"
 source "arch/arm/mach-rockchip/rk3328/Kconfig"
+source "arch/arm/mach-rockchip/rk3368/Kconfig"
 source "arch/arm/mach-rockchip/rk3399/Kconfig"
 endif
index 327b26705dcb18a614628ba4bdbd52a966f83abe..5ed19c93275946a3a2e5562bb70268e94443e3c3 100644 (file)
@@ -31,4 +31,5 @@ endif
 
 obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/
 obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/
+obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/
 obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/
diff --git a/arch/arm/mach-rockchip/rk3368/Kconfig b/arch/arm/mach-rockchip/rk3368/Kconfig
new file mode 100644 (file)
index 0000000..3f057cc
--- /dev/null
@@ -0,0 +1,6 @@
+if ROCKCHIP_RK3368
+
+config SYS_SOC
+       default "rockchip"
+
+endif
diff --git a/arch/arm/mach-rockchip/rk3368/Makefile b/arch/arm/mach-rockchip/rk3368/Makefile
new file mode 100644 (file)
index 0000000..46798c2
--- /dev/null
@@ -0,0 +1,8 @@
+#
+# Copyright (c) 2016 Andreas Färber
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+obj-y          += clk_rk3368.o
+obj-y          += rk3368.o
+obj-y          += syscon_rk3368.o
diff --git a/arch/arm/mach-rockchip/rk3368/clk_rk3368.c b/arch/arm/mach-rockchip/rk3368/clk_rk3368.c
new file mode 100644 (file)
index 0000000..2f98165
--- /dev/null
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2017 Rockchip Electronics Co., Ltd
+ * Author: Andy Yan <andy.yan@rock-chips.org>
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3368.h>
+
+int rockchip_get_clk(struct udevice **devp)
+{
+       return uclass_get_device_by_driver(UCLASS_CLK,
+                       DM_GET_DRIVER(rockchip_rk3368_cru), devp);
+}
+
+void *rockchip_get_cru(void)
+{
+       struct rk3368_clk_priv *priv;
+       struct udevice *dev;
+       int ret;
+
+       ret = rockchip_get_clk(&dev);
+       if (ret)
+               return ERR_PTR(ret);
+
+       priv = dev_get_priv(dev);
+
+       return priv->cru;
+}
diff --git a/arch/arm/mach-rockchip/rk3368/rk3368.c b/arch/arm/mach-rockchip/rk3368/rk3368.c
new file mode 100644 (file)
index 0000000..fb829a4
--- /dev/null
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2016 Rockchip Electronics Co., Ltd
+ * Copyright (c) 2016 Andreas Färber
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/armv8/mmu.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3368.h>
+#include <asm/arch/grf_rk3368.h>
+#include <syscon.h>
+
+#define IMEM_BASE                  0xFF8C0000
+
+/* Max MCU's SRAM value is 8K, begin at (IMEM_BASE + 4K) */
+#define MCU_SRAM_BASE                  (IMEM_BASE + 1024 * 4)
+#define MCU_SRAM_BASE_BIT31_BIT28      ((MCU_SRAM_BASE & GENMASK(31, 28)) >> 28)
+#define MCU_SRAM_BASE_BIT27_BIT12      ((MCU_SRAM_BASE & GENMASK(27, 12)) >> 12)
+/* exsram may using by mcu to accessing dram(0x0-0x20000000) */
+#define MCU_EXSRAM_BASE    (0)
+#define MCU_EXSRAM_BASE_BIT31_BIT28       ((MCU_EXSRAM_BASE & GENMASK(31, 28)) >> 28)
+#define MCU_EXSRAM_BASE_BIT27_BIT12       ((MCU_EXSRAM_BASE & GENMASK(27, 12)) >> 12)
+/* experi no used, reserved value = 0 */
+#define MCU_EXPERI_BASE    (0)
+#define MCU_EXPERI_BASE_BIT31_BIT28       ((MCU_EXPERI_BASE & GENMASK(31, 28)) >> 28)
+#define MCU_EXPERI_BASE_BIT27_BIT12       ((MCU_EXPERI_BASE & GENMASK(27, 12)) >> 12)
+
+static struct mm_region rk3368_mem_map[] = {
+       {
+               .virt = 0x0UL,
+               .phys = 0x0UL,
+               .size = 0x80000000UL,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+                        PTE_BLOCK_INNER_SHARE
+       }, {
+               .virt = 0xf0000000UL,
+               .phys = 0xf0000000UL,
+               .size = 0x10000000UL,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+                        PTE_BLOCK_NON_SHARE |
+                        PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       }, {
+               /* List terminator */
+               0,
+       }
+};
+
+struct mm_region *mem_map = rk3368_mem_map;
+
+#ifdef CONFIG_ARCH_EARLY_INIT_R
+static int mcu_init(void)
+{
+       struct rk3368_grf *grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+       struct rk3368_cru *cru = rockchip_get_cru();
+
+       rk_clrsetreg(&grf->soc_con14, MCU_SRAM_BASE_BIT31_BIT28_MASK,
+                    MCU_SRAM_BASE_BIT31_BIT28 << MCU_SRAM_BASE_BIT31_BIT28_SHIFT);
+       rk_clrsetreg(&grf->soc_con11, MCU_SRAM_BASE_BIT27_BIT12_MASK,
+                    MCU_SRAM_BASE_BIT27_BIT12 << MCU_SRAM_BASE_BIT27_BIT12_SHIFT);
+       rk_clrsetreg(&grf->soc_con14, MCU_EXSRAM_BASE_BIT31_BIT28_MASK,
+                    MCU_EXSRAM_BASE_BIT31_BIT28 << MCU_EXSRAM_BASE_BIT31_BIT28_SHIFT);
+       rk_clrsetreg(&grf->soc_con12, MCU_EXSRAM_BASE_BIT27_BIT12_MASK,
+                    MCU_EXSRAM_BASE_BIT27_BIT12 << MCU_EXSRAM_BASE_BIT27_BIT12_SHIFT);
+       rk_clrsetreg(&grf->soc_con14, MCU_EXPERI_BASE_BIT31_BIT28_MASK,
+                    MCU_EXPERI_BASE_BIT31_BIT28 << MCU_EXPERI_BASE_BIT31_BIT28_SHIFT);
+       rk_clrsetreg(&grf->soc_con13, MCU_EXPERI_BASE_BIT27_BIT12_MASK,
+                    MCU_EXPERI_BASE_BIT27_BIT12 << MCU_EXPERI_BASE_BIT27_BIT12_SHIFT);
+
+       rk_clrsetreg(&cru->clksel_con[12], MCU_PLL_SEL_MASK | MCU_CLK_DIV_MASK,
+                    (MCU_PLL_SEL_GPLL << MCU_PLL_SEL_SHIFT) |
+                    (5 << MCU_CLK_DIV_SHIFT));
+
+        /* mcu dereset, for start running */
+       rk_clrreg(&cru->softrst_con[1], MCU_PO_SRST_MASK | MCU_SYS_SRST_MASK);
+
+       return 0;
+}
+
+int arch_early_init_r(void)
+{
+       return mcu_init();
+}
+#endif
diff --git a/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c b/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c
new file mode 100644 (file)
index 0000000..03e97eb
--- /dev/null
@@ -0,0 +1,24 @@
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ * Author: Andy Yan <andy.yan@rock-chips.com>
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch/clock.h>
+
+static const struct udevice_id rk3368_syscon_ids[] = {
+       { .compatible = "rockchip,rk3368-grf",
+         .data = ROCKCHIP_SYSCON_GRF },
+       { .compatible = "rockchip,rk3368-pmugrf",
+         .data = ROCKCHIP_SYSCON_PMUGRF },
+       { }
+};
+
+U_BOOT_DRIVER(syscon_rk3368) = {
+       .name = "rk3368_syscon",
+       .id = UCLASS_SYSCON,
+       .of_match = rk3368_syscon_ids,
+};
diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h
new file mode 100644 (file)
index 0000000..8ebf232
--- /dev/null
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2016 Andreas Färber
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __CONFIG_RK3368_COMMON_H
+#define __CONFIG_RK3368_COMMON_H
+
+#define CONFIG_SYS_CACHELINE_SIZE      64
+
+#include <asm/arch/hardware.h>
+#include <linux/sizes.h>
+
+#define CONFIG_NR_DRAM_BANKS           1
+#define CONFIG_SYS_MAXARGS             16
+#define CONFIG_BAUDRATE                        115200
+#define CONFIG_SYS_MALLOC_LEN          (32 << 20)
+#define CONFIG_SYS_CBSIZE              1024
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_SYS_NS16550_MEM32
+
+#define CONFIG_SYS_TEXT_BASE           0x00200000
+#define CONFIG_SYS_INIT_SP_ADDR                0x00300000
+#define CONFIG_SYS_LOAD_ADDR           0x00280000
+
+#define CONFIG_BOUNCE_BUFFER
+
+#ifndef CONFIG_SPL_BUILD
+#define ENV_MEM_LAYOUT_SETTINGS \
+       "scriptaddr=0x00500000\0" \
+       "pxefile_addr_r=0x00600000\0" \
+       "fdt_addr_r=0x5600000\0" \
+       "kernel_addr_r=0x280000\0" \
+       "ramdisk_addr_r=0x5bf0000\0"
+
+#include <config_distro_defaults.h>
+
+#define BOOT_TARGET_DEVICES(func)
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+       BOOTENV
+
+#endif
+
+#endif
diff --git a/include/dt-bindings/clock/rk3368-cru.h b/include/dt-bindings/clock/rk3368-cru.h
new file mode 100644 (file)
index 0000000..9c5dd9b
--- /dev/null
@@ -0,0 +1,384 @@
+/*
+ * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H
+
+/* core clocks */
+#define PLL_APLLB              1
+#define PLL_APLLL              2
+#define PLL_DPLL               3
+#define PLL_CPLL               4
+#define PLL_GPLL               5
+#define PLL_NPLL               6
+#define ARMCLKB                        7
+#define ARMCLKL                        8
+
+/* sclk gates (special clocks) */
+#define SCLK_GPU_CORE          64
+#define SCLK_SPI0              65
+#define SCLK_SPI1              66
+#define SCLK_SPI2              67
+#define SCLK_SDMMC             68
+#define SCLK_SDIO0             69
+#define SCLK_EMMC              71
+#define SCLK_TSADC             72
+#define SCLK_SARADC            73
+#define SCLK_NANDC0            75
+#define SCLK_UART0             77
+#define SCLK_UART1             78
+#define SCLK_UART2             79
+#define SCLK_UART3             80
+#define SCLK_UART4             81
+#define SCLK_I2S_8CH           82
+#define SCLK_SPDIF_8CH         83
+#define SCLK_I2S_2CH           84
+#define SCLK_TIMER0            85
+#define SCLK_TIMER1            86
+#define SCLK_TIMER2            87
+#define SCLK_TIMER3            88
+#define SCLK_TIMER4            89
+#define SCLK_TIMER5            90
+#define SCLK_TIMER6            91
+#define SCLK_OTGPHY0           93
+#define SCLK_OTG_ADP           96
+#define SCLK_HSICPHY480M       97
+#define SCLK_HSICPHY12M                98
+#define SCLK_MACREF            99
+#define SCLK_VOP0_PWM          100
+#define SCLK_MAC_RX            102
+#define SCLK_MAC_TX            103
+#define SCLK_EDP_24M           104
+#define SCLK_EDP               105
+#define SCLK_RGA               106
+#define SCLK_ISP               107
+#define SCLK_HDCP              108
+#define SCLK_HDMI_HDCP         109
+#define SCLK_HDMI_CEC          110
+#define SCLK_HEVC_CABAC                111
+#define SCLK_HEVC_CORE         112
+#define SCLK_I2S_8CH_OUT       113
+#define SCLK_SDMMC_DRV         114
+#define SCLK_SDIO0_DRV         115
+#define SCLK_EMMC_DRV          117
+#define SCLK_SDMMC_SAMPLE      118
+#define SCLK_SDIO0_SAMPLE      119
+#define SCLK_EMMC_SAMPLE       121
+#define SCLK_USBPHY480M                122
+#define SCLK_PVTM_CORE         123
+#define SCLK_PVTM_GPU          124
+#define SCLK_PVTM_PMU          125
+#define SCLK_SFC               126
+#define SCLK_MAC               127
+#define SCLK_MACREF_OUT                128
+
+#define DCLK_VOP               190
+#define MCLK_CRYPTO            191
+
+/* aclk gates */
+#define ACLK_GPU_MEM           192
+#define ACLK_GPU_CFG           193
+#define ACLK_DMAC_BUS          194
+#define ACLK_DMAC_PERI         195
+#define ACLK_PERI_MMU          196
+#define ACLK_GMAC              197
+#define ACLK_VOP               198
+#define ACLK_VOP_IEP           199
+#define ACLK_RGA               200
+#define ACLK_HDCP              201
+#define ACLK_IEP               202
+#define ACLK_VIO0_NOC          203
+#define ACLK_VIP               204
+#define ACLK_ISP               205
+#define ACLK_VIO1_NOC          206
+#define ACLK_VIDEO             208
+#define ACLK_BUS               209
+#define ACLK_PERI              210
+
+/* pclk gates */
+#define PCLK_GPIO0             320
+#define PCLK_GPIO1             321
+#define PCLK_GPIO2             322
+#define PCLK_GPIO3             323
+#define PCLK_PMUGRF            324
+#define PCLK_MAILBOX           325
+#define PCLK_GRF               329
+#define PCLK_SGRF              330
+#define PCLK_PMU               331
+#define PCLK_I2C0              332
+#define PCLK_I2C1              333
+#define PCLK_I2C2              334
+#define PCLK_I2C3              335
+#define PCLK_I2C4              336
+#define PCLK_I2C5              337
+#define PCLK_SPI0              338
+#define PCLK_SPI1              339
+#define PCLK_SPI2              340
+#define PCLK_UART0             341
+#define PCLK_UART1             342
+#define PCLK_UART2             343
+#define PCLK_UART3             344
+#define PCLK_UART4             345
+#define PCLK_TSADC             346
+#define PCLK_SARADC            347
+#define PCLK_SIM               348
+#define PCLK_GMAC              349
+#define PCLK_PWM0              350
+#define PCLK_PWM1              351
+#define PCLK_TIMER0            353
+#define PCLK_TIMER1            354
+#define PCLK_EDP_CTRL          355
+#define PCLK_MIPI_DSI0         356
+#define PCLK_MIPI_CSI          358
+#define PCLK_HDCP              359
+#define PCLK_HDMI_CTRL         360
+#define PCLK_VIO_H2P           361
+#define PCLK_BUS               362
+#define PCLK_PERI              363
+#define PCLK_DDRUPCTL          364
+#define PCLK_DDRPHY            365
+#define PCLK_ISP               366
+#define PCLK_VIP               367
+#define PCLK_WDT               368
+
+/* hclk gates */
+#define HCLK_SFC               448
+#define HCLK_OTG0              449
+#define HCLK_HOST0             450
+#define HCLK_HOST1             451
+#define HCLK_HSIC              452
+#define HCLK_NANDC0            453
+#define HCLK_TSP               455
+#define HCLK_SDMMC             456
+#define HCLK_SDIO0             457
+#define HCLK_EMMC              459
+#define HCLK_HSADC             460
+#define HCLK_CRYPTO            461
+#define HCLK_I2S_2CH           462
+#define HCLK_I2S_8CH           463
+#define HCLK_SPDIF             464
+#define HCLK_VOP               465
+#define HCLK_ROM               467
+#define HCLK_IEP               468
+#define HCLK_ISP               469
+#define HCLK_RGA               470
+#define HCLK_VIO_AHB_ARBI      471
+#define HCLK_VIO_NOC           472
+#define HCLK_VIP               473
+#define HCLK_VIO_H2P           474
+#define HCLK_VIO_HDCPMMU       475
+#define HCLK_VIDEO             476
+#define HCLK_BUS               477
+#define HCLK_PERI              478
+
+#define CLK_NR_CLKS            (HCLK_PERI + 1)
+
+/* soft-reset indices */
+#define SRST_CORE_B0           0
+#define SRST_CORE_B1           1
+#define SRST_CORE_B2           2
+#define SRST_CORE_B3           3
+#define SRST_CORE_B0_PO                4
+#define SRST_CORE_B1_PO                5
+#define SRST_CORE_B2_PO                6
+#define SRST_CORE_B3_PO                7
+#define SRST_L2_B              8
+#define SRST_ADB_B             9
+#define SRST_PD_CORE_B_NIU     10
+#define SRST_PDBUS_STRSYS      11
+#define SRST_SOCDBG_B          14
+#define SRST_CORE_B_DBG                15
+
+#define SRST_DMAC1             18
+#define SRST_INTMEM            19
+#define SRST_ROM               20
+#define SRST_SPDIF8CH          21
+#define SRST_I2S8CH            23
+#define SRST_MAILBOX           24
+#define SRST_I2S2CH            25
+#define SRST_EFUSE_256         26
+#define SRST_MCU_SYS           28
+#define SRST_MCU_PO            29
+#define SRST_MCU_NOC           30
+#define SRST_EFUSE             31
+
+#define SRST_GPIO0             32
+#define SRST_GPIO1             33
+#define SRST_GPIO2             34
+#define SRST_GPIO3             35
+#define SRST_GPIO4             36
+#define SRST_PMUGRF            41
+#define SRST_I2C0              42
+#define SRST_I2C1              43
+#define SRST_I2C2              44
+#define SRST_I2C3              45
+#define SRST_I2C4              46
+#define SRST_I2C5              47
+
+#define SRST_DWPWM             48
+#define SRST_MMC_PERI          49
+#define SRST_PERIPH_MMU                50
+#define SRST_GRF               55
+#define SRST_PMU               56
+#define SRST_PERIPH_AXI                57
+#define SRST_PERIPH_AHB                58
+#define SRST_PERIPH_APB                59
+#define SRST_PERIPH_NIU                60
+#define SRST_PDPERI_AHB_ARBI   61
+#define SRST_EMEM              62
+#define SRST_USB_PERI          63
+
+#define SRST_DMAC2             64
+#define SRST_MAC               66
+#define SRST_GPS               67
+#define SRST_RKPWM             69
+#define SRST_USBHOST0          72
+#define SRST_HSIC              73
+#define SRST_HSIC_AUX          74
+#define SRST_HSIC_PHY          75
+#define SRST_HSADC             76
+#define SRST_NANDC0            77
+#define SRST_SFC               79
+
+#define SRST_SPI0              83
+#define SRST_SPI1              84
+#define SRST_SPI2              85
+#define SRST_SARADC            87
+#define SRST_PDALIVE_NIU       88
+#define SRST_PDPMU_INTMEM      89
+#define SRST_PDPMU_NIU         90
+#define SRST_SGRF              91
+
+#define SRST_VIO_ARBI          96
+#define SRST_RGA_NIU           97
+#define SRST_VIO0_NIU_AXI      98
+#define SRST_VIO_NIU_AHB       99
+#define SRST_LCDC0_AXI         100
+#define SRST_LCDC0_AHB         101
+#define SRST_LCDC0_DCLK                102
+#define SRST_VIP               104
+#define SRST_RGA_CORE          105
+#define SRST_IEP_AXI           106
+#define SRST_IEP_AHB           107
+#define SRST_RGA_AXI           108
+#define SRST_RGA_AHB           109
+#define SRST_ISP               110
+#define SRST_EDP_24M           111
+
+#define SRST_VIDEO_AXI         112
+#define SRST_VIDEO_AHB         113
+#define SRST_MIPIDPHYTX                114
+#define SRST_MIPIDSI0          115
+#define SRST_MIPIDPHYRX                116
+#define SRST_MIPICSI           117
+#define SRST_GPU               120
+#define SRST_HDMI              121
+#define SRST_EDP               122
+#define SRST_PMU_PVTM          123
+#define SRST_CORE_PVTM         124
+#define SRST_GPU_PVTM          125
+#define SRST_GPU_SYS           126
+#define SRST_GPU_MEM_NIU       127
+
+#define SRST_MMC0              128
+#define SRST_SDIO0             129
+#define SRST_EMMC              131
+#define SRST_USBOTG_AHB                132
+#define SRST_USBOTG_PHY                133
+#define SRST_USBOTG_CON                134
+#define SRST_USBHOST0_AHB      135
+#define SRST_USBHOST0_PHY      136
+#define SRST_USBHOST0_CON      137
+#define SRST_USBOTG_UTMI       138
+#define SRST_USBHOST1_UTMI     139
+#define SRST_USB_ADP           141
+
+#define SRST_CORESIGHT         144
+#define SRST_PD_CORE_AHB_NOC   145
+#define SRST_PD_CORE_APB_NOC   146
+#define SRST_GIC               148
+#define SRST_LCDC_PWM0         149
+#define SRST_RGA_H2P_BRG       153
+#define SRST_VIDEO             154
+#define SRST_GPU_CFG_NIU       157
+#define SRST_TSADC             159
+
+#define SRST_DDRPHY0           160
+#define SRST_DDRPHY0_APB       161
+#define SRST_DDRCTRL0          162
+#define SRST_DDRCTRL0_APB      163
+#define SRST_VIDEO_NIU         165
+#define SRST_VIDEO_NIU_AHB     167
+#define SRST_DDRMSCH0          170
+#define SRST_PDBUS_AHB         173
+#define SRST_CRYPTO            174
+
+#define SRST_UART0             179
+#define SRST_UART1             180
+#define SRST_UART2             181
+#define SRST_UART3             182
+#define SRST_UART4             183
+#define SRST_SIMC              186
+#define SRST_TSP               188
+#define SRST_TSP_CLKIN0                189
+
+#define SRST_CORE_L0           192
+#define SRST_CORE_L1           193
+#define SRST_CORE_L2           194
+#define SRST_CORE_L3           195
+#define SRST_CORE_L0_PO                195
+#define SRST_CORE_L1_PO                197
+#define SRST_CORE_L2_PO                198
+#define SRST_CORE_L3_PO                199
+#define SRST_L2_L              200
+#define SRST_ADB_L             201
+#define SRST_PD_CORE_L_NIU     202
+#define SRST_CCI_SYS           203
+#define SRST_CCI_DDR           204
+#define SRST_CCI               205
+#define SRST_SOCDBG_L          206
+#define SRST_CORE_L_DBG                207
+
+#define SRST_CORE_B0_NC                208
+#define SRST_CORE_B0_PO_NC     209
+#define SRST_L2_B_NC           210
+#define SRST_ADB_B_NC          211
+#define SRST_PD_CORE_B_NIU_NC  212
+#define SRST_PDBUS_STRSYS_NC   213
+#define SRST_CORE_L0_NC                214
+#define SRST_CORE_L0_PO_NC     215
+#define SRST_L2_L_NC           216
+#define SRST_ADB_L_NC          217
+#define SRST_PD_CORE_L_NIU_NC  218
+#define SRST_CCI_SYS_NC                219
+#define SRST_CCI_DDR_NC                220
+#define SRST_CCI_NC            221
+#define SRST_TRACE_NC          222
+
+#define SRST_TIMER00           224
+#define SRST_TIMER01           225
+#define SRST_TIMER02           226
+#define SRST_TIMER03           227
+#define SRST_TIMER04           228
+#define SRST_TIMER05           229
+#define SRST_TIMER10           230
+#define SRST_TIMER11           231
+#define SRST_TIMER12           232
+#define SRST_TIMER13           233
+#define SRST_TIMER14           234
+#define SRST_TIMER15           235
+#define SRST_TIMER0_APB                236
+#define SRST_TIMER1_APB                237
+
+#endif