void enable_basic_uboot_clocks(void)
 {
        u32 const clk_domains_essential[] = {
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+               (*prcm)->cm_ipu_clkstctrl,
+#endif
                0
        };
 
                (*prcm)->cm_l4per_i2c2_clkctrl,
                (*prcm)->cm_l4per_i2c3_clkctrl,
                (*prcm)->cm_l4per_i2c4_clkctrl,
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
+               (*prcm)->cm_ipu_i2c5_clkctrl,
+#else
                (*prcm)->cm_l4per_i2c5_clkctrl,
+#endif
                (*prcm)->cm_l3init_hsusbhost_clkctrl,
                (*prcm)->cm_l3init_fsusb_clkctrl,
                0
 
        .cm_dsp_clkstctrl                       = 0x4a005400,
        .cm_dsp_dsp_clkctrl                     = 0x4a005420,
 
+       /* cm IPU */
+       .cm_ipu_clkstctrl                       = 0x4a005540,
+       .cm_ipu_i2c5_clkctrl                    = 0x4a005578,
+
        /* prm irqstatus regs */
        .prm_irqstatus_mpu_2                    = 0x4ae06014,