SMDKC100 ARM ARMV7 (S5PC100 SoC)
s5p_goni ARM ARMV7 (S5PC110 SoC)
- s5pc210_universal ARM ARMV7 (S5PC210 SoC)
+ s5pc210_universal ARM ARMV7 (EXYNOS4210 SoC)
Chander Kashyap <k.chander@samsung.com>
- origen ARM ARMV7 (S5PC210 SoC)
- SMDKV310 ARM ARMV7 (S5PC210 SoC)
+ origen ARM ARMV7 (EXYNOS4210 SoC)
+ SMDKV310 ARM ARMV7 (EXYNOS4210 SoC)
Torsten Koschorrek <koschorrek@synertronixx.de>
scb9328 ARM920T (i.MXL)
ifeq ($(SOC),s5pc1xx)
LIBS += $(CPUDIR)/s5p-common/libs5p-common.o
endif
-ifeq ($(SOC),s5pc2xx)
+ifeq ($(SOC),exynos)
LIBS += $(CPUDIR)/s5p-common/libs5p-common.o
endif
--- /dev/null
+#
+# Copyright (C) 2009 Samsung Electronics
+# Minkyu Kang <mk7.kang@samsung.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).o
+
+COBJS += clock.o soc.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Copyright (C) 2010 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/clk.h>
+
+#ifndef CONFIG_SYS_CLK_FREQ_C210
+#define CONFIG_SYS_CLK_FREQ_C210 24000000
+#endif
+
+/* exynos4: return pll clock frequency */
+static unsigned long exynos4_get_pll_clk(int pllreg)
+{
+ struct exynos4_clock *clk =
+ (struct exynos4_clock *)samsung_get_base_clock();
+ unsigned long r, m, p, s, k = 0, mask, fout;
+ unsigned int freq;
+
+ switch (pllreg) {
+ case APLL:
+ r = readl(&clk->apll_con0);
+ break;
+ case MPLL:
+ r = readl(&clk->mpll_con0);
+ break;
+ case EPLL:
+ r = readl(&clk->epll_con0);
+ k = readl(&clk->epll_con1);
+ break;
+ case VPLL:
+ r = readl(&clk->vpll_con0);
+ k = readl(&clk->vpll_con1);
+ break;
+ default:
+ printf("Unsupported PLL (%d)\n", pllreg);
+ return 0;
+ }
+
+ /*
+ * APLL_CON: MIDV [25:16]
+ * MPLL_CON: MIDV [25:16]
+ * EPLL_CON: MIDV [24:16]
+ * VPLL_CON: MIDV [24:16]
+ */
+ if (pllreg == APLL || pllreg == MPLL)
+ mask = 0x3ff;
+ else
+ mask = 0x1ff;
+
+ m = (r >> 16) & mask;
+
+ /* PDIV [13:8] */
+ p = (r >> 8) & 0x3f;
+ /* SDIV [2:0] */
+ s = r & 0x7;
+
+ freq = CONFIG_SYS_CLK_FREQ_C210;
+
+ if (pllreg == EPLL) {
+ k = k & 0xffff;
+ /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
+ fout = (m + k / 65536) * (freq / (p * (1 << s)));
+ } else if (pllreg == VPLL) {
+ k = k & 0xfff;
+ /* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
+ fout = (m + k / 1024) * (freq / (p * (1 << s)));
+ } else {
+ if (s < 1)
+ s = 1;
+ /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
+ fout = m * (freq / (p * (1 << (s - 1))));
+ }
+
+ return fout;
+}
+
+/* exynos4: return ARM clock frequency */
+static unsigned long exynos4_get_arm_clk(void)
+{
+ struct exynos4_clock *clk =
+ (struct exynos4_clock *)samsung_get_base_clock();
+ unsigned long div;
+ unsigned long dout_apll;
+ unsigned int apll_ratio;
+
+ div = readl(&clk->div_cpu0);
+
+ /* APLL_RATIO: [26:24] */
+ apll_ratio = (div >> 24) & 0x7;
+
+ dout_apll = get_pll_clk(APLL) / (apll_ratio + 1);
+
+ return dout_apll;
+}
+
+/* exynos4: return pwm clock frequency */
+static unsigned long exynos4_get_pwm_clk(void)
+{
+ struct exynos4_clock *clk =
+ (struct exynos4_clock *)samsung_get_base_clock();
+ unsigned long pclk, sclk;
+ unsigned int sel;
+ unsigned int ratio;
+
+ if (s5p_get_cpu_rev() == 0) {
+ /*
+ * CLK_SRC_PERIL0
+ * PWM_SEL [27:24]
+ */
+ sel = readl(&clk->src_peril0);
+ sel = (sel >> 24) & 0xf;
+
+ if (sel == 0x6)
+ sclk = get_pll_clk(MPLL);
+ else if (sel == 0x7)
+ sclk = get_pll_clk(EPLL);
+ else if (sel == 0x8)
+ sclk = get_pll_clk(VPLL);
+ else
+ return 0;
+
+ /*
+ * CLK_DIV_PERIL3
+ * PWM_RATIO [3:0]
+ */
+ ratio = readl(&clk->div_peril3);
+ ratio = ratio & 0xf;
+ } else if (s5p_get_cpu_rev() == 1) {
+ sclk = get_pll_clk(MPLL);
+ ratio = 8;
+ } else
+ return 0;
+
+ pclk = sclk / (ratio + 1);
+
+ return pclk;
+}
+
+/* exynos4: return uart clock frequency */
+static unsigned long exynos4_get_uart_clk(int dev_index)
+{
+ struct exynos4_clock *clk =
+ (struct exynos4_clock *)samsung_get_base_clock();
+ unsigned long uclk, sclk;
+ unsigned int sel;
+ unsigned int ratio;
+
+ /*
+ * CLK_SRC_PERIL0
+ * UART0_SEL [3:0]
+ * UART1_SEL [7:4]
+ * UART2_SEL [8:11]
+ * UART3_SEL [12:15]
+ * UART4_SEL [16:19]
+ * UART5_SEL [23:20]
+ */
+ sel = readl(&clk->src_peril0);
+ sel = (sel >> (dev_index << 2)) & 0xf;
+
+ if (sel == 0x6)
+ sclk = get_pll_clk(MPLL);
+ else if (sel == 0x7)
+ sclk = get_pll_clk(EPLL);
+ else if (sel == 0x8)
+ sclk = get_pll_clk(VPLL);
+ else
+ return 0;
+
+ /*
+ * CLK_DIV_PERIL0
+ * UART0_RATIO [3:0]
+ * UART1_RATIO [7:4]
+ * UART2_RATIO [8:11]
+ * UART3_RATIO [12:15]
+ * UART4_RATIO [16:19]
+ * UART5_RATIO [23:20]
+ */
+ ratio = readl(&clk->div_peril0);
+ ratio = (ratio >> (dev_index << 2)) & 0xf;
+
+ uclk = sclk / (ratio + 1);
+
+ return uclk;
+}
+
+/* exynos4: set the mmc clock */
+static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
+{
+ struct exynos4_clock *clk =
+ (struct exynos4_clock *)samsung_get_base_clock();
+ unsigned int addr;
+ unsigned int val;
+
+ /*
+ * CLK_DIV_FSYS1
+ * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
+ * CLK_DIV_FSYS2
+ * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
+ */
+ if (dev_index < 2) {
+ addr = (unsigned int)&clk->div_fsys1;
+ } else {
+ addr = (unsigned int)&clk->div_fsys2;
+ dev_index -= 2;
+ }
+
+ val = readl(addr);
+ val &= ~(0xff << ((dev_index << 4) + 8));
+ val |= (div & 0xff) << ((dev_index << 4) + 8);
+ writel(val, addr);
+}
+
+unsigned long get_pll_clk(int pllreg)
+{
+ return exynos4_get_pll_clk(pllreg);
+}
+
+unsigned long get_arm_clk(void)
+{
+ return exynos4_get_arm_clk();
+}
+
+unsigned long get_pwm_clk(void)
+{
+ return exynos4_get_pwm_clk();
+}
+
+unsigned long get_uart_clk(int dev_index)
+{
+ return exynos4_get_uart_clk(dev_index);
+}
+
+void set_mmc_clk(int dev_index, unsigned int div)
+{
+ exynos4_set_mmc_clk(dev_index, div);
+}
--- /dev/null
+/*
+ * Copyright (c) 2010 Samsung Electronics.
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+void reset_cpu(ulong addr)
+{
+ writel(0x1, samsung_get_base_swreset());
+}
+++ /dev/null
-#
-# Copyright (C) 2009 Samsung Electronics
-# Minkyu Kang <mk7.kang@samsung.com>
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(SOC).o
-
-COBJS += clock.o soc.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
-
-all: $(obj).depend $(LIB)
-
-$(LIB): $(OBJS)
- $(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-/*
- * Copyright (C) 2010 Samsung Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/clk.h>
-
-#ifndef CONFIG_SYS_CLK_FREQ_C210
-#define CONFIG_SYS_CLK_FREQ_C210 24000000
-#endif
-
-/* s5pc210: return pll clock frequency */
-static unsigned long s5pc210_get_pll_clk(int pllreg)
-{
- struct s5pc210_clock *clk =
- (struct s5pc210_clock *)samsung_get_base_clock();
- unsigned long r, m, p, s, k = 0, mask, fout;
- unsigned int freq;
-
- switch (pllreg) {
- case APLL:
- r = readl(&clk->apll_con0);
- break;
- case MPLL:
- r = readl(&clk->mpll_con0);
- break;
- case EPLL:
- r = readl(&clk->epll_con0);
- k = readl(&clk->epll_con1);
- break;
- case VPLL:
- r = readl(&clk->vpll_con0);
- k = readl(&clk->vpll_con1);
- break;
- default:
- printf("Unsupported PLL (%d)\n", pllreg);
- return 0;
- }
-
- /*
- * APLL_CON: MIDV [25:16]
- * MPLL_CON: MIDV [25:16]
- * EPLL_CON: MIDV [24:16]
- * VPLL_CON: MIDV [24:16]
- */
- if (pllreg == APLL || pllreg == MPLL)
- mask = 0x3ff;
- else
- mask = 0x1ff;
-
- m = (r >> 16) & mask;
-
- /* PDIV [13:8] */
- p = (r >> 8) & 0x3f;
- /* SDIV [2:0] */
- s = r & 0x7;
-
- freq = CONFIG_SYS_CLK_FREQ_C210;
-
- if (pllreg == EPLL) {
- k = k & 0xffff;
- /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
- fout = (m + k / 65536) * (freq / (p * (1 << s)));
- } else if (pllreg == VPLL) {
- k = k & 0xfff;
- /* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
- fout = (m + k / 1024) * (freq / (p * (1 << s)));
- } else {
- if (s < 1)
- s = 1;
- /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
- fout = m * (freq / (p * (1 << (s - 1))));
- }
-
- return fout;
-}
-
-/* s5pc210: return ARM clock frequency */
-static unsigned long s5pc210_get_arm_clk(void)
-{
- struct s5pc210_clock *clk =
- (struct s5pc210_clock *)samsung_get_base_clock();
- unsigned long div;
- unsigned long dout_apll;
- unsigned int apll_ratio;
-
- div = readl(&clk->div_cpu0);
-
- /* APLL_RATIO: [26:24] */
- apll_ratio = (div >> 24) & 0x7;
-
- dout_apll = get_pll_clk(APLL) / (apll_ratio + 1);
-
- return dout_apll;
-}
-
-/* s5pc210: return pwm clock frequency */
-static unsigned long s5pc210_get_pwm_clk(void)
-{
- struct s5pc210_clock *clk =
- (struct s5pc210_clock *)samsung_get_base_clock();
- unsigned long pclk, sclk;
- unsigned int sel;
- unsigned int ratio;
-
- if (s5p_get_cpu_rev() == 0) {
- /*
- * CLK_SRC_PERIL0
- * PWM_SEL [27:24]
- */
- sel = readl(&clk->src_peril0);
- sel = (sel >> 24) & 0xf;
-
- if (sel == 0x6)
- sclk = get_pll_clk(MPLL);
- else if (sel == 0x7)
- sclk = get_pll_clk(EPLL);
- else if (sel == 0x8)
- sclk = get_pll_clk(VPLL);
- else
- return 0;
-
- /*
- * CLK_DIV_PERIL3
- * PWM_RATIO [3:0]
- */
- ratio = readl(&clk->div_peril3);
- ratio = ratio & 0xf;
- } else if (s5p_get_cpu_rev() == 1) {
- sclk = get_pll_clk(MPLL);
- ratio = 8;
- } else
- return 0;
-
- pclk = sclk / (ratio + 1);
-
- return pclk;
-}
-
-/* s5pc210: return uart clock frequency */
-static unsigned long s5pc210_get_uart_clk(int dev_index)
-{
- struct s5pc210_clock *clk =
- (struct s5pc210_clock *)samsung_get_base_clock();
- unsigned long uclk, sclk;
- unsigned int sel;
- unsigned int ratio;
-
- /*
- * CLK_SRC_PERIL0
- * UART0_SEL [3:0]
- * UART1_SEL [7:4]
- * UART2_SEL [8:11]
- * UART3_SEL [12:15]
- * UART4_SEL [16:19]
- * UART5_SEL [23:20]
- */
- sel = readl(&clk->src_peril0);
- sel = (sel >> (dev_index << 2)) & 0xf;
-
- if (sel == 0x6)
- sclk = get_pll_clk(MPLL);
- else if (sel == 0x7)
- sclk = get_pll_clk(EPLL);
- else if (sel == 0x8)
- sclk = get_pll_clk(VPLL);
- else
- return 0;
-
- /*
- * CLK_DIV_PERIL0
- * UART0_RATIO [3:0]
- * UART1_RATIO [7:4]
- * UART2_RATIO [8:11]
- * UART3_RATIO [12:15]
- * UART4_RATIO [16:19]
- * UART5_RATIO [23:20]
- */
- ratio = readl(&clk->div_peril0);
- ratio = (ratio >> (dev_index << 2)) & 0xf;
-
- uclk = sclk / (ratio + 1);
-
- return uclk;
-}
-
-/* s5pc210: set the mmc clock */
-static void s5pc210_set_mmc_clk(int dev_index, unsigned int div)
-{
- struct s5pc210_clock *clk =
- (struct s5pc210_clock *)samsung_get_base_clock();
- unsigned int addr;
- unsigned int val;
-
- /*
- * CLK_DIV_FSYS1
- * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
- * CLK_DIV_FSYS2
- * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
- */
- if (dev_index < 2) {
- addr = (unsigned int)&clk->div_fsys1;
- } else {
- addr = (unsigned int)&clk->div_fsys2;
- dev_index -= 2;
- }
-
- val = readl(addr);
- val &= ~(0xff << ((dev_index << 4) + 8));
- val |= (div & 0xff) << ((dev_index << 4) + 8);
- writel(val, addr);
-}
-
-unsigned long get_pll_clk(int pllreg)
-{
- return s5pc210_get_pll_clk(pllreg);
-}
-
-unsigned long get_arm_clk(void)
-{
- return s5pc210_get_arm_clk();
-}
-
-unsigned long get_pwm_clk(void)
-{
- return s5pc210_get_pwm_clk();
-}
-
-unsigned long get_uart_clk(int dev_index)
-{
- return s5pc210_get_uart_clk(dev_index);
-}
-
-void set_mmc_clk(int dev_index, unsigned int div)
-{
- s5pc210_set_mmc_clk(dev_index, div);
-}
+++ /dev/null
-/*
- * Copyright (c) 2010 Samsung Electronics.
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-
-void reset_cpu(ulong addr)
-{
- writel(0x1, samsung_get_base_swreset());
-}
--- /dev/null
+/*
+ * Copyright (C) 2010 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * MyungJoo Ham <myungjoo.ham@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARM_ARCH_ADC_H_
+#define __ASM_ARM_ARCH_ADC_H_
+
+#ifndef __ASSEMBLY__
+struct s5p_adc {
+ unsigned int adccon;
+ unsigned int adctsc;
+ unsigned int adcdly;
+ unsigned int adcdat0;
+ unsigned int adcdat1;
+ unsigned int adcupdn;
+ unsigned int adcclrint;
+ unsigned int adcmux;
+ unsigned int adcclrintpndnup;
+};
+#endif
+
+#endif /* __ASM_ARM_ARCH_ADC_H_ */
--- /dev/null
+/*
+ * (C) Copyright 2010 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __ASM_ARM_ARCH_CLK_H_
+#define __ASM_ARM_ARCH_CLK_H_
+
+#define APLL 0
+#define MPLL 1
+#define EPLL 2
+#define HPLL 3
+#define VPLL 4
+
+unsigned long get_pll_clk(int pllreg);
+unsigned long get_arm_clk(void);
+unsigned long get_pwm_clk(void);
+unsigned long get_uart_clk(int dev_index);
+void set_mmc_clk(int dev_index, unsigned int div);
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2010 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __ASM_ARM_ARCH_CLOCK_H_
+#define __ASM_ARM_ARCH_CLOCK_H_
+
+#ifndef __ASSEMBLY__
+struct exynos4_clock {
+ unsigned char res1[0x4200];
+ unsigned int src_leftbus;
+ unsigned char res2[0x1fc];
+ unsigned int mux_stat_leftbus;
+ unsigned char res4[0xfc];
+ unsigned int div_leftbus;
+ unsigned char res5[0xfc];
+ unsigned int div_stat_leftbus;
+ unsigned char res6[0x1fc];
+ unsigned int gate_ip_leftbus;
+ unsigned char res7[0x1fc];
+ unsigned int clkout_leftbus;
+ unsigned int clkout_leftbus_div_stat;
+ unsigned char res8[0x37f8];
+ unsigned int src_rightbus;
+ unsigned char res9[0x1fc];
+ unsigned int mux_stat_rightbus;
+ unsigned char res10[0xfc];
+ unsigned int div_rightbus;
+ unsigned char res11[0xfc];
+ unsigned int div_stat_rightbus;
+ unsigned char res12[0x1fc];
+ unsigned int gate_ip_rightbus;
+ unsigned char res13[0x1fc];
+ unsigned int clkout_rightbus;
+ unsigned int clkout_rightbus_div_stat;
+ unsigned char res14[0x3608];
+ unsigned int epll_lock;
+ unsigned char res15[0xc];
+ unsigned int vpll_lock;
+ unsigned char res16[0xec];
+ unsigned int epll_con0;
+ unsigned int epll_con1;
+ unsigned char res17[0x8];
+ unsigned int vpll_con0;
+ unsigned int vpll_con1;
+ unsigned char res18[0xe8];
+ unsigned int src_top0;
+ unsigned int src_top1;
+ unsigned char res19[0x8];
+ unsigned int src_cam;
+ unsigned int src_tv;
+ unsigned int src_mfc;
+ unsigned int src_g3d;
+ unsigned int src_image;
+ unsigned int src_lcd0;
+ unsigned int src_lcd1;
+ unsigned int src_maudio;
+ unsigned int src_fsys;
+ unsigned char res20[0xc];
+ unsigned int src_peril0;
+ unsigned int src_peril1;
+ unsigned char res21[0xb8];
+ unsigned int src_mask_top;
+ unsigned char res22[0xc];
+ unsigned int src_mask_cam;
+ unsigned int src_mask_tv;
+ unsigned char res23[0xc];
+ unsigned int src_mask_lcd0;
+ unsigned int src_mask_lcd1;
+ unsigned int src_mask_maudio;
+ unsigned int src_mask_fsys;
+ unsigned char res24[0xc];
+ unsigned int src_mask_peril0;
+ unsigned int src_mask_peril1;
+ unsigned char res25[0xb8];
+ unsigned int mux_stat_top;
+ unsigned char res26[0x14];
+ unsigned int mux_stat_mfc;
+ unsigned int mux_stat_g3d;
+ unsigned int mux_stat_image;
+ unsigned char res27[0xdc];
+ unsigned int div_top;
+ unsigned char res28[0xc];
+ unsigned int div_cam;
+ unsigned int div_tv;
+ unsigned int div_mfc;
+ unsigned int div_g3d;
+ unsigned int div_image;
+ unsigned int div_lcd0;
+ unsigned int div_lcd1;
+ unsigned int div_maudio;
+ unsigned int div_fsys0;
+ unsigned int div_fsys1;
+ unsigned int div_fsys2;
+ unsigned int div_fsys3;
+ unsigned int div_peril0;
+ unsigned int div_peril1;
+ unsigned int div_peril2;
+ unsigned int div_peril3;
+ unsigned int div_peril4;
+ unsigned int div_peril5;
+ unsigned char res29[0x18];
+ unsigned int div2_ratio;
+ unsigned char res30[0x8c];
+ unsigned int div_stat_top;
+ unsigned char res31[0xc];
+ unsigned int div_stat_cam;
+ unsigned int div_stat_tv;
+ unsigned int div_stat_mfc;
+ unsigned int div_stat_g3d;
+ unsigned int div_stat_image;
+ unsigned int div_stat_lcd0;
+ unsigned int div_stat_lcd1;
+ unsigned int div_stat_maudio;
+ unsigned int div_stat_fsys0;
+ unsigned int div_stat_fsys1;
+ unsigned int div_stat_fsys2;
+ unsigned int div_stat_fsys3;
+ unsigned int div_stat_peril0;
+ unsigned int div_stat_peril1;
+ unsigned int div_stat_peril2;
+ unsigned int div_stat_peril3;
+ unsigned int div_stat_peril4;
+ unsigned int div_stat_peril5;
+ unsigned char res32[0x18];
+ unsigned int div2_stat;
+ unsigned char res33[0x29c];
+ unsigned int gate_ip_cam;
+ unsigned int gate_ip_tv;
+ unsigned int gate_ip_mfc;
+ unsigned int gate_ip_g3d;
+ unsigned int gate_ip_image;
+ unsigned int gate_ip_lcd0;
+ unsigned int gate_ip_lcd1;
+ unsigned char res34[0x4];
+ unsigned int gate_ip_fsys;
+ unsigned char res35[0x8];
+ unsigned int gate_ip_gps;
+ unsigned int gate_ip_peril;
+ unsigned char res36[0xc];
+ unsigned int gate_ip_perir;
+ unsigned char res37[0xc];
+ unsigned int gate_block;
+ unsigned char res38[0x8c];
+ unsigned int clkout_cmu_top;
+ unsigned int clkout_cmu_top_div_stat;
+ unsigned char res39[0x37f8];
+ unsigned int src_dmc;
+ unsigned char res40[0xfc];
+ unsigned int src_mask_dmc;
+ unsigned char res41[0xfc];
+ unsigned int mux_stat_dmc;
+ unsigned char res42[0xfc];
+ unsigned int div_dmc0;
+ unsigned int div_dmc1;
+ unsigned char res43[0xf8];
+ unsigned int div_stat_dmc0;
+ unsigned int div_stat_dmc1;
+ unsigned char res44[0x2f8];
+ unsigned int gate_ip_dmc;
+ unsigned char res45[0xfc];
+ unsigned int clkout_cmu_dmc;
+ unsigned int clkout_cmu_dmc_div_stat;
+ unsigned char res46[0x5f8];
+ unsigned int dcgidx_map0;
+ unsigned int dcgidx_map1;
+ unsigned int dcgidx_map2;
+ unsigned char res47[0x14];
+ unsigned int dcgperf_map0;
+ unsigned int dcgperf_map1;
+ unsigned char res48[0x18];
+ unsigned int dvcidx_map;
+ unsigned char res49[0x1c];
+ unsigned int freq_cpu;
+ unsigned int freq_dpm;
+ unsigned char res50[0x18];
+ unsigned int dvsemclk_en;
+ unsigned int maxperf;
+ unsigned char res51[0x2f78];
+ unsigned int apll_lock;
+ unsigned char res52[0x4];
+ unsigned int mpll_lock;
+ unsigned char res53[0xf4];
+ unsigned int apll_con0;
+ unsigned int apll_con1;
+ unsigned int mpll_con0;
+ unsigned int mpll_con1;
+ unsigned char res54[0xf0];
+ unsigned int src_cpu;
+ unsigned char res55[0x1fc];
+ unsigned int mux_stat_cpu;
+ unsigned char res56[0xfc];
+ unsigned int div_cpu0;
+ unsigned int div_cpu1;
+ unsigned char res57[0xf8];
+ unsigned int div_stat_cpu0;
+ unsigned int div_stat_cpu1;
+ unsigned char res58[0x3f8];
+ unsigned int clkout_cmu_cpu;
+ unsigned int clkout_cmu_cpu_div_stat;
+ unsigned char res59[0x5f8];
+ unsigned int armclk_stopctrl;
+ unsigned int atclk_stopctrl;
+ unsigned char res60[0x8];
+ unsigned int parityfail_status;
+ unsigned int parityfail_clear;
+ unsigned char res61[0xe8];
+ unsigned int apll_con0_l8;
+ unsigned int apll_con0_l7;
+ unsigned int apll_con0_l6;
+ unsigned int apll_con0_l5;
+ unsigned int apll_con0_l4;
+ unsigned int apll_con0_l3;
+ unsigned int apll_con0_l2;
+ unsigned int apll_con0_l1;
+ unsigned int iem_control;
+ unsigned char res62[0xdc];
+ unsigned int apll_con1_l8;
+ unsigned int apll_con1_l7;
+ unsigned int apll_con1_l6;
+ unsigned int apll_con1_l5;
+ unsigned int apll_con1_l4;
+ unsigned int apll_con1_l3;
+ unsigned int apll_con1_l2;
+ unsigned int apll_con1_l1;
+ unsigned char res63[0xe0];
+ unsigned int div_iem_l8;
+ unsigned int div_iem_l7;
+ unsigned int div_iem_l6;
+ unsigned int div_iem_l5;
+ unsigned int div_iem_l4;
+ unsigned int div_iem_l3;
+ unsigned int div_iem_l2;
+ unsigned int div_iem_l1;
+};
+#endif
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2010 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _EXYNOS4_CPU_H
+#define _EXYNOS4_CPU_H
+
+#define EXYNOS4_ADDR_BASE 0x10000000
+
+/* EXYNOS4 */
+#define EXYNOS4_GPIO_PART3_BASE 0x03860000
+#define EXYNOS4_PRO_ID 0x10000000
+#define EXYNOS4_POWER_BASE 0x10020000
+#define EXYNOS4_SWRESET 0x10020400
+#define EXYNOS4_CLOCK_BASE 0x10030000
+#define EXYNOS4_SYSTIMER_BASE 0x10050000
+#define EXYNOS4_WATCHDOG_BASE 0x10060000
+#define EXYNOS4_MIU_BASE 0x10600000
+#define EXYNOS4_DMC0_BASE 0x10400000
+#define EXYNOS4_DMC1_BASE 0x10410000
+#define EXYNOS4_GPIO_PART2_BASE 0x11000000
+#define EXYNOS4_GPIO_PART1_BASE 0x11400000
+#define EXYNOS4_FIMD_BASE 0x11C00000
+#define EXYNOS4_USBOTG_BASE 0x12480000
+#define EXYNOS4_MMC_BASE 0x12510000
+#define EXYNOS4_SROMC_BASE 0x12570000
+#define EXYNOS4_USBPHY_BASE 0x125B0000
+#define EXYNOS4_UART_BASE 0x13800000
+#define EXYNOS4_ADC_BASE 0x13910000
+#define EXYNOS4_PWMTIMER_BASE 0x139D0000
+#define EXYNOS4_MODEM_BASE 0x13A00000
+
+#ifndef __ASSEMBLY__
+#include <asm/io.h>
+/* CPU detection macros */
+extern unsigned int s5p_cpu_id;
+extern unsigned int s5p_cpu_rev;
+
+static inline int s5p_get_cpu_rev(void)
+{
+ return s5p_cpu_rev;
+}
+
+static inline void s5p_set_cpu_id(void)
+{
+ s5p_cpu_id = readl(EXYNOS4_PRO_ID);
+ s5p_cpu_id = (0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12));
+
+ /*
+ * 0xC200: EXYNOS4210 EVT0
+ * 0xC210: EXYNOS4210 EVT1
+ */
+ if (s5p_cpu_id == 0xC200) {
+ s5p_cpu_id |= 0x10;
+ s5p_cpu_rev = 0;
+ } else if (s5p_cpu_id == 0xC210) {
+ s5p_cpu_rev = 1;
+ }
+}
+
+#define IS_SAMSUNG_TYPE(type, id) \
+static inline int cpu_is_##type(void) \
+{ \
+ return s5p_cpu_id == id ? 1 : 0; \
+}
+
+IS_SAMSUNG_TYPE(exynos4, 0xc210)
+
+#define SAMSUNG_BASE(device, base) \
+static inline unsigned int samsung_get_base_##device(void) \
+{ \
+ if (cpu_is_exynos4()) \
+ return EXYNOS4_##base; \
+ else \
+ return 0; \
+}
+
+SAMSUNG_BASE(adc, ADC_BASE)
+SAMSUNG_BASE(clock, CLOCK_BASE)
+SAMSUNG_BASE(fimd, FIMD_BASE)
+SAMSUNG_BASE(gpio_part1, GPIO_PART1_BASE)
+SAMSUNG_BASE(gpio_part2, GPIO_PART2_BASE)
+SAMSUNG_BASE(gpio_part3, GPIO_PART3_BASE)
+SAMSUNG_BASE(pro_id, PRO_ID)
+SAMSUNG_BASE(mmc, MMC_BASE)
+SAMSUNG_BASE(modem, MODEM_BASE)
+SAMSUNG_BASE(sromc, SROMC_BASE)
+SAMSUNG_BASE(swreset, SWRESET)
+SAMSUNG_BASE(timer, PWMTIMER_BASE)
+SAMSUNG_BASE(uart, UART_BASE)
+SAMSUNG_BASE(usb_phy, USBPHY_BASE)
+SAMSUNG_BASE(usb_otg, USBOTG_BASE)
+SAMSUNG_BASE(watchdog, WATCHDOG_BASE)
+#endif
+
+#endif /* _EXYNOS4_CPU_H */
--- /dev/null
+/*
+ * (C) Copyright 2010 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_GPIO_H
+#define __ASM_ARCH_GPIO_H
+
+#ifndef __ASSEMBLY__
+struct s5p_gpio_bank {
+ unsigned int con;
+ unsigned int dat;
+ unsigned int pull;
+ unsigned int drv;
+ unsigned int pdn_con;
+ unsigned int pdn_pull;
+ unsigned char res1[8];
+};
+
+struct exynos4_gpio_part1 {
+ struct s5p_gpio_bank a0;
+ struct s5p_gpio_bank a1;
+ struct s5p_gpio_bank b;
+ struct s5p_gpio_bank c0;
+ struct s5p_gpio_bank c1;
+ struct s5p_gpio_bank d0;
+ struct s5p_gpio_bank d1;
+ struct s5p_gpio_bank e0;
+ struct s5p_gpio_bank e1;
+ struct s5p_gpio_bank e2;
+ struct s5p_gpio_bank e3;
+ struct s5p_gpio_bank e4;
+ struct s5p_gpio_bank f0;
+ struct s5p_gpio_bank f1;
+ struct s5p_gpio_bank f2;
+ struct s5p_gpio_bank f3;
+};
+
+struct exynos4_gpio_part2 {
+ struct s5p_gpio_bank j0;
+ struct s5p_gpio_bank j1;
+ struct s5p_gpio_bank k0;
+ struct s5p_gpio_bank k1;
+ struct s5p_gpio_bank k2;
+ struct s5p_gpio_bank k3;
+ struct s5p_gpio_bank l0;
+ struct s5p_gpio_bank l1;
+ struct s5p_gpio_bank l2;
+ struct s5p_gpio_bank y0;
+ struct s5p_gpio_bank y1;
+ struct s5p_gpio_bank y2;
+ struct s5p_gpio_bank y3;
+ struct s5p_gpio_bank y4;
+ struct s5p_gpio_bank y5;
+ struct s5p_gpio_bank y6;
+ struct s5p_gpio_bank res1[80];
+ struct s5p_gpio_bank x0;
+ struct s5p_gpio_bank x1;
+ struct s5p_gpio_bank x2;
+ struct s5p_gpio_bank x3;
+};
+
+struct exynos4_gpio_part3 {
+ struct s5p_gpio_bank z;
+};
+
+/* functions */
+void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg);
+void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en);
+void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio);
+void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en);
+unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio);
+void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode);
+void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode);
+void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
+
+/* GPIO pins per bank */
+#define GPIO_PER_BANK 8
+
+#define exynos4_gpio_part1_get_nr(bank, pin) \
+ ((((((unsigned int) &(((struct exynos4_gpio_part1 *) \
+ EXYNOS4_GPIO_PART1_BASE)->bank)) \
+ - EXYNOS4_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
+ * GPIO_PER_BANK) + pin)
+
+#define GPIO_PART1_MAX ((sizeof(struct exynos4_gpio_part1) \
+ / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
+
+#define exynos4_gpio_part2_get_nr(bank, pin) \
+ (((((((unsigned int) &(((struct exynos4_gpio_part2 *) \
+ EXYNOS4_GPIO_PART2_BASE)->bank)) \
+ - EXYNOS4_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
+ * GPIO_PER_BANK) + pin) + GPIO_PART1_MAX)
+
+static inline unsigned int s5p_gpio_base(int nr)
+{
+ if (nr < GPIO_PART1_MAX)
+ return EXYNOS4_GPIO_PART1_BASE;
+ else
+ return EXYNOS4_GPIO_PART2_BASE;
+
+ return 0;
+}
+
+#endif
+
+/* Pin configurations */
+#define GPIO_INPUT 0x0
+#define GPIO_OUTPUT 0x1
+#define GPIO_IRQ 0xf
+#define GPIO_FUNC(x) (x)
+
+/* Pull mode */
+#define GPIO_PULL_NONE 0x0
+#define GPIO_PULL_DOWN 0x1
+#define GPIO_PULL_UP 0x3
+
+/* Drive Strength level */
+#define GPIO_DRV_1X 0x0
+#define GPIO_DRV_3X 0x1
+#define GPIO_DRV_2X 0x2
+#define GPIO_DRV_4X 0x3
+#define GPIO_DRV_FAST 0x0
+#define GPIO_DRV_SLOW 0x1
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2009 SAMSUNG Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __ASM_ARCH_MMC_H_
+#define __ASM_ARCH_MMC_H_
+
+#ifndef __ASSEMBLY__
+struct s5p_mmc {
+ unsigned int sysad;
+ unsigned short blksize;
+ unsigned short blkcnt;
+ unsigned int argument;
+ unsigned short trnmod;
+ unsigned short cmdreg;
+ unsigned int rspreg0;
+ unsigned int rspreg1;
+ unsigned int rspreg2;
+ unsigned int rspreg3;
+ unsigned int bdata;
+ unsigned int prnsts;
+ unsigned char hostctl;
+ unsigned char pwrcon;
+ unsigned char blkgap;
+ unsigned char wakcon;
+ unsigned short clkcon;
+ unsigned char timeoutcon;
+ unsigned char swrst;
+ unsigned int norintsts; /* errintsts */
+ unsigned int norintstsen; /* errintstsen */
+ unsigned int norintsigen; /* errintsigen */
+ unsigned short acmd12errsts;
+ unsigned char res1[2];
+ unsigned int capareg;
+ unsigned char res2[4];
+ unsigned int maxcurr;
+ unsigned char res3[0x34];
+ unsigned int control2;
+ unsigned int control3;
+ unsigned char res4[4];
+ unsigned int control4;
+ unsigned char res5[0x6e];
+ unsigned short hcver;
+ unsigned char res6[0xFF00];
+};
+
+struct mmc_host {
+ struct s5p_mmc *reg;
+ unsigned int version; /* SDHCI spec. version */
+ unsigned int clock; /* Current clock (MHz) */
+ int dev_index;
+};
+
+int s5p_mmc_init(int dev_index, int bus_width);
+
+#endif /* __ASSEMBLY__ */
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2009 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARM_ARCH_PWM_H_
+#define __ASM_ARM_ARCH_PWM_H_
+
+#define PRESCALER_0 (8 - 1) /* prescaler of timer 0, 1 */
+#define PRESCALER_1 (16 - 1) /* prescaler of timer 2, 3, 4 */
+
+/* Divider MUX */
+#define MUX_DIV_1 0 /* 1/1 period */
+#define MUX_DIV_2 1 /* 1/2 period */
+#define MUX_DIV_4 2 /* 1/4 period */
+#define MUX_DIV_8 3 /* 1/8 period */
+#define MUX_DIV_16 4 /* 1/16 period */
+
+#define MUX_DIV_SHIFT(x) (x * 4)
+
+#define TCON_OFFSET(x) ((x + 1) * (!!x) << 2)
+
+#define TCON_START(x) (1 << TCON_OFFSET(x))
+#define TCON_UPDATE(x) (1 << (TCON_OFFSET(x) + 1))
+#define TCON_INVERTER(x) (1 << (TCON_OFFSET(x) + 2))
+#define TCON_AUTO_RELOAD(x) (1 << (TCON_OFFSET(x) + 3))
+#define TCON4_AUTO_RELOAD (1 << 22)
+
+#ifndef __ASSEMBLY__
+struct s5p_timer {
+ unsigned int tcfg0;
+ unsigned int tcfg1;
+ unsigned int tcon;
+ unsigned int tcntb0;
+ unsigned int tcmpb0;
+ unsigned int tcnto0;
+ unsigned int tcntb1;
+ unsigned int tcmpb1;
+ unsigned int tcnto1;
+ unsigned int tcntb2;
+ unsigned int tcmpb2;
+ unsigned int tcnto2;
+ unsigned int tcntb3;
+ unsigned int res1;
+ unsigned int tcnto3;
+ unsigned int tcntb4;
+ unsigned int tcnto4;
+ unsigned int tintcstat;
+};
+#endif /* __ASSEMBLY__ */
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2010 Samsung Electronics
+ * Naveen Krishna Ch <ch.naveen@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Note: This file contains the register description for SROMC
+ *
+ */
+
+#ifndef __ASM_ARCH_SROMC_H_
+#define __ASM_ARCH_SROMC_H_
+
+#define SROMC_DATA16_WIDTH(x) (1<<((x*4)+0))
+#define SROMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/
+ /* 1-> Byte base address*/
+#define SROMC_WAIT_ENABLE(x) (1<<((x*4)+2))
+#define SROMC_BYTE_ENABLE(x) (1<<((x*4)+3))
+
+#define SROMC_BC_TACS(x) (x << 28) /* address set-up */
+#define SROMC_BC_TCOS(x) (x << 24) /* chip selection set-up */
+#define SROMC_BC_TACC(x) (x << 16) /* access cycle */
+#define SROMC_BC_TCOH(x) (x << 12) /* chip selection hold */
+#define SROMC_BC_TAH(x) (x << 8) /* address holding time */
+#define SROMC_BC_TACP(x) (x << 4) /* page mode access cycle */
+#define SROMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */
+
+#ifndef __ASSEMBLY__
+struct s5p_sromc {
+ unsigned int bw;
+ unsigned int bc[4];
+};
+#endif /* __ASSEMBLY__ */
+
+/* Configure the Band Width and Bank Control Regs for required SROMC Bank */
+void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf);
+
+#endif /* __ASM_ARCH_SROMC_H_ */
--- /dev/null
+/*
+ * Copyright (C) 2010 Samsung Electrnoics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+u32 get_device_type(void);
+void invalidate_dcache(u32);
+void l2_cache_disable(void);
+void l2_cache_enable(void);
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Heungjun Kim <riverful.kim@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __ASM_ARCH_UART_H_
+#define __ASM_ARCH_UART_H_
+
+#ifndef __ASSEMBLY__
+/* baudrate rest value */
+union br_rest {
+ unsigned short slot; /* udivslot */
+ unsigned char value; /* ufracval */
+};
+
+struct s5p_uart {
+ unsigned int ulcon;
+ unsigned int ucon;
+ unsigned int ufcon;
+ unsigned int umcon;
+ unsigned int utrstat;
+ unsigned int uerstat;
+ unsigned int ufstat;
+ unsigned int umstat;
+ unsigned char utxh;
+ unsigned char res1[3];
+ unsigned char urxh;
+ unsigned char res2[3];
+ unsigned int ubrdiv;
+ union br_rest rest;
+ unsigned char res3[0xffd0];
+};
+
+static inline int s5p_uart_divslot(void)
+{
+ return 0;
+}
+
+#endif /* __ASSEMBLY__ */
+
+#endif
+++ /dev/null
-/*
- * Copyright (C) 2010 Samsung Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- * MyungJoo Ham <myungjoo.ham@samsung.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARM_ARCH_ADC_H_
-#define __ASM_ARM_ARCH_ADC_H_
-
-#ifndef __ASSEMBLY__
-struct s5p_adc {
- unsigned int adccon;
- unsigned int adctsc;
- unsigned int adcdly;
- unsigned int adcdat0;
- unsigned int adcdat1;
- unsigned int adcupdn;
- unsigned int adcclrint;
- unsigned int adcmux;
- unsigned int adcclrintpndnup;
-};
-#endif
-
-#endif /* __ASM_ARM_ARCH_ADC_H_ */
+++ /dev/null
-/*
- * (C) Copyright 2010 Samsung Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#ifndef __ASM_ARM_ARCH_CLK_H_
-#define __ASM_ARM_ARCH_CLK_H_
-
-#define APLL 0
-#define MPLL 1
-#define EPLL 2
-#define HPLL 3
-#define VPLL 4
-
-unsigned long get_pll_clk(int pllreg);
-unsigned long get_arm_clk(void);
-unsigned long get_pwm_clk(void);
-unsigned long get_uart_clk(int dev_index);
-void set_mmc_clk(int dev_index, unsigned int div);
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2010 Samsung Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#ifndef __ASM_ARM_ARCH_CLOCK_H_
-#define __ASM_ARM_ARCH_CLOCK_H_
-
-#ifndef __ASSEMBLY__
-struct s5pc210_clock {
- unsigned char res1[0x4200];
- unsigned int src_leftbus;
- unsigned char res2[0x1fc];
- unsigned int mux_stat_leftbus;
- unsigned char res4[0xfc];
- unsigned int div_leftbus;
- unsigned char res5[0xfc];
- unsigned int div_stat_leftbus;
- unsigned char res6[0x1fc];
- unsigned int gate_ip_leftbus;
- unsigned char res7[0x1fc];
- unsigned int clkout_leftbus;
- unsigned int clkout_leftbus_div_stat;
- unsigned char res8[0x37f8];
- unsigned int src_rightbus;
- unsigned char res9[0x1fc];
- unsigned int mux_stat_rightbus;
- unsigned char res10[0xfc];
- unsigned int div_rightbus;
- unsigned char res11[0xfc];
- unsigned int div_stat_rightbus;
- unsigned char res12[0x1fc];
- unsigned int gate_ip_rightbus;
- unsigned char res13[0x1fc];
- unsigned int clkout_rightbus;
- unsigned int clkout_rightbus_div_stat;
- unsigned char res14[0x3608];
- unsigned int epll_lock;
- unsigned char res15[0xc];
- unsigned int vpll_lock;
- unsigned char res16[0xec];
- unsigned int epll_con0;
- unsigned int epll_con1;
- unsigned char res17[0x8];
- unsigned int vpll_con0;
- unsigned int vpll_con1;
- unsigned char res18[0xe8];
- unsigned int src_top0;
- unsigned int src_top1;
- unsigned char res19[0x8];
- unsigned int src_cam;
- unsigned int src_tv;
- unsigned int src_mfc;
- unsigned int src_g3d;
- unsigned int src_image;
- unsigned int src_lcd0;
- unsigned int src_lcd1;
- unsigned int src_maudio;
- unsigned int src_fsys;
- unsigned char res20[0xc];
- unsigned int src_peril0;
- unsigned int src_peril1;
- unsigned char res21[0xb8];
- unsigned int src_mask_top;
- unsigned char res22[0xc];
- unsigned int src_mask_cam;
- unsigned int src_mask_tv;
- unsigned char res23[0xc];
- unsigned int src_mask_lcd0;
- unsigned int src_mask_lcd1;
- unsigned int src_mask_maudio;
- unsigned int src_mask_fsys;
- unsigned char res24[0xc];
- unsigned int src_mask_peril0;
- unsigned int src_mask_peril1;
- unsigned char res25[0xb8];
- unsigned int mux_stat_top;
- unsigned char res26[0x14];
- unsigned int mux_stat_mfc;
- unsigned int mux_stat_g3d;
- unsigned int mux_stat_image;
- unsigned char res27[0xdc];
- unsigned int div_top;
- unsigned char res28[0xc];
- unsigned int div_cam;
- unsigned int div_tv;
- unsigned int div_mfc;
- unsigned int div_g3d;
- unsigned int div_image;
- unsigned int div_lcd0;
- unsigned int div_lcd1;
- unsigned int div_maudio;
- unsigned int div_fsys0;
- unsigned int div_fsys1;
- unsigned int div_fsys2;
- unsigned int div_fsys3;
- unsigned int div_peril0;
- unsigned int div_peril1;
- unsigned int div_peril2;
- unsigned int div_peril3;
- unsigned int div_peril4;
- unsigned int div_peril5;
- unsigned char res29[0x18];
- unsigned int div2_ratio;
- unsigned char res30[0x8c];
- unsigned int div_stat_top;
- unsigned char res31[0xc];
- unsigned int div_stat_cam;
- unsigned int div_stat_tv;
- unsigned int div_stat_mfc;
- unsigned int div_stat_g3d;
- unsigned int div_stat_image;
- unsigned int div_stat_lcd0;
- unsigned int div_stat_lcd1;
- unsigned int div_stat_maudio;
- unsigned int div_stat_fsys0;
- unsigned int div_stat_fsys1;
- unsigned int div_stat_fsys2;
- unsigned int div_stat_fsys3;
- unsigned int div_stat_peril0;
- unsigned int div_stat_peril1;
- unsigned int div_stat_peril2;
- unsigned int div_stat_peril3;
- unsigned int div_stat_peril4;
- unsigned int div_stat_peril5;
- unsigned char res32[0x18];
- unsigned int div2_stat;
- unsigned char res33[0x29c];
- unsigned int gate_ip_cam;
- unsigned int gate_ip_tv;
- unsigned int gate_ip_mfc;
- unsigned int gate_ip_g3d;
- unsigned int gate_ip_image;
- unsigned int gate_ip_lcd0;
- unsigned int gate_ip_lcd1;
- unsigned char res34[0x4];
- unsigned int gate_ip_fsys;
- unsigned char res35[0x8];
- unsigned int gate_ip_gps;
- unsigned int gate_ip_peril;
- unsigned char res36[0xc];
- unsigned int gate_ip_perir;
- unsigned char res37[0xc];
- unsigned int gate_block;
- unsigned char res38[0x8c];
- unsigned int clkout_cmu_top;
- unsigned int clkout_cmu_top_div_stat;
- unsigned char res39[0x37f8];
- unsigned int src_dmc;
- unsigned char res40[0xfc];
- unsigned int src_mask_dmc;
- unsigned char res41[0xfc];
- unsigned int mux_stat_dmc;
- unsigned char res42[0xfc];
- unsigned int div_dmc0;
- unsigned int div_dmc1;
- unsigned char res43[0xf8];
- unsigned int div_stat_dmc0;
- unsigned int div_stat_dmc1;
- unsigned char res44[0x2f8];
- unsigned int gate_ip_dmc;
- unsigned char res45[0xfc];
- unsigned int clkout_cmu_dmc;
- unsigned int clkout_cmu_dmc_div_stat;
- unsigned char res46[0x5f8];
- unsigned int dcgidx_map0;
- unsigned int dcgidx_map1;
- unsigned int dcgidx_map2;
- unsigned char res47[0x14];
- unsigned int dcgperf_map0;
- unsigned int dcgperf_map1;
- unsigned char res48[0x18];
- unsigned int dvcidx_map;
- unsigned char res49[0x1c];
- unsigned int freq_cpu;
- unsigned int freq_dpm;
- unsigned char res50[0x18];
- unsigned int dvsemclk_en;
- unsigned int maxperf;
- unsigned char res51[0x2f78];
- unsigned int apll_lock;
- unsigned char res52[0x4];
- unsigned int mpll_lock;
- unsigned char res53[0xf4];
- unsigned int apll_con0;
- unsigned int apll_con1;
- unsigned int mpll_con0;
- unsigned int mpll_con1;
- unsigned char res54[0xf0];
- unsigned int src_cpu;
- unsigned char res55[0x1fc];
- unsigned int mux_stat_cpu;
- unsigned char res56[0xfc];
- unsigned int div_cpu0;
- unsigned int div_cpu1;
- unsigned char res57[0xf8];
- unsigned int div_stat_cpu0;
- unsigned int div_stat_cpu1;
- unsigned char res58[0x3f8];
- unsigned int clkout_cmu_cpu;
- unsigned int clkout_cmu_cpu_div_stat;
- unsigned char res59[0x5f8];
- unsigned int armclk_stopctrl;
- unsigned int atclk_stopctrl;
- unsigned char res60[0x8];
- unsigned int parityfail_status;
- unsigned int parityfail_clear;
- unsigned char res61[0xe8];
- unsigned int apll_con0_l8;
- unsigned int apll_con0_l7;
- unsigned int apll_con0_l6;
- unsigned int apll_con0_l5;
- unsigned int apll_con0_l4;
- unsigned int apll_con0_l3;
- unsigned int apll_con0_l2;
- unsigned int apll_con0_l1;
- unsigned int iem_control;
- unsigned char res62[0xdc];
- unsigned int apll_con1_l8;
- unsigned int apll_con1_l7;
- unsigned int apll_con1_l6;
- unsigned int apll_con1_l5;
- unsigned int apll_con1_l4;
- unsigned int apll_con1_l3;
- unsigned int apll_con1_l2;
- unsigned int apll_con1_l1;
- unsigned char res63[0xe0];
- unsigned int div_iem_l8;
- unsigned int div_iem_l7;
- unsigned int div_iem_l6;
- unsigned int div_iem_l5;
- unsigned int div_iem_l4;
- unsigned int div_iem_l3;
- unsigned int div_iem_l2;
- unsigned int div_iem_l1;
-};
-#endif
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2010 Samsung Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#ifndef _S5PC2XX_CPU_H
-#define _S5PC2XX_CPU_H
-
-#define S5PC2XX_ADDR_BASE 0x10000000
-
-/* S5PC210 */
-#define S5PC210_GPIO_PART3_BASE 0x03860000
-#define S5PC210_PRO_ID 0x10000000
-#define S5PC210_POWER_BASE 0x10020000
-#define S5PC210_SWRESET 0x10020400
-#define S5PC210_CLOCK_BASE 0x10030000
-#define S5PC210_SYSTIMER_BASE 0x10050000
-#define S5PC210_WATCHDOG_BASE 0x10060000
-#define S5PC210_MIU_BASE 0x10600000
-#define S5PC210_DMC0_BASE 0x10400000
-#define S5PC210_DMC1_BASE 0x10410000
-#define S5PC210_GPIO_PART2_BASE 0x11000000
-#define S5PC210_GPIO_PART1_BASE 0x11400000
-#define S5PC210_FIMD_BASE 0x11C00000
-#define S5PC210_USBOTG_BASE 0x12480000
-#define S5PC210_MMC_BASE 0x12510000
-#define S5PC210_SROMC_BASE 0x12570000
-#define S5PC210_USBPHY_BASE 0x125B0000
-#define S5PC210_UART_BASE 0x13800000
-#define S5PC210_ADC_BASE 0x13910000
-#define S5PC210_PWMTIMER_BASE 0x139D0000
-#define S5PC210_MODEM_BASE 0x13A00000
-
-#ifndef __ASSEMBLY__
-#include <asm/io.h>
-/* CPU detection macros */
-extern unsigned int s5p_cpu_id;
-extern unsigned int s5p_cpu_rev;
-
-static inline int s5p_get_cpu_rev(void)
-{
- return s5p_cpu_rev;
-}
-
-static inline void s5p_set_cpu_id(void)
-{
- s5p_cpu_id = readl(S5PC210_PRO_ID);
- s5p_cpu_id = (0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12));
-
- /*
- * 0xC200: S5PC210 EVT0
- * 0xC210: S5PC210 EVT1
- */
- if (s5p_cpu_id == 0xC200) {
- s5p_cpu_id |= 0x10;
- s5p_cpu_rev = 0;
- } else if (s5p_cpu_id == 0xC210) {
- s5p_cpu_rev = 1;
- }
-}
-
-#define IS_SAMSUNG_TYPE(type, id) \
-static inline int cpu_is_##type(void) \
-{ \
- return s5p_cpu_id == id ? 1 : 0; \
-}
-
-IS_SAMSUNG_TYPE(s5pc210, 0xc210)
-
-#define SAMSUNG_BASE(device, base) \
-static inline unsigned int samsung_get_base_##device(void) \
-{ \
- if (cpu_is_s5pc210()) \
- return S5PC210_##base; \
- else \
- return 0; \
-}
-
-SAMSUNG_BASE(adc, ADC_BASE)
-SAMSUNG_BASE(clock, CLOCK_BASE)
-SAMSUNG_BASE(fimd, FIMD_BASE)
-SAMSUNG_BASE(gpio_part1, GPIO_PART1_BASE)
-SAMSUNG_BASE(gpio_part2, GPIO_PART2_BASE)
-SAMSUNG_BASE(gpio_part3, GPIO_PART3_BASE)
-SAMSUNG_BASE(pro_id, PRO_ID)
-SAMSUNG_BASE(mmc, MMC_BASE)
-SAMSUNG_BASE(modem, MODEM_BASE)
-SAMSUNG_BASE(sromc, SROMC_BASE)
-SAMSUNG_BASE(swreset, SWRESET)
-SAMSUNG_BASE(timer, PWMTIMER_BASE)
-SAMSUNG_BASE(uart, UART_BASE)
-SAMSUNG_BASE(usb_phy, USBPHY_BASE)
-SAMSUNG_BASE(usb_otg, USBOTG_BASE)
-SAMSUNG_BASE(watchdog, WATCHDOG_BASE)
-#endif
-
-#endif /* _S5PC2XX_CPU_H */
+++ /dev/null
-/*
- * (C) Copyright 2010 Samsung Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_GPIO_H
-#define __ASM_ARCH_GPIO_H
-
-#ifndef __ASSEMBLY__
-struct s5p_gpio_bank {
- unsigned int con;
- unsigned int dat;
- unsigned int pull;
- unsigned int drv;
- unsigned int pdn_con;
- unsigned int pdn_pull;
- unsigned char res1[8];
-};
-
-struct s5pc210_gpio_part1 {
- struct s5p_gpio_bank a0;
- struct s5p_gpio_bank a1;
- struct s5p_gpio_bank b;
- struct s5p_gpio_bank c0;
- struct s5p_gpio_bank c1;
- struct s5p_gpio_bank d0;
- struct s5p_gpio_bank d1;
- struct s5p_gpio_bank e0;
- struct s5p_gpio_bank e1;
- struct s5p_gpio_bank e2;
- struct s5p_gpio_bank e3;
- struct s5p_gpio_bank e4;
- struct s5p_gpio_bank f0;
- struct s5p_gpio_bank f1;
- struct s5p_gpio_bank f2;
- struct s5p_gpio_bank f3;
-};
-
-struct s5pc210_gpio_part2 {
- struct s5p_gpio_bank j0;
- struct s5p_gpio_bank j1;
- struct s5p_gpio_bank k0;
- struct s5p_gpio_bank k1;
- struct s5p_gpio_bank k2;
- struct s5p_gpio_bank k3;
- struct s5p_gpio_bank l0;
- struct s5p_gpio_bank l1;
- struct s5p_gpio_bank l2;
- struct s5p_gpio_bank y0;
- struct s5p_gpio_bank y1;
- struct s5p_gpio_bank y2;
- struct s5p_gpio_bank y3;
- struct s5p_gpio_bank y4;
- struct s5p_gpio_bank y5;
- struct s5p_gpio_bank y6;
- struct s5p_gpio_bank res1[80];
- struct s5p_gpio_bank x0;
- struct s5p_gpio_bank x1;
- struct s5p_gpio_bank x2;
- struct s5p_gpio_bank x3;
-};
-
-struct s5pc210_gpio_part3 {
- struct s5p_gpio_bank z;
-};
-
-/* functions */
-void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg);
-void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en);
-void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio);
-void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en);
-unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio);
-void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode);
-void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode);
-void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
-
-/* GPIO pins per bank */
-#define GPIO_PER_BANK 8
-
-#define s5pc210_gpio_part1_get_nr(bank, pin) \
- ((((((unsigned int) &(((struct s5pc210_gpio_part1 *) \
- S5PC210_GPIO_PART1_BASE)->bank)) \
- - S5PC210_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
- * GPIO_PER_BANK) + pin)
-
-#define GPIO_PART1_MAX ((sizeof(struct s5pc210_gpio_part1) \
- / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
-
-#define s5pc210_gpio_part2_get_nr(bank, pin) \
- (((((((unsigned int) &(((struct s5pc210_gpio_part2 *) \
- S5PC210_GPIO_PART2_BASE)->bank)) \
- - S5PC210_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
- * GPIO_PER_BANK) + pin) + GPIO_PART1_MAX)
-
-static inline unsigned int s5p_gpio_base(int nr)
-{
- if (nr < GPIO_PART1_MAX)
- return S5PC210_GPIO_PART1_BASE;
- else
- return S5PC210_GPIO_PART2_BASE;
-
- return 0;
-}
-
-#endif
-
-/* Pin configurations */
-#define GPIO_INPUT 0x0
-#define GPIO_OUTPUT 0x1
-#define GPIO_IRQ 0xf
-#define GPIO_FUNC(x) (x)
-
-/* Pull mode */
-#define GPIO_PULL_NONE 0x0
-#define GPIO_PULL_DOWN 0x1
-#define GPIO_PULL_UP 0x3
-
-/* Drive Strength level */
-#define GPIO_DRV_1X 0x0
-#define GPIO_DRV_3X 0x1
-#define GPIO_DRV_2X 0x2
-#define GPIO_DRV_4X 0x3
-#define GPIO_DRV_FAST 0x0
-#define GPIO_DRV_SLOW 0x1
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2009 SAMSUNG Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- */
-
-#ifndef __ASM_ARCH_MMC_H_
-#define __ASM_ARCH_MMC_H_
-
-#ifndef __ASSEMBLY__
-struct s5p_mmc {
- unsigned int sysad;
- unsigned short blksize;
- unsigned short blkcnt;
- unsigned int argument;
- unsigned short trnmod;
- unsigned short cmdreg;
- unsigned int rspreg0;
- unsigned int rspreg1;
- unsigned int rspreg2;
- unsigned int rspreg3;
- unsigned int bdata;
- unsigned int prnsts;
- unsigned char hostctl;
- unsigned char pwrcon;
- unsigned char blkgap;
- unsigned char wakcon;
- unsigned short clkcon;
- unsigned char timeoutcon;
- unsigned char swrst;
- unsigned int norintsts; /* errintsts */
- unsigned int norintstsen; /* errintstsen */
- unsigned int norintsigen; /* errintsigen */
- unsigned short acmd12errsts;
- unsigned char res1[2];
- unsigned int capareg;
- unsigned char res2[4];
- unsigned int maxcurr;
- unsigned char res3[0x34];
- unsigned int control2;
- unsigned int control3;
- unsigned char res4[4];
- unsigned int control4;
- unsigned char res5[0x6e];
- unsigned short hcver;
- unsigned char res6[0xFF00];
-};
-
-struct mmc_host {
- struct s5p_mmc *reg;
- unsigned int version; /* SDHCI spec. version */
- unsigned int clock; /* Current clock (MHz) */
- int dev_index;
-};
-
-int s5p_mmc_init(int dev_index, int bus_width);
-
-#endif /* __ASSEMBLY__ */
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2009 Samsung Electronics
- * Kyungmin Park <kyungmin.park@samsung.com>
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARM_ARCH_PWM_H_
-#define __ASM_ARM_ARCH_PWM_H_
-
-#define PRESCALER_0 (8 - 1) /* prescaler of timer 0, 1 */
-#define PRESCALER_1 (16 - 1) /* prescaler of timer 2, 3, 4 */
-
-/* Divider MUX */
-#define MUX_DIV_1 0 /* 1/1 period */
-#define MUX_DIV_2 1 /* 1/2 period */
-#define MUX_DIV_4 2 /* 1/4 period */
-#define MUX_DIV_8 3 /* 1/8 period */
-#define MUX_DIV_16 4 /* 1/16 period */
-
-#define MUX_DIV_SHIFT(x) (x * 4)
-
-#define TCON_OFFSET(x) ((x + 1) * (!!x) << 2)
-
-#define TCON_START(x) (1 << TCON_OFFSET(x))
-#define TCON_UPDATE(x) (1 << (TCON_OFFSET(x) + 1))
-#define TCON_INVERTER(x) (1 << (TCON_OFFSET(x) + 2))
-#define TCON_AUTO_RELOAD(x) (1 << (TCON_OFFSET(x) + 3))
-#define TCON4_AUTO_RELOAD (1 << 22)
-
-#ifndef __ASSEMBLY__
-struct s5p_timer {
- unsigned int tcfg0;
- unsigned int tcfg1;
- unsigned int tcon;
- unsigned int tcntb0;
- unsigned int tcmpb0;
- unsigned int tcnto0;
- unsigned int tcntb1;
- unsigned int tcmpb1;
- unsigned int tcnto1;
- unsigned int tcntb2;
- unsigned int tcmpb2;
- unsigned int tcnto2;
- unsigned int tcntb3;
- unsigned int res1;
- unsigned int tcnto3;
- unsigned int tcntb4;
- unsigned int tcnto4;
- unsigned int tintcstat;
-};
-#endif /* __ASSEMBLY__ */
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2010 Samsung Electronics
- * Naveen Krishna Ch <ch.naveen@samsung.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * Note: This file contains the register description for SROMC
- *
- */
-
-#ifndef __ASM_ARCH_SROMC_H_
-#define __ASM_ARCH_SROMC_H_
-
-#define SROMC_DATA16_WIDTH(x) (1<<((x*4)+0))
-#define SROMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/
- /* 1-> Byte base address*/
-#define SROMC_WAIT_ENABLE(x) (1<<((x*4)+2))
-#define SROMC_BYTE_ENABLE(x) (1<<((x*4)+3))
-
-#define SROMC_BC_TACS(x) (x << 28) /* address set-up */
-#define SROMC_BC_TCOS(x) (x << 24) /* chip selection set-up */
-#define SROMC_BC_TACC(x) (x << 16) /* access cycle */
-#define SROMC_BC_TCOH(x) (x << 12) /* chip selection hold */
-#define SROMC_BC_TAH(x) (x << 8) /* address holding time */
-#define SROMC_BC_TACP(x) (x << 4) /* page mode access cycle */
-#define SROMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */
-
-#ifndef __ASSEMBLY__
-struct s5p_sromc {
- unsigned int bw;
- unsigned int bc[4];
-};
-#endif /* __ASSEMBLY__ */
-
-/* Configure the Band Width and Bank Control Regs for required SROMC Bank */
-void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf);
-
-#endif /* __ASM_ARCH_SROMC_H_ */
+++ /dev/null
-/*
- * Copyright (C) 2010 Samsung Electrnoics
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _SYS_PROTO_H_
-#define _SYS_PROTO_H_
-
-u32 get_device_type(void);
-void invalidate_dcache(u32);
-void l2_cache_disable(void);
-void l2_cache_enable(void);
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2009 Samsung Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- * Heungjun Kim <riverful.kim@samsung.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#ifndef __ASM_ARCH_UART_H_
-#define __ASM_ARCH_UART_H_
-
-#ifndef __ASSEMBLY__
-/* baudrate rest value */
-union br_rest {
- unsigned short slot; /* udivslot */
- unsigned char value; /* ufracval */
-};
-
-struct s5p_uart {
- unsigned int ulcon;
- unsigned int ucon;
- unsigned int ufcon;
- unsigned int umcon;
- unsigned int utrstat;
- unsigned int uerstat;
- unsigned int ufstat;
- unsigned int umstat;
- unsigned char utxh;
- unsigned char res1[3];
- unsigned char urxh;
- unsigned char res2[3];
- unsigned int ubrdiv;
- union br_rest rest;
- unsigned char res3[0xffd0];
-};
-
-static inline int s5p_uart_divslot(void)
-{
- return 0;
-}
-
-#endif /* __ASSEMBLY__ */
-
-#endif
/*
- * Lowlevel setup for ORIGEN board based on S5PV310
+ * Lowlevel setup for ORIGEN board based on EXYNOS4210
*
* Copyright (C) 2011 Samsung Electronics
*
/* r5 has always zero */
mov r5, #0
- ldr r7, =S5PC210_GPIO_PART1_BASE
- ldr r6, =S5PC210_GPIO_PART2_BASE
+ ldr r7, =EXYNOS4_GPIO_PART1_BASE
+ ldr r6, =EXYNOS4_GPIO_PART2_BASE
/* check reset status */
- ldr r0, =(S5PC210_POWER_BASE + INFORM1_OFFSET)
+ ldr r0, =(EXYNOS4_POWER_BASE + INFORM1_OFFSET)
ldr r1, [r0]
/* AFTR wakeup reset */
exit_wakeup:
/* Load return address and jump to kernel */
- ldr r0, =(S5PC210_POWER_BASE + INFORM0_OFFSET)
+ ldr r0, =(EXYNOS4_POWER_BASE + INFORM0_OFFSET)
- /* r1 = physical address of s5pc210_cpu_resume function */
+ /* r1 = physical address of exynos4210_cpu_resume function */
ldr r1, [r0]
/* Jump to kernel*/
*/
system_clock_init:
push {lr}
- ldr r0, =S5PC210_CLOCK_BASE
+ ldr r0, =EXYNOS4_CLOCK_BASE
/* APLL(1), MPLL(1), CORE(0), HPM(0) */
ldr r1, =CLK_SRC_CPU_VAL
/* setup UART0-UART3 GPIOs (part1) */
mov r0, r7
- ldr r1, =S5PC210_GPIO_A0_CON_VAL
- str r1, [r0, #S5PC210_GPIO_A0_CON_OFFSET]
- ldr r1, =S5PC210_GPIO_A1_CON_VAL
- str r1, [r0, #S5PC210_GPIO_A1_CON_OFFSET]
+ ldr r1, =EXYNOS4_GPIO_A0_CON_VAL
+ str r1, [r0, #EXYNOS4_GPIO_A0_CON_OFFSET]
+ ldr r1, =EXYNOS4_GPIO_A1_CON_VAL
+ str r1, [r0, #EXYNOS4_GPIO_A1_CON_OFFSET]
- ldr r0, =S5PC210_UART_BASE
- add r0, r0, #S5PC210_DEFAULT_UART_OFFSET
+ ldr r0, =EXYNOS4_UART_BASE
+ add r0, r0, #EXYNOS4_DEFAULT_UART_OFFSET
ldr r1, =ULCON_VAL
str r1, [r0, #ULCON_OFFSET]
/*
- * Memory setup for ORIGEN board based on S5PV310
+ * Memory setup for ORIGEN board based on EXYNOS4210
*
* Copyright (C) 2011 Samsung Electronics
*
str r1, [r0]
#ifdef SET_MIU
- ldr r0, =S5PC210_MIU_BASE
+ ldr r0, =EXYNOS4_MIU_BASE
/* Interleave: 2Bit, Interleave_bit1: 0x21, Interleave_bit2: 0x7 */
ldr r1, =0x20001507
str r1, [r0, #APB_SFR_INTERLEAVE_CONF_OFFSET]
str r1, [r0, #APB_SFR_ARBRITATION_CONF_OFFSET]
#endif
/* DREX0 */
- ldr r0, =S5PC210_DMC0_BASE
+ ldr r0, =EXYNOS4_DMC0_BASE
/*
* DLL Parameter Setting:
bne 8b
/* DREX1 */
- ldr r0, =S5PC210_DMC1_BASE @0x10410000
+ ldr r0, =EXYNOS4_DMC1_BASE @0x10410000
/*
* DLL Parameter Setting:
bne 8b
/* turn on DREX0, DREX1 */
- ldr r0, =S5PC210_DMC0_BASE
+ ldr r0, =EXYNOS4_DMC0_BASE
ldr r1, =0x0FFF303a
str r1, [r0, #DMC_CONCONTROL]
- ldr r0, =S5PC210_DMC1_BASE
+ ldr r0, =EXYNOS4_DMC1_BASE
ldr r1, =0x0FFF303a
str r1, [r0, #DMC_CONCONTROL]
#include <asm/arch/mmc.h>
DECLARE_GLOBAL_DATA_PTR;
-struct s5pc210_gpio_part1 *gpio1;
-struct s5pc210_gpio_part2 *gpio2;
+struct exynos4_gpio_part1 *gpio1;
+struct exynos4_gpio_part2 *gpio2;
int board_init(void)
{
- gpio1 = (struct s5pc210_gpio_part1 *) S5PC210_GPIO_PART1_BASE;
- gpio2 = (struct s5pc210_gpio_part2 *) S5PC210_GPIO_PART2_BASE;
+ gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE;
+ gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE;
gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
return 0;
#define INFORM1_OFFSET 0x804
/* GPIO Offsets for UART: GPIO Contol Register */
-#define S5PC210_GPIO_A0_CON_OFFSET 0x00
-#define S5PC210_GPIO_A1_CON_OFFSET 0x20
+#define EXYNOS4_GPIO_A0_CON_OFFSET 0x00
+#define EXYNOS4_GPIO_A1_CON_OFFSET 0x20
/* UART Register offsets */
#define ULCON_OFFSET 0x00
* UART GPIO_A0/GPIO_A1 Control Register Value
* 0x2: UART Function
*/
-#define S5PC210_GPIO_A0_CON_VAL 0x22222222
-#define S5PC210_GPIO_A1_CON_VAL 0x222222
+#define EXYNOS4_GPIO_A0_CON_VAL 0x22222222
+#define EXYNOS4_GPIO_A1_CON_VAL 0x222222
/* ULCON: UART Line Control Value 8N1 */
#define WORD_LEN_5_BIT 0x00
/*
- * Lowlevel setup for SMDKV310 board based on S5PC210
+ * Lowlevel setup for SMDKV310 board based on EXYNOS4210
*
* Copyright (C) 2011 Samsung Electronics
*
/* r5 has always zero */
mov r5, #0
- ldr r7, =S5PC210_GPIO_PART1_BASE
- ldr r6, =S5PC210_GPIO_PART2_BASE
+ ldr r7, =EXYNOS4_GPIO_PART1_BASE
+ ldr r6, =EXYNOS4_GPIO_PART2_BASE
/* check reset status */
- ldr r0, =(S5PC210_POWER_BASE + 0x81C) @ INFORM7
+ ldr r0, =(EXYNOS4_POWER_BASE + 0x81C) @ INFORM7
ldr r1, [r0]
/* AFTR wakeup reset */
exit_wakeup:
/* Load return address and jump to kernel */
- ldr r0, =(S5PC210_POWER_BASE + 0x800) @ INFORM0
+ ldr r0, =(EXYNOS4_POWER_BASE + 0x800) @ INFORM0
- /* r1 = physical address of s5pc210_cpu_resume function */
+ /* r1 = physical address of exynos4210_cpu_resume function */
ldr r1, [r0]
/* Jump to kernel*/
*/
system_clock_init:
push {lr}
- ldr r0, =S5PC210_CLOCK_BASE
+ ldr r0, =EXYNOS4_CLOCK_BASE
/* APLL(1), MPLL(1), CORE(0), HPM(0) */
ldr r1, =0x0101
/* setup UART0-UART3 GPIOs (part1) */
mov r0, r7
ldr r1, =0x22222222
- str r1, [r0, #0x00] @ S5PC210_GPIO_A0_OFFSET
+ str r1, [r0, #0x00] @ EXYNOS4_GPIO_A0_OFFSET
ldr r1, =0x00222222
- str r1, [r0, #0x20] @ S5PC210_GPIO_A1_OFFSET
+ str r1, [r0, #0x20] @ EXYNOS4_GPIO_A1_OFFSET
- ldr r0, =S5PC210_UART_BASE
- add r0, r0, #S5PC210_DEFAULT_UART_OFFSET
+ ldr r0, =EXYNOS4_UART_BASE
+ add r0, r0, #EXYNOS4_DEFAULT_UART_OFFSET
ldr r1, =0x3C5
str r1, [r0, #0x4]
/*
- * Memory setup for SMDKV310 board based on S5PC210
+ * Memory setup for SMDKV310 board based on EXYNOS4210
*
* Copyright (C) 2011 Samsung Electronics
*
str r1, [r0]
#ifdef SET_MIU
- ldr r0, =S5PC210_MIU_BASE @0x10600000
+ ldr r0, =EXYNOS4_MIU_BASE @0x10600000
#ifdef CONFIG_MIU_1BIT_INTERLEAVED
ldr r1, =0x0000000c
str r1, [r0, #0x400] @MIU_INTLV_CONFIG
#endif
#endif
/* DREX0 */
- ldr r0, =S5PC210_DMC0_BASE @0x10400000
+ ldr r0, =EXYNOS4_DMC0_BASE @0x10400000
ldr r1, =0xe0000086
str r1, [r0, #0x1C] @DMC_PHYCONTROL1
bne 8b
/* DREX1 */
- ldr r0, =S5PC210_DMC1_BASE @0x10410000
+ ldr r0, =EXYNOS4_DMC1_BASE @0x10410000
ldr r1, =0xe0000086
str r1, [r0, #0x1C] @DMC_PHYCONTROL1
#include <asm/arch/sromc.h>
DECLARE_GLOBAL_DATA_PTR;
-struct s5pc210_gpio_part1 *gpio1;
-struct s5pc210_gpio_part2 *gpio2;
+struct exynos4_gpio_part1 *gpio1;
+struct exynos4_gpio_part2 *gpio2;
static void smc9115_pre_init(void)
{
int board_init(void)
{
- gpio1 = (struct s5pc210_gpio_part1 *) S5PC210_GPIO_PART1_BASE;
- gpio2 = (struct s5pc210_gpio_part2 *) S5PC210_GPIO_PART2_BASE;
+ gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE;
+ gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE;
smc9115_pre_init();
/*
- * Lowlevel setup for universal board based on S5PC210
+ * Lowlevel setup for universal board based on EXYNOS4210
*
* Copyright (C) 2010 Samsung Electronics
* Kyungmin Park <kyungmin.park@samsung.com>
/* r5 has always zero */
mov r5, #0
- ldr r7, =S5PC210_GPIO_PART1_BASE
- ldr r6, =S5PC210_GPIO_PART2_BASE
+ ldr r7, =EXYNOS4_GPIO_PART1_BASE
+ ldr r6, =EXYNOS4_GPIO_PART2_BASE
/* System Timer */
- ldr r0, =S5PC210_SYSTIMER_BASE
+ ldr r0, =EXYNOS4_SYSTIMER_BASE
ldr r1, =0x5000
str r1, [r0, #0x0]
ldr r1, =0xffffffff
/* PMIC manual reset */
/* nPOWER: XEINT_23: GPX2[7] */
- add r0, r6, #0xC40 @ S5PC210_GPIO_X2_OFFSET
+ add r0, r6, #0xC40 @ EXYNOS4_GPIO_X2_OFFSET
ldr r1, [r0, #0x0]
bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit
orr r1, r1, #(0x1 << 28) @ Output
bl system_clock_init
/* Disable Watchdog */
- ldr r0, =S5PC210_WATCHDOG_BASE @0x10060000
+ ldr r0, =EXYNOS4_WATCHDOG_BASE @0x10060000
str r5, [r0]
/* UART */
*/
mov r0, r7
ldr r1, =0x22222222
- str r1, [r0, #0x00] @ S5PC210_GPIO_A0_OFFSET
+ str r1, [r0, #0x00] @ EXYNOS4_GPIO_A0_OFFSET
ldr r1, =0x00223322
- str r1, [r0, #0x20] @ S5PC210_GPIO_A1_OFFSET
+ str r1, [r0, #0x20] @ EXYNOS4_GPIO_A1_OFFSET
- /* UART_SEL GPY4[7] (part2) at S5PC210 */
- add r0, r6, #0x1A0 @ S5PC210_GPIO_Y4_OFFSET
+ /* UART_SEL GPY4[7] (part2) at EXYNOS4 */
+ add r0, r6, #0x1A0 @ EXYNOS4_GPIO_Y4_OFFSET
ldr r1, [r0, #0x0]
bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit
orr r1, r1, #(0x1 << 28)
nop
system_clock_init:
- ldr r0, =S5PC210_CLOCK_BASE
+ ldr r0, =EXYNOS4_CLOCK_BASE
/* APLL(1), MPLL(1), CORE(0), HPM(0) */
ldr r1, =0x0101
nop
system_power_init:
- ldr r0, =S5PC210_POWER_BASE @ 0x10020000
+ ldr r0, =EXYNOS4_POWER_BASE @ 0x10020000
ldr r2, =0x330C @ PS_HOLD_CONTROL
ldr r1, [r0, r2]
DECLARE_GLOBAL_DATA_PTR;
-struct s5pc210_gpio_part1 *gpio1;
-struct s5pc210_gpio_part2 *gpio2;
+struct exynos4_gpio_part1 *gpio1;
+struct exynos4_gpio_part2 *gpio2;
unsigned int board_rev;
u32 get_board_rev(void)
int board_init(void)
{
- gpio1 = (struct s5pc210_gpio_part1 *) S5PC210_GPIO_PART1_BASE;
- gpio2 = (struct s5pc210_gpio_part2 *) S5PC210_GPIO_PART2_BASE;
+ gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE;
+ gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE;
gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210;
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
omap5_evm arm armv7 omap5_evm ti omap5
s5p_goni arm armv7 goni samsung s5pc1xx
smdkc100 arm armv7 smdkc100 samsung s5pc1xx
-origen arm armv7 origen samsung s5pc2xx
-s5pc210_universal arm armv7 universal_c210 samsung s5pc2xx
-smdkv310 arm armv7 smdkv310 samsung s5pc2xx
+origen arm armv7 origen samsung exynos
+s5pc210_universal arm armv7 universal_c210 samsung exynos
+smdkv310 arm armv7 smdkv310 samsung exynos
harmony arm armv7 harmony nvidia tegra2
seaboard arm armv7 seaboard nvidia tegra2
ventana arm armv7 ventana nvidia tegra2
/*
* Copyright (C) 2011 Samsung Electronics
*
- * Configuration settings for the SAMSUNG ORIGEN (S5PV310) board.
+ * Configuration settings for the SAMSUNG ORIGEN (EXYNOS4210) board.
*
* See file CREDITS for list of people who contributed to this
* project.
/* High Level Configuration Options */
#define CONFIG_SAMSUNG 1 /* SAMSUNG core */
#define CONFIG_S5P 1 /* S5P Family */
-#define CONFIG_S5PC210 1 /* which is in a S5PC210 SoC */
+#define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */
#define CONFIG_ORIGEN 1 /* working with ORIGEN*/
#include <asm/arch/cpu.h> /* get chip and board defs */
#define CONFIG_SERIAL_MULTI 1
#define CONFIG_SERIAL2 1 /* use SERIAL 2 */
#define CONFIG_BAUDRATE 115200
-#define S5PC210_DEFAULT_UART_OFFSET 0x020000
+#define EXYNOS4_DEFAULT_UART_OFFSET 0x020000
/* SD/MMC configuration */
#define CONFIG_GENERIC_MMC 1
* Copyright (C) 2010 Samsung Electronics
* Minkyu Kang <mk7.kang@samsung.com>
*
- * Configuation settings for the SAMSUNG Universal (s5pc100) board.
+ * Configuation settings for the SAMSUNG Universal (EXYNOS4210) board.
*
* See file CREDITS for list of people who contributed to this
* project.
*/
#define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */
#define CONFIG_S5P 1 /* which is in a S5P Family */
-#define CONFIG_S5PC210 1 /* which is in a S5PC210 */
+#define CONFIG_EXYNOS4210 1 /* which is in a EXYNOS4210 */
#define CONFIG_UNIVERSAL 1 /* working with Universal */
#include <asm/arch/cpu.h> /* get chip and board defs */
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define CONFIG_SYS_TEXT_BASE 0x44800000
-/* input clock of PLL: Universal has 24MHz input clock at S5PC210 */
+/* input clock of PLL: Universal has 24MHz input clock at EXYNOS4210 */
#define CONFIG_SYS_CLK_FREQ_C210 24000000
#define CONFIG_SETUP_MEMORY_TAGS
/*
* I2C Settings
*/
-#define CONFIG_SOFT_I2C_GPIO_SCL s5pc210_gpio_part1_get_nr(b, 7)
-#define CONFIG_SOFT_I2C_GPIO_SDA s5pc210_gpio_part1_get_nr(b, 6)
+#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_part1_get_nr(b, 7)
+#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_part1_get_nr(b, 6)
#define CONFIG_SOFT_I2C
#define CONFIG_SOFT_I2C_READ_REPEATED_START
/*
* Copyright (C) 2011 Samsung Electronics
*
- * Configuration settings for the SAMSUNG SMDKV310 (S5PC210) board.
+ * Configuration settings for the SAMSUNG SMDKV310 (EXYNOS4210) board.
*
* See file CREDITS for list of people who contributed to this
* project.
/* High Level Configuration Options */
#define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */
#define CONFIG_S5P 1 /* S5P Family */
-#define CONFIG_S5PC210 1 /* which is in a S5PC210 SoC */
+#define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */
#define CONFIG_SMDKV310 1 /* working with SMDKV310*/
#include <asm/arch/cpu.h> /* get chip and board defs */
#define CONFIG_SERIAL_MULTI 1
#define CONFIG_SERIAL1 1 /* use SERIAL 1 */
#define CONFIG_BAUDRATE 115200
-#define S5PC210_DEFAULT_UART_OFFSET 0x010000
+#define EXYNOS4_DEFAULT_UART_OFFSET 0x010000
/* SD/MMC configuration */
#define CONFIG_GENERIC_MMC 1
projects / u-boot / commitdiff