Changes since U-Boot 1.1.1:
======================================================================
+* Patch by Curt Brune, 17 May 2004:
+ - Add support for Samsung S3C4510B CPU (ARM7tdmi based SoC)
+ - Add support for ESPD-Inc. EVB4510 Board
+
+* Patch by Marc Leeman, 11 May 2004:
+ Fix for MPC8245 - reading PPC Memory from another device with the
+ PPC as PCI target device corrupts data due to interenal hardware
+ buffering.
+
* Fix "cls" command when used with splash screen
* Increase NFS download timeout (now 1 min - 10 sec is to short for a
E: obrown@adventnetworks.com
D: Port to the gw8260 board
+N: Curt Brune
+E: curt@cucy.com
+D: Added support for Samsung S3C4510B CPU (ARM7tdmi based SoC)
+D: Added support for ESPD-Inc. EVB4510 Board
+W: http://www.cucy.com
+
N: Jonathan De Bruyne
E: jonathan.debruyne@siemens.atea.be
D: Port to Siemens IAD210 board
## ARM7 Systems
#########################################################################
-LIST_ARM7="B2 ep7312 impa7"
+LIST_ARM7="B2 ep7312 evb4510 impa7 modnet50"
#########################################################################
## ARM9 Systems
modnet50_config : unconfig
@./mkconfig $(@:_config=) arm arm720t modnet50
+evb4510_config : unconfig
+ @./mkconfig $(@:_config=) arm arm720t evb4510
+
#########################################################################
## AT91RM9200 Systems
#########################################################################
--- /dev/null
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := evb4510.o flash.o
+SOBJS := memsetup.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $^
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- /dev/null
+#
+# Copyright (c) 2004 Cucy Systems (http://www.cucy.com)
+# Curt Brune <curt@cucy.com>
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0x007d0000
--- /dev/null
+/*
+ * Copyright (c) 2004 Cucy Systems (http://www.cucy.com)
+ * Curt Brune <curt@cucy.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/hardware.h>
+#include <command.h>
+
+/* ------------------------------------------------------------------------- */
+
+
+#define PUT_LED(val) (PUT_REG(REG_IOPDATA, (~val)&0xFF))
+#define GET_LED() ((~GET_REG( REG_IOPDATA)) & 0xFF)
+#define SET_LED(val) { u32 led = GET_LED(); led |= 1 << (val); PUT_LED( led); }
+#define CLR_LED(val) { u32 led = GET_LED(); led &= ~(1 << (val)); PUT_LED( led); }
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+int board_init (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ icache_enable();
+
+ /* address for the kernel command line */
+ gd->bd->bi_boot_params = 0x800;
+
+ /* enable board LEDs for output */
+ PUT_REG( REG_IOPDATA, 0x0);
+ PUT_REG( REG_IOPMODE, 0xFFFF);
+ PUT_REG( REG_IOPDATA, 0xFF);
+
+ /* enable LED 7 to show we're alive */
+ SET_LED( 7);
+
+ /* configure free running timer 1 */
+ /* Stop timer 1 */
+ CLR_REG( REG_TMOD, TM1_RUN);
+
+ /* Configure for toggle mode */
+ SET_REG( REG_TMOD, TM1_TOGGLE);
+
+ /* Load Timer data register with count down value */
+ PUT_REG( REG_TDATA1, 0xFFFFFFFF);
+
+ /* Clear timer counter register */
+ PUT_REG( REG_TCNT1, 0x0);
+
+ /* Start timer -- count down timer */
+ SET_REG( REG_TMOD, TM1_RUN);
+
+ return 0;
+}
+
+int dram_init (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+#if CONFIG_NR_DRAM_BANKS == 2
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
+#endif
+ return 0;
+}
--- /dev/null
+/*
+ *
+ * Copyright (c) 2004 Cucy Systems (http://www.cucy.com)
+ * Curt Brune <curt@cucy.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/hardware.h>
+#include <flash.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+typedef enum {
+ FLASH_DEV_U9_512KB = 0,
+ FLASH_DEV_U7_2MB = 1
+} FLASH_DEV;
+
+#define FLASH_DQ7 (0x80)
+#define FLASH_DQ5 (0x20)
+
+#define PROG_ADDR (0xAAA)
+#define SETUP_ADDR (0xAAA)
+#define ID_ADDR (0xAAA)
+#define UNLOCK_ADDR1 (0xAAA)
+#define UNLOCK_ADDR2 (0x555)
+
+#define UNLOCK_CMD1 (0xAA)
+#define UNLOCK_CMD2 (0x55)
+#define ERASE_SUSPEND_CMD (0xB0)
+#define ERASE_RESUME_CMD (0x30)
+#define RESET_CMD (0xF0)
+#define ID_CMD (0x90)
+#define SELECT_CMD (0x90)
+#define CHIPERASE_CMD (0x10)
+#define BYPASS_CMD (0x20)
+#define SECERASE_CMD (0x30)
+#define PROG_CMD (0xa0)
+#define SETUP_CMD (0x80)
+
+#if 0
+#define WRITE_UNLOCK(addr) { \
+ PUT__U8( addr + UNLOCK_ADDR1, UNLOCK_CMD1); \
+ PUT__U8( addr + UNLOCK_ADDR2, UNLOCK_CMD2); \
+}
+
+/* auto select command */
+#define CMD_ID(addr) WRITE_UNLOCK(addr); { \
+ PUT__U8( addr + ID_ADDR, ID_CMD); \
+}
+
+#define CMD_RESET(addr) WRITE_UNLOCK(addr); { \
+ PUT__U8( addr + ID_ADDR, RESET_CMD); \
+}
+
+#define CMD_ERASE_SEC(base, addr) WRITE_UNLOCK(base); \
+ PUT__U8( base + SETUP_ADDR, SETUP_CMD); \
+ WRITE_UNLOCK(base); \
+ PUT__U8( addr, SECERASE_CMD);
+
+#define CMD_ERASE_CHIP(base) WRITE_UNLOCK(base); \
+ PUT__U8( base + SETUP_ADDR, SETUP_CMD); \
+ WRITE_UNLOCK(base); \
+ PUT__U8( base + SETUP_ADDR, CHIPERASE_CMD);
+
+/* prepare for bypass programming */
+#define CMD_UNLOCK_BYPASS(addr) WRITE_UNLOCK(addr); { \
+ PUT__U8( addr + ID_ADDR, 0x20); \
+}
+
+/* terminate bypass programming */
+#define CMD_BYPASS_RESET(addr) { \
+ PUT__U8(addr, 0x90); \
+ PUT__U8(addr, 0x00); \
+}
+#endif
+
+inline static void FLASH_CMD_UNLOCK (FLASH_DEV dev, u32 base)
+{
+ switch (dev) {
+ case FLASH_DEV_U7_2MB:
+ PUT__U8 (base + 0xAAA, 0xAA);
+ PUT__U8 (base + 0x555, 0x55);
+ break;
+ case FLASH_DEV_U9_512KB:
+ PUT__U8 (base + 0x555, 0xAA);
+ PUT__U8 (base + 0x2AA, 0x55);
+ break;
+ }
+}
+
+inline static void FLASH_CMD_SELECT (FLASH_DEV dev, u32 base)
+{
+ switch (dev) {
+ case FLASH_DEV_U7_2MB:
+ FLASH_CMD_UNLOCK (dev, base);
+ PUT__U8 (base + 0xAAA, SELECT_CMD);
+ break;
+ case FLASH_DEV_U9_512KB:
+ FLASH_CMD_UNLOCK (dev, base);
+ PUT__U8 (base + 0x555, SELECT_CMD);
+ break;
+ }
+}
+
+inline static void FLASH_CMD_RESET (FLASH_DEV dev, u32 base)
+{
+ switch (dev) {
+ case FLASH_DEV_U7_2MB:
+ FLASH_CMD_UNLOCK (dev, base);
+ PUT__U8 (base + 0xAAA, RESET_CMD);
+ break;
+ case FLASH_DEV_U9_512KB:
+ FLASH_CMD_UNLOCK (dev, base);
+ PUT__U8 (base + 0x555, RESET_CMD);
+ break;
+ }
+}
+
+inline static void FLASH_CMD_ERASE_SEC (FLASH_DEV dev, u32 base, u32 addr)
+{
+ switch (dev) {
+ case FLASH_DEV_U7_2MB:
+ FLASH_CMD_UNLOCK (dev, base);
+ PUT__U8 (base + 0xAAA, SETUP_CMD);
+ FLASH_CMD_UNLOCK (dev, base);
+ PUT__U8 (addr, SECERASE_CMD);
+ break;
+ case FLASH_DEV_U9_512KB:
+ FLASH_CMD_UNLOCK (dev, base);
+ PUT__U8 (base + 0x555, SETUP_CMD);
+ FLASH_CMD_UNLOCK (dev, base);
+ PUT__U8 (addr, SECERASE_CMD);
+ break;
+ }
+}
+
+inline static void FLASH_CMD_ERASE_CHIP (FLASH_DEV dev, u32 base)
+{
+ switch (dev) {
+ case FLASH_DEV_U7_2MB:
+ FLASH_CMD_UNLOCK (dev, base);
+ PUT__U8 (base + 0xAAA, SETUP_CMD);
+ FLASH_CMD_UNLOCK (dev, base);
+ PUT__U8 (base, CHIPERASE_CMD);
+ break;
+ case FLASH_DEV_U9_512KB:
+ FLASH_CMD_UNLOCK (dev, base);
+ PUT__U8 (base + 0x555, SETUP_CMD);
+ FLASH_CMD_UNLOCK (dev, base);
+ PUT__U8 (base, CHIPERASE_CMD);
+ break;
+ }
+}
+
+inline static void FLASH_CMD_UNLOCK_BYPASS (FLASH_DEV dev, u32 base)
+{
+ switch (dev) {
+ case FLASH_DEV_U7_2MB:
+ FLASH_CMD_UNLOCK (dev, base);
+ PUT__U8 (base + 0xAAA, BYPASS_CMD);
+ break;
+ case FLASH_DEV_U9_512KB:
+ FLASH_CMD_UNLOCK (dev, base);
+ PUT__U8 (base + 0x555, BYPASS_CMD);
+ break;
+ }
+}
+
+inline static void FLASH_CMD_BYPASS_RESET (FLASH_DEV dev, u32 base)
+{
+ PUT__U8 (base, SELECT_CMD);
+ PUT__U8 (base, 0x0);
+}
+
+/* poll for flash command completion */
+static u16 _flash_poll (FLASH_DEV dev, u32 addr, u16 data, ulong timeOut)
+{
+ u32 done = 0;
+ ulong t0;
+
+ u16 error = 0;
+ volatile u16 flashData;
+
+ data = data & 0xFF;
+ t0 = get_timer (0);
+ while (get_timer (t0) < timeOut) {
+ /* for( i = 0; i < POLL_LOOPS; i++) { */
+ /* Read the Data */
+ flashData = GET__U8 (addr);
+
+ /* FLASH_DQ7 = Data? */
+ if ((flashData & FLASH_DQ7) == (data & FLASH_DQ7)) {
+ done = 1;
+ break;
+ }
+
+ /* Check Timeout (FLASH_DQ5==1) */
+ if (flashData & FLASH_DQ5) {
+ /* Read the Data */
+ flashData = GET__U8 (addr);
+
+ /* FLASH_DQ7 = Data? */
+ if (!((flashData & FLASH_DQ7) == (data & FLASH_DQ7))) {
+ printf ("_flash_poll(): FLASH_DQ7 & flashData not equal to write value\n");
+ error = ERR_PROG_ERROR;
+ }
+ FLASH_CMD_RESET (dev, addr);
+ done = 1;
+ break;
+ }
+ /* spin delay */
+ udelay (10);
+ }
+
+
+ /* error update */
+ if (!done) {
+ printf ("_flash_poll(): Timeout\n");
+ error = ERR_TIMOUT;
+ }
+
+ /* Check the data */
+ if (!error) {
+ /* Read the Data */
+ flashData = GET__U8 (addr);
+ if (flashData != data) {
+ error = ERR_PROG_ERROR;
+ printf ("_flash_poll(): flashData(0x%04x) not equal to data(0x%04x)\n",
+ flashData, data);
+ }
+ }
+
+ return error;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static int _flash_check_protection (flash_info_t * info, int s_first, int s_last)
+{
+ int sect, prot = 0;
+
+ for (sect = s_first; sect <= s_last; sect++)
+ if (info->protect[sect]) {
+ printf (" Flash sector %d protected.\n", sect);
+ prot++;
+ }
+ return prot;
+}
+
+static int _detectFlash (FLASH_DEV dev, u32 base, u8 venId, u8 devId)
+{
+
+ u32 baseAddr = base | CACHE_DISABLE_MASK;
+ u8 vendorId, deviceId;
+
+ /* printf(__FUNCTION__"(): detecting flash @ 0x%08x\n", base); */
+
+ /* Send auto select command and read manufacturer info */
+ FLASH_CMD_SELECT (dev, baseAddr);
+ vendorId = GET__U8 (baseAddr);
+ FLASH_CMD_RESET (dev, baseAddr);
+
+ /* Send auto select command and read device info */
+ FLASH_CMD_SELECT (dev, baseAddr);
+
+ if (dev == FLASH_DEV_U7_2MB) {
+ deviceId = GET__U8 (baseAddr + 2);
+ } else if (dev == FLASH_DEV_U9_512KB) {
+ deviceId = GET__U8 (baseAddr + 1);
+ } else {
+ return 0;
+ }
+
+ FLASH_CMD_RESET (dev, baseAddr);
+
+ /* printf (__FUNCTION__"(): found vendorId 0x%04x, deviceId 0x%04x\n",
+ vendorId, deviceId);
+ */
+
+ return (vendorId == venId) && (deviceId == devId);
+
+}
+
+/******************************************************************************
+ *
+ * Public u-boot interface functions below
+ *
+ *****************************************************************************/
+
+/***************************************************************************
+ *
+ * Flash initialization
+ *
+ * This board has two banks of flash, but the base addresses depend on
+ * how the board is jumpered.
+ *
+ * The two flash types are:
+ *
+ * AMD Am29LV160DB (2MB) sectors layout 16KB, 2x8KB, 32KB, 31x64KB
+ *
+ * AMD Am29LV040B (512KB) sectors: 8x64KB
+ *****************************************************************************/
+
+unsigned long flash_init (void)
+{
+ flash_info_t *info;
+ u16 i;
+ u32 flashtest;
+ s16 amd160 = -1;
+ u32 amd160base = 0;
+
+#if CFG_MAX_FLASH_BANKS == 2
+ s16 amd040 = -1;
+ u32 amd040base = 0;
+#endif
+
+ /* configure PHYS_FLASH_1 */
+ if (_detectFlash (FLASH_DEV_U7_2MB, PHYS_FLASH_1, 0x1, 0x49)) {
+ amd160 = 0;
+ amd160base = PHYS_FLASH_1;
+#if CFG_MAX_FLASH_BANKS == 1
+ }
+#else
+ if (_detectFlash
+ (FLASH_DEV_U9_512KB, PHYS_FLASH_2, 0x1, 0x4F)) {
+ amd040 = 1;
+ amd040base = PHYS_FLASH_2;
+ } else {
+ printf (__FUNCTION__
+ "(): Unable to detect PHYS_FLASH_2: 0x%08x\n",
+ PHYS_FLASH_2);
+ }
+ } else if (_detectFlash (FLASH_DEV_U9_512KB, PHYS_FLASH_1, 0x1, 0x4F)) {
+ amd040 = 0;
+ amd040base = PHYS_FLASH_1;
+ if (_detectFlash (FLASH_DEV_U7_2MB, PHYS_FLASH_2, 0x1, 0x49)) {
+ amd160 = 1;
+ amd160base = PHYS_FLASH_2;
+ } else {
+ printf (__FUNCTION__
+ "(): Unable to detect PHYS_FLASH_2: 0x%08x\n",
+ PHYS_FLASH_2);
+ }
+ }
+#endif
+ else {
+ printf (__FUNCTION__
+ "(): Unable to detect PHYS_FLASH_1: 0x%08x\n",
+ PHYS_FLASH_1);
+ }
+
+ /* Configure AMD Am29LV160DB (2MB) */
+ info = &flash_info[amd160];
+ info->flash_id = FLASH_DEV_U7_2MB;
+ info->sector_count = 35;
+ info->size = 2 * 1024 * 1024; /* 2MB */
+ /* 1*16K Boot Block
+ 2*8K Parameter Block
+ 1*32K Small Main Block */
+ info->start[0] = amd160base;
+ info->start[1] = amd160base + 0x4000;
+ info->start[2] = amd160base + 0x6000;
+ info->start[3] = amd160base + 0x8000;
+ for (i = 1; i < info->sector_count; i++)
+ info->start[3 + i] = amd160base + i * (64 * 1024);
+
+ for (i = 0; i < info->sector_count; i++) {
+ /* Write auto select command sequence and query sector protection */
+ FLASH_CMD_SELECT (info->flash_id,
+ info->start[i] | CACHE_DISABLE_MASK);
+ flashtest =
+ GET__U8 (((info->start[i] + 4) | CACHE_DISABLE_MASK));
+ FLASH_CMD_RESET (info->flash_id,
+ amd160base | CACHE_DISABLE_MASK);
+ info->protect[i] = (flashtest & 0x0001);
+ }
+
+ /*
+ * protect monitor and environment sectors in 2MB flash
+ */
+ flash_protect (FLAG_PROTECT_SET,
+ amd160base, amd160base + monitor_flash_len - 1, info);
+
+ flash_protect (FLAG_PROTECT_SET,
+ CFG_ENV_ADDR, CFG_ENV_ADDR + CFG_ENV_SIZE - 1, info);
+
+#if CFG_MAX_FLASH_BANKS == 2
+ /* Configure AMD Am29LV040B (512KB) */
+ info = &flash_info[amd040];
+ info->flash_id = FLASH_DEV_U9_512KB;
+ info->sector_count = 8;
+ info->size = 512 * 1024; /* 512KB, 8 x 64KB */
+ for (i = 0; i < info->sector_count; i++) {
+ info->start[i] = amd040base + i * (64 * 1024);
+ /* Write auto select command sequence and query sector protection */
+ FLASH_CMD_SELECT (info->flash_id,
+ info->start[i] | CACHE_DISABLE_MASK);
+ flashtest =
+ GET__U8 (((info->start[i] + 2) | CACHE_DISABLE_MASK));
+ FLASH_CMD_RESET (info->flash_id,
+ amd040base | CACHE_DISABLE_MASK);
+ info->protect[i] = (flashtest & 0x0001);
+ }
+#endif
+
+ return flash_info[0].size
+#if CFG_MAX_FLASH_BANKS == 2
+ + flash_info[1].size
+#endif
+ ;
+}
+
+void flash_print_info (flash_info_t * info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_DEV_U7_2MB) {
+ printf ("AMD Am29LV160DB (2MB) 16KB,2x8KB,32KB,31x64KB\n");
+ } else if (info->flash_id == FLASH_DEV_U9_512KB) {
+ printf ("AMD Am29LV040B (512KB) 8x64KB\n");
+ } else {
+ printf ("Unknown flash_id ...\n");
+ return;
+ }
+
+ printf (" Size: %ld KB in %d Sectors\n",
+ info->size >> 10, info->sector_count);
+ printf (" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; i++) {
+ if ((i % 4) == 0)
+ printf ("\n ");
+ printf (" S%02d @ 0x%08lX%s", i,
+ info->start[i], info->protect[i] ? " !" : " ");
+ }
+ printf ("\n");
+}
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+ u16 i, error = 0;
+
+ printf ("\n");
+
+ /* check flash protection bits */
+ if (_flash_check_protection (info, s_first, s_last)) {
+ printf (" Flash erase aborted due to protected sectors\n");
+ return ERR_PROTECTED;
+ }
+
+ if ((s_first < info->sector_count) && (s_first <= s_last)) {
+ for (i = s_first; i <= s_last && !error; i++) {
+ printf (" Erasing Sector %d @ 0x%08lx ... ", i,
+ info->start[i]);
+ /* bypass the cache to access the flash memory */
+ FLASH_CMD_ERASE_SEC (info->flash_id,
+ (info->
+ start[0] | CACHE_DISABLE_MASK),
+ (info->
+ start[i] | CACHE_DISABLE_MASK));
+ /* look for sector to become 0xFF after erase */
+ error = _flash_poll (info->flash_id,
+ info->
+ start[i] | CACHE_DISABLE_MASK,
+ 0xFF, CFG_FLASH_ERASE_TOUT);
+ FLASH_CMD_RESET (info->flash_id,
+ (info->
+ start[0] | CACHE_DISABLE_MASK));
+ printf ("done\n");
+ if (error) {
+ break;
+ }
+ }
+ } else
+ error = ERR_INVAL;
+
+ return error;
+}
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+ u16 error = 0, i;
+ u32 n;
+ u8 *bp, *bps;
+
+ /* Write Setup */
+ /* bypass the cache to access the flash memory */
+ FLASH_CMD_UNLOCK_BYPASS (info->flash_id,
+ (info->start[0] | CACHE_DISABLE_MASK));
+
+ /* Write the Data to Flash */
+
+ bp = (u8 *) (addr | CACHE_DISABLE_MASK);
+ bps = (u8 *) src;
+
+ for (n = 0; n < cnt && !error; n++, bp++, bps++) {
+
+ if (!(n % (cnt / 15))) {
+ printf (".");
+ }
+
+ /* write the flash command for flash memory */
+ *bp = 0xA0;
+
+ /* Write the data */
+ *bp = *bps;
+
+ /* Check if the write is done */
+ for (i = 0; i < 0xff; i++);
+ error = _flash_poll (info->flash_id, (u32) bp, *bps,
+ CFG_FLASH_WRITE_TOUT);
+ if (error) {
+ return error;
+ }
+ }
+
+ /* Reset the Flash Mode to read */
+ FLASH_CMD_BYPASS_RESET (info->flash_id, info->start[0]);
+
+ printf (" ");
+
+ return error;
+}
--- /dev/null
+/*
+ * Copyright (c) 2004 Cucy Systems (http://www.cucy.com)
+ * Curt Brune <curt@cucy.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#include <config.h>
+#include <version.h>
+#include <asm/hardware.h>
+
+/***********************************************************************
+ * Configure Memory Map
+ *
+ * This memory map allows us to relocate from FLASH to SRAM. After
+ * power-on reset the CPU only knows about the FLASH memory at address
+ * 0x00000000. After memsetup completes the memory map will be:
+ *
+ * Memory Addr
+ * 0x00000000
+ * to 8MB SRAM (U5) -- 8MB Map
+ * 0x00800000
+ *
+ * 0x01000000
+ * to 2MB Flash @ 0x00000000 (U7) -- 2MB Map
+ * 0x01200000
+ *
+ * 0x02000000
+ * to 512KB Flash @ 0x02000000 (U9) -- 2MB Map
+ * 0x02080000
+ *
+ * Load all 12 memory registers with the STMIA instruction since
+ * memory access is disabled once these registers are written. The
+ * last register written re-enables memory access. For more info see
+ * the user's manual for the S3C4510B, available from Samsung's web
+ * site. Search for part number "S3C4510B".
+ *
+ ***********************************************************************/
+
+.globl memsetup
+memsetup:
+
+ /* preserve the temp register (r12 AKA ip) and remap it. */
+ ldr r1, =SRAM_BASE+0xC
+ add r0, r12, #0x01000000
+ str r0, [r1]
+
+ /* remap the link register for when we return */
+ add lr, lr, #0x01000000
+
+ /* store a short program in the on chip SRAM, which is
+ * unaffected when remapping memory. Note the cache must be
+ * disabled for the on chip SRAM to be available.
+ */
+ ldr r1, =SRAM_BASE
+ ldr r0, =0xe8801ffe /* stmia r0, {r1-r12} */
+ str r0, [r1]
+ add r1, r1, #4
+ ldr r0, =0xe59fc000 /* ldr r12, [pc, #0] */
+ str r0, [r1]
+ add r1, r1, #4
+ ldr r0, =0xe1a0f00e /* mov pc, lr */
+ str r0, [r1]
+
+ adr r0, memory_map_data
+ ldmia r0, {r1-r12}
+ ldr r0, =REG_EXTDBWTH
+
+ ldr pc, =SRAM_BASE
+
+.globl reset_cpu
+reset_cpu:
+ /*
+ * reset the cpu by re-mapping FLASH 0 to 0x0 and jumping to
+ * address 0x0. We accomplish this by storing a few
+ * instructions into the on chip SRAM (8KB) and run from
+ * there. Note the cache must be disabled for the on chip
+ * SRAM to be available.
+ *
+ * load r2 with REG_ROMCON0
+ * load r3 with 0x12040060 configure FLASH bank 0 @ 0x00000000
+ * load r4 with REG_DRAMCON0
+ * load r5 with 0x08000380 configure RAM bank 0 @ 0x01000000
+ * load r6 with REG_REFEXTCON
+ * load r7 with 0x9c218360
+ * load r8 with 0x0
+ * store str r3,[r2] @ SRAM_BASE
+ * store str r5,[r4] @ SRAM_BASE + 0x4
+ * store str r7,[r6] @ SRAM_BASE + 0x8
+ * store mov pc,r8 @ SRAM_BASE + 0xC
+ * mov pc, SRAM_BASE
+ *
+ */
+
+ /* disable cache */
+ ldr r0, =REG_SYSCFG
+ ldr r1, =0x83ffffa0 /* cache-disabled */
+ str r1, [r0]
+
+ ldr r2, =REG_ROMCON0
+ ldr r3, =0x02000060 /* Bank0 2MB FLASH @ 0x00000000 */
+ ldr r4, =REG_DRAMCON0
+ ldr r5, =0x18040380 /* DRAM0 8MB SRAM @ 0x01000000 */
+ ldr r6, =REG_REFEXTCON
+ ldr r7, =0xce278360
+ ldr r8, =0x00000000
+ ldr r1, =SRAM_BASE
+ ldr r0, =0xe5823000 /* str r3, [r2] */
+ str r0, [r1]
+ ldr r1, =SRAM_BASE+4
+ ldr r0, =0xe5845000 /* str r5, [r4] */
+ str r0, [r1]
+ ldr r1, =SRAM_BASE+8
+ ldr r0, =0xe5867000 /* str r7, [r6] */
+ str r0, [r1]
+ ldr r1, =SRAM_BASE+0xC
+ ldr r0, =0xe1a0f008 /* mov pc, r8 */
+ str r0, [r1]
+ ldr r1, =SRAM_BASE
+ mov pc, r1
+
+ /* never return */
+
+/************************************************************************
+ * Below are twelve 32-bit values for the twelve memory registers of
+ * the system manager, starting with register REG_EXTDBWTH.
+ ***********************************************************************/
+memory_map_data:
+ .long 0x00f03005 /* memory widths */
+ .long 0x12040060 /* Bank0 2MB FLASH @ 0x01000000 */
+ .long 0x22080060 /* Bank1 512KB FLASH @ 0x02000000 */
+ .long 0x00000000
+ .long 0x00000000
+ .long 0x00000000
+ .long 0x00000000
+ .long 0x08000380 /* DRAM0 8MB SRAM @ 0x00000000 */
+ .long 0x00000000
+ .long 0x00000000
+ .long 0x00000000
+ .long 0x9c218360 /* enable memory */
--- /dev/null
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/arm720t/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_info 0 : { *(.debug_info) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ .debug_aranges 0 : { *(.debug_aranges) }
+}
int board_init (void)
{
- volatile unsigned int *IOConfReg;
-
-
DECLARE_GLOBAL_DATA_PTR;
/* arch number of OMAP 730 P2 Board - Same as the Innovator! */
peripheral_power_enable ();
-
/* Backup LED indication via GPIO_140 -> Red led if MUX correctly setup */
toggle_backup_led();
/* Hold GSM in reset until needed */
*((volatile unsigned short *)M_CTL) &= ~1;
-
/*
* CSx timings, GPIO Mux ... setup
*/
{
vu_long *addr = (vu_long*)(info->start[0]);
ulong start;
- ulong rev;
int flag;
- int i;
/* Check if Flash is (sufficiently) erased */
if ((*((vu_long *)dest) & data) != data) {
int
do_jffs2_fsload(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
- struct part_info* jffs2_part_info(int);
- int jffs2_1pass_load(char *, struct part_info *,const char *);
- char *fsname;
-
+ struct part_info* jffs2_part_info(int);
+ int jffs2_1pass_load(char *, struct part_info *,const char *);
+ char *fsname;
char *filename;
+ int size;
+ struct part_info *part;
+ ulong offset = load_addr;
/* pre-set Boot file name */
if ((filename = getenv("bootfile")) == NULL) {
filename = "uImage";
}
- ulong offset = load_addr;
- int size;
- struct part_info *part;
-
if (argc == 2) {
filename = argv[1];
}
#include <common.h>
#include <command.h>
#include <clps7111.h>
-
-/* read co-processor 15, register #1 (control register) */
-static unsigned long read_p15_c1(void)
-{
- unsigned long value;
-
- __asm__ __volatile__(
- "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n"
- : "=r" (value)
- :
- : "memory");
- /* printf("p15/c1 is = %08lx\n", value); */
- return value;
-}
-
-/* write to co-processor 15, register #1 (control register) */
-static void write_p15_c1(unsigned long value)
-{
- /* printf("write %08lx to p15/c1\n", value); */
- __asm__ __volatile__(
- "mcr p15, 0, %0, c1, c0, 0 @ write it back\n"
- :
- : "r" (value)
- : "memory");
-
- read_p15_c1();
-}
-
-static void cp_delay (void)
-{
- volatile int i;
-
- /* copro seems to need some delay between reading and writing */
- for (i = 0; i < 100; i++);
-}
-
-/* See also ARM Ref. Man. */
-#define C1_MMU (1<<0) /* mmu off/on */
-#define C1_ALIGN (1<<1) /* alignment faults off/on */
-#define C1_IDC (1<<2) /* icache and/or dcache off/on */
-#define C1_WRITE_BUFFER (1<<3) /* write buffer off/on */
-#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */
-#define C1_SYS_PROT (1<<8) /* system protection */
-#define C1_ROM_PROT (1<<9) /* ROM protection */
-#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */
+#include <asm/hardware.h>
int cpu_init (void)
{
* and we set the CPU-speed to 73 MHz - see start.S for details
*/
+#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312)
unsigned long i;
disable_interrupts ();
-#ifdef CONFIG_NETARM
- return 0;
-#endif
+
/* turn off I-cache */
asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
i &= ~0x1000;
/* flush I-cache */
asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
-
#ifdef CONFIG_ARM7_REVD
/* go to high speed */
IO_SYSCON3 = (IO_SYSCON3 & ~CLKCTL) | CLKCTL_73;
+#endif
+#elif defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B)
+ disable_interrupts ();
+ /* Nothing more needed */
+#else
+#error No cleanup_before_linux() defined for this CPU type
#endif
return 0;
}
return (0);
}
+/*
+ * Instruction and Data cache enable and disable functions
+ *
+ */
+
+#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM)
+/* read co-processor 15, register #1 (control register) */
+static unsigned long read_p15_c1(void)
+{
+ unsigned long value;
+
+ __asm__ __volatile__(
+ "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n"
+ : "=r" (value)
+ :
+ : "memory");
+ /* printf("p15/c1 is = %08lx\n", value); */
+ return value;
+}
+
+/* write to co-processor 15, register #1 (control register) */
+static void write_p15_c1(unsigned long value)
+{
+ /* printf("write %08lx to p15/c1\n", value); */
+ __asm__ __volatile__(
+ "mcr p15, 0, %0, c1, c0, 0 @ write it back\n"
+ :
+ : "r" (value)
+ : "memory");
+
+ read_p15_c1();
+}
+
+static void cp_delay (void)
+{
+ volatile int i;
+
+ /* copro seems to need some delay between reading and writing */
+ for (i = 0; i < 100; i++);
+}
+
+/* See also ARM Ref. Man. */
+#define C1_MMU (1<<0) /* mmu off/on */
+#define C1_ALIGN (1<<1) /* alignment faults off/on */
+#define C1_IDC (1<<2) /* icache and/or dcache off/on */
+#define C1_WRITE_BUFFER (1<<3) /* write buffer off/on */
+#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */
+#define C1_SYS_PROT (1<<8) /* system protection */
+#define C1_ROM_PROT (1<<9) /* ROM protection */
+#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */
+
void icache_enable (void)
{
ulong reg;
{
return (read_p15_c1 () & C1_IDC) != 0;
}
+
+#elif defined(CONFIG_S3C4510B)
+
+void icache_enable (void)
+{
+ s32 i;
+
+ /* disable all cache bits */
+ CLR_REG( REG_SYSCFG, 0x3F);
+
+ /* 8KB cache, write enable */
+ SET_REG( REG_SYSCFG, CACHE_WRITE_BUFF | CACHE_MODE_01);
+
+ /* clear TAG RAM bits */
+ for ( i = 0; i < 256; i++)
+ PUT_REG( CACHE_TAG_RAM + 4*i, 0x00000000);
+
+ /* clear SET0 RAM */
+ for(i=0; i < 1024; i++)
+ PUT_REG( CACHE_SET0_RAM + 4*i, 0x00000000);
+
+ /* clear SET1 RAM */
+ for(i=0; i < 1024; i++)
+ PUT_REG( CACHE_SET1_RAM + 4*i, 0x00000000);
+
+ /* enable cache */
+ SET_REG( REG_SYSCFG, CACHE_ENABLE);
+
+}
+
+void icache_disable (void)
+{
+ /* disable all cache bits */
+ CLR_REG( REG_SYSCFG, 0x3F);
+}
+
+int icache_status (void)
+{
+ return GET_REG( REG_SYSCFG) & CACHE_ENABLE;
+}
+
+void dcache_enable (void)
+{
+ /* we don't have seperate instruction/data caches */
+ icache_enable();
+}
+
+void dcache_disable (void)
+{
+ /* we don't have seperate instruction/data caches */
+ icache_disable();
+}
+
+int dcache_status (void)
+{
+ /* we don't have seperate instruction/data caches */
+ return icache_status();
+}
+
+#else
+#error No icache/dcache enable/disable functions defined for this CPU type
+#endif
#include <common.h>
#include <clps7111.h>
-
#include <asm/proc-armv/ptrace.h>
-#ifdef CONFIG_NETARM
-#include <asm/arch/netarm_registers.h>
-#endif
+#include <asm/hardware.h>
extern void reset_cpu(ulong addr);
int interrupt_init (void)
{
-#ifdef CONFIG_NETARM
+
+#if defined(CONFIG_NETARM)
/* disable all interrupts */
IRQEN = 0;
/* set timer 2 counter */
lastdec = TIMER_LOAD_VAL;
-#else
+#elif defined(CONFIG_IMPA7) || defined(CONFIG_EP7312)
/* disable all interrupts */
IO_INTMR1 = 0;
/* set timer 1 counter */
lastdec = IO_TC1D = TIMER_LOAD_VAL;
+#elif defined(CONFIG_S3C4510B)
+ /* Nothing to do, interrupts not supported */
+ lastdec = 0;
+#else
+#error No interrupt_init() defined for this CPU type
#endif
timestamp = 0;
* timer without interrupts
*/
+
+#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_NETARM)
+
void reset_timer (void)
{
reset_timer_masked ();
while (get_timer_masked () < tmo)
/*NOP*/;
}
+
+#elif defined(CONFIG_S3C4510B)
+
+#define TMR_OFFSET (0x1000)
+
+void udelay (unsigned long usec)
+{
+ u32 rDATA;
+
+ rDATA = t_data_us(usec);
+
+ /* Stop timer 0 */
+ CLR_REG( REG_TMOD, TM0_RUN);
+
+ /* Configure for toggle mode */
+ SET_REG( REG_TMOD, TM0_TOGGLE);
+
+ /* Load Timer data register with count down value plus offset */
+ PUT_REG( REG_TDATA0, rDATA + TMR_OFFSET);
+
+ /* Clear timer counter register */
+ PUT_REG( REG_TCNT0, 0x0);
+
+ /* Start timer -- count down timer */
+ SET_REG( REG_TMOD, TM0_RUN);
+
+ /* spin during count down */
+ while ( GET_REG( REG_TCNT0) > TMR_OFFSET);
+
+ /* Stop timer */
+ CLR_REG( REG_TMOD, TM0_RUN);
+
+}
+
+ulong get_timer (ulong base)
+{
+ return (0xFFFFFFFF - GET_REG( REG_TCNT1)) - base;
+}
+
+#else
+#error Timer routines not defined for this CPU type
+#endif
/*
- * (C) Copyright 2002
+ * (C) Copyright 2002-2004
* Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
*
* (C) Copyright 2002
*/
#include <common.h>
-#include <clps7111.h>
-#ifndef CONFIG_NETARM
+#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312)
+
+#include <clps7111.h>
void serial_setbrg (void)
{
unsigned int reg = 0;
- if (gd->baudrate == 1200)
- reg = 191;
- else if (gd->baudrate == 9600)
- reg = 23;
- else if (gd->baudrate == 19200)
- reg = 11;
- else if (gd->baudrate == 38400)
- reg = 5;
- else if (gd->baudrate == 57600)
- reg = 3;
- else if (gd->baudrate == 115200)
- reg = 1;
- else
- hang ();
+ switch (gd->baudrate) {
+ case 1200: reg = 191; break;
+ case 9600: reg = 23; break;
+ case 19200: reg = 11; break;
+ case 38400: reg = 5; break;
+ case 57600: reg = 3; break;
+ case 115200: reg = 1; break;
+ default: hang (); break;
+ }
/* init serial serial 1,2 */
IO_SYSCON1 = SYSCON1_UART1EN;
}
}
-#endif /* CONFIG_NETARM */
+#endif /* defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) */
*/
#include <common.h>
-#include <asm/arch/netarm_registers.h>
#ifdef CONFIG_NETARM
+#include <asm/hardware.h>
+
#define PORTA (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTA))
#define PORTB (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_PORTB))
#include <config.h>
#include <version.h>
-#ifdef CONFIG_NETARM
-#include <asm/arch/netarm_registers.h>
-#endif
+#include <asm/hardware.h>
/*
*************************************************************************
_start_armboot: .word start_armboot
-
/*
*************************************************************************
*
*************************************************************************
*/
+#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312)
/* Interupt-Controller base addresses */
INTMR1: .word 0x80000280 @ 32 bit size
#define CLKCTL_49 0x4 /* 49.152 MHz */
#define CLKCTL_73 0x6 /* 73.728 MHz */
+#endif
+
cpu_init_crit:
-#ifndef CONFIG_NETARM
+#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312)
+
/*
* mask all IRQs by clearing all bits in the INTMRs
*/
bic r0, r0, #0x0000008f @ clear bits 7, 3:0 (B--- WCAM)
orr r0, r0, #0x00000002 @ set bit 2 (A) Align
mcr p15,0,r0,c1,c0
-#else /* CONFIG_NETARM */
+#elif defined(CONFIG_NETARM)
/*
* prior to software reset : need to set pin PORTC4 to be *HRESET
*/
mov r1, #0
ldr r0, =NETARM_GEN_MODULE_BASE
str r1, [r0, #+NETARM_GEN_INTR_ENABLE]
-#endif /* CONFIG_NETARM */
+
+#elif defined(CONFIG_S3C4510B)
+
+ /*
+ * Mask off all IRQ sources
+ */
+ ldr r1, =REG_INTMASK
+ ldr r0, =0x3FFFFF
+ str r0, [r1]
+
+ /*
+ * Disable Cache
+ */
+ ldr r0, =REG_SYSCFG
+ ldr r1, =0x83ffffa0 /* cache-disabled */
+ str r1, [r0]
+
+#else
+#error No cpu_init_crit() defined for current CPU type
+#endif
#ifdef CONFIG_ARM7_REVD
/* set clock speed */
#endif
+#if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312)
.align 5
.globl reset_cpu
reset_cpu:
-#ifndef CONFIG_NETARM
mov ip, #0
mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
bic ip, ip, #0x2100 @ ..v....s........
mcr p15, 0, ip, c1, c0, 0 @ ctrl register
mov pc, r0
-#else
+#elif defined(CONFIG_NETARM)
+ .align 5
+.globl reset_cpu
+reset_cpu:
ldr r1, =NETARM_MEM_MODULE_BASE
ldr r0, [r1, #+NETARM_MEM_CS0_BASE_ADDR]
ldr r1, =0xFFFFF000
ldr r1, =NETARM_GEN_SW_SVC_RESETB
str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
mov pc, r0
+#elif defined(CONFIG_S3C4510B)
+/* Nothing done here as reseting the CPU is board specific, depending
+ * on external peripherals such as watchdog timers, etc. */
+#else
+#error No reset_cpu() defined for current CPU type
#endif
*/
#define M_CONFIG_WRITE_HALFWORD( addr, data ) \
- __asm__ __volatile__( \
- " \
- stw %2,0(%0)\n \
- sync\n \
- sth %3,2(%1)\n \
- sync\n \
- " \
- : /* no output */ \
- : "r" (CONFIG_ADDR), "r" (CONFIG_DATA), \
- "r" (PCISWAP(addr & ~3)), "r" (PCISWAP(data << 16)) \
- );
-
- M_CONFIG_WRITE_HALFWORD(PCIACR, 0x8000);
+ __asm__ __volatile__(" \
+ stw %2,0(%0)\n \
+ sync\n \
+ sth %3,2(%1)\n \
+ sync\n \
+ " \
+ : /* no output */ \
+ : "r" (CONFIG_ADDR), "r" (CONFIG_DATA), \
+ "r" (PCISWAP(addr & ~3)), "r" (PCISWAP(data << 16)) \
+ );
+
+ M_CONFIG_WRITE_HALFWORD(PCIACR, 0x8000);
#endif
- CONFIG_WRITE_BYTE(PCLSR, 0x8); /* set PCI cache line size */
+ CONFIG_WRITE_BYTE(PCLSR, 0x8); /* set PCI cache line size */
+
+ /*
+ * Note that although this bit is cleared after a hard reset, it
+ * must be explicitly set and then cleared by software during
+ * initialization in order to guarantee correct operation of the
+ * DLL and the SDRAM_CLK[0:3] signals (if they are used).
+ */
+ CONFIG_READ_BYTE (AMBOR, val);
+ CONFIG_WRITE_BYTE(AMBOR, val & 0xDF);
+ CONFIG_WRITE_BYTE(AMBOR, val | 0x20);
+ CONFIG_WRITE_BYTE(AMBOR, val & 0xDF);
+#ifdef CONFIG_MPC8245
+ /* silicon bug 28 MPC8245 */
+ CONFIG_READ_BYTE(AMBOR,val);
+ CONFIG_WRITE_BYTE(AMBOR,val|0x1);
+
+ CONFIG_READ_BYTE(PCMBCR,val);
+ /* in order not to corrupt data which is being read over the PCI bus
+ * with the PPC as master, we need to reduce the number of PCMRBs to 1,
+ * 4.11 in the processor user manual
+ * */
- /*
- * Note that although this bit is cleared after a hard reset, it
- * must be explicitly set and then cleared by software during
- * initialization in order to guarantee correct operation of the
- * DLL and the SDRAM_CLK[0:3] signals (if they are used).
- */
- CONFIG_READ_BYTE (AMBOR, val);
- CONFIG_WRITE_BYTE(AMBOR, val & 0xDF);
- CONFIG_WRITE_BYTE(AMBOR, val | 0x20);
- CONFIG_WRITE_BYTE(AMBOR, val & 0xDF);
+#if 1
+ CONFIG_WRITE_BYTE(PCMBCR,(val|0xC0)); /* 1 PCMRB */
+#else
+ CONFIG_WRITE_BYTE(PCMBCR,(val|0x80)); /* 2 PCMRBs */
+ CONFIG_WRITE_BYTE(PCMBCR,(val|0x40)); /* 3 PCMRBs */
+#endif
+#endif
- CONFIG_READ_WORD(PICR1, val);
+ CONFIG_READ_WORD(PICR1, val);
#if defined(CONFIG_MPC8240)
- CONFIG_WRITE_WORD( PICR1,
- (val & (PICR1_ADDRESS_MAP | PICR1_RCS0)) |
- PIRC1_MSK | PICR1_PROC_TYPE_603E |
- PICR1_FLASH_WR_EN | PICR1_MCP_EN |
- PICR1_CF_DPARK | PICR1_EN_PCS |
- PICR1_CF_APARK );
+ CONFIG_WRITE_WORD( PICR1,
+ (val & (PICR1_ADDRESS_MAP | PICR1_RCS0)) |
+ PIRC1_MSK | PICR1_PROC_TYPE_603E |
+ PICR1_FLASH_WR_EN | PICR1_MCP_EN |
+ PICR1_CF_DPARK | PICR1_EN_PCS |
+ PICR1_CF_APARK );
#elif defined(CONFIG_MPC8245)
- CONFIG_WRITE_WORD( PICR1,
- (val & (PICR1_RCS0)) |
- PICR1_PROC_TYPE_603E |
- PICR1_FLASH_WR_EN | PICR1_MCP_EN |
- PICR1_CF_DPARK | PICR1_NO_BUSW_CK |
- PICR1_DEC| PICR1_CF_APARK | 0x10); /* 8245 UM says bit 4 must be set */
+ CONFIG_WRITE_WORD( PICR1,
+ (val & (PICR1_RCS0)) |
+ PICR1_PROC_TYPE_603E |
+ PICR1_FLASH_WR_EN | PICR1_MCP_EN |
+ PICR1_CF_DPARK | PICR1_NO_BUSW_CK |
+ PICR1_DEC| PICR1_CF_APARK | 0x10); /* 8245 UM says bit 4 must be set */
#else
#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
#endif
- CONFIG_READ_WORD(PICR2, val);
- val= val & ~ (PICR2_CF_SNOOP_WS_MASK | PICR2_CF_APHASE_WS_MASK); /*mask off waitstate bits*/
+ CONFIG_READ_WORD(PICR2, val);
+ val= val & ~ (PICR2_CF_SNOOP_WS_MASK | PICR2_CF_APHASE_WS_MASK); /*mask off waitstate bits*/
#ifndef CONFIG_PN62
- val |= PICR2_CF_SNOOP_WS_1WS | PICR2_CF_APHASE_WS_1WS; /*1 wait state*/
+ val |= PICR2_CF_SNOOP_WS_1WS | PICR2_CF_APHASE_WS_1WS; /*1 wait state*/
#endif
- CONFIG_WRITE_WORD(PICR2, val);
+ CONFIG_WRITE_WORD(PICR2, val);
- CONFIG_WRITE_WORD(EUMBBAR, CFG_EUMB_ADDR);
+ CONFIG_WRITE_WORD(EUMBBAR, CFG_EUMB_ADDR);
#ifndef CFG_RAMBOOT
- CONFIG_WRITE_WORD(MCCR1, (CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) |
+ CONFIG_WRITE_WORD(MCCR1, (CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) |
(CFG_BANK0_ROW) |
(CFG_BANK1_ROW << MCCR1_BANK1ROW_SHIFT) |
(CFG_BANK2_ROW << MCCR1_BANK2ROW_SHIFT) |
(CFG_BANK5_ROW << MCCR1_BANK5ROW_SHIFT) |
(CFG_BANK6_ROW << MCCR1_BANK6ROW_SHIFT) |
(CFG_BANK7_ROW << MCCR1_BANK7ROW_SHIFT) |
- (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT));
+ (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT));
#endif
#if defined(CFG_ASRISE) && defined(CFG_ASFALL)
- CONFIG_WRITE_WORD(MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT |
- CFG_ASRISE << MCCR2_ASRISE_SHIFT |
- CFG_ASFALL << MCCR2_ASFALL_SHIFT);
+ CONFIG_WRITE_WORD(MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT |
+ CFG_ASRISE << MCCR2_ASRISE_SHIFT |
+ CFG_ASFALL << MCCR2_ASFALL_SHIFT);
#else
- CONFIG_WRITE_WORD(MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT);
+ CONFIG_WRITE_WORD(MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT);
#endif
#if defined(CONFIG_MPC8240)
- CONFIG_WRITE_WORD(MCCR3,
- (((CFG_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) |
- (CFG_REFREC << MCCR3_REFREC_SHIFT) |
- (CFG_RDLAT << MCCR3_RDLAT_SHIFT));
+ CONFIG_WRITE_WORD(MCCR3,
+ (((CFG_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) |
+ (CFG_REFREC << MCCR3_REFREC_SHIFT) |
+ (CFG_RDLAT << MCCR3_RDLAT_SHIFT));
#elif defined(CONFIG_MPC8245)
- CONFIG_WRITE_WORD(MCCR3,
- (((CFG_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) |
- (CFG_REFREC << MCCR3_REFREC_SHIFT));
+ CONFIG_WRITE_WORD(MCCR3,
+ (((CFG_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) |
+ (CFG_REFREC << MCCR3_REFREC_SHIFT));
#else
#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
#endif
(CFG_SDMODE_BURSTLEN)) <<MCCR4_SDMODE_SHIFT) |
(((CFG_BSTOPRE & 0x03c0) >> 6) <<MCCR4_BSTOPRE6TO9_SHIFT ));
#elif defined(CONFIG_MPC8245)
- CONFIG_READ_WORD(MCCR1, val);
- val &= MCCR1_DBUS_SIZE0; /* test for 64-bit mem bus */
+ CONFIG_READ_WORD(MCCR1, val);
+ val &= MCCR1_DBUS_SIZE0; /* test for 64-bit mem bus */
- CONFIG_WRITE_WORD(MCCR4,
- (CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) |
- (CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
- (CFG_EXTROM ? MCCR4_EXTROM : 0) |
- (CFG_REGDIMM ? MCCR4_REGDIMM : 0) |
- (CFG_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) |
- ((CFG_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) |
- (CFG_DBUS_SIZE2 << MCCR4_DBUS_SIZE2_SHIFT) |
- (((CFG_SDMODE_CAS_LAT <<4) | (CFG_SDMODE_WRAP <<3) |
- (val ? 2 : 3)) << MCCR4_SDMODE_SHIFT) |
- (CFG_ACTORW << MCCR4_ACTTORW_SHIFT) |
- (((CFG_BSTOPRE & 0x03c0) >> 6) <<MCCR4_BSTOPRE6TO9_SHIFT ));
+ CONFIG_WRITE_WORD(MCCR4,
+ (CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) |
+ (CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
+ (CFG_EXTROM ? MCCR4_EXTROM : 0) |
+ (CFG_REGDIMM ? MCCR4_REGDIMM : 0) |
+ (CFG_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) |
+ ((CFG_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) |
+ (CFG_DBUS_SIZE2 << MCCR4_DBUS_SIZE2_SHIFT) |
+ (((CFG_SDMODE_CAS_LAT <<4) | (CFG_SDMODE_WRAP <<3) |
+ (val ? 2 : 3)) << MCCR4_SDMODE_SHIFT) |
+ (CFG_ACTORW << MCCR4_ACTTORW_SHIFT) |
+ (((CFG_BSTOPRE & 0x03c0) >> 6) <<MCCR4_BSTOPRE6TO9_SHIFT ));
#else
#error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
#endif
- CONFIG_WRITE_WORD(MSAR1,
- ( (CFG_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
- (((CFG_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
- (((CFG_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
- (((CFG_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
- CONFIG_WRITE_WORD(EMSAR1,
- ( (CFG_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
- (((CFG_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
- (((CFG_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
- (((CFG_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
- CONFIG_WRITE_WORD(MSAR2,
- ( (CFG_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
- (((CFG_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
- (((CFG_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
- (((CFG_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
- CONFIG_WRITE_WORD(EMSAR2,
- ( (CFG_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
- (((CFG_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
- (((CFG_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
- (((CFG_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
- CONFIG_WRITE_WORD(MEAR1,
- ( (CFG_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
- (((CFG_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
- (((CFG_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
- (((CFG_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
- CONFIG_WRITE_WORD(EMEAR1,
- ( (CFG_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
- (((CFG_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
- (((CFG_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
- (((CFG_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
- CONFIG_WRITE_WORD(MEAR2,
- ( (CFG_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
- (((CFG_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
- (((CFG_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
- (((CFG_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
- CONFIG_WRITE_WORD(EMEAR2,
- ( (CFG_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
- (((CFG_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
- (((CFG_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
- (((CFG_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
-
- CONFIG_WRITE_BYTE(ODCR, CFG_ODCR);
+ CONFIG_WRITE_WORD(MSAR1,
+ ( (CFG_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
+ (((CFG_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
+ (((CFG_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
+ (((CFG_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
+ CONFIG_WRITE_WORD(EMSAR1,
+ ( (CFG_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
+ (((CFG_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
+ (((CFG_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
+ (((CFG_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
+ CONFIG_WRITE_WORD(MSAR2,
+ ( (CFG_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
+ (((CFG_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
+ (((CFG_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
+ (((CFG_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
+ CONFIG_WRITE_WORD(EMSAR2,
+ ( (CFG_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
+ (((CFG_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
+ (((CFG_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
+ (((CFG_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
+ CONFIG_WRITE_WORD(MEAR1,
+ ( (CFG_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
+ (((CFG_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
+ (((CFG_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
+ (((CFG_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
+ CONFIG_WRITE_WORD(EMEAR1,
+ ( (CFG_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
+ (((CFG_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
+ (((CFG_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
+ (((CFG_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
+ CONFIG_WRITE_WORD(MEAR2,
+ ( (CFG_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
+ (((CFG_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
+ (((CFG_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
+ (((CFG_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
+ CONFIG_WRITE_WORD(EMEAR2,
+ ( (CFG_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
+ (((CFG_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
+ (((CFG_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
+ (((CFG_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
+
+ CONFIG_WRITE_BYTE(ODCR, CFG_ODCR);
#ifdef CFG_DLL_MAX_DELAY
CONFIG_WRITE_BYTE(MIOCR1, CFG_DLL_MAX_DELAY); /* needed to make DLL lock */
#endif
CONFIG_WRITE_BYTE(MIOCR2, CFG_SDRAM_DSCD); /* change memory input */
#endif /* setup & hold time */
- CONFIG_WRITE_BYTE(MBER,
- CFG_BANK0_ENABLE |
- (CFG_BANK1_ENABLE << 1) |
- (CFG_BANK2_ENABLE << 2) |
- (CFG_BANK3_ENABLE << 3) |
- (CFG_BANK4_ENABLE << 4) |
- (CFG_BANK5_ENABLE << 5) |
- (CFG_BANK6_ENABLE << 6) |
- (CFG_BANK7_ENABLE << 7));
+ CONFIG_WRITE_BYTE(MBER,
+ CFG_BANK0_ENABLE |
+ (CFG_BANK1_ENABLE << 1) |
+ (CFG_BANK2_ENABLE << 2) |
+ (CFG_BANK3_ENABLE << 3) |
+ (CFG_BANK4_ENABLE << 4) |
+ (CFG_BANK5_ENABLE << 5) |
+ (CFG_BANK6_ENABLE << 6) |
+ (CFG_BANK7_ENABLE << 7));
#ifdef CFG_PGMAX
- CONFIG_WRITE_BYTE(MPMR, CFG_PGMAX);
+ CONFIG_WRITE_BYTE(MPMR, CFG_PGMAX);
#endif
- /* ! Wait 200us before initialize other registers */
- /*FIXME: write a decent udelay wait */
- __asm__ __volatile__(
- " mtctr %0 \n \
- 0: bdnz 0b\n"
- :
- : "r" (0x10000));
+ /* ! Wait 200us before initialize other registers */
+ /*FIXME: write a decent udelay wait */
+ __asm__ __volatile__(
+ " mtctr %0 \n \
+ 0: bdnz 0b\n"
+ :
+ : "r" (0x10000));
- CONFIG_READ_WORD(MCCR1, val);
- CONFIG_WRITE_WORD(MCCR1, val | MCCR1_MEMGO); /* set memory access going */
- __asm__ __volatile__("eieio");
+ CONFIG_READ_WORD(MCCR1, val);
+ CONFIG_WRITE_WORD(MCCR1, val | MCCR1_MEMGO); /* set memory access going */
+ __asm__ __volatile__("eieio");
#endif /* !CONFIG_MOUSSE && !CONFIG_BMW */
}
#ifdef CONFIG_MOUSSE
#ifdef INCLUDE_MPC107_REPORT
-struct MPC107_s{
- unsigned int iobase;
- char desc[120];
-} MPC107Regs[] ={
- {BMC_BASE+0x0, "MPC107 Vendor/Device ID"},
- {BMC_BASE+0x4, "MPC107 PCI Command/Status Register"},
- {BMC_BASE+0x8, "MPC107 Revision"},
- {BMC_BASE+0xC, "MPC107 Cache Line Size"},
- {BMC_BASE+0x10, "MPC107 LMBAR"},
- {BMC_BASE+0x14, "MPC824x PCSR"},
- {BMC_BASE+0xA8, "MPC824x PICR1"},
- {BMC_BASE+0xAC, "MPC824x PICR2"},
- {BMC_BASE+0x46, "MPC824x PACR"},
- {BMC_BASE+0x310, "MPC824x ITWR"},
- {BMC_BASE+0x300, "MPC824x OMBAR"},
- {BMC_BASE+0x308, "MPC824x OTWR"},
- {BMC_BASE+0x14, "MPC107 Peripheral Control and Status Register"},
- {BMC_BASE+0x78, "MPC107 EUMBAR"},
- {BMC_BASE+0xC0, "MPC107 Processor Bus Error Status"},
- {BMC_BASE+0xC4, "MPC107 PCI Bus Error Status"},
- {BMC_BASE+0xC8, "MPC107 Processor/PCI Error Address"},
- {BMC_BASE+0xE0, "MPC107 AMBOR Register"},
- {BMC_BASE+0xF0, "MPC107 MCCR1 Register"},
- {BMC_BASE+0xF4, "MPC107 MCCR2 Register"},
- {BMC_BASE+0xF8, "MPC107 MCCR3 Register"},
- {BMC_BASE+0xFC, "MPC107 MCCR4 Register"}
+struct MPC107_s {
+ unsigned int iobase;
+ char desc[120];
+} MPC107Regs[] = {
+ { BMC_BASE + 0x00, "MPC107 Vendor/Device ID" },
+ { BMC_BASE + 0x04, "MPC107 PCI Command/Status Register" },
+ { BMC_BASE + 0x08, "MPC107 Revision" },
+ { BMC_BASE + 0x0C, "MPC107 Cache Line Size" },
+ { BMC_BASE + 0x10, "MPC107 LMBAR" },
+ { BMC_BASE + 0x14, "MPC824x PCSR" },
+ { BMC_BASE + 0xA8, "MPC824x PICR1" },
+ { BMC_BASE + 0xAC, "MPC824x PICR2" },
+ { BMC_BASE + 0x46, "MPC824x PACR" },
+ { BMC_BASE + 0x310, "MPC824x ITWR" },
+ { BMC_BASE + 0x300, "MPC824x OMBAR" },
+ { BMC_BASE + 0x308, "MPC824x OTWR" },
+ { BMC_BASE + 0x14, "MPC107 Peripheral Control and Status Register" },
+ { BMC_BASE + 0x78, "MPC107 EUMBAR" },
+ { BMC_BASE + 0xC0, "MPC107 Processor Bus Error Status" },
+ { BMC_BASE + 0xC4, "MPC107 PCI Bus Error Status" },
+ { BMC_BASE + 0xC8, "MPC107 Processor/PCI Error Address" },
+ { BMC_BASE + 0xE0, "MPC107 AMBOR Register" },
+ { BMC_BASE + 0xF0, "MPC107 MCCR1 Register" },
+ { BMC_BASE + 0xF4, "MPC107 MCCR2 Register" },
+ { BMC_BASE + 0xF8, "MPC107 MCCR3 Register" },
+ { BMC_BASE + 0xFC, "MPC107 MCCR4 Register" },
};
#define N_MPC107_Regs (sizeof(MPC107Regs)/sizeof(MPC107Regs[0]))
#endif /* INCLUDE_MPC107_REPORT */
bcm570x.o bcm570x_autoneg.o cfb_console.o cfi_flash.o \
cs8900.o ct69000.o dataflash.o dc2114x.o \
e1000.o eepro100.o \
- i8042.o i82365.o inca-ip_sw.o \
+ i8042.o i82365.o inca-ip_sw.o keyboard.o \
lan91c96.o natsemi.o netarm_eth.o \
ns16550.o ns8382x.o ns87308.o \
pci.o pci_auto.o pci_indirect.o \
pcnet.o plb2800_eth.o \
- ps2ser.o ps2mult.o pc_keyb.o keyboard.o \
+ ps2ser.o ps2mult.o pc_keyb.o \
rtl8019.o rtl8139.o rtl8169.o \
- s3c24x0_i2c.o sed13806.o sed156x.o \
+ s3c24x0_i2c.o s3c4510b_eth.o s3c4510b_uart.o \
+ sed13806.o sed156x.o \
serial.o serial_max3100.o serial_pl010.o serial_pl011.o \
serial_xuartlite.o sl811_usb.o \
smc91111.o smiLynxEM.o status_led.o sym53c8xx.o \
extern void eth_halt (void);
extern int eth_rx (void);
extern int eth_send (volatile void *packet, int length);
+#if 0
static int smc_hw_init (void);
+#endif
/*
* This is called by register_netdev(). It is responsible for
}
+#if 0
/*-------------------------------------------------------------------------
* smc_hw_init()
*
}
return 0;
}
+#endif /* 0 */
#endif /* COMMANDS & CFG_NET */
#endif
#if PCNET_DEBUG_LEVEL > 0
-#define DEBUG1(fmt,args...) printf (fmt ,##args)
+#define PCNET_DEBUG1(fmt,args...) printf (fmt ,##args)
#if PCNET_DEBUG_LEVEL > 1
-#define DEBUG2(fmt,args...) printf (fmt ,##args)
+#define PCNET_DEBUG2(fmt,args...) printf (fmt ,##args)
#else
-#define DEBUG2(fmt,args...)
+#define PCNET_DEBUG2(fmt,args...)
#endif
#else
-#define DEBUG1(fmt,args...)
-#define DEBUG2(fmt,args...)
+#define PCNET_DEBUG1(fmt,args...)
+#define PCNET_DEBUG2(fmt,args...)
#endif
#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) \
u16 command, status;
int dev_nr = 0;
- DEBUG1("\npcnet_initialize...\n");
+ PCNET_DEBUG1("\npcnet_initialize...\n");
for (dev_nr = 0; ; dev_nr++) {
pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &dev->iobase);
dev->iobase &= ~0xf;
- DEBUG1("%s: devbusfn=0x%x iobase=0x%x: ",
+ PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%x: ",
dev->name, devbusfn, dev->iobase);
command = PCI_COMMAND_IO | PCI_COMMAND_MASTER;
return -1;
}
- DEBUG1("AMD %s\n", chipname);
+ PCNET_DEBUG1("AMD %s\n", chipname);
#ifdef PCNET_HAS_PROM
/*
int i, val;
u32 addr;
- DEBUG1("%s: pcnet_init...\n", dev->name);
+ PCNET_DEBUG1("%s: pcnet_init...\n", dev->name);
/* Switch pcnet to 32bit mode */
pcnet_write_bcr (dev, 20, 2);
lp->rx_ring[i].base = PCI_TO_MEM_LE(dev, lp->rx_buf[i]);
lp->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ);
lp->rx_ring[i].status = cpu_to_le16(0x8000);
- DEBUG1("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n",
+ PCNET_DEBUG1("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n",
i, lp->rx_ring[i].base, lp->rx_ring[i].buf_length,
lp->rx_ring[i].status);
}
/*
* Setup Init Block.
*/
- DEBUG1("Init block at 0x%p: MAC", &lp->init_block);
+ PCNET_DEBUG1("Init block at 0x%p: MAC", &lp->init_block);
for (i = 0; i < 6; i++) {
lp->init_block.phys_addr[i] = dev->enetaddr[i];
- DEBUG1(" %02x", lp->init_block.phys_addr[i]);
+ PCNET_DEBUG1(" %02x", lp->init_block.phys_addr[i]);
}
lp->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS |
lp->init_block.rx_ring = PCI_TO_MEM_LE(dev, lp->rx_ring);
lp->init_block.tx_ring = PCI_TO_MEM_LE(dev, lp->tx_ring);
- DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n",
+ PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n",
lp->init_block.tlen_rlen,
lp->init_block.rx_ring, lp->init_block.tx_ring);
int i, status;
struct pcnet_tx_head *entry = &lp->tx_ring[lp->cur_tx];
- DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len, packet);
+ PCNET_DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len, packet);
/* Wait for completion by testing the OWN bit */
for (i = 1000; i > 0; i--) {
if ((status & 0x8000) == 0)
break;
udelay(100);
- DEBUG2(".");
+ PCNET_DEBUG2(".");
}
if (i <= 0) {
printf("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n",
if (++lp->cur_tx >= TX_RING_SIZE)
lp->cur_tx = 0;
- DEBUG2("done\n");
+ PCNET_DEBUG2("done\n");
return pkt_len;
}
if (status != 0x03) { /* There was an error. */
printf("%s: Rx%d", dev->name, lp->cur_rx);
- DEBUG1(" (status=0x%x)", status);
+ PCNET_DEBUG1(" (status=0x%x)", status);
if (status & 0x20) printf(" Frame");
if (status & 0x10) printf(" Overflow");
if (status & 0x08) printf(" CRC");
dev->name, lp->cur_rx, pkt_len);
} else {
NetReceive(lp->rx_buf[lp->cur_rx], pkt_len);
- DEBUG2("Rx%d: %d bytes from 0x%p\n",
+ PCNET_DEBUG2("Rx%d: %d bytes from 0x%p\n",
lp->cur_rx, pkt_len, lp->rx_buf[lp->cur_rx]);
}
}
{
int i;
- DEBUG1("%s: pcnet_halt...\n", dev->name);
+ PCNET_DEBUG1("%s: pcnet_halt...\n", dev->name);
/* Reset the PCnet controller */
pcnet_reset (dev);
--- /dev/null
+/***********************************************************************
+ *
+ * Copyright (c) 2004 Cucy Systems (http://www.cucy.com)
+ * Curt Brune <curt@cucy.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Description: Ethernet interface for Samsung S3C4510B SoC
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_DRIVER_S3C4510_ETH
+
+#include <command.h>
+#include <net.h>
+#include <asm/hardware.h>
+#include "s3c4510b_eth.h"
+
+static TX_FrameDescriptor txFDbase[ETH_MaxTxFrames];
+static MACFrame txFrameBase[ETH_MaxTxFrames];
+static RX_FrameDescriptor rxFDbase[PKTBUFSRX];
+static ETH m_eth;
+
+static s32 TxFDinit( ETH *eth) {
+
+ s32 i;
+ MACFrame *txFrmBase;
+
+ /* disable cache for access to the TX buffers */
+ txFrmBase = (MACFrame *)( (u32)txFrameBase | CACHE_DISABLE_MASK);
+
+ /* store start of Tx descriptors and set current */
+ eth->m_curTX_FD = (TX_FrameDescriptor *) ((u32)txFDbase | CACHE_DISABLE_MASK);
+ eth->m_baseTX_FD = eth->m_curTX_FD;
+
+ for ( i = 0; i < ETH_MaxTxFrames; i++) {
+ eth->m_baseTX_FD[i].m_frameDataPtr.bf.dataPtr = (u32)&txFrmBase[i];
+ eth->m_baseTX_FD[i].m_frameDataPtr.bf.owner = 0x0; /* CPU owner */
+ eth->m_baseTX_FD[i].m_opt.ui = 0x0;
+ eth->m_baseTX_FD[i].m_status.ui = 0x0;
+ eth->m_baseTX_FD[i].m_nextFD = ð->m_baseTX_FD[i+1];
+ }
+
+ /* make the list circular */
+ eth->m_baseTX_FD[i-1].m_nextFD = ð->m_baseTX_FD[0];
+
+ PUT_REG( REG_BDMATXPTR, (u32)eth->m_curTX_FD);
+
+ return 0;
+}
+
+static s32 RxFDinit( ETH *eth) {
+
+ s32 i;
+ /* MACFrame *rxFrmBase; */
+
+ /* disable cache for access to the RX buffers */
+ /* rxFrmBase = (MACFrame *)( (u32)rxFrameBase | CACHE_DISABLE_MASK); */
+
+ /* store start of Rx descriptors and set current */
+ eth->m_curRX_FD = (RX_FrameDescriptor *)((u32)rxFDbase | CACHE_DISABLE_MASK);
+ eth->m_baseRX_FD = eth->m_curRX_FD;
+ for ( i = 0; i < PKTBUFSRX; i++) {
+ eth->m_baseRX_FD[i].m_frameDataPtr.bf.dataPtr = (u32)NetRxPackets[i] | CACHE_DISABLE_MASK;
+ eth->m_baseRX_FD[i].m_frameDataPtr.bf.owner = 0x1; /* BDMA owner */
+ eth->m_baseRX_FD[i].m_reserved = 0x0;
+ eth->m_baseRX_FD[i].m_status.ui = 0x0;
+ eth->m_baseRX_FD[i].m_nextFD = ð->m_baseRX_FD[i+1];
+ }
+
+ /* make the list circular */
+ eth->m_baseRX_FD[i-1].m_nextFD = ð->m_baseRX_FD[0];
+
+ PUT_REG( REG_BDMARXPTR, (u32)eth->m_curRX_FD);
+
+ return 0;
+}
+
+/*
+ * Public u-boot interface functions below
+ */
+
+int eth_init(bd_t *bis)
+{
+
+ ETH *eth = &m_eth;
+
+ /* store our MAC address */
+ eth->m_mac = bis->bi_enetaddr;
+
+ /* setup DBMA and MAC */
+ PUT_REG( REG_BDMARXCON, ETH_BRxRS); /* reset BDMA RX machine */
+ PUT_REG( REG_BDMATXCON, ETH_BTxRS); /* reset BDMA TX machine */
+ PUT_REG( REG_MACCON , ETH_SwReset); /* reset MAC machine */
+ PUT_REG( REG_BDMARXLSZ, sizeof(MACFrame));
+ PUT_REG( REG_MACCON , 0); /* reset MAC machine */
+
+ /* init frame descriptors */
+ TxFDinit( eth);
+ RxFDinit( eth);
+
+ /* init the CAM with our MAC address */
+ PUT_REG( REG_CAM_BASE, (eth->m_mac[0] << 24) |
+ (eth->m_mac[1] << 16) |
+ (eth->m_mac[2] << 8) |
+ (eth->m_mac[3]));
+ PUT_REG( REG_CAM_BASE + 0x4, (eth->m_mac[4] << 24) |
+ (eth->m_mac[5] << 16));
+
+ /* enable CAM address 1 -- the MAC we just loaded */
+ PUT_REG( REG_CAMEN, 0x1);
+
+ PUT_REG( REG_CAMCON,
+ ETH_BroadAcc | /* accept broadcast packetes */
+ ETH_CompEn); /* enable compare mode (check against the CAM) */
+
+ /* configure the BDMA Transmitter control */
+ PUT_REG( REG_BDMATXCON,
+ ETH_BTxBRST | /* BDMA Tx burst size 16 words */
+ ETH_BTxMSL110 | /* BDMA Tx wait to fill 6/8 of the BDMA */
+ ETH_BTxSTSKO | /* BDMA Tx interrupt(Stop) on non-owner TX FD */
+ ETH_BTxEn); /* BDMA Tx Enable */
+
+ /* configure the MAC Transmitter control */
+ PUT_REG( REG_MACTXCON,
+ ETH_EnComp | /* interrupt when the MAC transmits or discards packet */
+ ETH_TxEn); /* MAC transmit enable */
+
+ /* configure the BDMA Receiver control */
+ PUT_REG( REG_BDMARXCON,
+ ETH_BRxBRST | /* BDMA Rx Burst Size 16 words */
+ ETH_BRxSTSKO | /* BDMA Rx interrupt(Stop) on non-owner RX FD */
+ ETH_BRxMAINC | /* BDMA Rx Memory Address increment */
+ ETH_BRxDIE | /* BDMA Rx Every Received Frame Interrupt Enable */
+ ETH_BRxNLIE | /* BDMA Rx NULL List Interrupt Enable */
+ ETH_BRxNOIE | /* BDMA Rx Not Owner Interrupt Enable */
+ ETH_BRxLittle | /* BDMA Rx Little endian */
+ ETH_BRxEn); /* BDMA Rx Enable */
+
+ /* configure the MAC Receiver control */
+ PUT_REG( REG_MACRXCON,
+ ETH_RxEn); /* MAC ETH_RxEn */
+
+ return 0;
+
+}
+
+/* Send a packet */
+s32 eth_send(volatile void *packet, s32 length)
+{
+
+ u32 i;
+ ETH *eth = &m_eth;
+
+ if ( eth->m_curTX_FD->m_frameDataPtr.bf.owner) {
+ printf(__FUNCTION__"(): TX Frame. CPU not owner.\n");
+ return -1;
+ }
+
+ /* copy user data into frame data pointer */
+ memcpy((void *)eth->m_curTX_FD->m_frameDataPtr.bf.dataPtr,
+ (void *)packet,
+ length);
+
+ /* Set TX Frame flags */
+ eth->m_curTX_FD->m_opt.bf.widgetAlign = 0;
+ eth->m_curTX_FD->m_opt.bf.frameDataDir = 1;
+ eth->m_curTX_FD->m_opt.bf.littleEndian = 1;
+ eth->m_curTX_FD->m_opt.bf.macTxIrqEnbl = 1;
+ eth->m_curTX_FD->m_opt.bf.no_crc = 0;
+ eth->m_curTX_FD->m_opt.bf.no_padding = 0;
+
+ /* Set TX Frame length */
+ eth->m_curTX_FD->m_status.bf.len = length;
+
+ /* Change ownership to BDMA */
+ eth->m_curTX_FD->m_frameDataPtr.bf.owner = 1;
+
+ /* Enable MAC and BDMA Tx control register */
+ SET_REG( REG_BDMATXCON, ETH_BTxEn);
+ SET_REG( REG_MACTXCON, ETH_TxEn);
+
+ /* poll on TX completion status */
+ while ( !eth->m_curTX_FD->m_status.bf.complete) {
+ /* sleep */
+ for ( i = 0; i < 0x10000; i ++);
+ }
+
+ /* Change the Tx frame descriptor for next use */
+ eth->m_curTX_FD = eth->m_curTX_FD->m_nextFD;
+
+ return 0;
+}
+
+/* Check for received packets */
+s32 eth_rx (void)
+{
+ s32 nLen = 0;
+ ETH *eth = &m_eth;
+
+ /* check if packet ready */
+ if ( (GET_REG( REG_BDMASTAT)) & ETH_S_BRxRDF) {
+ /* process all waiting packets */
+ while ( !eth->m_curRX_FD->m_frameDataPtr.bf.owner) {
+ nLen = eth->m_curRX_FD->m_status.bf.len;
+ /* call back u-boot -- may call eth_send() */
+ NetReceive ((u8 *)eth->m_curRX_FD->m_frameDataPtr.ui, nLen);
+ /* set owner back to CPU */
+ eth->m_curRX_FD->m_frameDataPtr.bf.owner = 1;
+ /* clear status */
+ eth->m_curRX_FD->m_status.ui = 0x0;
+ /* advance to next descriptor */
+ eth->m_curRX_FD = eth->m_curRX_FD->m_nextFD;
+ /* clear received frame bit */
+ PUT_REG( REG_BDMASTAT, ETH_S_BRxRDF);
+ }
+ }
+
+ return nLen;
+}
+
+/* Halt ethernet engine */
+void eth_halt(void)
+{
+ /* disable MAC */
+ PUT_REG( REG_MACCON, ETH_HaltReg);
+}
+
+#endif
--- /dev/null
+#ifndef __S3C4510B_ETH_H
+#define __S3C4510B_ETH_H
+/*
+ * Copyright (c) 2004 Cucy Systems (http://www.cucy.com)
+ * Curt Brune <curt@cucy.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * MODULE: $Id:$
+ * Description: Ethernet interface
+ * Runtime Env: ARM7TDMI
+ * Change History:
+ * 03-02-04 Create (Curt Brune) curt@cucy.com
+ *
+ */
+
+#define __packed __attribute__ ((packed))
+
+#define ETH_MAC_ADDR_SIZE (6) /* dst,src addr is 6bytes each */
+#define ETH_MaxTxFrames (16) /* Max number of Tx Frames */
+
+/* Buffered DMA Receiver Control Register */
+#define ETH_BRxBRST 0x0000F /* BDMA Rx Burst Size * BRxBRST */
+ /* = Burst Data Size 16 */
+#define ETH_BRxSTSKO 0x00020 /* BDMA Rx Stop/Skip Frame or Interrupt(=1) */
+ /* case of not OWNER the current Frame */
+#define ETH_BRxMAINC 0x00040 /* BDMA Rx Memory Address Inc/Dec */
+#define ETH_BRxDIE 0x00080 /* BDMA Rx Every Received Frame Interrupt Enable */
+#define ETH_BRxNLIE 0x00100 /* BDMA Rx NULL List Interrupt Enable */
+#define ETH_BRxNOIE 0x00200 /* BDMA Rx Not Owner Interrupt Enable */
+#define ETH_BRxMSOIE 0x00400 /* BDMA Rx Maximum Size over Interrupr Enable */
+#define ETH_BRxLittle 0x00800 /* BDMA Rx Big/Little Endian */
+#define ETH_BRxBig 0x00000 /* BDMA Rx Big/Little Endian */
+#define ETH_BRxWA01 0x01000 /* BDMA Rx Word Alignment- one invalid byte */
+#define ETH_BRxWA10 0x02000 /* BDMA Rx Word Alignment- two invalid byte */
+#define ETH_BRxWA11 0x03000 /* BDMA Rx Word Alignment- three invalid byte */
+#define ETH_BRxEn 0x04000 /* BDMA Rx Enable */
+#define ETH_BRxRS 0x08000 /* BDMA Rx Reset */
+#define ETH_RxEmpty 0x10000 /* BDMA Rx Buffer empty interrupt */
+#define ETH_BRxEarly 0x20000 /* BDMA Rx Early notify Interrupt */
+
+/* Buffered DMA Trasmit Control Register(BDMATXCON) */
+#define ETH_BTxBRST 0x0000F /* BDMA Tx Burst Size = 16 */
+#define ETH_BTxSTSKO 0x00020 /* BDMA Tx Stop/Skip Frame or Interrupt in case */
+ /* of not Owner the current frame */
+#define ETH_BTxCPIE 0x00080 /* BDMA Tx Complete to send control */
+ /* packet Enable */
+#define ETH_BTxNOIE 0x00200 /* BDMA Tx Buffer Not Owner */
+#define ETH_BTxEmpty 0x00400 /* BDMA Tx Buffer Empty Interrupt */
+
+/* BDMA Tx buffer can be moved to the MAC Tx IO when the new frame comes in. */
+#define ETH_BTxMSL000 0x00000 /* No wait to fill the BDMA */
+#define ETH_BTxMSL001 0x00800 /* wait to fill 1/8 of the BDMA */
+#define ETH_BTxMSL010 0x01000 /* wait to fill 2/8 of the BDMA */
+#define ETH_BTxMSL011 0x01800 /* wait to fill 3/8 of the BDMA */
+#define ETH_BTxMSL100 0x02000 /* wait to fill 4/8 of the BDMA */
+#define ETH_BTxMSL101 0x02800 /* wait to fill 5/8 of the BDMA */
+#define ETH_BTxMSL110 0x03000 /* wait to fill 6/8 of the BDMA */
+#define ETH_BTxMSL111 0x03800 /* wait to fill 7/8 of the BDMA */
+#define ETH_BTxEn 0x04000 /* BDMA Tx Enable */
+#define ETH_BTxRS 0x08000 /* BDMA Tx Reset */
+
+/* BDMA Status Register */
+#define ETH_S_BRxRDF 0x00001 /* BDMA Rx Done Every Received Frame */
+#define ETH_S_BRxNL 0x00002 /* BDMA Rx NULL List */
+#define ETH_S_BRxNO 0x00004 /* BDMA Rx Not Owner */
+#define ETH_S_BRxMSO 0x00008 /* BDMA Rx Maximum Size Over */
+#define ETH_S_BRxEmpty 0x00010 /* BDMA Rx Buffer Empty */
+#define ETH_S_BRxSEarly 0x00020 /* Early Notify */
+#define ETH_S_BRxFRF 0x00080 /* One more frame data in BDMA receive buffer */
+#define ETH_S_BTxCCP 0x10000 /* BDMA Tx Complete to send Control Packet */
+#define ETH_S_BTxNL 0x20000 /* BDMA Tx Null List */
+#define ETH_S_BTxNO 0x40000 /* BDMA Tx Not Owner */
+#define ETH_S_BTxEmpty 0x100000 /* BDMA Tx Buffer Empty */
+
+/* MAC Control Register */
+#define ETH_HaltReg 0x0001 /* stop transmission and reception */
+ /* after completion of any current packets */
+#define ETH_HaltImm 0x0002 /* Stop transmission and reception immediately */
+#define ETH_SwReset 0x0004 /* reset all Ethernet controller state machines */
+ /* and FIFOs */
+#define ETH_FullDup 0x0008 /* allow transmission to begin while reception */
+ /* is occurring */
+#define ETH_MACLoop 0x0010 /* MAC loopback */
+#define ETH_ConnM00 0x0000 /* Automatic-default */
+#define ETH_ConnM01 0x0020 /* Force 10Mbits endec */
+#define ETH_ConnM10 0x0040 /* Force MII (rate determined by MII clock */
+#define ETH_MIIOFF 0x0040 /* Force MII (rate determined by MII clock */
+#define ETH_Loop10 0x0080 /* Loop 10Mbps */
+#define ETH_MissRoll 0x0400 /* Missed error counter rolled over */
+#define ETH_MDCOFF 0x1000 /* MII Station Management Clock Off */
+#define ETH_EnMissRoll 0x2000 /* Interrupt when missed error counter rolls */
+ /* over */
+#define ETH_Link10 0x8000 /* Link status 10Mbps */
+
+/* CAM control register(CAMCON) */
+#define ETH_StationAcc 0x0001 /* Accept any packet with a unicast station */
+ /* address */
+#define ETH_GroupAcc 0x0002 /* Accept any packet with multicast-group */
+ /* station address */
+#define ETH_BroadAcc 0x0004 /* Accept any packet with a broadcast station */
+ /* address */
+#define ETH_NegCAM 0x0008 /* 0: Accept packets CAM recognizes, */
+ /* reject others */
+ /* 1: reject packets CAM recognizes, */
+ /* accept others */
+#define ETH_CompEn 0x0010 /* Compare Enable mode */
+
+/* Transmit Control Register(MACTXCON) */
+#define ETH_TxEn 0x0001 /* transmit Enable */
+#define ETH_TxHalt 0x0002 /* Transmit Halt Request */
+#define ETH_NoPad 0x0004 /* suppress Padding */
+#define ETH_NoCRC 0x0008 /* Suppress CRC */
+#define ETH_FBack 0x0010 /* Fast Back-off */
+#define ETH_NoDef 0x0020 /* Disable the defer counter */
+#define ETH_SdPause 0x0040 /* Send Pause */
+#define ETH_MII10En 0x0080 /* MII 10Mbps mode enable */
+#define ETH_EnUnder 0x0100 /* Enable Underrun */
+#define ETH_EnDefer 0x0200 /* Enable Deferral */
+#define ETH_EnNCarr 0x0400 /* Enable No Carrier */
+#define ETH_EnExColl 0x0800 /* interrupt if 16 collision occur */
+ /* in the same packet */
+#define ETH_EnLateColl 0x1000 /* interrupt if collision occurs after */
+ /* 512 bit times(64 bytes times) */
+#define ETH_EnTxPar 0x2000 /* interrupt if the MAC transmit FIFO */
+ /* has a parity error */
+#define ETH_EnComp 0x4000 /* interrupt when the MAC transmits or */
+ /* discards one packet */
+
+/* Transmit Status Register(MACTXSTAT) */
+#define ETH_ExColl 0x0010 /* Excessive collision */
+#define ETH_TxDeffered 0x0020 /* set if 16 collisions occur for same packet */
+#define ETH_Paused 0x0040 /* packet waited because of pause during */
+ /* transmission */
+#define ETH_IntTx 0x0080 /* set if transmission of packet causes an */
+ /* interrupt condiftion */
+#define ETH_Under 0x0100 /* MAC transmit FIFO becomes empty during */
+ /* transmission */
+#define ETH_Defer 0x0200 /* MAC defers for MAC deferral */
+#define ETH_NCarr 0x0400 /* No carrier sense detected during the */
+ /* transmission of a packet */
+#define ETH_SQE 0x0800 /* Signal Quality Error */
+#define ETH_LateColl 0x1000 /* a collision occures after 512 bit times */
+#define ETH_TxPar 0x2000 /* MAC transmit FIFO has detected a parity error */
+#define ETH_Comp 0x4000 /* MAC transmit or discards one packet */
+#define ETH_TxHalted 0x8000 /* Transmission was halted by clearing */
+ /* TxEn or Halt immedite */
+
+/* Receive Control Register (MACRXCON) */
+#define ETH_RxEn 0x0001
+#define ETH_RxHalt 0x0002
+#define ETH_LongEn 0x0004
+#define ETH_ShortEn 0x0008
+#define ETH_StripCRC 0x0010
+#define ETH_PassCtl 0x0020
+#define ETH_IgnoreCRC 0x0040
+#define ETH_EnAlign 0x0100
+#define ETH_EnCRCErr 0x0200
+#define ETH_EnOver 0x0400
+#define ETH_EnLongErr 0x0800
+#define ETH_EnRxPar 0x2000
+#define ETH_EnGood 0x4000
+
+/* Receive Status Register(MACRXSTAT) */
+#define ETH_MCtlRecd 0x0020
+#define ETH_MIntRx 0x0040
+#define ETH_MRx10Stat 0x0080
+#define ETH_MAllignErr 0x0100
+#define ETH_MCRCErr 0x0200
+#define ETH_MOverflow 0x0400
+#define ETH_MLongErr 0x0800
+#define ETH_MRxPar 0x2000
+#define ETH_MRxGood 0x4000
+#define ETH_MRxHalted 0x8000
+
+/* type of ethernet packets */
+#define ETH_TYPE_ARP (0x0806)
+#define ETH_TYPE_IP (0x0800)
+
+#define ETH_HDR_SIZE (14)
+
+/* bit field for frame data pointer word */
+typedef struct __BF_FrameDataPtr {
+ u32 dataPtr:31;
+ u32 owner: 1;
+} BF_FrameDataPtr;
+
+typedef union _FrameDataPtr {
+ u32 ui;
+ BF_FrameDataPtr bf;
+} FrameDataPtr;
+
+typedef struct __BF_TX_Options {
+ u32 no_padding: 1;
+ u32 no_crc: 1;
+ u32 macTxIrqEnbl: 1;
+ u32 littleEndian: 1;
+ u32 frameDataDir: 1;
+ u32 widgetAlign: 2;
+ u32 reserved:25;
+} BF_TX_Options;
+
+typedef union _TX_Options {
+ u32 ui;
+ BF_TX_Options bf;
+} TX_Options;
+
+typedef struct __BF_RX_Status {
+ u32 len:16; /* frame length */
+ u32 reserved1: 3;
+ u32 overMax: 1;
+ u32 reserved2: 1;
+ u32 ctrlRcv: 1;
+ u32 intRx: 1;
+ u32 rx10stat: 1;
+ u32 alignErr: 1;
+ u32 crcErr: 1;
+ u32 overFlow: 1;
+ u32 longErr: 1;
+ u32 reserved3: 1;
+ u32 parityErr: 1;
+ u32 good: 1;
+ u32 halted: 1;
+} BF_RX_Status;
+
+typedef union _RX_Status {
+ u32 ui;
+ BF_RX_Status bf;
+} RX_Status;
+
+typedef struct __BF_TX_Status {
+ u32 len:16; /* frame length */
+ u32 txCollCnt: 4;
+ u32 exColl: 1;
+ u32 txDefer: 1;
+ u32 paused: 1;
+ u32 intTx: 1;
+ u32 underRun: 1;
+ u32 defer: 1;
+ u32 noCarrier: 1;
+ u32 SQErr: 1;
+ u32 lateColl: 1;
+ u32 parityErr: 1;
+ u32 complete: 1;
+ u32 halted: 1;
+} BF_TX_Status;
+
+typedef union _TX_Status {
+ u32 ui;
+ BF_TX_Status bf;
+} TX_Status;
+
+/* TX descriptor structure */
+typedef struct __TX_FrameDescriptor {
+ volatile FrameDataPtr m_frameDataPtr;
+ TX_Options m_opt;
+ volatile TX_Status m_status;
+ struct __TX_FrameDescriptor *m_nextFD;
+} TX_FrameDescriptor;
+
+/* RX descriptor structure */
+typedef struct __RX_FrameDescriptor {
+ volatile FrameDataPtr m_frameDataPtr;
+ u32 m_reserved;
+ volatile RX_Status m_status;
+ struct __RX_FrameDescriptor *m_nextFD;
+} RX_FrameDescriptor;
+
+/* MAC Frame Structure */
+typedef struct __MACFrame {
+ u8 m_dstAddr[6] __packed;
+ u8 m_srcAddr[6] __packed;
+ u16 m_lengthOrType __packed;
+ u8 m_payload[1506] __packed;
+} MACFrame;
+
+/* Ethernet Control block */
+typedef struct __ETH {
+ TX_FrameDescriptor *m_curTX_FD; /* pointer to current TX frame descriptor */
+ TX_FrameDescriptor *m_baseTX_FD; /* pointer to base TX frame descriptor */
+ RX_FrameDescriptor *m_curRX_FD; /* pointer to current RX frame descriptor */
+ RX_FrameDescriptor *m_baseRX_FD; /* pointer to base RX frame descriptor */
+ u8 *m_mac; /* pointer to our MAC address */
+} ETH;
+
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2004 Cucy Systems (http://www.cucy.com)
+ * Curt Brune <curt@cucy.com>
+ *
+ * (C) Copyright 2004
+ * DAVE Srl
+ * http://www.dave-tech.it
+ * http://www.wawnet.biz
+ * mailto:info@wawnet.biz
+ *
+ * (C) Copyright 2002-2004
+ * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * MODULE: $Id:$
+ * Description: UART/Serial interface for Samsung S3C4510B SoC
+ * Runtime Env: ARM7TDMI
+ * Change History:
+ * 03-02-04 Create (Curt Brune) curt@cucy.com
+ *
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_DRIVER_S3C4510_UART
+
+#include <asm/hardware.h>
+#include "s3c4510b_uart.h"
+
+static UART *uart;
+
+/* flush serial input queue. returns 0 on success or negative error
+ * number otherwise
+ */
+static int serial_flush_input(void)
+{
+ volatile u32 tmp;
+
+ /* keep on reading as long as the receiver is not empty */
+ while( uart->m_stat.bf.rxReady) {
+ tmp = uart->m_rx;
+ }
+
+ return 0;
+}
+
+
+/* flush output queue. returns 0 on success or negative error number
+ * otherwise
+ */
+static int serial_flush_output(void)
+{
+ /* wait until the transmitter is no longer busy */
+ while( !uart->m_stat.bf.txBufEmpty);
+
+ return 0;
+}
+
+
+void serial_setbrg (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ UART_LINE_CTRL ulctrl;
+ UART_CTRL uctrl;
+ UART_BAUD_DIV ubd;
+
+ serial_flush_output();
+ serial_flush_input();
+
+ /* control register */
+ uctrl.ui = 0x0;
+ uctrl.bf.rxMode = 0x1;
+ uctrl.bf.rxIrq = 0x0;
+ uctrl.bf.txMode = 0x1;
+ uctrl.bf.DSR = 0x0;
+ uctrl.bf.sendBreak = 0x0;
+ uctrl.bf.loopBack = 0x0;
+ uart->m_ctrl.ui = uctrl.ui;
+
+ /* line control register */
+ ulctrl.ui = 0x0;
+ ulctrl.bf.wordLen = 0x3; /* 8 bit data */
+ ulctrl.bf.nStop = 0x0; /* 1 stop bit */
+ ulctrl.bf.parity = 0x0; /* no parity */
+ ulctrl.bf.clk = 0x0; /* internal clock */
+ ulctrl.bf.infra_red = 0x0; /* no infra_red */
+ uart->m_lineCtrl.ui = ulctrl.ui;
+
+ ubd.ui = 0x0;
+
+ /* see table on page 10-15 in SAMSUNG S3C4510B manual */
+ /* get correct divisor */
+ switch(gd->baudrate) {
+ case 1200: ubd.bf.cnt0 = 1301; break;
+ case 2400: ubd.bf.cnt0 = 650; break;
+ case 4800: ubd.bf.cnt0 = 324; break;
+ case 9600: ubd.bf.cnt0 = 162; break;
+ case 19200: ubd.bf.cnt0 = 80; break;
+ case 38400: ubd.bf.cnt0 = 40; break;
+ case 57600: ubd.bf.cnt0 = 26; break;
+ case 115200: ubd.bf.cnt0 = 13; break;
+ }
+
+ uart->m_baudDiv.ui = ubd.ui;
+ uart->m_baudCnt = 0x0;
+ uart->m_baudClk = 0x0;
+
+}
+
+
+/*
+ * Initialise the serial port with the given baudrate. The settings
+ * are always 8 data bits, no parity, 1 stop bit, no start bits.
+ *
+ */
+int serial_init (void)
+{
+
+#if CONFIG_SERIAL1 == 1
+ uart = (UART *)UART0_BASE;
+#elif CONFIG_SERIAL1 == 2
+ uart = (UART *)UART1_BASE;
+#else
+#error CONFIG_SERIAL1 not equal to 1 or 2
+#endif
+
+ serial_setbrg ();
+
+ return (0);
+}
+
+
+/*
+ * Output a single byte to the serial port.
+ */
+void serial_putc (const char c)
+{
+ /* wait for room in the transmit FIFO */
+ while( !uart->m_stat.bf.txBufEmpty);
+
+ uart->m_tx = c;
+
+ /*
+ to be polite with serial console add a line feed
+ to the carriage return character
+ */
+ if (c=='\n')
+ serial_putc('\r');
+}
+
+/*
+ * Test if an input byte is ready from the serial port. Returns non-zero on
+ * success, 0 otherwise.
+ */
+int serial_tstc (void)
+{
+ return uart->m_stat.bf.rxReady;
+}
+
+/*
+ * Read a single byte from the serial port. Returns 1 on success, 0
+ * otherwise. When the function is succesfull, the character read is
+ * written into its argument c.
+ */
+int serial_getc (void)
+{
+ int rv;
+
+ for(;;) {
+ rv = serial_tstc();
+
+ if (rv) {
+ return uart->m_rx & 0xFF;
+ }
+ }
+}
+
+void serial_puts (const char *s)
+{
+ while (*s) {
+ serial_putc (*s++);
+ }
+
+ /* busy wait for tx complete */
+ while ( !uart->m_stat.bf.txComplete);
+
+ /* clear break */
+ uart->m_ctrl.bf.sendBreak = 0;
+
+}
+
+#endif
--- /dev/null
+#ifndef __UART_H
+#define __UART_H
+
+/*
+ * Copyright (c) 2004 Cucy Systems (http://www.cucy.com)
+ * Curt Brune <curt@cucy.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Description: S3C4510B UART register layout
+ */
+
+/* UART LINE CONTROL register */
+typedef struct __BF_UART_LINE_CTRL {
+ u32 wordLen: 2;
+ u32 nStop: 1;
+ u32 parity: 3;
+ u32 clk: 1;
+ u32 infra_red: 1;
+ u32 unused:24;
+} BF_UART_LINE_CTRL;
+
+typedef union _UART_LINE_CTRL {
+ u32 ui;
+ BF_UART_LINE_CTRL bf;
+} UART_LINE_CTRL;
+
+/* UART CONTROL register */
+typedef struct __BF_UART_CTRL {
+ u32 rxMode: 2;
+ u32 rxIrq: 1;
+ u32 txMode: 2;
+ u32 DSR: 1;
+ u32 sendBreak: 1;
+ u32 loopBack: 1;
+ u32 unused:24;
+} BF_UART_CTRL;
+
+typedef union _UART_CTRL {
+ u32 ui;
+ BF_UART_CTRL bf;
+} UART_CTRL;
+
+/* UART STATUS register */
+typedef struct __BF_UART_STAT {
+ u32 overrun: 1;
+ u32 parity: 1;
+ u32 frame: 1;
+ u32 breakIrq: 1;
+ u32 DTR: 1;
+ u32 rxReady: 1;
+ u32 txBufEmpty: 1;
+ u32 txComplete: 1;
+ u32 unused:24;
+} BF_UART_STAT;
+
+typedef union _UART_STAT {
+ u32 ui;
+ BF_UART_STAT bf;
+} UART_STAT;
+
+/* UART BAUD_DIV register */
+typedef struct __BF_UART_BAUD_DIV {
+ u32 cnt1: 4;
+ u32 cnt0:12;
+ u32 unused:16;
+} BF_UART_BAUD_DIV;
+
+typedef union _UART_BAUD_DIV {
+ u32 ui;
+ BF_UART_BAUD_DIV bf;
+} UART_BAUD_DIV;
+
+/* UART register block */
+typedef struct __UART {
+ volatile UART_LINE_CTRL m_lineCtrl;
+ volatile UART_CTRL m_ctrl;
+ volatile UART_STAT m_stat;
+ volatile u32 m_tx;
+ volatile u32 m_rx;
+ volatile UART_BAUD_DIV m_baudDiv;
+ volatile u32 m_baudCnt;
+ volatile u32 m_baudClk;
+} UART;
+
+#define NL 0x0A
+#define CR 0x0D
+#define BSP 0x08
+#define ESC 0x1B
+#define CTRLZ 0x1A
+#define RUBOUT 0x7F
+
+#endif
address = smc_mac_addr[i + 1] << 8;
address |= smc_mac_addr[i];
- SMC_outw (address, ADDR0_REG + i);
+ SMC_outw (address, (ADDR0_REG + i));
}
#else
for (i = 0; i < 6; i++)
- SMC_outb (smc_mac_addr[i], ADDR0_REG + i);
+ SMC_outb (smc_mac_addr[i], (ADDR0_REG + i));
#endif
return 0;
SMC_SELECT_BANK (1);
for (i=0; i<6; i++)
{
- v_rom_mac[i] = SMC_inb (ADDR0_REG + i);
+ v_rom_mac[i] = SMC_inb ((ADDR0_REG + i));
valid_mac |= v_rom_mac[i];
}
--- /dev/null
+#ifndef __ARM7_HW_H
+#define __ARM7_HW_H
+
+/*
+ * Copyright (c) 2004 Cucy Systems (http://www.cucy.com)
+ * Curt Brune <curt@cucy.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#if defined(CONFIG_S3C4510B)
+#include <asm-arm/arch-arm720t/s3c4510b.h>
+#elif defined(CONFIG_NETARM)
+#include <asm-arm/arch-arm720t/netarm_registers.h>
+#elif defined(CONFIG_IMPA7)
+/* include IMPA7 specific hardware file if there was one */
+#elif defined(CONFIG_EP7312)
+/* include EP7312 specific hardware file if there was one */
+#else
+#error No hardware file defined for this configuration
+#endif
+
+#endif /* __ARM7_HW_H */
--- /dev/null
+#ifndef __HW_S3C4510_H
+#define __HW_S3C4510_H
+
+/*
+ * Copyright (c) 2004 Cucy Systems (http://www.cucy.com)
+ * Curt Brune <curt@cucy.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Description: Samsung S3C4510B register layout
+ */
+
+/*------------------------------------------------------------------------
+ * ASIC Address Definition
+ *----------------------------------------------------------------------*/
+
+/* L1 8KB on chip SRAM base address */
+#define SRAM_BASE (0x03fe0000)
+
+/* Special Register Start Address After System Reset */
+#define REG_BASE (0x03ff0000)
+#define SPSTR (REG_BASE)
+
+/* *********************** */
+/* System Manager Register */
+/* *********************** */
+#define REG_SYSCFG (REG_BASE+0x0000)
+
+#define REG_CLKCON (REG_BASE+0x3000)
+#define REG_EXTACON0 (REG_BASE+0x3008)
+#define REG_EXTACON1 (REG_BASE+0x300c)
+#define REG_EXTDBWTH (REG_BASE+0x3010)
+#define REG_ROMCON0 (REG_BASE+0x3014)
+#define REG_ROMCON1 (REG_BASE+0x3018)
+#define REG_ROMCON2 (REG_BASE+0x301c)
+#define REG_ROMCON3 (REG_BASE+0x3020)
+#define REG_ROMCON4 (REG_BASE+0x3024)
+#define REG_ROMCON5 (REG_BASE+0x3028)
+#define REG_DRAMCON0 (REG_BASE+0x302c)
+#define REG_DRAMCON1 (REG_BASE+0x3030)
+#define REG_DRAMCON2 (REG_BASE+0x3034)
+#define REG_DRAMCON3 (REG_BASE+0x3038)
+#define REG_REFEXTCON (REG_BASE+0x303c)
+
+/* *********************** */
+/* Ethernet BDMA Register */
+/* *********************** */
+#define REG_BDMATXCON (REG_BASE+0x9000)
+#define REG_BDMARXCON (REG_BASE+0x9004)
+#define REG_BDMATXPTR (REG_BASE+0x9008)
+#define REG_BDMARXPTR (REG_BASE+0x900c)
+#define REG_BDMARXLSZ (REG_BASE+0x9010)
+#define REG_BDMASTAT (REG_BASE+0x9014)
+
+/* Content Address Memory */
+#define REG_CAM_BASE (REG_BASE+0x9100)
+
+#define REG_BDMATXBUF (REG_BASE+0x9200)
+#define REG_BDMARXBUF (REG_BASE+0x9800)
+
+/* *********************** */
+/* Ethernet MAC Register */
+/* *********************** */
+#define REG_MACCON (REG_BASE+0xa000)
+#define REG_CAMCON (REG_BASE+0xa004)
+#define REG_MACTXCON (REG_BASE+0xa008)
+#define REG_MACTXSTAT (REG_BASE+0xa00c)
+#define REG_MACRXCON (REG_BASE+0xa010)
+#define REG_MACRXSTAT (REG_BASE+0xa014)
+#define REG_STADATA (REG_BASE+0xa018)
+#define REG_STACON (REG_BASE+0xa01c)
+#define REG_CAMEN (REG_BASE+0xa028)
+#define REG_EMISSCNT (REG_BASE+0xa03c)
+#define REG_EPZCNT (REG_BASE+0xa040)
+#define REG_ERMPZCNT (REG_BASE+0xa044)
+#define REG_ETXSTAT (REG_BASE+0x9040)
+#define REG_MACRXDESTR (REG_BASE+0xa064)
+#define REG_MACRXSTATEM (REG_BASE+0xa090)
+#define REG_MACRXFIFO (REG_BASE+0xa200)
+
+/********************/
+/* I2C Bus Register */
+/********************/
+#define REG_I2C_CON (REG_BASE+0xf000)
+#define REG_I2C_BUF (REG_BASE+0xf004)
+#define REG_I2C_PS (REG_BASE+0xf008)
+#define REG_I2C_COUNT (REG_BASE+0xf00c)
+
+/********************/
+/* GDMA 0 */
+/********************/
+#define REG_GDMACON0 (REG_BASE+0xb000)
+#define REG_GDMA0_RUN_ENABLE (REG_BASE+0xb020)
+#define REG_GDMASRC0 (REG_BASE+0xb004)
+#define REG_GDMADST0 (REG_BASE+0xb008)
+#define REG_GDMACNT0 (REG_BASE+0xb00c)
+
+/********************/
+/* GDMA 1 */
+/********************/
+#define REG_GDMACON1 (REG_BASE+0xc000)
+#define REG_GDMA1_RUN_ENABLE (REG_BASE+0xc020)
+#define REG_GDMASRC1 (REG_BASE+0xc004)
+#define REG_GDMADST1 (REG_BASE+0xc008)
+#define REG_GDMACNT1 (REG_BASE+0xc00c)
+
+/********************/
+/* UART 0 */
+/********************/
+#define UART0_BASE (REG_BASE+0xd000)
+#define REG_UART0_LCON (REG_BASE+0xd000)
+#define REG_UART0_CTRL (REG_BASE+0xd004)
+#define REG_UART0_STAT (REG_BASE+0xd008)
+#define REG_UART0_TXB (REG_BASE+0xd00c)
+#define REG_UART0_RXB (REG_BASE+0xd010)
+#define REG_UART0_BAUD_DIV (REG_BASE+0xd014)
+#define REG_UART0_BAUD_CNT (REG_BASE+0xd018)
+#define REG_UART0_BAUD_CLK (REG_BASE+0xd01C)
+
+/********************/
+/* UART 1 */
+/********************/
+#define UART1_BASE (REG_BASE+0xe000)
+#define REG_UART1_LCON (REG_BASE+0xe000)
+#define REG_UART1_CTRL (REG_BASE+0xe004)
+#define REG_UART1_STAT (REG_BASE+0xe008)
+#define REG_UART1_TXB (REG_BASE+0xe00c)
+#define REG_UART1_RXB (REG_BASE+0xe010)
+#define REG_UART1_BAUD_DIV (REG_BASE+0xe014)
+#define REG_UART1_BAUD_CNT (REG_BASE+0xe018)
+#define REG_UART1_BAUD_CLK (REG_BASE+0xe01C)
+
+/********************/
+/* Timer Register */
+/********************/
+#define REG_TMOD (REG_BASE+0x6000)
+#define REG_TDATA0 (REG_BASE+0x6004)
+#define REG_TDATA1 (REG_BASE+0x6008)
+#define REG_TCNT0 (REG_BASE+0x600c)
+#define REG_TCNT1 (REG_BASE+0x6010)
+
+/**********************/
+/* I/O Port Interface */
+/**********************/
+#define REG_IOPMODE (REG_BASE+0x5000)
+#define REG_IOPCON (REG_BASE+0x5004)
+#define REG_IOPDATA (REG_BASE+0x5008)
+
+/*********************************/
+/* Interrupt Controller Register */
+/*********************************/
+#define REG_INTMODE (REG_BASE+0x4000)
+#define REG_INTPEND (REG_BASE+0x4004)
+#define REG_INTMASK (REG_BASE+0x4008)
+
+#define REG_INTPRI0 (REG_BASE+0x400c)
+#define REG_INTPRI1 (REG_BASE+0x4010)
+#define REG_INTPRI2 (REG_BASE+0x4014)
+#define REG_INTPRI3 (REG_BASE+0x4018)
+#define REG_INTPRI4 (REG_BASE+0x401c)
+#define REG_INTPRI5 (REG_BASE+0x4020)
+#define REG_INTOFFSET (REG_BASE+0x4024)
+#define REG_INTPNDPRI (REG_BASE+0x4028)
+#define REG_INTPNDTST (REG_BASE+0x402C)
+
+/*********************************/
+/* CACHE CONTROL MASKS */
+/*********************************/
+#define CACHE_STALL (0x00000001)
+#define CACHE_ENABLE (0x00000002)
+#define CACHE_WRITE_BUFF (0x00000004)
+#define CACHE_MODE (0x00000030)
+#define CACHE_MODE_00 (0x00000000)
+#define CACHE_MODE_01 (0x00000010)
+#define CACHE_MODE_10 (0x00000020)
+
+/*********************************/
+/* CACHE RAM BASE ADDRESSES */
+/*********************************/
+#define CACHE_SET0_RAM (0x10000000)
+#define CACHE_SET1_RAM (0x10800000)
+#define CACHE_TAG_RAM (0x11000000)
+
+/*********************************/
+/* CACHE_DISABLE MASK */
+/*********************************/
+#define CACHE_DISABLE_MASK (0x04000000)
+
+#define GET_REG(reg) (*((volatile u32 *)(reg)))
+#define PUT_REG(reg, val) (*((volatile u32 *)(reg)) = ((u32)(val)))
+#define SET_REG(reg, mask) (PUT_REG((reg), GET_REG((reg)) | mask))
+#define CLR_REG(reg, mask) (PUT_REG((reg), GET_REG((reg)) & ~mask))
+#define PUT_U16(reg, val) (*((volatile u16 *)(reg)) = ((u16)(val)))
+#define PUT__U8(reg, val) (*((volatile u8 *)(reg)) = (( u8)((val)&0xFF)))
+#define GET__U8(reg) (*((volatile u8 *)(reg)))
+
+/***********************************/
+/* CLOCK CONSTANTS -- 50 MHz Clock */
+/***********************************/
+
+#define CLK_FREQ_MHZ (50)
+#define t_data_us(t) ((t)*CLK_FREQ_MHZ-1) /* t is time tick,unit[us] */
+#define t_data_ms(t) (t_data_us((t)*1000)) /* t is time tick,unit[ms] */
+
+/*********************************************************/
+/* TIMER MODE REGISTER */
+/*********************************************************/
+#define TM0_RUN 0x01 /* Timer 0 enable */
+#define TM0_TOGGLE 0x02 /* 0, interval mode */
+#define TM0_OUT_1 0x04 /* Timer 0 Initial TOUT0 value */
+#define TM1_RUN 0x08 /* Timer 1 enable */
+#define TM1_TOGGLE 0x10 /* 0, interval mode */
+#define TM1_OUT_1 0x20 /* Timer 0 Initial TOUT0 value */
+
+#endif /* __S3C4510_h */
--- /dev/null
+/*
+ * Copyright (c) 2004 Cucy Systems (http://www.cucy.com)
+ * Curt Brune <curt@cucy.com>
+ *
+ * Configuation settings for evb4510 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * If we are developing, we might want to start u-boot from ram
+ * so we MUST NOT initialize critical regs like mem-timing ...
+ *
+ * Also swap the flash1 and flash2 addresses during debug.
+ *
+ */
+#define CONFIG_INIT_CRITICAL /* undef for developing */
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARM7 1 /* This is a ARM7 CPU */
+#define CONFIG_ARM_THUMB 1 /* this is an ARM7TDMI */
+#define CONFIG_S3C4510B 1 /* it's a S3C4510B chip */
+#define CONFIG_EVB4510 1 /* on an EVB4510 Board */
+
+#undef CONFIG_USE_IRQ /* don't need them anymore */
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
+#define CFG_GBL_DATA_SIZE 128
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_DRIVER_S3C4510_ETH 1
+#define CONFIG_DRIVER_S3C4510_I2C 1
+#define CONFIG_DRIVER_S3C4510_UART 1
+#define CONFIG_DRIVER_S3C4510_FLASH 1
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL1 2 /* we use Serial line 2, could also use 1 */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BAUDRATE 19200
+
+#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_ETHADDR 00:40:95:36:35:33
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_IPADDR 10.0.0.11
+#define CONFIG_SERVERIP 10.0.0.1
+#define CONFIG_CMDLINE_TAG /* submit bootargs to kernel */
+
+/*#define CONFIG_BOOTDELAY 10*/
+/* args and cmd for uClinux-image @ 0x10020000, ramdisk-image @ 0x100a0000 */
+#define CONFIG_BOOTCOMMAND "bootm 0x10020000 0x100a0000"
+#define CONFIG_BOOTARGS "console=ttyS0,19200 initrd=0x100a0040,530K root=/dev/ram keepinitrd"
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 19200 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "evb4510 # " /* Monitor Command Prompt */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x00000000 /* memtest works on */
+#define CFG_MEMTEST_END 0x00780000 /* 4 ... 8 MB in DRAM */
+
+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+#define CFG_LOAD_ADDR 0x00000000 /* default load address */
+
+#define CFG_HZ 50000000 /* decrementer freq: 50 MHz */
+
+ /* valid baudrates */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+*/
+#define CONFIG_STACKSIZE (128*1024) /* regular stack */
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
+#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map after relocation
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 banks of DRAM */
+#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x00800000 /* 8 MB */
+
+#define PHYS_FLASH_1 0x01000000 /* Flash Bank #1 */
+#define PHYS_FLASH_1_SIZE 0x00200000 /* 2 MB (one chip, 8bit access) */
+
+#define PHYS_FLASH_2 0x02000000 /* Flash Bank #2 */
+#define PHYS_FLASH_2_SIZE 0x00080000 /* 512KB (one chip, 8bit access) */
+
+#define CFG_FLASH_BASE PHYS_FLASH_1
+#define CFG_FLASH_SIZE PHYS_FLASH_1_SIZE
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 35 /* max number of sectors on one chip */
+#define CFG_MAIN_SECT_SIZE 0x00010000 /* main size of sectors on one chip */
+
+/* timeout values are in ticks */
+#define CFG_FLASH_ERASE_TOUT (4*CFG_HZ) /* Timeout for Flash Erase */
+#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
+
+/* environment settings */
+#define CFG_ENV_IS_IN_FLASH
+#undef CFG_ENV_IS_NOWHERE
+
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x20000) /* environment start address */
+#define CFG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */
+#define CFG_ENV_SIZE 0x4000 /* max size for environment */
+
+#endif /* __CONFIG_H */
static inline void set_led_state(int state)
{
static unsigned long hw_led_state = 0;
- volatile unsigned short *led_address = 0x04000016;
+ volatile unsigned short *led_address = (volatile unsigned short *)0x04000016;
hw_led_state = ((unsigned long)state);
*((unsigned short *) (led_address)) = (unsigned short) (~hw_led_state & 0xFFFF);
}
-static inline void spin_up_leds()
+static inline void spin_up_leds(void)
{
volatile int i, j, k;
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