u-boot: Disables MPC8548CDS 2T_TIMING for DDR by default

This patch disables MPC8548CDS 2T_TIMING for DDR by default.

Signed-off-by:Ebony Zhu <ebony.zhu@freescale.com>

diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index bfd316cb945b6214b60a4b92e48c07817754fa88..687fe84850de385a765f5a3176521e8482273c75 100644 (file)
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -41,7 +41,7 @@
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_SPD_EEPROM              /* Use SPD EEPROM for DDR setup*/
 #define CONFIG_DDR_DLL                 /* possible DLL fix needed */
-#define CONFIG_DDR_2T_TIMING           /* Sets the 2T timing bit */
+#undef CONFIG_DDR_2T_TIMING            /* Sets the 2T timing bit */
 
 #define CONFIG_DDR_ECC                 /* only for ECC DDR module */
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER      /* DDR controller or DMA? */