ARM: exynos: clock: modify the set_mmc_clk for exynos4

Modified the mmc_set_clock for eynos4.
The goal of this patch is that fsys-div register should be reset.
And retore the div-value, not using the value of lowlevel_init.
(For using SDMMC4, this patch is needs)

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index 2c2029a984c3720d3169c71623a2fe7aa2b8c9bb..400d134d549de542a532022a3ecf6e20c0093d27 100644 (file)
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -869,7 +869,7 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
 {
        struct exynos4_clock *clk =
                (struct exynos4_clock *)samsung_get_base_clock();
-       unsigned int addr;
+       unsigned int addr, clear_bit, set_bit;
 
        /*
         * CLK_DIV_FSYS1
@@ -877,20 +877,26 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
         * CLK_DIV_FSYS2
         * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
         * CLK_DIV_FSYS3
-        * MMC4_PRE_RATIO [15:8]
+        * MMC4_RATIO [3:0]
         */
        if (dev_index < 2) {
                addr = (unsigned int)&clk->div_fsys1;
-       }  else if (dev_index == 4) {
+               clear_bit = MASK_PRE_RATIO(dev_index);
+               set_bit = SET_PRE_RATIO(dev_index, div);
+       } else if (dev_index == 4) {
                addr = (unsigned int)&clk->div_fsys3;
                dev_index -= 4;
+               /* MMC4 is controlled with the MMC4_RATIO value */
+               clear_bit = MASK_RATIO(dev_index);
+               set_bit = SET_RATIO(dev_index, div);
        } else {
                addr = (unsigned int)&clk->div_fsys2;
                dev_index -= 2;
+               clear_bit = MASK_PRE_RATIO(dev_index);
+               set_bit = SET_PRE_RATIO(dev_index, div);
        }
 
-       clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
-                       (div & 0xff) << ((dev_index << 4) + 8));
+       clrsetbits_le32(addr, clear_bit, set_bit);
 }
 
 /* exynos5: set the mmc clock */

diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h
index cdeef324ccefaf1bd0a199ced5c538dfd817c451..ffbc07e228cb8bb1c86694b72d2225183a21b199 100644 (file)
--- a/arch/arm/include/asm/arch-exynos/clk.h
+++ b/arch/arm/include/asm/arch-exynos/clk.h
@@ -16,6 +16,11 @@
 #define BPLL   5
 #define RPLL   6
 
+#define MASK_PRE_RATIO(x)      (0xff << ((x << 4) + 8))
+#define MASK_RATIO(x)          (0xf << (x << 4))
+#define SET_PRE_RATIO(x, y)    ((y & 0xff) << ((x << 4) + 8))
+#define SET_RATIO(x, y)                ((y & 0xf) << (x << 4))
+
 enum pll_src_bit {
        EXYNOS_SRC_MPLL = 6,
        EXYNOS_SRC_EPLL,