writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
        writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
 
-       if ((omap_revision() >= OMAP5430_ES1_0) ||
-                               (omap_revision() == DRA752_ES1_0)) {
+       if ((omap_revision() >= OMAP5430_ES1_0) || is_dra7xx()) {
                writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0,
                        &emif->emif_l3_config);
        } else if (omap_revision() >= OMAP4460_ES1_0) {
         * The same sequence should work on OMAP5432 as well. But strange that
         * it is not working
         */
-       if (omap_revision() == DRA752_ES1_0) {
+       if (is_dra7xx()) {
                do_ext_phy_settings(base, regs);
                writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
                writel(regs->sdram_config_init, &emif->emif_sdram_config);
 
        break;
 
        case DRA752_ES1_0:
+       case DRA752_ES1_1:
        *prcm = &dra7xx_prcm;
        *dplls_data = &dra7xx_dplls;
        *omap_vcores = &dra752_volts;
                *regs = &ioregs_omap5432_es2;
                break;
        case DRA752_ES1_0:
+       case DRA752_ES1_1:
                *regs = &ioregs_dra7xx_es1;
                break;
 
 
        case DRA752_CONTROL_ID_CODE_ES1_0:
                *omap_si_rev = DRA752_ES1_0;
                break;
+       case DRA752_CONTROL_ID_CODE_ES1_1:
+               *omap_si_rev = DRA752_ES1_1;
+               break;
        default:
                *omap_si_rev = OMAP5430_SILICON_ID_INVALID;
        }
 
                *regs = &emif_regs_ddr3_532_mhz_1cs_es2;
                break;
        case DRA752_ES1_0:
+       case DRA752_ES1_1:
                switch (emif_nr) {
                case 1:
                        *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
                *dmm_lisa_regs = &lisa_map_4G_x_2_x_2;
                break;
        case DRA752_ES1_0:
+       case DRA752_ES1_1:
        default:
                *dmm_lisa_regs = &lisa_map_2G_x_2_x_2_2G_x_1_x_2;
        }
                *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
                break;
        case DRA752_ES1_0:
+       case DRA752_ES1_1:
                if (emif_nr == 1) {
                        *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1;
                        *size =
                             sizeof(omap5_bug_00339_regs[0]);
                break;
        case DRA752_ES1_0:
+       case DRA752_ES1_1:
                bug_00339_regs_ptr = dra_bug_00339_regs;
                *iterations = sizeof(dra_bug_00339_regs)/
                             sizeof(dra_bug_00339_regs[0]);
 
 #define OMAP5432_CONTROL_ID_CODE_ES1_0         0x0B99802F
 #define OMAP5432_CONTROL_ID_CODE_ES2_0          0x1B99802F
 #define DRA752_CONTROL_ID_CODE_ES1_0           0x0B99002F
+#define DRA752_CONTROL_ID_CODE_ES1_1           0x1B99002F
 
 /* UART */
 #define UART1_BASE             (OMAP54XX_L4_PER_BASE + 0x6a000)
 
 
 /* DRA7XX */
 #define DRA752_ES1_0   0x07520100
+#define DRA752_ES1_1   0x07520110
 
 /*
  * SRAM scratch space entries