help
This is the divider that is used to derive SDHC clock from Platform
clock, in another word SDHC_clk = Platform_clk / this_divider.
+
+config SYS_FSL_QMAN_CLK_DIV
+ int "QMAN clock divider"
+ default 1 if ARCH_LS1043A
+ default 2
+ help
+ This is the divider that is used to derive QMAN clock from Platform
+ clock, in another word QMAN_clk = Platform_clk / this_divider.
endmenu
config RESV_RAM
ccsr_sec_t __iomem *sec;
#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
- if (fdt_fixup_kaslr(blob))
- fdt_fixup_remove_jr(blob);
+ fdt_fixup_remove_jr(blob);
+ fdt_fixup_kaslr(blob);
#endif
sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
CONFIG_SYS_FSL_IFC_CLK_DIV;
#endif
#ifdef CONFIG_SYS_DPAA_QBMAN
- sys_info->freq_qman = sys_info->freq_systembus;
+ sys_info->freq_qman = (sys_info->freq_systembus /
+ CONFIG_SYS_FSL_PCLK_DIV) /
+ CONFIG_SYS_FSL_QMAN_CLK_DIV;
#endif
}
* NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just
* placeholders.
*/
-#ifdef CONFIG_FSL_TZASC_1
- ldr x1, =TZASC_GATE_KEEPER(0)
- ldr w0, [x1] /* Filter 0 Gate Keeper Register */
- orr w0, w0, #1 << 0 /* Set open_request for Filter 0 */
- str w0, [x1]
- ldr x1, =TZASC_REGION_ATTRIBUTES_0(0)
- ldr w0, [x1] /* Region-0 Attributes Register */
- orr w0, w0, #1 << 31 /* Set Sec global write en, Bit[31] */
- orr w0, w0, #1 << 30 /* Set Sec global read en, Bit[30] */
- str w0, [x1]
+.macro tzasc_prog, xreg
+
+ mov x12, TZASC1_BASE
+ mov x16, #0x10000
+ mul x14, \xreg, x16
+ add x14, x14,x12
+ mov x1, #0x8
+ add x1, x1, x14
+
+ ldr w0, [x1] /* Filter 0 Gate Keeper Register */
+ orr w0, w0, #1 << 0 /* Set open_request for Filter 0 */
+ str w0, [x1]
+
+ mov x1, #0x110
+ add x1, x1, x14
+
+ ldr w0, [x1] /* Region-0 Attributes Register */
+ orr w0, w0, #1 << 31 /* Set Sec global write en, Bit[31] */
+ orr w0, w0, #1 << 30 /* Set Sec global read en, Bit[30] */
+ str w0, [x1]
+
+ mov x1, #0x114
+ add x1, x1, x14
+
+ ldr w0, [x1] /* Region-0 Access Register */
+ mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */
+ str w0, [x1]
+.endm
+
+#ifdef CONFIG_FSL_TZASC_1
+ mov x13, #0
+ tzasc_prog x13
- ldr x1, =TZASC_REGION_ID_ACCESS_0(0)
- ldr w0, [x1] /* Region-0 Access Register */
- mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */
- str w0, [x1]
#endif
#ifdef CONFIG_FSL_TZASC_2
- ldr x1, =TZASC_GATE_KEEPER(1)
- ldr w0, [x1] /* Filter 0 Gate Keeper Register */
- orr w0, w0, #1 << 0 /* Set open_request for Filter 0 */
- str w0, [x1]
-
- ldr x1, =TZASC_REGION_ATTRIBUTES_0(1)
- ldr w0, [x1] /* Region-1 Attributes Register */
- orr w0, w0, #1 << 31 /* Set Sec global write en, Bit[31] */
- orr w0, w0, #1 << 30 /* Set Sec global read en, Bit[30] */
- str w0, [x1]
+ mov x13, #1
+ tzasc_prog x13
- ldr x1, =TZASC_REGION_ID_ACCESS_0(1)
- ldr w0, [x1] /* Region-1 Attributes Register */
- mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */
- str w0, [x1]
#endif
isb
dsb sy
porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
porsr1);
+ out_be32((void *)(CONFIG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff);
#endif
}
u32 *loadable_l, u32 *loadable_h)
{
phys_addr_t sec_firmware_loadable_addr = 0;
- int conf_node_off, ld_node_off;
+ int conf_node_off, ld_node_off, images;
char *conf_node_name = NULL;
const void *data;
size_t size;
ulong load;
+ const char *name, *str, *type;
+ int len;
conf_node_name = SEC_FIRMEWARE_FIT_CNF_NAME;
conf_node_off = fit_conf_get_node(sec_firmware_img, conf_node_name);
if (conf_node_off < 0) {
printf("SEC Firmware: %s: no such config\n", conf_node_name);
- return -ENOENT;
+ return -ENOENT;
+ }
+
+ /* find the node holding the images information */
+ images = fdt_path_offset(sec_firmware_img, FIT_IMAGES_PATH);
+ if (images < 0) {
+ printf("%s: Cannot find /images node: %d\n", __func__, images);
+ return -1;
+ }
+
+ type = FIT_LOADABLE_PROP;
+
+ name = fdt_getprop(sec_firmware_img, conf_node_off, type, &len);
+ if (!name) {
+ /* Loadables not present */
+ return 0;
}
- ld_node_off = fit_conf_get_prop_node(sec_firmware_img, conf_node_off,
- FIT_LOADABLE_PROP);
- if (ld_node_off >= 0) {
- printf("SEC Firmware: '%s' present in config\n",
- FIT_LOADABLE_PROP);
+ printf("SEC Firmware: '%s' present in config\n", type);
+
+ for (str = name; str && ((str - name) < len);
+ str = strchr(str, '\0') + 1) {
+ printf("%s: '%s'\n", type, str);
+ ld_node_off = fdt_subnode_offset(sec_firmware_img, images, str);
+ if (ld_node_off < 0) {
+ printf("cannot find image node '%s': %d\n", str,
+ ld_node_off);
+ return -EINVAL;
+ }
/* Verify secure firmware image */
if (!(fit_image_verify(sec_firmware_img, ld_node_off))) {
memcpy((void *)sec_firmware_loadable_addr, data, size);
flush_dcache_range(sec_firmware_loadable_addr,
sec_firmware_loadable_addr + size);
- }
- /* Populate address ptrs for loadable image with loadbale addr */
- out_le32(loadable_l, (sec_firmware_loadable_addr & WORD_MASK));
- out_le32(loadable_h, (sec_firmware_loadable_addr >> WORD_SHIFT));
+ /* Populate loadable address only for Trusted OS */
+ if (!strcmp(str, "trustedOS@1")) {
+ /*
+ * Populate address ptrs for loadable image with
+ * loadbale addr
+ */
+ out_le32(loadable_l, (sec_firmware_loadable_addr &
+ WORD_MASK));
+ out_le32(loadable_h, (sec_firmware_loadable_addr >>
+ WORD_SHIFT));
+ }
+ }
return 0;
}
*/
bool sec_firmware_support_hwrng(void)
{
- uint8_t rand[8];
if (sec_firmware_addr & SEC_FIRMWARE_RUNNING) {
- if (!sec_firmware_get_random(rand, 8))
return true;
}
#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT)
/* Check if random seed generation is supported */
- if (sec_firmware_support_hwrng() == false)
+ if (sec_firmware_support_hwrng() == false) {
+ printf("WARNING: SEC firmware not running, no kaslr-seed\n");
return 0;
+ }
ret = sec_firmware_get_random(rand, 8);
if (ret < 0) {
if (images->ft_addr) {
off = fdt_path_offset(images->ft_addr, "/memory");
- if (off < 0) {
+ if (off > 0) {
if (arch_fixup_fdt(images->ft_addr))
puts("## WARNING: fixup memory failed!\n");
}
+/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2013,2014 Renesas Electronics Corporation
* Copyright (C) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
- *
- * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __EHCI_RMOBILE_H__
.word 0xcafec0d3; /* Checksum, zero-pad */
nop;
- b reset; /* SoCFPGA jumps here */
- nop;
+ b reset; /* SoCFPGA Gen5 jumps here */
+ b reset; /* SoCFPGA Gen10 trampoline */
nop;
nop;
#endif
(
cat << EOF
+/* SPDX-License-Identifier: BSD-3-Clause */
/*
* Altera SoCFPGA SDRAM configuration
*
- * SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __SOCFPGA_SDRAM_CONFIG_H__
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Thumb-1 drop-in for the linux/include/asm-arm/proc-armv/system.h
*
* The original file does not build in Thumb mode. However, in U-Boot
* we don't use interrupt context, so we can redefine these as empty
* memory barriers, which makes Thumb-1 compiler happy.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
/*
.globl __secondary_start_page
.align 12
__secondary_start_page:
+#ifdef CONFIG_SYS_FSL_ERRATUM_A005125
+ msync
+ isync
+ mfspr r3, SPRN_HDBCR0
+ oris r3, r3, 0x0080
+ mtspr SPRN_HDBCR0, r3
+#endif
/* First do some preliminary setup */
lis r3, HID0_EMCP@h /* enable machine check */
#ifndef CONFIG_E500MC
#if defined(CONFIG_TARGET_LS1088ARDB)
{2, 1666, 0, 8, 8, 0x090A0B0E, 0x0F10110D,},
- {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
+ {2, 1900, 0, 8, 9, 0x0A0B0C10, 0x1112140E,},
{2, 2300, 0, 8, 9, 0x0A0C0E11, 0x1214160F,},
{}
#elif defined(CONFIG_TARGET_LS1088AQDS)
{2, 1666, 0, 8, 8, 0x0A0A0C0E, 0x0F10110C,},
- {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,},
+ {2, 1900, 0, 8, 9, 0x0A0B0C10, 0x1112140E,},
{2, 2300, 0, 4, 9, 0x0A0C0D11, 0x1214150E,},
{}
*/
#include <common.h>
+#include <command.h>
#include <netdev.h>
#include <asm/io.h>
#include <asm/arch/fsl_serdes.h>
#include <hwconfig.h>
#include <fsl_mdio.h>
#include <malloc.h>
+#include <phy.h>
#include <fm_eth.h>
#include <i2c.h>
#include <miiphy.h>
F: configs/ls2080aqds_sdcard_defconfig
LS2080A_SECURE_BOOT BOARD
-M: Saksham Jain <saksham.jain@nxp.freescale.com>
-S: Maintained
+#M: Saksham Jain <saksham.jain@nxp.freescale.com>
+S: Orphan (since 2018-05)
F: configs/ls2080aqds_SECURE_BOOT_defconfig
F: configs/ls2081ardb_defconfig
LS2080A_SECURE_BOOT BOARD
-M: Saksham Jain <saksham.jain@nxp.freescale.com>
-S: Maintained
+#M: Saksham Jain <saksham.jain@nxp.freescale.com>
+S: Orphan (since 2018-05)
F: configs/ls2080ardb_SECURE_BOOT_defconfig
LS2088A_QSPI_SECURE_BOOT BOARD
MPC8315ERDB BOARD
-M: Dave Liu <daveliu@freescale.com>
-S: Maintained
+#M: Dave Liu <daveliu@freescale.com>
+S: Orphan (since 2018-05)
F: board/freescale/mpc8315erdb/
F: include/configs/MPC8315ERDB.h
F: configs/MPC8315ERDB_defconfig
MPC8323ERDB BOARD
-M: Michael Barkowski <michael.barkowski@freescale.com>
-S: Maintained
+#M: Michael Barkowski <michael.barkowski@freescale.com>
+S: Orphan (since 2018-05)
F: board/freescale/mpc8323erdb/
F: include/configs/MPC8323ERDB.h
F: configs/MPC8323ERDB_defconfig
MPC832XEMDS BOARD
-M: Dave Liu <daveliu@freescale.com>
-S: Maintained
+#M: Dave Liu <daveliu@freescale.com>
+S: Orphan (since 2018-05)
F: board/freescale/mpc832xemds/
F: include/configs/MPC832XEMDS.h
F: configs/MPC832XEMDS_defconfig
MPC8349EMDS BOARD
-M: Kim Phillips <kim.phillips@freescale.com>
-S: Maintained
+#M: Kim Phillips <kim.phillips@freescale.com>
+S: Orphan (since 2018-05)
F: board/freescale/mpc8349emds/
F: include/configs/MPC8349EMDS.h
F: configs/MPC8349EMDS_defconfig
MPC837XEMDS BOARD
-M: Dave Liu <daveliu@freescale.com>
-S: Maintained
+#M: Dave Liu <daveliu@freescale.com>
+S: Orphan (since 2018-05)
F: board/freescale/mpc837xemds/
F: include/configs/MPC837XEMDS.h
F: configs/MPC837XEMDS_defconfig
P1022DS BOARD
-M: Timur Tabi <timur@freescale.com>
+M: Timur Tabi <timur@tabi.org>
S: Maintained
F: board/freescale/p1022ds/
F: include/configs/P1022DS.h
T102XQDS BOARD
-M: Shengzhou Liu <Shengzhou.Liu@freescale.com>
-S: Maintained
+#M: Shengzhou Liu <Shengzhou.Liu@freescale.com>
+S: Orphan (since 2018-05)
F: board/freescale/t102xqds/
F: include/configs/T102xQDS.h
F: configs/T1024QDS_defconfig
T102XRDB BOARD
-M: Shengzhou Liu <Shengzhou.Liu@freescale.com>
-S: Maintained
+#M: Shengzhou Liu <Shengzhou.Liu@freescale.com>
+S: Orphan (since 2018-05)
F: board/freescale/t102xrdb/
F: include/configs/T102xRDB.h
F: configs/T1024RDB_defconfig
T4QDS BOARD
-M: Shaohui Xie <Shaohui.Xie@freescale.com>
-S: Maintained
+#M: Shaohui Xie <Shaohui.Xie@freescale.com>
+S: Orphan (since 2018-05)
F: board/freescale/t4qds/
F: include/configs/T4240QDS.h
F: configs/T4160QDS_defconfig
T4RDB BOARD
-M: Chunhe Lan <Chunhe.Lan@freescale.com>
-S: Maintained
+#M: Chunhe Lan <Chunhe.Lan@freescale.com>
+S: Orphan (since 2018-05)
F: board/freescale/t4rdb/
F: include/configs/T4240RDB.h
F: configs/T4160RDB_defconfig
#include <environment.h>
#include <fsl_esdhc.h>
#include <netdev.h>
+#include <bootcount.h>
#include "common.h"
DECLARE_GLOBAL_DATA_PTR;
env_load();
s = env_get("BOOT_FROM");
- if (s && strcmp(s, "ACTIVE") == 0) {
+ if (s && !bootcount_error() && strcmp(s, "ACTIVE") == 0) {
spl_boot_list[0] = BOOT_DEVICE_MMC1;
spl_boot_list[1] = spl_boot_device();
}
+// SPDX-License-Identifier: GPL-2.0+
/******************************************************************************
* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
* (c) Copyright 2017 Opal Kelly Inc.
-*
-* SPDX-License-Identifier: GPL-2.0+
*****************************************************************************/
#include <asm/arch/ps7_init_gpl.h>
+// SPDX-License-Identifier: GPL-2.0+
/******************************************************************************
* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
-*
-* SPDX-License-Identifier: GPL-2.0+
-*
-*
******************************************************************************/
/****************************************************************************/
/**
+// SPDX-License-Identifier: GPL-2.0+
/******************************************************************************
* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
-*
-* SPDX-License-Identifier: GPL-2.0+
-*
-*
******************************************************************************/
/****************************************************************************/
/**
+// SPDX-License-Identifier: GPL-2.0+
/******************************************************************************
* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
-*
-* SPDX-License-Identifier: GPL-2.0+
-*
-*
******************************************************************************/
/****************************************************************************/
/**
+// SPDX-License-Identifier: GPL-2.0+
/******************************************************************************
* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
-*
-* SPDX-License-Identifier: GPL-2.0+
-*
-*
******************************************************************************/
/****************************************************************************/
/**
+// SPDX-License-Identifier: GPL-2.0+
/*
* EFI application loader
*
* Copyright (c) 2016 Alexander Graf
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <charset.h>
#include <menu.h>
#include <post.h>
#include <u-boot/sha256.h>
+#include <bootcount.h>
DECLARE_GLOBAL_DATA_PTR;
{
char *s;
int bootdelay;
-#ifdef CONFIG_BOOTCOUNT_LIMIT
- unsigned long bootcount = 0;
- unsigned long bootlimit = 0;
-#endif /* CONFIG_BOOTCOUNT_LIMIT */
-
-#ifdef CONFIG_BOOTCOUNT_LIMIT
- bootcount = bootcount_load();
- bootcount++;
- bootcount_store(bootcount);
- env_set_ulong("bootcount", bootcount);
- bootlimit = env_get_ulong("bootlimit", 10, 0);
-#endif /* CONFIG_BOOTCOUNT_LIMIT */
+
+ bootcount_inc();
s = env_get("bootdelay");
bootdelay = s ? (int)simple_strtol(s, NULL, 10) : CONFIG_BOOTDELAY;
s = env_get("failbootcmd");
} else
#endif /* CONFIG_POST */
-#ifdef CONFIG_BOOTCOUNT_LIMIT
- if (bootlimit && (bootcount > bootlimit)) {
- printf("Warning: Bootlimit (%u) exceeded. Using altbootcmd.\n",
- (unsigned)bootlimit);
+ if (bootcount_error())
s = env_get("altbootcmd");
- } else
-#endif /* CONFIG_BOOTCOUNT_LIMIT */
+ else
s = env_get("bootcmd");
process_fdt_options(gd->fdt_blob);
{ IH_TYPE_PBLIMAGE, "pblimage", "Freescale PBL Boot Image",},
{ IH_TYPE_RAMDISK, "ramdisk", "RAMDisk Image", },
{ IH_TYPE_SCRIPT, "script", "Script", },
- { IH_TYPE_SOCFPGAIMAGE, "socfpgaimage", "Altera SOCFPGA preloader",},
+ { IH_TYPE_SOCFPGAIMAGE, "socfpgaimage", "Altera SoCFPGA CV/AV preloader",},
+ { IH_TYPE_SOCFPGAIMAGE_V1, "socfpgaimage_v1", "Altera SoCFPGA A10 preloader",},
{ IH_TYPE_STANDALONE, "standalone", "Standalone Program", },
{ IH_TYPE_UBLIMAGE, "ublimage", "Davinci UBL image",},
{ IH_TYPE_MXSIMAGE, "mxsimage", "Freescale MXS Boot Image",},
BOOT_DEVICE_BOOTROM (or fall-through to the next boot device in the
boot device list, if not implemented for a given board)
+config SPL_BOOTCOUNT_LIMIT
+ bool "Support bootcount in SPL"
+ depends on SPL_ENV_SUPPORT
+ help
+ On some boards, which use 'falcon' mode, it is necessary to check
+ and increment the number of boot attempts. Such boards do not
+ use proper U-Boot for normal boot flow and hence needs those
+ adjustments to be done in the SPL.
+
config SPL_RAW_IMAGE_SUPPORT
bool "Support SPL loading and booting of RAW images"
default n if (ARCH_MX6 && (SPL_MMC_SUPPORT || SPL_SATA_SUPPORT))
#include <dm/root.h>
#include <linux/compiler.h>
#include <fdt_support.h>
+#include <bootcount.h>
DECLARE_GLOBAL_DATA_PTR;
spl_board_init();
#endif
+ bootcount_inc();
+
memset(&spl_image, '\0', sizeof(spl_image));
#ifdef CONFIG_SYS_SPL_ARGS_ADDR
spl_image.arg = (void *)CONFIG_SYS_SPL_ARGS_ADDR;
}
-#ifdef DEBUG
+#if defined(DEBUG) && !defined(CONFIG_USE_TINY_PRINTF)
/*
* Note: this debug setup works by storing the strings in a fixed buffer
*/
static char *zm_out_start = zm_debug_buf;
static int
-zm_dprintf (char *fmt, ...)
+zm_dprintf(char *fmt, ...)
{
- int len;
- va_list args;
-
- va_start (args, fmt);
- len = diag_vsprintf (zm_out, fmt, args);
- zm_out += len;
- return len;
+ int len;
+ va_list args;
+
+ va_start(args, fmt);
+ len = diag_vsprintf(zm_out, fmt, args);
+ va_end(args);
+ zm_out += len;
+ return len;
}
static void
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_SPL_BOOTCOUNT_LIMIT=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
CONFIG_SPL_DMA_SUPPORT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_FSL_ESDHC=y
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
+CONFIG_SYS_BOOTCOUNT_ADDR=0x020CC068
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT"
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT"
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
CONFIG_SD_BOOT=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT_QSPI"
CONFIG_SD_BOOT=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT"
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, QSPI_BOOT"
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT_QSPI"
CONFIG_SD_BOOT=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT_QSPI"
CONFIG_SD_BOOT=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x3000000 default_hugepagesz=2m hugepagesz=2m hugepages=256"
# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
+CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
<!--
- Copyright (c) 2018 Heinrich Schuchardt
+SPDX-License-Identifier: GPL-2.0+
- SPDX-License-Identifier: GPL-2.0+
+Copyright (c) 2018 Heinrich Schuchardt
-->
# UEFI on U-Boot
--- /dev/null
+/dts-v1/;
+
+/*
+ * Example FIT image description file demonstrating the usage
+ * of SEC Firmware and multiple loadable images loaded by the u-boot.
+ * For booting PPA (SEC Firmware), "firmware" is searched and loaded.
+ *
+ * Multiple binaries will be loaded as "loadables" (if present) at their
+ * respective load offsets from firmware image address.
+ */
+
+/{
+ description = "PPA Firmware";
+ #address-cells = <1>;
+ images {
+ firmware@1 {
+ description = "PPA Firmware: <version>";
+ data = /incbin/("../obj/monitor.bin");
+ type = "firmware";
+ arch = "arm64";
+ compression = "none";
+ };
+ trustedOS@1 {
+ description = "Trusted OS";
+ data = /incbin/("../../tee.bin");
+ type = "OS";
+ arch = "arm64";
+ compression = "none";
+ load = <0x00200000>;
+ };
+ fuse_scr {
+ description = "Fuse Script";
+ data = /incbin/("../../fuse_scr.bin");
+ type = "firmware";
+ arch = "arm64";
+ compression = "none";
+ load = <0x00180000>;
+ };
+ };
+
+ configurations {
+ default = "config-1";
+ config-1 {
+ description = "PPA Secure firmware";
+ firmware = "firmware@1";
+ loadables = "trustedOS@1", "fuse_scr";
+ };
+ };
+};
ifndef CONFIG_TPL_BUILD
ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_SPL_BOOTCOUNT_LIMIT) += bootcount/
obj-$(CONFIG_SPL_CPU_SUPPORT) += cpu/
obj-$(CONFIG_SPL_CRYPTO_SUPPORT) += crypto/
obj-$(CONFIG_SPL_GPIO_SUPPORT) += gpio/
/* returns nonzero if entire page is blank */
static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
- u32 *eccstat, unsigned int bufnum)
+ u32 eccstat, unsigned int bufnum)
{
- u32 reg = eccstat[bufnum / 4];
- int errors;
-
- errors = (reg >> ((3 - bufnum % 4) * 8)) & 15;
-
- return errors;
+ return (eccstat >> ((3 - bufnum % 4) * 8)) & 15;
}
/*
struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
u32 timeo = (CONFIG_SYS_HZ * 10) / 1000;
u32 time_start;
- u32 eccstat[8] = {0};
+ u32 eccstat;
int i;
/* set the chip select for NAND Transaction */
if (ctrl->eccread) {
int errors;
int bufnum = ctrl->page & priv->bufnum_mask;
- int sector = bufnum * chip->ecc.steps;
- int sector_end = sector + chip->ecc.steps - 1;
-
- for (i = sector / 4; i <= sector_end / 4; i++) {
- if (i >= ARRAY_SIZE(eccstat)) {
- printf("%s: eccstat too small for %d\n",
- __func__, i);
- return -EIO;
- }
+ int sector_start = bufnum * chip->ecc.steps;
+ int sector_end = sector_start + chip->ecc.steps - 1;
+ u32 *eccstat_regs;
- eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]);
- }
+ eccstat_regs = ifc->ifc_nand.nand_eccstat;
+ eccstat = ifc_in32(&eccstat_regs[sector_start / 4]);
+
+ for (i = sector_start; i <= sector_end; i++) {
+ if ((i != sector_start) && !(i % 4))
+ eccstat = ifc_in32(&eccstat_regs[i / 4]);
- for (i = sector; i <= sector_end; i++) {
errors = check_read_ecc(mtd, ctrl, eccstat, i);
if (errors == 15) {
struct fsl_ifc_ctrl *ctrl = priv->ctrl;
struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
u32 nand_fsr;
+ int status;
if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
return NAND_STATUS_FAIL;
return NAND_STATUS_FAIL;
nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr);
+ status = nand_fsr >> 24;
/* Chip sometimes reporting write protect even when it's not */
- nand_fsr = nand_fsr | NAND_STATUS_WP;
- return nand_fsr;
+ return status | NAND_STATUS_WP;
}
static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
/*
* Freescale Layerscape MC I/O wrapper
*
- * Copyright (C) 2013-2016 Freescale Semiconductor, Inc.
+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*/
#include <fsl-mc/fsl_mc_sys.h>
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2013-2016 Freescale Semiconductor
+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*/
/*
* Freescale Layerscape MC I/O wrapper
*
- * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
* Author: Prabhakar Kushwaha <prabhakar@freescale.com>
*/
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2013-2016 Freescale Semiconductor
+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*/
/*
* Freescale Layerscape MC I/O wrapper
*
- * Copyright (C) 2013-2016 Freescale Semiconductor, Inc.
+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*/
/* SPDX-License-Identifier: GPL-2.0+ */
-/* Copyright 2013-2016 Freescale Semiconductor Inc.
+/* Copyright 2013-2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*/
#ifndef __FSL_DPMNG_CMD_H
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2017 NXP Semiconductors
- * Copyright (C) 2014 Freescale Semiconductor
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
*/
#include <common.h>
#include <errno.h>
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2014-2016 Freescale Semiconductor
+ * Copyright 2014-2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*/
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2014-2016 Freescale Semiconductor
+ * Copyright 2014-2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*/
+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 - 2015 Freescale Semiconductor, Inc.
*
- * SPDX-License-Identifier: GPL-2.0+
- *
* Driver for the Vitesse VSC9953 L2 Switch
*/
out_be32(addr, val) : out_le32(addr, val);
}
+static inline int is_controller_busy(const struct fsl_qspi_priv *priv)
+{
+ u32 val;
+ const u32 mask = QSPI_SR_BUSY_MASK | QSPI_SR_AHB_ACC_MASK |
+ QSPI_SR_IP_ACC_MASK;
+ unsigned int retry = 5;
+
+ do {
+ val = qspi_read32(priv->flags, &priv->regs->sr);
+
+ if ((~val & mask) == mask)
+ return 0;
+
+ udelay(1);
+ } while (--retry);
+
+ return -ETIMEDOUT;
+}
+
/* QSPI support swapping the flash read/write data
* in hardware for LS102xA, but not for VF610 */
static inline u32 qspi_endian_xchg(u32 data)
priv->num_chipselect = plat->num_chipselect;
/* make sure controller is not busy anywhere */
- ret = wait_for_bit_le32(&priv->regs->sr,
- QSPI_SR_BUSY_MASK |
- QSPI_SR_AHB_ACC_MASK |
- QSPI_SR_IP_ACC_MASK,
- false, 100, false);
+ ret = is_controller_busy(priv);
if (ret) {
debug("ERROR : The controller is busy\n");
priv = dev_get_priv(bus);
/* make sure controller is not busy anywhere */
- ret = wait_for_bit_le32(&priv->regs->sr,
- QSPI_SR_BUSY_MASK |
- QSPI_SR_AHB_ACC_MASK |
- QSPI_SR_IP_ACC_MASK,
- false, 100, false);
+ ret = is_controller_busy(priv);
if (ret) {
debug("ERROR : The controller is busy\n");
+// SPDX-License-Identifier: GPL-2.0
/*
* EHCI HCD (Host Controller Driver) for USB.
*
* Copyright (C) 2013,2014 Renesas Electronics Corporation
* Copyright (C) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
- *
- * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
+# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2015 Google, Inc
# Written by Simon Glass <sjg@chromium.org>
-#
-# SPDX-License-Identifier: GPL-2.0+
obj-$(CONFIG_VIDEO_BRIDGE) += video-bridge-uclass.o
obj-$(CONFIG_VIDEO_BRIDGE_PARADE_PS862X) += ps862x.o
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Portable Executable and Common Object Constants
*
*
* based on the "Microsoft Portable Executable and Common Object File Format
* Specification", revision 11, 2017-01-23
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_PE_H
* (C) Copyright 2012
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*/
+#ifndef _BOOTCOUNT_H__
+#define _BOOTCOUNT_H__
#include <common.h>
#include <asm/io.h>
#include <asm/byteorder.h>
+#if defined(CONFIG_SPL_BOOTCOUNT_LIMIT) || defined(CONFIG_BOOTCOUNT_LIMIT)
+
#if !defined(CONFIG_SYS_BOOTCOUNT_LE) && !defined(CONFIG_SYS_BOOTCOUNT_BE)
# if __BYTE_ORDER == __LITTLE_ENDIAN
# define CONFIG_SYS_BOOTCOUNT_LE
return in_be32(addr);
}
#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+static inline int bootcount_error(void)
+{
+ unsigned long bootcount = bootcount_load();
+ unsigned long bootlimit = env_get_ulong("bootlimit", 10, 0);
+
+ if (bootlimit && bootcount > bootlimit) {
+ printf("Warning: Bootlimit (%lu) exceeded.", bootlimit);
+ if (!(gd->flags & GD_FLG_SPL_INIT))
+ printf(" Using altbootcmd.");
+ printf("\n");
+
+ return 1;
+ }
+
+ return 0;
+}
+
+static inline void bootcount_inc(void)
+{
+ unsigned long bootcount = bootcount_load();
+
+ if (gd->flags & GD_FLG_SPL_INIT) {
+ bootcount_store(++bootcount);
+ return;
+ }
+
+#ifndef CONFIG_SPL_BUILD
+ /* Only increment bootcount when no bootcount support in SPL */
+#ifndef CONFIG_SPL_BOOTCOUNT_LIMIT
+ bootcount_store(++bootcount);
+#endif
+ env_set_ulong("bootcount", bootcount);
+#endif /* !CONFIG_SPL_BUILD */
+}
+
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_BOOTCOUNT_LIMIT)
+void bootcount_store(ulong a) {};
+ulong bootcount_load(void) { return 0; }
+#endif /* CONFIG_SPL_BUILD && !CONFIG_SPL_BOOTCOUNT_LIMIT */
+#else
+static inline int bootcount_error(void) { return 0; }
+static inline void bootcount_inc(void) {}
+#endif /* CONFIG_SPL_BOOTCOUNT_LIMIT || CONFIG_BOOTCOUNT_LIMIT */
+#endif /* _BOOTCOUNT_H__ */
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* charset conversion utils
*
* Copyright (c) 2017 Rob Clark
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CHARSET_H_
#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
#endif
/* Command line configuration */
-#define CONFIG_CMD_GREPENV
#define CONFIG_CMD_CACHE
/* Miscellaneous configurable options */
"mcinitcmd=fsl_mc start mc 0x580a00000" \
" 0x580e00000 \0"
-#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
- "earlycon=uart8250,mmio,0x21c0500 " \
- "ramdisk_size=0x3000000 default_hugepagesz=2m" \
- " hugepagesz=2m hugepages=256"
#if defined(CONFIG_QSPI_BOOT)
#define CONFIG_BOOTCOMMAND "sf probe 0:0;" \
"sf read 0x80200000 0xd00000 0x100000;"\
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* EFI application loader
*
* Copyright (c) 2017 Heinrich Schuchardt
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _EFI_DRIVER_H
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* EFI application loader
*
* Copyright (c) 2016 Alexander Graf
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _EFI_LOADER_H
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* EFI application loader
*
* Copyright (c) 2017 Heinrich Schuchardt <xypron.glpk@gmx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _EFI_SELFTEST_H
/*
* Freescale Layerscape MC I/O wrapper
*
- * Copyright (C) 2013-2016 Freescale Semiconductor, Inc.
+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*/
/*!
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2013-2016 Freescale Semiconductor
+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*/
/*
* Freescale Layerscape MC I/O wrapper
*
- * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2015-2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
* Author: Prabhakar Kushwaha <prabhakar@freescale.com>
*/
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2013-2016 Freescale Semiconductor
+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*/
#ifndef _FSL_DPNI_H
/*
* Freescale Layerscape MC I/O wrapper
*
- * Copyright (C) 2013-2016 Freescale Semiconductor, Inc.
+ * Copyright 2013-2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*/
#ifndef _FSL_DPRC_H
/* SPDX-License-Identifier: GPL-2.0+ */
-/* Copyright 2013-2016 Freescale Semiconductor Inc.
+/* Copyright 2013-2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*/
#ifndef __FSL_MC_CMD_H
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2014-2016 Freescale Semiconductor
+ * Copyright 2014-2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*/
u32 nand_erattr1;
u32 res19[0x10];
u32 nand_fsr;
- u32 res20[0x3];
- u32 nand_eccstat[6];
+ u32 res20[0x1];
+ u32 nand_eccstat[8];
u32 res21[0x1c];
u32 nanndcr;
u32 res22[0x2];
IH_TYPE_MXSIMAGE, /* Freescale MXSBoot Image */
IH_TYPE_GPIMAGE, /* TI Keystone GPHeader Image */
IH_TYPE_ATMELIMAGE, /* ATMEL ROM bootable Image */
- IH_TYPE_SOCFPGAIMAGE, /* Altera SOCFPGA Preloader */
+ IH_TYPE_SOCFPGAIMAGE, /* Altera SOCFPGA CV/AV Preloader */
IH_TYPE_X86_SETUP, /* x86 setup.bin Image */
IH_TYPE_LPC32XXIMAGE, /* x86 setup.bin Image */
IH_TYPE_LOADABLE, /* A list of typeless images */
IH_TYPE_FIRMWARE_IVT, /* Firmware Image with HABv4 IVT */
IH_TYPE_PMMC, /* TI Power Management Micro-Controller Firmware */
IH_TYPE_STM32IMAGE, /* STMicroelectronics STM32 Image */
+ IH_TYPE_SOCFPGAIMAGE_V1, /* Altera SOCFPGA A10 Preloader */
IH_TYPE_COUNT, /* Number of image types */
};
*
* Copyright (C) 2006 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
*/
#ifndef _LINUX_LOG2_H
#include <linux/types.h>
#include <linux/bitops.h>
-/*
- * deal with unrepresentable constant logarithms
- */
-extern __attribute__((const, noreturn))
-int ____ilog2_NaN(void);
-
/*
* non-constant log of base 2 calculators
* - the arch may override these in asm/bitops.h if they can be implemented
}
#endif
-/*
- * Determine whether some value is a power of two, where zero is
+/**
+ * is_power_of_2() - check if a value is a power of two
+ * @n: the value to check
+ *
+ * Determine whether some value is a power of two, where zero is
* *not* considered a power of two.
+ * Return: true if @n is a power of 2, otherwise false.
*/
-
static inline __attribute__((const))
bool is_power_of_2(unsigned long n)
{
return (n != 0 && ((n & (n - 1)) == 0));
}
-/*
- * round up to nearest power of two
+/**
+ * __roundup_pow_of_two() - round up to nearest power of two
+ * @n: value to round up
*/
static inline __attribute__((const))
unsigned long __roundup_pow_of_two(unsigned long n)
return 1UL << fls_long(n - 1);
}
-/*
- * round down to nearest power of two
+/**
+ * __rounddown_pow_of_two() - round down to nearest power of two
+ * @n: value to round down
*/
static inline __attribute__((const))
unsigned long __rounddown_pow_of_two(unsigned long n)
}
/**
- * ilog2 - log of base 2 of 32-bit or a 64-bit unsigned value
- * @n - parameter
+ * ilog2 - log base 2 of 32-bit or a 64-bit unsigned value
+ * @n: parameter
*
* constant-capable log of base 2 calculation
* - this can be used to initialise global variables from constant data, hence
- * the massive ternary operator construction
+ * the massive ternary operator construction
*
* selects the appropriately-sized optimised version depending on sizeof(n)
*/
#define ilog2(n) \
( \
__builtin_constant_p(n) ? ( \
- (n) < 1 ? ____ilog2_NaN() : \
+ (n) < 2 ? 0 : \
(n) & (1ULL << 63) ? 63 : \
(n) & (1ULL << 62) ? 62 : \
(n) & (1ULL << 61) ? 61 : \
(n) & (1ULL << 4) ? 4 : \
(n) & (1ULL << 3) ? 3 : \
(n) & (1ULL << 2) ? 2 : \
- (n) & (1ULL << 1) ? 1 : \
- (n) & (1ULL << 0) ? 0 : \
- ____ilog2_NaN() \
- ) : \
+ 1) : \
(sizeof(n) <= 4) ? \
__ilog2_u32(n) : \
__ilog2_u64(n) \
/**
* roundup_pow_of_two - round the given value up to nearest power of two
- * @n - parameter
+ * @n: parameter
*
* round the given value up to the nearest power of two
* - the result is undefined when n == 0
/**
* rounddown_pow_of_two - round the given value down to nearest power of two
- * @n - parameter
+ * @n: parameter
*
* round the given value down to the nearest power of two
* - the result is undefined when n == 0
__rounddown_pow_of_two(n) \
)
+static inline __attribute_const__
+int __order_base_2(unsigned long n)
+{
+ return n > 1 ? ilog2(n - 1) + 1 : 0;
+}
+
/**
* order_base_2 - calculate the (rounded up) base 2 order of the argument
* @n: parameter
* ob2(5) = 3
* ... and so on.
*/
-
-#define order_base_2(n) ilog2(roundup_pow_of_two(n))
-
+#define order_base_2(n) \
+( \
+ __builtin_constant_p(n) ? ( \
+ ((n) == 0 || (n) == 1) ? 0 : \
+ ilog2((n) - 1) + 1) : \
+ __order_base_2(n) \
+)
#endif /* _LINUX_LOG2_H */
+/* SPDX-License-Identifier: GPL-2.0 */
/*
* LiMon Monitor (LiMon) - Network.
*
* Copyright 1994 - 2000 Neil Russell.
* (See License)
- * SPDX-License-Identifier: GPL-2.0
*
* History
* 9/16/00 bor adapted to TQM823L/STK8xxL board, RARP/TFTP boot added
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Portable Executable binary format structures
*
* Copyright (c) 2016 Alexander Graf
*
* Based on wine code
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _PE_H
+// SPDX-License-Identifier: GPL-2.0+
/*
* charset conversion utils
*
* Copyright (c) 2017 Rob Clark
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <charset.h>
+# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2017 Heinrich Schuchardt
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
# This file only gets included with CONFIG_EFI_LOADER set, so all
# object inclusion implicitly depends on it
+// SPDX-License-Identifier: GPL-2.0+
/*
* EFI block driver
*
* Copyright (c) 2017 Heinrich Schuchardt
*
- * SPDX-License-Identifier: GPL-2.0+
- *
* The EFI uclass creates a handle for this driver and installs the
* driver binding protocol on it.
*
+// SPDX-License-Identifier: GPL-2.0+
/*
* Uclass for EFI drivers
*
* Copyright (c) 2017 Heinrich Schuchardt
*
- * SPDX-License-Identifier: GPL-2.0+
- *
* For each EFI driver the uclass
* - creates a handle
* - installs the driver binding protocol
+# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2016 Alexander Graf
#
-# SPDX-License-Identifier: GPL-2.0+
-#
# This file only gets included with CONFIG_EFI_LOADER set, so all
# object inclusion implicitly depends on it
+// SPDX-License-Identifier: GPL-2.0+
/*
* EFI utils
*
* Copyright (c) 2017 Rob Clark
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+// SPDX-License-Identifier: GPL-2.0+
/*
* EFI application boot time services
*
* Copyright (c) 2016 Alexander Graf
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+// SPDX-License-Identifier: GPL-2.0+
/*
* EFI application console interface
*
* Copyright (c) 2016 Alexander Graf
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+// SPDX-License-Identifier: GPL-2.0+
/*
* EFI device path interface
*
* Copyright (c) 2017 Heinrich Schuchardt
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+// SPDX-License-Identifier: GPL-2.0+
/*
* EFI device path interface
*
* Copyright (c) 2017 Leif Lindholm
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+// SPDX-License-Identifier: GPL-2.0+
/*
* EFI application disk support
*
* Copyright (c) 2016 Alexander Graf
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+// SPDX-License-Identifier: GPL-2.0+
/*
* EFI utils
*
* Copyright (c) 2017 Rob Clark
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+// SPDX-License-Identifier: GPL-2.0+
/*
* EFI application disk support
*
* Copyright (c) 2016 Alexander Graf
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+// SPDX-License-Identifier: GPL-2.0+
/*
* EFI image loader
*
* based partly on wine code
*
* Copyright (c) 2016 Alexander Graf
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+// SPDX-License-Identifier: GPL-2.0+
/*
* EFI application memory management
*
* Copyright (c) 2016 Alexander Graf
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+// SPDX-License-Identifier: GPL-2.0+
/*
* EFI application network access support
*
* Copyright (c) 2016 Alexander Graf
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+// SPDX-License-Identifier: GPL-2.0+
/*
* EFI application runtime services
*
* Copyright (c) 2016 Alexander Graf
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+// SPDX-License-Identifier: GPL-2.0+
/*
* EFI application tables support
*
* Copyright (c) 2016 Alexander Graf
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+// SPDX-License-Identifier: GPL-2.0+
/*
* EFI utils
*
* Copyright (c) 2017 Rob Clark
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <malloc.h>
+// SPDX-License-Identifier: GPL-2.0+
/*
* EFI watchdog
*
* Copyright (c) 2017 Heinrich Schuchardt
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
-:
-# (C) Copyright 2017, Heinrich Schuchardt <xypron.glpk@gmx.de>
-#
-# SPDX-License-Identifier: GPL-2.0+
+# SPDX-License-Identifier: GPL-2.0+
#
+# (C) Copyright 2017, Heinrich Schuchardt <xypron.glpk@gmx.de>
# This file only gets included with CONFIG_EFI_LOADER set, so all
# object inclusion implicitly depends on it
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Non-zero 8 byte strings of a disk image
*
* Generated with tools/file2include
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#define EFI_ST_DISK_IMG { 0x00010000, { \
+// SPDX-License-Identifier: BSD-2-Clause
/*
LZ4 - Fast LZ compression algorithm
Copyright (C) 2011-2015, Yann Collet.
- SPDX-License-Identifier: BSD-2-Clause
-
You can contact the author at :
- LZ4 source repository : https://github.com/Cyan4973/lz4
- LZ4 public forum : https://groups.google.com/forum/#!forum/lz4c
+// SPDX-License-Identifier: GPL-2.0
/*
* Copied from Linux Monitor (LiMon) - Networking.
*
* Copyright 2000 Roland Borde
* Copyright 2000 Paolo Scaffardi
* Copyright 2000-2002 Wolfgang Denk, wd@denx.de
- * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
+/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copied from Linux Monitor (LiMon) - Networking.
*
* Copyright 2000 Roland Borde
* Copyright 2000 Paolo Scaffardi
* Copyright 2000-2002 Wolfgang Denk, wd@denx.de
- * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __ARP_H__
+// SPDX-License-Identifier: GPL-2.0
/*
* Copied from Linux Monitor (LiMon) - Networking.
*
* Copyright 2000 Roland Borde
* Copyright 2000 Paolo Scaffardi
* Copyright 2000-2002 Wolfgang Denk, wd@denx.de
- * SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
+/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copied from Linux Monitor (LiMon) - Networking.
*
* Copyright 2000 Roland Borde
* Copyright 2000 Paolo Scaffardi
* Copyright 2000-2002 Wolfgang Denk, wd@denx.de
- * SPDX-License-Identifier: GPL-2.0
*/
#if defined(CONFIG_CMD_CDP)
+// SPDX-License-Identifier: GPL-2.0
/*
* Copied from Linux Monitor (LiMon) - Networking.
*
* Copyright 2000 Roland Borde
* Copyright 2000 Paolo Scaffardi
* Copyright 2000-2002 Wolfgang Denk, wd@denx.de
- * SPDX-License-Identifier: GPL-2.0
*/
/*
+// SPDX-License-Identifier: GPL-2.0
/*
* Copied from Linux Monitor (LiMon) - Networking.
*
* Copyright 2000 Roland Borde
* Copyright 2000 Paolo Scaffardi
* Copyright 2000-2002 Wolfgang Denk, wd@denx.de
- * SPDX-License-Identifier: GPL-2.0
*/
#include "ping.h"
+/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copied from Linux Monitor (LiMon) - Networking.
*
* Copyright 2000 Roland Borde
* Copyright 2000 Paolo Scaffardi
* Copyright 2000-2002 Wolfgang Denk, wd@denx.de
- * SPDX-License-Identifier: GPL-2.0
*/
#ifndef __PING_H__
endif
endif
+ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
+MKIMAGEFLAGS_$(SPL_BIN).sfp = -T socfpgaimage_v1
+else
MKIMAGEFLAGS_$(SPL_BIN).sfp = -T socfpgaimage
+endif
$(obj)/$(SPL_BIN).sfp: $(obj)/$(SPL_BIN).bin FORCE
$(call if_changed,mkimage)
#!/bin/bash
+# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2014 Suriyan Ramasami
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
# Invoke this test script from U-Boot base directory as ./test/fs/fs-test.sh
# It currently tests the fs/sb and native commands for ext4 and fat partitions
count = fread(buf, 1, count, file);
/* Generate output */
+ printf("/* SPDX-License-Identifier: GPL-2.0+ */\n");
printf("/*\n");
printf(" * Non-zero %u byte strings of a disk image\n", BLOCK_SIZE);
printf(" *\n");
printf(" * Generated with tools/file2include\n");
- printf(" *\n");
- printf(" * SPDX-License-Identifier: GPL-2.0+\n");
printf(" */\n\n");
printf("#define EFI_ST_DISK_IMG { 0x%08zx, { \\\n", count);
printf("\\x%02x", buf[j]);
printf("\"}, /* ");
for (j = i; j < i + BLOCK_SIZE && j < count; ++j) {
- if (buf[j] >= 0x20 && buf[j] <= 0x7e)
+ if (buf[j] != '*' && buf[j] >= 0x20 && buf[j] <= 0x7e)
printf("%c", buf[j]);
else
printf(".");
{
printf("ifdtool v%s -- ", IFDTOOL_VERSION);
printf("Copyright (C) 2014 Google Inc.\n\n");
- printf("SPDX-License-Identifier: GPL-2.0+\n");
+ printf("SPDX-License-Identifier: GPL-2.0+\n");
}
static void print_usage(const char *name)
/*
* Copyright (C) 2014 Charles Manning <cdhmanning@gmail.com>
*
- * Reference doc http://www.altera.com.cn/literature/hb/cyclone-v/cv_5400A.pdf
- * Note this doc is not entirely accurate. Of particular interest to us is the
- * "header" length field being in U32s and not bytes.
+ * Reference documents:
+ * Cyclone V SoC: https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/cyclone-v/cv_5400a.pdf
+ * Arria V SoC: https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/arria-v/av_5400a.pdf
+ * Arria 10 SoC: https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/arria-10/a10_5400a.pdf
*
- * "Header" is a structure of the following format.
- * this is positioned at 0x40.
+ * Bootable SoCFPGA image requires a structure of the following format
+ * positioned at offset 0x40 of the bootable image. Endian is LSB.
*
- * Endian is LSB.
+ * There are two versions of the SoCFPGA header format, v0 and v1.
+ * The version 0 is used by Cyclone V SoC and Arria V SoC, while
+ * the version 1 is used by the Arria 10 SoC.
*
+ * Version 0:
* Offset Length Usage
* -----------------------
- * 0x40 4 Validation word 0x31305341
- * 0x44 1 Version (whatever, zero is fine)
- * 0x45 1 Flags (unused, zero is fine)
- * 0x46 2 Length (in units of u32, including the end checksum).
- * 0x48 2 Zero
+ * 0x40 4 Validation word (0x31305341)
+ * 0x44 1 Version (0x0)
+ * 0x45 1 Flags (unused, zero is fine)
+ * 0x46 2 Length (in units of u32, including the end checksum).
+ * 0x48 2 Zero (0x0)
* 0x4A 2 Checksum over the header. NB Not CRC32
*
+ * Version 1:
+ * Offset Length Usage
+ * -----------------------
+ * 0x40 4 Validation word (0x31305341)
+ * 0x44 1 Version (0x1)
+ * 0x45 1 Flags (unused, zero is fine)
+ * 0x46 2 Header length (in units of u8).
+ * 0x48 4 Length (in units of u8).
+ * 0x4C 4 Image entry offset from standard of header
+ * 0x50 2 Zero (0x0)
+ * 0x52 2 Checksum over the header. NB Not CRC32
+ *
* At the end of the code we have a 32-bit CRC checksum over whole binary
* excluding the CRC.
*
* Note that the CRC used here is **not** the zlib/Adler crc32. It is the
* CRC-32 used in bzip2, ethernet and elsewhere.
*
+ * The Image entry offset in version 1 image is relative the the start of
+ * the header, 0x40, and must not be a negative number. Therefore, it is
+ * only possible to make the SoCFPGA jump forward. The U-Boot bootloader
+ * places a trampoline instruction at offset 0x5c, 0x14 bytes from the
+ * start of the SoCFPGA header, which jumps to the reset vector.
+ *
* The image is padded out to 64k, because that is what is
* typically used to write the image to the boot medium.
*/
#define HEADER_OFFSET 0x40
#define VALIDATION_WORD 0x31305341
-#define PADDED_SIZE 0x10000
-/* To allow for adding CRC, the max input size is a bit smaller. */
-#define MAX_INPUT_SIZE (PADDED_SIZE - sizeof(uint32_t))
-
-static uint8_t buffer[PADDED_SIZE];
+static uint8_t buffer_v0[0x10000];
+static uint8_t buffer_v1[0x40000];
+
+struct socfpga_header_v0 {
+ uint32_t validation;
+ uint8_t version;
+ uint8_t flags;
+ uint16_t length_u32;
+ uint16_t zero;
+ uint16_t checksum;
+};
+
+struct socfpga_header_v1 {
+ uint32_t validation;
+ uint8_t version;
+ uint8_t flags;
+ uint16_t header_u8;
+ uint32_t length_u8;
+ uint32_t entry_offset;
+ uint16_t zero;
+ uint16_t checksum;
+};
+
+static unsigned int sfp_hdr_size(uint8_t ver)
+{
+ if (ver == 0)
+ return sizeof(struct socfpga_header_v0);
+ if (ver == 1)
+ return sizeof(struct socfpga_header_v1);
+ return 0;
+}
-static struct socfpga_header {
- uint32_t validation;
- uint8_t version;
- uint8_t flags;
- uint16_t length_u32;
- uint16_t zero;
- uint16_t checksum;
-} header;
+static unsigned int sfp_pad_size(uint8_t ver)
+{
+ if (ver == 0)
+ return sizeof(buffer_v0);
+ if (ver == 1)
+ return sizeof(buffer_v1);
+ return 0;
+}
/*
* The header checksum is just a very simple checksum over
* the header area.
* There is still a crc32 over the whole lot.
*/
-static uint16_t hdr_checksum(struct socfpga_header *header)
+static uint16_t sfp_hdr_checksum(uint8_t *buf, unsigned char ver)
{
- int len = sizeof(*header) - sizeof(header->checksum);
- uint8_t *buf = (uint8_t *)header;
uint16_t ret = 0;
+ int len = sfp_hdr_size(ver) - sizeof(ret);
while (--len)
ret += *buf++;
return ret;
}
-
-static void build_header(uint8_t *buf, uint8_t version, uint8_t flags,
- uint16_t length_bytes)
+static void sfp_build_header(uint8_t *buf, uint8_t ver, uint8_t flags,
+ uint32_t length_bytes)
{
- header.validation = cpu_to_le32(VALIDATION_WORD);
- header.version = version;
- header.flags = flags;
- header.length_u32 = cpu_to_le16(length_bytes/4);
- header.zero = 0;
- header.checksum = cpu_to_le16(hdr_checksum(&header));
-
- memcpy(buf, &header, sizeof(header));
+ struct socfpga_header_v0 header_v0 = {
+ .validation = cpu_to_le32(VALIDATION_WORD),
+ .version = 0,
+ .flags = flags,
+ .length_u32 = cpu_to_le16(length_bytes / 4),
+ .zero = 0,
+ };
+
+ struct socfpga_header_v1 header_v1 = {
+ .validation = cpu_to_le32(VALIDATION_WORD),
+ .version = 1,
+ .flags = flags,
+ .header_u8 = cpu_to_le16(sizeof(header_v1)),
+ .length_u8 = cpu_to_le32(length_bytes),
+ .entry_offset = cpu_to_le32(0x14), /* Trampoline offset */
+ .zero = 0,
+ };
+
+ uint16_t csum;
+
+ if (ver == 0) {
+ csum = sfp_hdr_checksum((uint8_t *)&header_v0, 0);
+ header_v0.checksum = cpu_to_le16(csum);
+ memcpy(buf, &header_v0, sizeof(header_v0));
+ } else {
+ csum = sfp_hdr_checksum((uint8_t *)&header_v1, 1);
+ header_v1.checksum = cpu_to_le16(csum);
+ memcpy(buf, &header_v1, sizeof(header_v1));
+ }
}
/*
* Perform a rudimentary verification of header and return
* size of image.
*/
-static int verify_header(const uint8_t *buf)
+static int sfp_verify_header(const uint8_t *buf, uint8_t *ver)
{
- memcpy(&header, buf, sizeof(header));
+ struct socfpga_header_v0 header_v0;
+ struct socfpga_header_v1 header_v1;
+ uint16_t hdr_csum, sfp_csum;
+ uint32_t img_len;
- if (le32_to_cpu(header.validation) != VALIDATION_WORD)
- return -1;
- if (le16_to_cpu(header.checksum) != hdr_checksum(&header))
+ /*
+ * Header v0 is always smaller than Header v1 and the validation
+ * word and version field is at the same place, so use Header v0
+ * to check for version during verifiction and upgrade to Header
+ * v1 if needed.
+ */
+ memcpy(&header_v0, buf, sizeof(header_v0));
+
+ if (le32_to_cpu(header_v0.validation) != VALIDATION_WORD)
return -1;
- return le16_to_cpu(header.length_u32) * 4;
+ if (header_v0.version == 0) {
+ hdr_csum = le16_to_cpu(header_v0.checksum);
+ sfp_csum = sfp_hdr_checksum((uint8_t *)&header_v0, 0);
+ img_len = le16_to_cpu(header_v0.length_u32) * 4;
+ } else if (header_v0.version == 1) {
+ memcpy(&header_v1, buf, sizeof(header_v1));
+ hdr_csum = le16_to_cpu(header_v1.checksum);
+ sfp_csum = sfp_hdr_checksum((uint8_t *)&header_v1, 1);
+ img_len = le32_to_cpu(header_v1.length_u8);
+ } else { /* Invalid version */
+ return -EINVAL;
+ }
+
+ /* Verify checksum */
+ if (hdr_csum != sfp_csum)
+ return -EINVAL;
+
+ return img_len;
}
/* Sign the buffer and return the signed buffer size */
-static int sign_buffer(uint8_t *buf,
- uint8_t version, uint8_t flags,
- int len, int pad_64k)
+static int sfp_sign_buffer(uint8_t *buf, uint8_t ver, uint8_t flags,
+ int len, int pad_64k)
{
uint32_t calc_crc;
/* Align the length up */
- len = (len + 3) & (~3);
+ len = (len + 3) & ~3;
/* Build header, adding 4 bytes to length to hold the CRC32. */
- build_header(buf + HEADER_OFFSET, version, flags, len + 4);
+ sfp_build_header(buf + HEADER_OFFSET, ver, flags, len + 4);
/* Calculate and apply the CRC */
calc_crc = ~pbl_crc32(0, (char *)buf, len);
if (!pad_64k)
return len + 4;
- return PADDED_SIZE;
+ return sfp_pad_size(ver);
}
/* Verify that the buffer looks sane */
-static int verify_buffer(const uint8_t *buf)
+static int sfp_verify_buffer(const uint8_t *buf)
{
int len; /* Including 32bit CRC */
uint32_t calc_crc;
uint32_t buf_crc;
+ uint8_t ver = 0;
- len = verify_header(buf + HEADER_OFFSET);
+ len = sfp_verify_header(buf + HEADER_OFFSET, &ver);
if (len < 0) {
debug("Invalid header\n");
return -1;
}
- if (len < HEADER_OFFSET || len > PADDED_SIZE) {
+ if (len < HEADER_OFFSET || len > sfp_pad_size(ver)) {
debug("Invalid header length (%i)\n", len);
return -1;
}
/* mkimage glue functions */
static int socfpgaimage_verify_header(unsigned char *ptr, int image_size,
- struct image_tool_params *params)
+ struct image_tool_params *params)
{
- if (image_size != PADDED_SIZE)
+ if (image_size < 0x80)
return -1;
- return verify_buffer(ptr);
+ return sfp_verify_buffer(ptr);
}
static void socfpgaimage_print_header(const void *ptr)
{
- if (verify_buffer(ptr) == 0)
+ if (sfp_verify_buffer(ptr) == 0)
printf("Looks like a sane SOCFPGA preloader\n");
else
printf("Not a sane SOCFPGA preloader\n");
(params->lflag && (params->dflag || params->fflag));
}
-static int socfpgaimage_check_image_types(uint8_t type)
+static int socfpgaimage_check_image_types_v0(uint8_t type)
{
if (type == IH_TYPE_SOCFPGAIMAGE)
return EXIT_SUCCESS;
return EXIT_FAILURE;
}
+static int socfpgaimage_check_image_types_v1(uint8_t type)
+{
+ if (type == IH_TYPE_SOCFPGAIMAGE_V1)
+ return EXIT_SUCCESS;
+ return EXIT_FAILURE;
+}
+
/*
* To work in with the mkimage framework, we do some ugly stuff...
*
* First, socfpgaimage_vrec_header() is called.
- * We prepend a fake header big enough to make the file PADDED_SIZE.
+ * We prepend a fake header big enough to make the file sfp_pad_size().
* This gives us enough space to do what we want later.
*
* Next, socfpgaimage_set_header() is called.
*/
static int data_size;
-#define FAKE_HEADER_SIZE (PADDED_SIZE - data_size)
-static int socfpgaimage_vrec_header(struct image_tool_params *params,
- struct image_type_params *tparams)
+static int sfp_fake_header_size(unsigned int size, uint8_t ver)
+{
+ return sfp_pad_size(ver) - size;
+}
+
+static int sfp_vrec_header(struct image_tool_params *params,
+ struct image_type_params *tparams, uint8_t ver)
{
struct stat sbuf;
if (params->datafile &&
stat(params->datafile, &sbuf) == 0 &&
- sbuf.st_size <= MAX_INPUT_SIZE) {
+ sbuf.st_size <= (sfp_pad_size(ver) - sizeof(uint32_t))) {
data_size = sbuf.st_size;
- tparams->header_size = FAKE_HEADER_SIZE;
+ tparams->header_size = sfp_fake_header_size(data_size, ver);
}
return 0;
+
+}
+
+static int socfpgaimage_vrec_header_v0(struct image_tool_params *params,
+ struct image_type_params *tparams)
+{
+ return sfp_vrec_header(params, tparams, 0);
}
-static void socfpgaimage_set_header(void *ptr, struct stat *sbuf, int ifd,
- struct image_tool_params *params)
+static int socfpgaimage_vrec_header_v1(struct image_tool_params *params,
+ struct image_type_params *tparams)
+{
+ return sfp_vrec_header(params, tparams, 1);
+}
+
+static void sfp_set_header(void *ptr, unsigned char ver)
{
uint8_t *buf = (uint8_t *)ptr;
/*
* This function is called after vrec_header() has been called.
- * At this stage we have the FAKE_HEADER_SIZE dummy bytes followed by
- * data_size image bytes. Total = PADDED_SIZE.
+ * At this stage we have the sfp_fake_header_size() dummy bytes
+ * followed by data_size image bytes. Total = sfp_pad_size().
* We need to fix the buffer by moving the image bytes back to
* the beginning of the buffer, then actually do the signing stuff...
*/
- memmove(buf, buf + FAKE_HEADER_SIZE, data_size);
- memset(buf + data_size, 0, FAKE_HEADER_SIZE);
+ memmove(buf, buf + sfp_fake_header_size(data_size, ver), data_size);
+ memset(buf + data_size, 0, sfp_fake_header_size(data_size, ver));
- sign_buffer(buf, 0, 0, data_size, 0);
+ sfp_sign_buffer(buf, ver, 0, data_size, 0);
+}
+
+static void socfpgaimage_set_header_v0(void *ptr, struct stat *sbuf, int ifd,
+ struct image_tool_params *params)
+{
+ sfp_set_header(ptr, 0);
+}
+
+static void socfpgaimage_set_header_v1(void *ptr, struct stat *sbuf, int ifd,
+ struct image_tool_params *params)
+{
+ sfp_set_header(ptr, 1);
}
U_BOOT_IMAGE_TYPE(
socfpgaimage,
- "Altera SOCFPGA preloader support",
+ "Altera SoCFPGA Cyclone V / Arria V image support",
+ 0, /* This will be modified by vrec_header() */
+ (void *)buffer_v0,
+ socfpgaimage_check_params,
+ socfpgaimage_verify_header,
+ socfpgaimage_print_header,
+ socfpgaimage_set_header_v0,
+ NULL,
+ socfpgaimage_check_image_types_v0,
+ NULL,
+ socfpgaimage_vrec_header_v0
+);
+
+U_BOOT_IMAGE_TYPE(
+ socfpgaimage_v1,
+ "Altera SoCFPGA Arria10 image support",
0, /* This will be modified by vrec_header() */
- (void *)buffer,
+ (void *)buffer_v1,
socfpgaimage_check_params,
socfpgaimage_verify_header,
socfpgaimage_print_header,
- socfpgaimage_set_header,
+ socfpgaimage_set_header_v1,
NULL,
- socfpgaimage_check_image_types,
+ socfpgaimage_check_image_types_v1,
NULL,
- socfpgaimage_vrec_header
+ socfpgaimage_vrec_header_v1
);
projects / u-boot / commitdiff