]> git.sur5r.net Git - u-boot/commitdiff
armv8/fsl_lsch2: Add the OCRAM initialization
authorHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Fri, 16 Dec 2016 09:15:46 +0000 (17:15 +0800)
committerYork Sun <york.sun@nxp.com>
Wed, 18 Jan 2017 17:27:27 +0000 (09:27 -0800)
Clear the content to zero and the ECC error bit of OCRAM1/2.

The OCRAM must be initialized to ZERO by the unit of 8-Byte before
accessing it, or else it will generate ECC error. And the IBR has
accessed the OCRAM before this initialization, so the ECC error
status bit should to be cleared.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Pratiyush Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
arch/arm/include/asm/arch-fsl-layerscape/config.h

index 340445922d7e5a809dd6f88b369599f59f0e414b..04a2598006510b37463a89f09f4ea39ea7ef1b54 100644 (file)
@@ -229,10 +229,47 @@ ENTRY(lowlevel_init)
        isb
 #endif
 
+#if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD)
+       bl      fsl_ocram_init
+#endif
+
        mov     lr, x29                 /* Restore LR */
        ret
 ENDPROC(lowlevel_init)
 
+#if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD)
+ENTRY(fsl_ocram_init)
+       mov     x28, lr                 /* Save LR */
+       bl      fsl_clear_ocram
+       bl      fsl_ocram_clear_ecc_err
+       mov     lr, x28                 /* Restore LR */
+       ret
+ENDPROC(fsl_ocram_init)
+
+ENTRY(fsl_clear_ocram)
+/* Clear OCRAM */
+       ldr     x0, =CONFIG_SYS_FSL_OCRAM_BASE
+       ldr     x1, =(CONFIG_SYS_FSL_OCRAM_BASE + CONFIG_SYS_FSL_OCRAM_SIZE)
+       mov     x2, #0
+clear_loop:
+       str     x2, [x0]
+       add     x0, x0, #8
+       cmp     x0, x1
+       b.lo    clear_loop
+       ret
+ENDPROC(fsl_clear_ocram)
+
+ENTRY(fsl_ocram_clear_ecc_err)
+       /* OCRAM1/2 ECC status bit */
+       mov     w1, #0x60
+       ldr     x0, =DCSR_DCFG_SBEESR2
+       str     w1, [x0]
+       ldr     x0, =DCSR_DCFG_MBEESR2
+       str     w1, [x0]
+       ret
+ENDPROC(fsl_ocram_init)
+#endif
+
 #ifdef CONFIG_FSL_LSCH3
        .globl get_svr
 get_svr:
index b3818723eeb699a0fb69d44879e9bbcfee4fcec3..045825eb979d14849101e42d3e25f951ec041c01 100644 (file)
 #define SYS_FSL_OCRAM_SPACE_SIZE               0x00200000 /* 2M space */
 #define CONFIG_SYS_FSL_OCRAM_SIZE              0x00020000 /* Real size 128K */
 
+#define DCSR_DCFG_SBEESR2                      0x20140534
+#define DCSR_DCFG_MBEESR2                      0x20140544
+
 #define CONFIG_SYS_FSL_CCSR_SCFG_BE
 #define CONFIG_SYS_FSL_ESDHC_BE
 #define CONFIG_SYS_FSL_WDOG_BE