]> git.sur5r.net Git - u-boot/commitdiff
MX: Added Freescale Power Management Driver
authorStefano Babic <sbabic@denx.de>
Sun, 4 Apr 2010 21:08:03 +0000 (23:08 +0200)
committerTom <Tom@bumblecow.com>
Mon, 10 May 2010 16:21:53 +0000 (11:21 -0500)
The patch add supports for the Freescale's Power
Management Controller (known as Atlas) used together with i.MX31/51
processors. It was tested with a MC13783 (MX31) and
MC13892 (MX51).

Signed-off-by: Stefano Babic <sbabic@denx.de>
drivers/misc/Makefile
drivers/misc/fsl_pmic.c [new file with mode: 0644]
include/fsl_pmic.h [new file with mode: 0644]

index f6df60faef9fd0688ab6f53c7203241de9a3b507..96aa331be0a8639f6dc2d3e5a38ab5787be051b1 100644 (file)
@@ -31,6 +31,7 @@ COBJS-$(CONFIG_FSL_LAW) += fsl_law.o
 COBJS-$(CONFIG_NS87308) += ns87308.o
 COBJS-$(CONFIG_STATUS_LED) += status_led.o
 COBJS-$(CONFIG_TWL4030_LED) += twl4030_led.o
+COBJS-$(CONFIG_FSL_PMIC) += fsl_pmic.o
 
 COBJS  := $(COBJS-y)
 SRCS   := $(COBJS:.o=.c)
diff --git a/drivers/misc/fsl_pmic.c b/drivers/misc/fsl_pmic.c
new file mode 100644 (file)
index 0000000..87f0aed
--- /dev/null
@@ -0,0 +1,200 @@
+/*
+ * (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <spi.h>
+#include <asm/errno.h>
+#include <linux/types.h>
+#include <fsl_pmic.h>
+
+static struct spi_slave *slave;
+
+struct spi_slave *pmic_spi_probe(void)
+{
+       return spi_setup_slave(CONFIG_FSL_PMIC_BUS,
+               CONFIG_FSL_PMIC_CS,
+               CONFIG_FSL_PMIC_CLK,
+               CONFIG_FSL_PMIC_MODE);
+}
+
+void pmic_spi_free(struct spi_slave *slave)
+{
+       if (slave)
+               spi_free_slave(slave);
+}
+
+u32 pmic_reg(u32 reg, u32 val, u32 write)
+{
+       u32 pmic_tx, pmic_rx;
+
+       if (!slave) {
+               slave = pmic_spi_probe();
+
+               if (!slave)
+                       return -1;
+       }
+
+       if (reg > 63 || write > 1) {
+               printf("<reg num> = %d is invalid. Should be less then 63\n",
+                       reg);
+               return -1;
+       }
+
+       if (spi_claim_bus(slave))
+               return -1;
+
+       pmic_tx = (write << 31) | (reg << 25) | (val & 0x00FFFFFF);
+
+       if (spi_xfer(slave, 4 << 3, &pmic_tx, &pmic_rx,
+                       SPI_XFER_BEGIN | SPI_XFER_END)) {
+               spi_release_bus(slave);
+               return -1;
+       }
+
+       if (write) {
+               pmic_tx &= ~(1 << 31);
+               if (spi_xfer(slave, 4 << 3, &pmic_tx, &pmic_rx,
+                       SPI_XFER_BEGIN | SPI_XFER_END)) {
+                       spi_release_bus(slave);
+                       return -1;
+               }
+       }
+
+       spi_release_bus(slave);
+       return pmic_rx;
+}
+
+void pmic_reg_write(u32 reg, u32 value)
+{
+       pmic_reg(reg, value, 1);
+}
+
+u32 pmic_reg_read(u32 reg)
+{
+       return pmic_reg(reg, 0, 0);
+}
+
+void pmic_show_pmic_info(void)
+{
+       u32 rev_id;
+
+       rev_id = pmic_reg_read(REG_IDENTIFICATION);
+       printf("PMIC ID: 0x%08x [Rev: ", rev_id);
+       switch (rev_id & 0x1F) {
+       case 0x1:
+               puts("1.0");
+               break;
+       case 0x9:
+               puts("1.1");
+               break;
+       case 0xA:
+               puts("1.2");
+               break;
+       case 0x10:
+               puts("2.0");
+               break;
+       case 0x11:
+               puts("2.1");
+               break;
+       case 0x18:
+               puts("3.0");
+               break;
+       case 0x19:
+               puts("3.1");
+               break;
+       case 0x1A:
+               puts("3.2");
+               break;
+       case 0x2:
+               puts("3.2A");
+               break;
+       case 0x1B:
+               puts("3.3");
+               break;
+       case 0x1D:
+               puts("3.5");
+               break;
+       default:
+               puts("unknown");
+               break;
+       }
+       puts("]\n");
+}
+
+static void pmic_dump(int numregs)
+{
+       u32 val;
+       int i;
+
+       pmic_show_pmic_info();
+       for (i = 0; i < numregs; i++) {
+               val = pmic_reg_read(i);
+               if (!(i % 8))
+                       printf ("\n0x%02x: ", i);
+               printf("%08x ", val);
+       }
+       puts("\n");
+}
+
+int do_pmic(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+       char *cmd;
+       int nregs;
+       u32 val;
+
+       /* at least two arguments please */
+       if (argc < 2) {
+               cmd_usage(cmdtp);
+               return 1;
+       }
+
+       cmd = argv[1];
+       if (strcmp(cmd, "dump") == 0) {
+               if (argc < 3) {
+                       cmd_usage(cmdtp);
+                       return 1;
+               }
+               nregs = simple_strtoul(argv[2], NULL, 16);
+               pmic_dump(nregs);
+               return 0;
+       }
+       if (strcmp(cmd, "write") == 0) {
+               if (argc < 4) {
+                       cmd_usage(cmdtp);
+                       return 1;
+               }
+               nregs = simple_strtoul(argv[2], NULL, 16);
+               val = simple_strtoul(argv[3], NULL, 16);
+               pmic_reg_write(nregs, val);
+               return 0;
+       }
+       /* No subcommand found */
+       return 1;
+}
+
+U_BOOT_CMD(
+       pmic,   CONFIG_SYS_MAXARGS, 1, do_pmic,
+       "Freescale PMIC (Atlas)",
+       "dump [numregs] dump registers\n"
+       "pmic write <reg> <value> - write register"
+);
diff --git a/include/fsl_pmic.h b/include/fsl_pmic.h
new file mode 100644 (file)
index 0000000..e3abde6
--- /dev/null
@@ -0,0 +1,128 @@
+/*
+ * (C) Copyright 2010
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __FSL_PMIC_H__
+#define __FSL_PMIC_H__
+
+/*
+ * The registers of different PMIC has the same meaning
+ * but the bit positions of the fields can differ or
+ * some fields has a meaning only on some devices.
+ * You have to check with the internal SPI bitmap
+ * (see Freescale Documentation) to set the registers
+ * for the device you are using
+ */
+enum {
+       REG_INT_STATUS0 = 0,
+       REG_INT_MASK0,
+       REG_INT_SENSE0,
+       REG_INT_STATUS1,
+       REG_INT_MASK1,
+       REG_INT_SENSE1,
+       REG_PU_MODE_S,
+       REG_IDENTIFICATION,
+       REG_UNUSED0,
+       REG_ACC0,
+       REG_ACC1,               /*10 */
+       REG_UNUSED1,
+       REG_UNUSED2,
+       REG_POWER_CTL0,
+       REG_POWER_CTL1,
+       REG_POWER_CTL2,
+       REG_REGEN_ASSIGN,
+       REG_UNUSED3,
+       REG_MEM_A,
+       REG_MEM_B,
+       REG_RTC_TIME,           /*20 */
+       REG_RTC_ALARM,
+       REG_RTC_DAY,
+       REG_RTC_DAY_ALARM,
+       REG_SW_0,
+       REG_SW_1,
+       REG_SW_2,
+       REG_SW_3,
+       REG_SW_4,
+       REG_SW_5,
+       REG_SETTING_0,          /*30 */
+       REG_SETTING_1,
+       REG_MODE_0,
+       REG_MODE_1,
+       REG_POWER_MISC,
+       REG_UNUSED4,
+       REG_UNUSED5,
+       REG_UNUSED6,
+       REG_UNUSED7,
+       REG_UNUSED8,
+       REG_UNUSED9,            /*40 */
+       REG_UNUSED10,
+       REG_UNUSED11,
+       REG_ADC0,
+       REG_ADC1,
+       REG_ADC2,
+       REG_ADC3,
+       REG_ADC4,
+       REG_CHARGE,
+       REG_USB0,
+       REG_USB1,               /*50 */
+       REG_LED_CTL0,
+       REG_LED_CTL1,
+       REG_LED_CTL2,
+       REG_LED_CTL3,
+       REG_UNUSED12,
+       REG_UNUSED13,
+       REG_TRIM0,
+       REG_TRIM1,
+       REG_TEST0,
+       REG_TEST1,              /*60 */
+       REG_TEST2,
+       REG_TEST3,
+       REG_TEST4,
+};
+
+/* REG_POWER_MISC */
+#define GPO1EN         (1 << 6)
+#define GPO1STBY       (1 << 7)
+#define GPO2EN         (1 << 8)
+#define GPO2STBY       (1 << 9)
+#define GPO3EN         (1 << 10)
+#define GPO3STBY       (1 << 11)
+#define GPO4EN         (1 << 12)
+#define GPO4STBY       (1 << 13)
+#define PWGT1SPIEN     (1 << 15)
+#define PWGT2SPIEN     (1 << 16)
+#define PWUP           (1 << 21)
+
+/* Power Control 0 */
+#define COINCHEN       (1 << 23)
+#define BATTDETEN      (1 << 19)
+
+/* Interrupt status 1 */
+#define RTCRSTI                (1 << 7)
+
+void pmic_show_pmic_info(void);
+void pmic_reg_write(u32 reg, u32 value);
+u32 pmic_reg_read(u32 reg);
+
+#endif