Add support for VoiceBlue board.
* Patch by Ladislav Michl, 05 Apr 2005:
Fix netboot_common() prototypes.
* Cleanup.
Changes for U-Boot 1.1.3:
======================================================================
+* Patch by Ladislav Michl, 05 Apr 2005:
+ Add support for VoiceBlue board.
+
+* Patch by Ladislav Michl, 05 Apr 2005:
+ Fix netboot_common() prototypes.
+
* Patch by Steven Scholz, 05 Apr 2005:
Use i.MX watchdog timer for reset_cpu()
* Patch by Tolunay Orkun, 16 November 2004:
fix incorrect onboard Xilinx CPLD base address
-
+
* Patch by Jerry Van Baren, 08 Nov 2004:
- Add low-boot option for MPC8260ADS board (if lowboot is selected,
the jumper for the HRCW source should select flash. If lowboot is
lpd7a400 mx1ads mx1fs2 omap1510inn \
omap1610h2 omap1610inn omap730p2 scb9328 \
smdk2400 smdk2410 trab VCMA9 \
- versatile \
+ versatile voiceblue \
"
#########################################################################
versatile_config : unconfig
@./mkconfig $(@:_config=) arm arm926ejs versatile
+voiceblue_smallflash_config \
+voiceblue_config: unconfig
+ @if [ "$(findstring _smallflash_,$@)" ] ; then \
+ echo "... boot from lower flash bank" ; \
+ echo "#define VOICEBLUE_SMALL_FLASH" >>include/config.h ; \
+ echo "VOICEBLUE_SMALL_FLASH=y" >board/voiceblue/config.tmp ; \
+ else \
+ echo "... boot from upper flash bank" ; \
+ >include/config.h ; \
+ echo "VOICEBLUE_SMALL_FLASH=n" >board/voiceblue/config.tmp ; \
+ fi
+ @./mkconfig -a voiceblue arm arm925t voiceblue
+
#########################################################################
## S3C44B0 Systems
#########################################################################
- CONFIG_SKIP_LOWLEVEL_INIT
- CONFIG_SKIP_RELOCATE_UBOOT
- [ARM only] If these variables are defined, then
- certain low level initializations (like setting up
- the memory controller) are omitted and/or U-Boot does
- not relocate itself into RAM.
- Normally these variables MUST NOT be defined. The
- only exception is when U-Boot is loaded (to RAM) by
- some other boot loader or by a debugger which
- performs these intializations itself.
+ [ARM only] If these variables are defined, then
+ certain low level initializations (like setting up
+ the memory controller) are omitted and/or U-Boot does
+ not relocate itself into RAM.
+ Normally these variables MUST NOT be defined. The
+ only exception is when U-Boot is loaded (to RAM) by
+ some other boot loader or by a debugger which
+ performs these intializations itself.
Building the Software:
ulong size;
size = dramSetup ();
-
+
return get_ram_size((ulong *)CFG_SDRAM_BASE, size);
}
--- /dev/null
+# (C) Copyright 2000-2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de
+#
+# (C) Copyright 2005
+# Ladislav Michl, 2N Telekomunikace, michl@2n.cz
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License version 2 as
+# published by the Free Software Foundation.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := voiceblue.o
+SOBJS := setup.o
+
+gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
+
+LOAD_ADDR = 0x10400000
+
+all: $(LIB) eeprom.srec eeprom.bin
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS) $(SOBJS)
+
+eeprom.srec: eeprom.o
+ $(LD) -g -Ttext $(LOAD_ADDR) -o $(<:.o=) -e $(<:.o=) $^ \
+ -L../../examples -lstubs \
+ -L../../lib_generic -lgeneric \
+ -L$(gcclibdir) -lgcc
+ $(OBJCOPY) -O srec $(<:.o=) $@
+
+eeprom.bin: eeprom.srec
+ $(OBJCOPY) -O binary $< $@ 2>/dev/null
+
+clean:
+ rm -f $(SOBJS) $(OBJS) eeprom eeprom.srec eeprom.bin
+
+distclean: clean
+ rm -f $(LIB) core config.tmp *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- /dev/null
+#
+# Linux-Kernel is expected to be at 1000'8000,
+# entry 1000'8000 (mem base + reserved)
+#
+
+sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
+
+ifeq ($(VOICEBLUE_SMALL_FLASH),y)
+# We load ourself to internal SRAM at 2001'2000
+# Check map file when changing TEXT_BASE.
+# Everything has fit into 192kB internal SRAM!
+TEXT_BASE = 0x20012000
+else
+# Running in SDRAM...
+TEXT_BASE = 0x13000000
+endif
--- /dev/null
+/*
+ * (C) Copyright 2005
+ * Ladislav Michl, 2N Telekomunikace, michl@2n.cz
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Some code shamelessly stolen back from Robin Getz.
+ */
+
+#define DEBUG
+
+#include <common.h>
+#include <exports.h>
+#include "../drivers/smc91111.h"
+
+#define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE
+
+static int verify_macaddr(char *);
+static int set_mac(char *);
+
+int eeprom(int argc, char *argv[])
+{
+ app_startup(argv);
+ if (get_version() != XF_VERSION) {
+ printf("Wrong XF_VERSION.\n");
+ printf("Application expects ABI version %d\n", XF_VERSION);
+ printf("Actual U-Boot ABI version %d\n", (int)get_version());
+ return 1;
+ }
+
+ if ((SMC_inw (BANK_SELECT) & 0xFF00) != 0x3300) {
+ printf("SMSC91111 not found.\n");
+ return 2;
+ }
+
+ if (argc != 2) {
+ printf("VoiceBlue EEPROM writer\n");
+ printf("Built: %s at %s\n", __DATE__ , __TIME__ );
+ printf("Usage:\n\t<mac_address>");
+ return 3;
+ }
+
+ set_mac(argv[1]);
+ if (verify_macaddr(argv[1])) {
+ printf("*** ERROR ***\n");
+ return 4;
+ }
+
+ return 0;
+}
+
+static u16 read_eeprom_reg(u16 reg)
+{
+ int timeout;
+
+ SMC_SELECT_BANK(2);
+ SMC_outw(reg, PTR_REG);
+
+ SMC_SELECT_BANK(1);
+ SMC_outw(SMC_inw (CTL_REG) | CTL_EEPROM_SELECT | CTL_RELOAD,
+ CTL_REG);
+ timeout = 100;
+ while((SMC_inw (CTL_REG) & CTL_RELOAD) && --timeout)
+ udelay(100);
+ if (timeout == 0) {
+ printf("Timeout Reading EEPROM register %02x\n", reg);
+ return 0;
+ }
+
+ return SMC_inw (GP_REG);
+}
+
+static int write_eeprom_reg(u16 value, u16 reg)
+{
+ int timeout;
+
+ SMC_SELECT_BANK(2);
+ SMC_outw(reg, PTR_REG);
+
+ SMC_SELECT_BANK(1);
+ SMC_outw(value, GP_REG);
+ SMC_outw(SMC_inw (CTL_REG) | CTL_EEPROM_SELECT | CTL_STORE, CTL_REG);
+ timeout = 100;
+ while ((SMC_inw(CTL_REG) & CTL_STORE) && --timeout)
+ udelay (100);
+ if (timeout == 0) {
+ printf("Timeout Writing EEPROM register %02x\n", reg);
+ return 0;
+ }
+
+ return 1;
+}
+
+static int verify_macaddr(char *s)
+{
+ u16 reg;
+ int i, err = 0;
+
+ printf("Verifying MAC Address: ");
+ err = i = 0;
+ for (i = 0; i < 3; i++) {
+ reg = read_eeprom_reg(0x20 + i);
+ printf("%02x:%02x%c", reg & 0xff, reg >> 8, i != 2 ? ':' : '\n');
+ err |= reg != ((u16 *)s)[i];
+ }
+
+ return err ? 0 : 1;
+}
+
+static int set_mac(char *s)
+{
+ int i;
+ char *e, eaddr[6];
+
+ /* turn string into mac value */
+ for (i = 0; i < 6; i++) {
+ eaddr[i] = simple_strtoul(s, &e, 16);
+ s = (*e) ? e+1 : e;
+ }
+
+ for (i = 0; i < 3; i++)
+ write_eeprom_reg(*(((u16 *)eaddr) + i), 0x20 + i);
+
+ return 0;
+}
--- /dev/null
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2004 Ales Jindra <jindra@2n.cz>
+ * (C) Copyright 2005 Ladislav Michl <michl@2n.cz>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+_TEXT_BASE:
+ .word TEXT_BASE /* SDRAM load addr from config.mk */
+
+OMAP5910_LPG1_BASE: .word 0xfffbd000
+OMAP5910_TIPB_SWITCHES_BASE: .word 0xfffbc800
+OMAP5910_MPU_TC_BASE: .word 0xfffecc00
+OMAP5910_MPU_CLKM_BASE: .word 0xfffece00
+OMAP5910_ULPD_PWR_MNG_BASE: .word 0xfffe0800
+OMAP5910_DPLL1_BASE: .word 0xfffecf00
+OMAP5910_GPIO_BASE: .word 0xfffce000
+OMAP5910_MPU_WD_TIMER_BASE: .word 0xfffec800
+OMAP5910_MPUI_BASE: .word 0xfffec900
+
+_OMAP5910_ARM_CKCTL: .word OMAP5910_ARM_CKCTL
+_OMAP5910_ARM_EN_CLK: .word OMAP5910_ARM_EN_CLK
+
+OMAP5910_MPUI_CTRL: .word 0x0000ff1b
+
+VAL_EMIFS_CS0_CONFIG: .word 0x00009090
+VAL_EMIFS_CS1_CONFIG: .word 0x00003031
+VAL_EMIFS_CS2_CONFIG: .word 0x00003031
+VAL_EMIFS_CS3_CONFIG: .word 0x0000c0c0
+VAL_EMIFS_DYN_WAIT: .word 0x00000000
+/* autorefresh counter 0x246 ((64000000/13.4)-400)/8192) */
+ /* SLRF SD_RET ARE SDRAM_TYPE ARCV SDRAM_FREQUENCY PWD CLK */
+VAL_EMIFF_SDRAM_CONFIG: .word ((0 << 0) | (0 << 1) | (3 << 2) | (0xd << 4) | (0x246 << 8) | (0 << 24) | (0 << 26) | (0 << 27))
+VAL_EMIFF_SDRAM_CONFIG2: .word 0x00000003
+VAL_EMIFF_MRS: .word 0x00000037
+
+/*
+ * GPIO04 - D4 (Onboard LED)
+ * GPIO07 - LAN91C111 reset
+ */
+GPIO_DIRECTION:
+ .word 0x0000ff6f
+/*
+ * Disable everything, but D4 LED (connected through invertor)
+ */
+GPIO_OUTPUT:
+ .word 0x00000010
+
+MUX_CONFIG_BASE:
+ .word 0xfffe1000
+
+MUX_CONFIG_VALUES:
+ .align 4
+ .word 0x00000000 @ FUNC_MUX_CTRL_0
+ .word 0x00000000 @ FUNC_MUX_CTRL_1
+ .word 0x00000000 @ FUNC_MUX_CTRL_2
+ .word 0x00000000 @ FUNC_MUX_CTRL_3
+ .word 0x00000000 @ FUNC_MUX_CTRL_4
+ .word 0x12082480 @ FUNC_MUX_CTRL_5
+ .word 0x00000004 @ FUNC_MUX_CTRL_6
+ .word 0x00000003 @ FUNC_MUX_CTRL_7
+ .word 0x10001200 @ FUNC_MUX_CTRL_8
+ .word 0x01201012 @ FUNC_MUX_CTRL_9
+ .word 0x02081248 @ FUNC_MUX_CTRL_A
+ .word 0x00001248 @ FUNC_MUX_CTRL_B
+ .word 0x12240000 @ FUNC_MUX_CTRL_C
+ .word 0x00002000 @ FUNC_MUX_CTRL_D
+ .word 0x00000000 @ PULL_DWN_CTRL_0
+ .word 0x0000085f @ PULL_DWN_CTRL_1
+ .word 0x01001000 @ PULL_DWN_CTRL_2
+ .word 0x00000000 @ PULL_DWN_CTRL_3
+ .word 0x00000000 @ GATE_INH_CTRL_0
+ .word 0x00000000 @ VOLTAGE_CTRL_0
+ .word 0x00000000 @ TEST_DBG_CTRL_0
+ .word 0x00000006 @ MOD_CONF_CTRL_0
+ .word 0x0000eaef @ COMP_MODE_CTRL_0
+
+MUX_CONFIG_OFFSETS:
+ .align 1
+ .byte 0x00 @ FUNC_MUX_CTRL_0
+ .byte 0x04 @ FUNC_MUX_CTRL_1
+ .byte 0x08 @ FUNC_MUX_CTRL_2
+ .byte 0x10 @ FUNC_MUX_CTRL_3
+ .byte 0x14 @ FUNC_MUX_CTRL_4
+ .byte 0x18 @ FUNC_MUX_CTRL_5
+ .byte 0x1c @ FUNC_MUX_CTRL_6
+ .byte 0x20 @ FUNC_MUX_CTRL_7
+ .byte 0x24 @ FUNC_MUX_CTRL_8
+ .byte 0x28 @ FUNC_MUX_CTRL_9
+ .byte 0x2c @ FUNC_MUX_CTRL_A
+ .byte 0x30 @ FUNC_MUX_CTRL_B
+ .byte 0x34 @ FUNC_MUX_CTRL_C
+ .byte 0x38 @ FUNC_MUX_CTRL_D
+ .byte 0x40 @ PULL_DWN_CTRL_0
+ .byte 0x44 @ PULL_DWN_CTRL_1
+ .byte 0x48 @ PULL_DWN_CTRL_2
+ .byte 0x4c @ PULL_DWN_CTRL_3
+ .byte 0x50 @ GATE_INH_CTRL_0
+ .byte 0x60 @ VOLTAGE_CTRL_0
+ .byte 0x70 @ TEST_DBG_CTRL_0
+ .byte 0x80 @ MOD_CONF_CTRL_0
+ .byte 0x0c @ COMP_MODE_CTRL_0
+ .byte 0xff
+
+.globl platformsetup
+platformsetup:
+ /* Improve performance a bit... */
+ mrc p15, 0, r1, c0, c0, 0 @ read C15 ID register
+ mrc p15, 0, r1, c0, c0, 1 @ read C15 Cache information register
+ mrc p15, 0, r1, c1, c0, 0 @ read C15 Control register
+ orr r1, r1, #0x1000 @ enable I-cache, map interrupt vector 0xffff0000
+ mcr p15, 0, r1, c1, c0, 0 @ write C15 Control register
+ mov r1, #0x00
+ mcr p15, 0, r1, c7, c5, 0 @ Flush I-cache
+ nop
+ nop
+ nop
+ nop
+
+ /* Setup clocking mode */
+ ldr r0, OMAP5910_MPU_CLKM_BASE @ prepare base of CLOCK unit
+ ldrh r1, [r0, #0x18] @ get reset status
+ bic r1, r1, #(7 << 11) @ clear clock select
+ orr r1, r1, #(2 << 11) @ set synchronous scalable
+ mov r2, #0 @ set wait counter to 100 clock cycles
+
+icache_loop:
+ cmp r2, #0x01
+ streqh r1, [r0, #0x18]
+ add r2, r2, #0x01
+ cmp r2, #0x10
+ bne icache_loop
+ nop
+
+ /* Setup clock divisors */
+ ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit
+ ldr r1, _OMAP5910_ARM_CKCTL
+ orr r1, r1, #0x2000 @ enable DSP clock
+ strh r1, [r0, #0x00] @ setup clock divisors
+
+ /* Setup DPLL to generate requested freq */
+ ldr r0, OMAP5910_DPLL1_BASE @ base of DPLL1 register
+ mov r1, #0x0010 @ set PLL_ENABLE
+ orr r1, r1, #0x2000 @ set IOB to new locking
+ orr r1, r1, #(OMAP5910_DPLL_MUL << 7) @ setup multiplier CLKREF
+ orr r1, r1, #(OMAP5910_DPLL_DIV << 5) @ setup divider CLKREF
+ strh r1, [r0] @ write
+
+locking:
+ ldrh r1, [r0] @ get DPLL value
+ tst r1, #0x01
+ beq locking @ while LOCK not set
+
+ /* Enable clock */
+ ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit
+ mov r1, #(1 << 10) @ disable idle mode do not check
+ @ nWAKEUP pin, other remain active
+ strh r1, [r0, #0x04]
+ ldr r1, _OMAP5910_ARM_EN_CLK
+ strh r1, [r0, #0x08]
+ mov r1, #0x003f @ FLASH.RP not enabled in idle and
+ @ max delayed ( 32 x CLKIN )
+ strh r1, [r0, #0x0c]
+
+ /* Configure 5910 pins functions to match our board. */
+ ldr r0, MUX_CONFIG_BASE
+ adr r1, MUX_CONFIG_VALUES
+ adr r2, MUX_CONFIG_OFFSETS
+next_mux_cfg:
+ ldrb r3, [r2], #1
+ ldr r4, [r1], #4
+ cmp r3, #0xff
+ strne r4, [r0, r3]
+ bne next_mux_cfg
+
+ /* Configure GPIO pins (also enables onboard LED) */
+ ldr r0, OMAP5910_GPIO_BASE
+ ldr r1, GPIO_OUTPUT
+ strh r1, [r0, #0x04]
+ ldr r1, GPIO_DIRECTION
+ strh r1, [r0, #0x08]
+
+ /* EnablePeripherals */
+ ldr r0, OMAP5910_MPU_CLKM_BASE @ CLOCK unit
+ mov r1, #0x0001 @ Peripheral enable
+ strh r1, [r0, #0x14]
+
+ /* Program LED Pulse Generator */
+ ldr r0, OMAP5910_LPG1_BASE @ 1st LED Pulse Generator
+ mov r1, #0x7F @ Set obscure frequency in
+ strb r1, [r0, #0x00] @ LCR
+ mov r1, #0x01 @ Enable clock (CLK_EN) in
+ strb r1, [r0, #0x04] @ PMR
+
+ /* TIPB Lock UART1 */
+ ldr r0, OMAP5910_TIPB_SWITCHES_BASE @ prepare base of TIPB switches
+ mov r1, #1 @ ARM allocated
+ strh r1, [r0,#0x04] @ clear IRQ line and status bits
+ strh r1, [r0,#0x00]
+ ldrh r1, [r0,#0x04]
+
+ /* Disable watchdog */
+ ldr r0, OMAP5910_MPU_WD_TIMER_BASE
+ mov r1, #0xf5
+ strh r1, [r0, #0x8]
+ mov r1, #0xa0
+ strh r1, [r0, #0x8]
+
+ /* Enable MCLK */
+ ldr r0, OMAP5910_ULPD_PWR_MNG_BASE
+ mov r1, #0x6
+ strh r1, [r0, #0x34]
+ strh r1, [r0, #0x34]
+
+ /* Setup clock divisors */
+ ldr r0, OMAP5910_ULPD_PWR_MNG_BASE @ base of ULDPL DPLL1 register
+
+ mov r1, #0x0010 @ set PLL_ENABLE
+ orr r1, r1, #0x2000 @ set IOB to new locking
+ strh r1, [r0] @ write
+
+ulocking:
+ ldrh r1, [r0] @ get DPLL value
+ tst r1, #1
+ beq ulocking @ while LOCK not set
+
+ /* EMIF init */
+ ldr r0, OMAP5910_MPU_TC_BASE
+ ldrh r1, [r0, #0x0c] @ EMIFS_CONFIG_REG
+ bic r1, r1, #0x0c @ pwr down disabled, flash WP
+ orr r1, r1, #0x01
+ str r1, [r0, #0x0c]
+
+ ldr r1, VAL_EMIFS_CS0_CONFIG
+ str r1, [r0, #0x10] @ EMIFS_CS0_CONFIG
+ ldr r1, VAL_EMIFS_CS1_CONFIG
+ str r1, [r0, #0x14] @ EMIFS_CS1_CONFIG
+ ldr r1, VAL_EMIFS_CS2_CONFIG
+ str r1, [r0, #0x18] @ EMIFS_CS2_CONFIG
+ ldr r1, VAL_EMIFS_CS3_CONFIG
+ str r1, [r0, #0x1c] @ EMIFS_CS3_CONFIG
+ ldr r1, VAL_EMIFS_DYN_WAIT
+ str r1, [r0, #0x40] @ EMIFS_CFG_DYN_WAIT
+
+ /* Setup SDRAM */
+ ldr r1, VAL_EMIFF_SDRAM_CONFIG
+ str r1, [r0, #0x20] @ EMIFF_SDRAM_CONFIG
+ ldr r1, VAL_EMIFF_SDRAM_CONFIG2
+ str r1, [r0, #0x3c] @ EMIFF_SDRAM_CONFIG2
+ ldr r1, VAL_EMIFF_MRS
+ str r1, [r0, #0x24] @ EMIFF_MRS
+ /* SDRAM needs 100us to stabilize */
+ mov r0, #0x4000
+sdelay:
+ subs r0, r0, #0x1
+ bne sdelay
+
+ /* back to arch calling code */
+ mov pc, lr
+.end
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/arm925t/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
--- /dev/null
+/*
+ * (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+int board_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ unsigned int val;
+
+ *((volatile unsigned char *) VOICEBLUE_LED_REG) = 0xaa;
+
+ /* arch number of VoiceBlue board */
+ /* TODO: use define from asm/mach-types.h */
+ gd->bd->bi_arch_number = 218;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0x10000100;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ *((volatile unsigned short *) VOICEBLUE_LED_REG) = 0xff;
+
+ /* Take the Ethernet controller out of reset and wait
+ * for the EEPROM load to complete. */
+ *((volatile unsigned short *) GPIO_DATA_OUTPUT_REG) |= 0x80;
+ udelay(10); /* doesn't work before interrupt_init call */
+ *((volatile unsigned short *) GPIO_DATA_OUTPUT_REG) &= ~0x80;
+ udelay(500);
+
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+ return 0;
+}
+
+#ifndef VOICEBLUE_SMALL_FLASH
+
+#include <jffs2/jffs2.h>
+
+extern flash_info_t flash_info[];
+static struct part_info partinfo;
+static int current_part = -1;
+
+/* Partition table (Linux MTD see it this way)
+ *
+ * 0 - U-Boot
+ * 1 - env
+ * 2 - redundant env
+ * 3 - data1 (jffs2)
+ * 4 - data2 (jffs2)
+ */
+
+static struct {
+ ulong offset;
+ ulong size;
+} part[5];
+
+static void partition_flash(flash_info_t *info)
+{
+ char mtdparts[128];
+ int i, n, size, psize;
+ const ulong plen[3] = { CFG_MONITOR_LEN, CFG_ENV_SIZE, CFG_ENV_SIZE };
+
+ size = n = 0;
+ for (i = 0; i < 4; i++) {
+ part[i].offset = info->start[n];
+ psize = i < 3 ? plen[i] : (info->size - size) / 2;
+ while (part[i].size < psize) {
+ if (++n > info->sector_count) {
+ printf("Partitioning error. System halted.\n");
+ while (1) ;
+ }
+ part[i].size += info->start[n] - info->start[n - 1];
+ }
+ size += part[i].size;
+ }
+ part[4].offset = info->start[n];
+ part[4].size = info->start[info->sector_count - 1] - info->start[n];
+
+ sprintf(mtdparts, "omapflash.0:"
+ "%dk(U-Boot)ro,%dk(env),%dk(r_env),%dk(data1),-(data2)",
+ part[0].size >> 10, part[1].size >> 10,
+ part[2].size >> 10, part[3].size >> 10);
+ setenv ("mtdparts", mtdparts);
+}
+
+struct part_info* jffs2_part_info(int part_num)
+{
+ void *jffs2_priv_saved = partinfo.jffs2_priv;
+
+ if (part_num != 3 && part_num != 4)
+ return NULL;
+
+ if (current_part != part_num) {
+ memset(&partinfo, 0, sizeof(partinfo));
+ current_part = part_num;
+ partinfo.offset = (char*) part[part_num].offset;
+ partinfo.size = part[part_num].size;
+ partinfo.usr_priv = ¤t_part;
+ partinfo.jffs2_priv = jffs2_priv_saved;
+ }
+
+ return &partinfo;
+}
+
+#endif
+
+int misc_init_r(void)
+{
+ *((volatile unsigned short *) VOICEBLUE_LED_REG) = 0x55;
+
+#ifndef VOICEBLUE_SMALL_FLASH
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf("Unknown flash. System halted.\n");
+ while (1) ;
+ }
+ partition_flash(&flash_info[0]);
+#endif
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ *((volatile unsigned char *) VOICEBLUE_LED_REG) = 0x00;
+
+ return 0;
+}
extern int do_bootm (cmd_tbl_t *, int, int, char *[]);
-static int netboot_common (int, cmd_tbl_t *, int , char *[]);
+static int netboot_common (proto_t, cmd_tbl_t *, int , char *[]);
int do_bootp (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
}
static int
-netboot_common (int proto, cmd_tbl_t *cmdtp, int argc, char *argv[])
+netboot_common (proto_t proto, cmd_tbl_t *cmdtp, int argc, char *argv[])
{
char *s;
int rcode = 0;
*/
void reset_cpu (ulong ignored)
{
- S3C24X0_WATCHDOG * const watchdog;
+ volatile S3C24X0_WATCHDOG * watchdog;
#ifdef CONFIG_TRAB
+ extern void disable_vfd (void);
+
disable_vfd();
#endif
gd->inp_clk = CFG_MPC8220_CLKIN;
/* Read XLB to PCI(INP) clock multiplier */
- pci2bus = (*((volatile u32 *)PCI_REG_PCIGSCR) &
+ pci2bus = (*((volatile u32 *)PCI_REG_PCIGSCR) &
PCI_REG_PCIGSCR_PCI2XLB_CLK_MASK)>>PCI_REG_PCIGSCR_PCI2XLB_CLK_BIT;
/* XLB bus clock */
/* MBAR is mirrored into the MBAR SPR */
mtspr MBAR,r3
- mtspr SPRN_SPRG7W,r3
+ mtspr SPRN_SPRG7W,r3
lis r4, CFG_DEFAULT_MBAR@h
stw r3, 0(r4)
#endif /* CFG_DEFAULT_MBAR */
/* write to CSR: RX/TX baud rate from timers */
psc->sr_csr = 0xdd000000;
- psc->mr1_2 = PSC_MR1_BITS_CHAR_8 | PSC_MR1_NO_PARITY | PSC_MR2_STOP_BITS_1;
+ psc->mr1_2 = PSC_MR1_BITS_CHAR_8 | PSC_MR1_NO_PARITY | PSC_MR2_STOP_BITS_1;
/* Setting up BaudRate */
counter = ((gd->bus_clk / gd->baudrate)) >> 5;
struct phy_info *curphy;
/* Assign a Physical address to the TBI */
-
+
{
volatile tsec_t *regs = (volatile tsec_t *)(TSEC_BASE_ADDR);
regs->tbipa = TBIPA_VALUE;
uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv)
{
- unsigned int speed;
- if (priv->link) {
- speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK;
-
- switch (speed) {
- case MIIM_LXT971_SR2_10HDX:
- priv->speed = 10;
- priv->duplexity = 0;
- break;
- case MIIM_LXT971_SR2_10FDX:
- priv->speed = 10;
- priv->duplexity = 1;
- break;
- case MIIM_LXT971_SR2_100HDX:
- priv->speed = 100;
- priv->duplexity = 0;
- default:
- priv->speed = 100;
- priv->duplexity = 1;
- break;
- }
- } else {
- priv->speed = 0;
- priv->duplexity = 0;
- }
-
- return 0;
+ unsigned int speed;
+ if (priv->link) {
+ speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK;
+
+ switch (speed) {
+ case MIIM_LXT971_SR2_10HDX:
+ priv->speed = 10;
+ priv->duplexity = 0;
+ break;
+ case MIIM_LXT971_SR2_10FDX:
+ priv->speed = 10;
+ priv->duplexity = 1;
+ break;
+ case MIIM_LXT971_SR2_100HDX:
+ priv->speed = 100;
+ priv->duplexity = 0;
+ default:
+ priv->speed = 100;
+ priv->duplexity = 1;
+ break;
+ }
+ } else {
+ priv->speed = 0;
+ priv->duplexity = 0;
+ }
+
+ return 0;
}
static struct phy_info phy_info_lxt971 = {
/*
* Flexbus Chipselect configuration
- * Beware: Some CS# seem to be mandatory (if these CS# are not set,
- * board can hang-up in unpredictable place).
+ * Beware: Some CS# seem to be mandatory (if these CS# are not set,
+ * board can hang-up in unpredictable place).
* Sorcery_Memory_Map v0.3 is possibly wrong with CPLD CS#
*/
/* Workaround of hang-up after setting ctrl register for flash
After reset this register has value 0x003ffd80, which differs
- from suggested only by the number of wait states.
+ from suggested only by the number of wait states.
#define CFG_CS0_CTRL 0x003f1580
*/
/*
* Various low-level settings
*/
-#define CFG_HID0_INIT 0
-#define CFG_HID0_FINAL 0
+#define CFG_HID0_INIT 0
+#define CFG_HID0_FINAL 0
#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl
+ *
+ * Configuation settings for the TI OMAP VoiceBlue board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/omap1510.h>
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARM925T 1 /* This is an arm925t CPU */
+#define CONFIG_OMAP 1 /* in a TI OMAP core */
+#define CONFIG_OMAP1510 1 /* which is in a 5910 */
+
+/* Input clock of PLL */
+#define CONFIG_SYS_CLK_FREQ 150000000 /* 150MHz input clock */
+#define CONFIG_XTAL_FREQ 12000000
+
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+
+#define CONFIG_MISC_INIT_R /* There is nothing to really init */
+#define BOARD_LATE_INIT /* but we flash the LEDs here */
+
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS 1
+#define CONFIG_INITRD_TAG 1
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
+#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE SZ_64M
+
+#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
+#define PHYS_FLASH_2 0x0c000000
+
+#define CFG_LOAD_ADDR PHYS_SDRAM_1 + 0x400000 /* default load address */
+
+/*
+ * FLASH organization
+ */
+#define CFG_FLASH_CFI /* Flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER /* Use the common driver */
+#define CFG_MAX_FLASH_BANKS 1
+#ifdef VOICEBLUE_SMALL_FLASH
+#define CFG_FLASH_BANKS_LIST { PHYS_FLASH_2 }
+#else
+#define CFG_FLASH_BANKS_LIST { PHYS_FLASH_1 }
+#endif
+
+/* FIXME: Does not work on AMD flash */
+/* #define CFG_FLASH_USE_BUFFER_WRITE 1 */ /* use buffered writes (20x faster) */
+#define CFG_MAX_FLASH_SECT 512 /* max # of sectors on one chip */
+
+#define CFG_MONITOR_BASE PHYS_FLASH_1
+#define CFG_MONITOR_LEN SZ_128K
+
+/*
+ * Environment settings
+ */
+#ifdef VOICEBLUE_SMALL_FLASH
+#define CFG_ENV_IS_NOWHERE
+#define CFG_ENV_SIZE SZ_1K
+#else
+#define CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_ADDR (PHYS_FLASH_1 + CFG_MONITOR_LEN)
+#define CFG_ENV_SIZE SZ_8K
+#define CFG_ENV_SECT_SIZE SZ_64K
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CFG_JFFS_CUSTOM_PART /* see board/voiceblue/jffs2parts.c */
+#endif
+
+/*
+ * Size of malloc() pool
+ */
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#ifdef VOICEBLUE_SMALL_FLASH
+#define CFG_MALLOC_LEN (SZ_64K - CFG_GBL_DATA_SIZE)
+#else
+#define CFG_MALLOC_LEN (SZ_4M - CFG_GBL_DATA_SIZE)
+#endif
+
+/*
+ * The stack size is set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE SZ_8K /* regular stack */
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_DRIVER_SMC91111
+#define CONFIG_SMC91111_BASE 0x08000300
+
+/*
+ * NS16550 Configuration
+ */
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE (-4)
+#define CFG_NS16550_CLK (CONFIG_XTAL_FREQ) /* can be 12M/32Khz or 48Mhz */
+#define CFG_NS16550_COM1 OMAP1510_UART1_BASE /* uart1 */
+
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+#ifdef VOICEBLUE_SMALL_FLASH
+#define CONFIG_COMMANDS (CFG_CMD_BDI | \
+ CFG_CMD_LOADB | \
+ CFG_CMD_IMI | \
+ CFG_CMD_FLASH | \
+ CFG_CMD_MEMORY | \
+ CFG_CMD_NET | \
+ CFG_CMD_BOOTD | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_PING | \
+ CFG_CMD_RUN)
+#else
+#define CONFIG_COMMANDS (CFG_CMD_BDI | \
+ CFG_CMD_LOADB | \
+ CFG_CMD_IMI | \
+ CFG_CMD_FLASH | \
+ CFG_CMD_MEMORY | \
+ CFG_CMD_NET | \
+ CFG_CMD_ENV | \
+ CFG_CMD_BOOTD | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_PING | \
+ CFG_CMD_RUN | \
+ CFG_CMD_JFFS2)
+#endif
+
+#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
+#define CONFIG_LOOPW
+
+#ifdef VOICEBLUE_SMALL_FLASH
+#define CONFIG_BOOTDELAY 0
+#undef CONFIG_BOOTARGS /* the preboot command will set bootargs*/
+#define CFG_AUTOLOAD "n" /* No autoload */
+#define CONFIG_PREBOOT "run setup"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "setup=setenv bootargs console=ttyS0,$(baudrate) " \
+ "root=/dev/nfs ip=dhcp\0" \
+ "update=erase c000000 c03ffff; " \
+ "cp.b 10400000 c000000 $(filesize)\0"
+#else
+#define CONFIG_BOOTDELAY 3
+#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
+#define CFG_AUTOLOAD "n" /* No autoload */
+#define CONFIG_BOOTCOMMAND "run nboot"
+#define CONFIG_PREBOOT "run setup"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "ospart=0\0" \
+ "swapos=no\0" \
+ "setpart=" \
+ "if test $swapos = yes; then " \
+ "if test $ospart -eq 0; then chpart 4; else chpart 3; fi; "\
+ "setenv swapos no; saveenv; " \
+ "else " \
+ "if test $ospart -eq 0; then chpart 3; else chpart 4; fi; "\
+ "fi\0" \
+ "setup=setenv bootargs console=ttyS0,$baudrate " \
+ "mtdparts=$mtdparts\0" \
+ "nfsargs=setenv bootargs $bootargs " \
+ "root=/dev/nfs ip=dhcp; run setpart\0" \
+ "flashargs=setenv bootargs $bootargs " \
+ "root=/dev/mtdblock$partition " \
+ "rootfstype=jffs2; run setpart\0" \
+ "nboot=run nfsargs; bootp; tftp; bootm\0" \
+ "fboot=run flashargs; fsload /boot/uImage; bootm\0"
+#endif
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#ifndef VOICEBLUE_SMALL_FLASH
+#define CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#define CONFIG_AUTO_COMPLETE
+#endif
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "# " /* Monitor Command Prompt */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START PHYS_SDRAM_1
+#define CFG_MEMTEST_END PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE
+
+#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
+
+/* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1.
+ * This time is further subdivided by a local divisor.
+ */
+#define CFG_TIMERBASE OMAP1510_TIMER1_BASE
+#define CFG_PVT 7 /* 2^(pvt+1), divide by 256 */
+#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
+
+#define OMAP5910_DPLL_DIV 1
+#define OMAP5910_DPLL_MUL ((CONFIG_SYS_CLK_FREQ * \
+ (1 << OMAP5910_DPLL_DIV)) / CONFIG_XTAL_FREQ)
+
+#define OMAP5910_ARM_PER_DIV 2 /* CKL/4 */
+#define OMAP5910_LCD_DIV 2 /* CKL/4 */
+#define OMAP5910_ARM_DIV 0 /* CKL/1 */
+#define OMAP5910_DSP_DIV 0 /* CKL/1 */
+#define OMAP5910_TC_DIV 1 /* CKL/2 */
+#define OMAP5910_DSP_MMU_DIV 1 /* CKL/2 */
+#define OMAP5910_ARM_TIM_SEL 1 /* CKL used for MPU timers */
+
+#define OMAP5910_ARM_EN_CLK 0x03d6 /* 0000 0011 1101 0110b Clock Enable */
+#define OMAP5910_ARM_CKCTL ((OMAP5910_ARM_PER_DIV) | \
+ (OMAP5910_LCD_DIV << 2) | \
+ (OMAP5910_ARM_DIV << 4) | \
+ (OMAP5910_DSP_DIV << 6) | \
+ (OMAP5910_TC_DIV << 8) | \
+ (OMAP5910_DSP_MMU_DIV << 10) | \
+ (OMAP5910_ARM_TIM_SEL << 12))
+
+#define VOICEBLUE_LED_REG 0x04030000
+
+#endif /* __CONFIG_H */
uint tmp;
timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE3);
-
+
while (usec > 0) {
if (usec > 65000)
tmp = 65000;
timerp[MCFTIMER_PCSR] =
(5 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW;
- timerp[MCFTIMER_PMR] = tmp;
+ timerp[MCFTIMER_PMR] = tmp;
while (timerp[MCFTIMER_PCNTR] > 0);
}
}
projects / u-boot / commitdiff