]> git.sur5r.net Git - u-boot/commitdiff
powerpc/c29xpcie: Add secure boot support
authorPo Liu <Po.Liu@freescale.com>
Wed, 26 Nov 2014 01:38:48 +0000 (09:38 +0800)
committerYork Sun <yorksun@freescale.com>
Fri, 16 Jan 2015 17:27:06 +0000 (09:27 -0800)
Add NOR and SPI flash secure boot target for C29XPCIE board.

Signed-off-by: Po Liu <Po.Liu@freescale.com>
Signed-off-by: Mingkai.Hu <Mingkai.Hu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
board/freescale/c29xpcie/MAINTAINERS
configs/C29XPCIE_NOR_SECBOOT_defconfig [new file with mode: 0644]
configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig [new file with mode: 0644]
include/configs/C29XPCIE.h

index db2e5e3bd321c33fddbd5f7e92e620347810bde2..33088396f572f790df27f4f358478dcf524f11d2 100644 (file)
@@ -6,3 +6,5 @@ F:      include/configs/C29XPCIE.h
 F:     configs/C29XPCIE_defconfig
 F:     configs/C29XPCIE_NAND_defconfig
 F:     configs/C29XPCIE_SPIFLASH_defconfig
+F:     configs/C29XPCIE_NOR_SECBOOT_defconfig
+F:     configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig
diff --git a/configs/C29XPCIE_NOR_SECBOOT_defconfig b/configs/C29XPCIE_NOR_SECBOOT_defconfig
new file mode 100644 (file)
index 0000000..86751cf
--- /dev/null
@@ -0,0 +1,4 @@
+CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,SECURE_BOOT"
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_C29XPCIE=y
diff --git a/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig b/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig
new file mode 100644 (file)
index 0000000..d1a42b2
--- /dev/null
@@ -0,0 +1,4 @@
+CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,SPIFLASH,SECURE_BOOT"
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_C29XPCIE=y
index ecb3d7b25fd710f6ac8d4abfeb24af901987a11c..e24b9233687eef4dcccd8c3c8a842e95b25d22b2 100644 (file)
 
 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
 
+#include <asm/fsl_secure_boot.h>
+
 #endif /* __CONFIG_H */