ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR,
txpp, rxpp);
#endif
+
+#ifdef CONFIG_XILINX_LL_TEMAC
+# ifdef XILINX_LLTEMAC_BASEADDR
+# ifdef XILINX_LLTEMAC_FIFO_BASEADDR
+ ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR,
+ XILINX_LL_TEMAC_M_FIFO, XILINX_LLTEMAC_FIFO_BASEADDR);
+# elif XILINX_LLTEMAC_SDMA_CTRL_BASEADDR
+# if XILINX_LLTEMAC_SDMA_USE_DCR == 1
+ ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR,
+ XILINX_LL_TEMAC_M_SDMA_DCR,
+ XILINX_LLTEMAC_SDMA_CTRL_BASEADDR);
+# else
+ ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR,
+ XILINX_LL_TEMAC_M_SDMA_PLB,
+ XILINX_LLTEMAC_SDMA_CTRL_BASEADDR);
+# endif
+# endif
+# endif
+# ifdef XILINX_LLTEMAC_BASEADDR1
+# ifdef XILINX_LLTEMAC_FIFO_BASEADDR1
+ ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1,
+ XILINX_LL_TEMAC_M_FIFO, XILINX_LLTEMAC_FIFO_BASEADDR1);
+# elif XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1
+# if XILINX_LLTEMAC_SDMA_USE_DCR == 1
+ ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1,
+ XILINX_LL_TEMAC_M_SDMA_DCR,
+ XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1);
+# else
+ ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1,
+ XILINX_LL_TEMAC_M_SDMA_PLB,
+ XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1);
+# endif
+# endif
+# endif
+#endif
+
return ret;
}