Changes since U-Boot 1.1.4:
======================================================================
+* Update PK1C20 board
+ -Update base addresses for standard configuration
+ -Eliminate use of CACHE_BYPASS in board code
+ Patch by Scott McNutt, 08 Jun 2006
+
* Nios II - Fix I/O Macros and mini-app stubs
-Fix asm/io.h macros
-Eliminate use of CACHE_BYPASS in cpu code
#if defined(CONFIG_NIOS)
#include <nios.h>
#else
-#include <nios2.h>
+#include <asm/io.h>
#endif
#define SECTSZ (64 * 1024)
void flash_print_info (flash_info_t * info)
{
int i, k;
- unsigned long size;
int erased;
- volatile unsigned char *flash;
+ unsigned long *addr;
printf (" Size: %ld KB in %d Sectors\n",
info->size >> 10, info->sector_count);
for (i = 0; i < info->sector_count; ++i) {
/* Check if whole sector is erased */
- if (i != (info->sector_count - 1))
- size = info->start[i + 1] - info->start[i];
- else
- size = info->start[0] + info->size - info->start[i];
erased = 1;
- flash = (volatile unsigned char *) CACHE_BYPASS(info->start[i]);
- for (k = 0; k < size; k++) {
- if (*flash++ != 0xff) {
+ addr = (unsigned long *) info->start[i];
+ for (k = 0; k < SECTSZ/sizeof(unsigned long); k++) {
+ if ( readl(addr++) != (unsigned long)-1) {
erased = 0;
break;
}
if ((i % 5) == 0)
printf ("\n ");
printf (" %08lX%s%s",
- CACHE_NO_BYPASS(info->start[i]),
+ info->start[i],
erased ? " E" : " ",
info->protect[i] ? "RO " : " ");
}
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
- volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *)
- CACHE_BYPASS(info->start[0]);
- volatile CFG_FLASH_WORD_SIZE *addr2;
+ unsigned char *addr = (unsigned char *) info->start[0];
+ unsigned char *addr2;
int prot, sect;
ulong start;
*/
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
- addr2 = (CFG_FLASH_WORD_SIZE *)
- CACHE_BYPASS((info->start[sect]));
- *addr = 0xaa;
- *addr = 0x55;
- *addr = 0x80;
- *addr = 0xaa;
- *addr = 0x55;
- *addr2 = 0x30;
+ addr2 = (unsigned char *) info->start[sect];
+ writeb (addr, 0xaa);
+ writeb (addr, 0x55);
+ writeb (addr, 0x80);
+ writeb (addr, 0xaa);
+ writeb (addr, 0x55);
+ writeb (addr2, 0x30);
/* Now just wait for 0xff & provide some user
* feedback while we wait.
*/
start = get_timer (0);
- while (*addr2 != 0xff) {
+ while ( readb (addr2) != 0xff) {
udelay (1000 * 1000);
putc ('.');
if (get_timer (start) > CFG_FLASH_ERASE_TOUT) {
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
- vu_char *cmd = (vu_char *) CACHE_BYPASS(info->start[0]);
- vu_char *dst = (vu_char *) CACHE_BYPASS(addr);
+ vu_char *cmd = (vu_char *) info->start[0];
+ vu_char *dst = (vu_char *) addr;
unsigned char b;
ulong start;
while (cnt) {
/* Check for sufficient erase */
b = *src;
- if ((*dst & b) != b) {
- printf ("%02x : %02x\n", *dst, b);
+ if ((readb (dst) & b) != b) {
+ printf ("%02x : %02x\n", readb (dst), b);
return (2);
}
- *cmd = 0xaa;
- *cmd = 0x55;
- *cmd = 0xa0;
- *dst = b;
+ writeb (cmd, 0xaa);
+ writeb (cmd, 0x55);
+ writeb (cmd, 0xa0);
+ writeb (dst, b);
/* Verify write */
start = get_timer (0);
- while (*dst != b) {
+ while (readb (dst) != b) {
if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
return 1;
}
# MA 02111-1307 USA
#
-TEXT_BASE = 0x018e0000
+TEXT_BASE = 0x01fc0000
PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include
*/
#include <common.h>
-#include <nios2.h>
+#include <asm/io.h>
#include <nios2-io.h>
#include <status_led.h>
void __led_init (led_id_t mask, int state)
{
- nios_pio_t *pio = (nios_pio_t *)CACHE_BYPASS(CFG_LEDPIO_ADDR);
+ nios_pio_t *pio = (nios_pio_t *)CFG_LEDPIO_ADDR;
if (state == STATUS_LED_ON)
val &= ~mask;
else
val |= mask;
- pio->data = val;
+ writel (&pio->data, val);
}
void __led_set (led_id_t mask, int state)
{
- nios_pio_t *pio = (nios_pio_t *)CACHE_BYPASS(CFG_LEDPIO_ADDR);
+ nios_pio_t *pio = (nios_pio_t *)CFG_LEDPIO_ADDR;
if (state == STATUS_LED_ON)
val &= ~mask;
else
val |= mask;
- pio->data = val;
+ writel (&pio->data, val);
}
void __led_toggle (led_id_t mask)
{
- nios_pio_t *pio = (nios_pio_t *)CACHE_BYPASS(CFG_LEDPIO_ADDR);
+ nios_pio_t *pio = (nios_pio_t *)CFG_LEDPIO_ADDR;
val ^= mask;
- pio->data = val;
+ writel (&pio->data, val);
}
#define CFG_RESET_ADDR 0x00000000 /* Hard-reset address */
#define CFG_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/
-#define CFG_NIOS_SYSID_BASE 0x00920828 /* System id address */
+#define CFG_NIOS_SYSID_BASE 0x021208b8 /* System id address */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/
/*------------------------------------------------------------------------
#define CFG_FLASH_SIZE 0x00800000 /* 8 MByte */
#define CFG_SDRAM_BASE 0x01000000 /* SDRAM base addr */
#define CFG_SDRAM_SIZE 0x01000000 /* 16 MByte */
-#define CFG_SRAM_BASE 0x00800000 /* SRAM base addr */
+#define CFG_SRAM_BASE 0x02000000 /* SRAM base addr */
#define CFG_SRAM_SIZE 0x00100000 /* 1 MB (only 1M mapped)*/
/*------------------------------------------------------------------------
* -Global data is placed below the heap.
* -The stack is placed below global data (&grows down).
*----------------------------------------------------------------------*/
-#define CFG_MONITOR_LEN (128 * 1024) /* Reserve 128k */
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 128k */
#define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/
#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
* CONSOLE
*----------------------------------------------------------------------*/
#if defined(CONFIG_CONSOLE_JTAG)
-#define CFG_NIOS_CONSOLE 0x00920820 /* JTAG UART base addr */
+#define CFG_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */
#else
-#define CFG_NIOS_CONSOLE 0x009208a0 /* UART base addr */
+#define CFG_NIOS_CONSOLE 0x02120840 /* UART base addr */
#endif
#define CFG_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */
* EPCS Device -- wne CFG_NIOS_EPCSBASE is defined code/commands for
* epcs device access is enabled. The base address is the epcs
* _register_ base address, NOT THE ADDRESS OF THE MEMORY BLOCK.
- * The register base is currently at offset 0x400 from the memory base.
+ * The register base is currently at offset 0x600 from the memory base.
*----------------------------------------------------------------------*/
-#define CFG_NIOS_EPCSBASE 0x00900400 /* EPCS register base */
+#define CFG_NIOS_EPCSBASE 0x02100200 /* EPCS register base */
/*------------------------------------------------------------------------
* DEBUG
* registers, we can slow it down to 10 msec using TMRCNT. If the default
* period is acceptable, TMRCNT can be left undefined.
*----------------------------------------------------------------------*/
-#define CFG_NIOS_TMRBASE 0x00920860 /* Tick timer base addr */
+#define CFG_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */
#define CFG_NIOS_TMRIRQ 3 /* Timer IRQ num */
#define CFG_NIOS_TMRMS 10 /* 10 msec per tick */
#define CFG_NIOS_TMRCNT (CFG_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
* must implement its own led routines -- leds are, after all,
* board-specific, no?
*----------------------------------------------------------------------*/
-#define CFG_LEDPIO_ADDR 0x00920840 /* LED PIO base addr */
+#define CFG_LEDPIO_ADDR 0x02120870 /* LED PIO base addr */
#define CONFIG_STATUS_LED /* Enable status driver */
#define STATUS_LED_BIT 1 /* Bit-0 on PIO */
* way out to avoid changes there -- define the base address to ensure
* cache bypass so there's no need to monkey with inx/outx macros.
*----------------------------------------------------------------------*/
-#define CONFIG_SMC91111_BASE 0x80910300 /* Base addr (bypass) */
+#define CONFIG_SMC91111_BASE 0x82110300 /* Base addr (bypass) */
#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */
#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */
#define CONFIG_SMC_USE_32_BIT /* 32-bit interface */
projects / u-boot / commitdiff