+++ /dev/null
-/*
- * Copyright (C) 2011
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef _DV_AINTC_DEFS_H_
-#define _DV_AINTC_DEFS_H_
-
-struct dv_aintc_regs {
- unsigned int fiq0; /* 0x00 */
- unsigned int fiq1; /* 0x04 */
- unsigned int irq0; /* 0x08 */
- unsigned int irq1; /* 0x0c */
- unsigned int fiqentry; /* 0x10 */
- unsigned int irqentry; /* 0x14 */
- unsigned int eint0; /* 0x18 */
- unsigned int eint1; /* 0x1c */
- unsigned int intctl; /* 0x20 */
- unsigned int eabase; /* 0x24 */
- unsigned char rsvd0[8]; /* 0x28 */
- unsigned int intpri0; /* 0x30 */
- unsigned int intpri1; /* 0x34 */
- unsigned int intpri2; /* 0x38 */
- unsigned int intpri3; /* 0x3c */
- unsigned int intpri4; /* 0x40 */
- unsigned int intpri5; /* 0x44 */
- unsigned int intpri6; /* 0x48 */
- unsigned int intpri7; /* 0x4c */
-};
-
-#define dv_aintc_regs ((struct dv_aintc_regs *)DAVINCI_ARM_INTC_BASE)
-
-#define DV_AINTC_INTCTL_IDMODE (1 << 2)
-
-#endif /* _DV_AINTC_DEFS_H_ */
+++ /dev/null
-/*
- * SoC-specific lowlevel code for DA850
- *
- * Copyright (C) 2011
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef __DA850_LOWLEVEL_H
-#define __DA850_LOWLEVEL_H
-
-#include <asm/arch/pinmux_defs.h>
-
-/* pinmux_resource[] vector is defined in the board specific file */
-extern const struct pinmux_resource pinmuxes[];
-extern const int pinmuxes_size;
-
-extern const struct lpsc_resource lpsc[];
-extern const int lpsc_size;
-
-/* NOR Boot Configuration Word Field Descriptions */
-#define DA850_NORBOOT_COPY_XK(X) ((X - 1) << 8)
-#define DA850_NORBOOT_METHOD_DIRECT (1 << 4)
-#define DA850_NORBOOT_16BIT (1 << 0)
-
-#define dv_maskbits(addr, val) \
- writel((readl(addr) & val), addr)
-
-void da850_lpc_transition(unsigned char pscnum, unsigned char module,
- unsigned char domain, unsigned char state);
-void da850_psc_init(void);
-void da850_pinmux_ctl(unsigned long offset, unsigned long mask,
- unsigned long value);
-
-#endif /* #ifndef __DA850_LOWLEVEL_H */
+++ /dev/null
-/*
- * da8xx-usb.h -- TI's DA8xx platform specific usb wrapper definitions.
- *
- * Author: Ajay Kumar Gupta <ajay.gupta@ti.com>
- *
- * Based on drivers/usb/musb/davinci.h
- *
- * Copyright (C) 2009 Texas Instruments Incorporated
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef __DA8XX_MUSB_H__
-#define __DA8XX_MUSB_H__
-
-#include <asm/arch/hardware.h>
-#include <asm/arch/gpio.h>
-
-/* Base address of da8xx usb0 wrapper */
-#define DA8XX_USB_OTG_BASE 0x01E00000
-
-/* Base address of da8xx musb core */
-#define DA8XX_USB_OTG_CORE_BASE (DA8XX_USB_OTG_BASE + 0x400)
-
-/* Timeout for DA8xx usb module */
-#define DA8XX_USB_OTG_TIMEOUT 0x3FFFFFF
-
-/*
- * DA8xx platform USB wrapper register overlay.
- */
-struct da8xx_usb_regs {
- dv_reg revision;
- dv_reg control;
- dv_reg status;
- dv_reg emulation;
- dv_reg mode;
- dv_reg autoreq;
- dv_reg srpfixtime;
- dv_reg teardown;
- dv_reg intsrc;
- dv_reg intsrc_set;
- dv_reg intsrc_clr;
- dv_reg intmsk;
- dv_reg intmsk_set;
- dv_reg intmsk_clr;
- dv_reg intsrcmsk;
- dv_reg eoi;
- dv_reg intvector;
- dv_reg grndis_size[4];
-};
-
-#define da8xx_usb_regs ((struct da8xx_usb_regs *)DA8XX_USB_OTG_BASE)
-
-/* DA8XX interrupt bits definitions */
-#define DA8XX_USB_TX_ENDPTS_MASK 0x1f /* ep0 + 4 tx */
-#define DA8XX_USB_RX_ENDPTS_MASK 0x1e /* 4 rx */
-#define DA8XX_USB_TXINT_SHIFT 0
-#define DA8XX_USB_RXINT_SHIFT 8
-
-#define DA8XX_USB_USBINT_MASK 0x01ff0000 /* 8 Mentor, DRVVBUS */
-#define DA8XX_USB_TXINT_MASK \
- (DA8XX_USB_TX_ENDPTS_MASK << DA8XX_USB_TXINT_SHIFT)
-#define DA8XX_USB_RXINT_MASK \
- (DA8XX_USB_RX_ENDPTS_MASK << DA8XX_USB_RXINT_SHIFT)
-
-/* DA8xx CFGCHIP2 (USB 2.0 PHY Control) register bits */
-#define CFGCHIP2_PHYCLKGD (1 << 17)
-#define CFGCHIP2_VBUSSENSE (1 << 16)
-#define CFGCHIP2_RESET (1 << 15)
-#define CFGCHIP2_OTGMODE (3 << 13)
-#define CFGCHIP2_NO_OVERRIDE (0 << 13)
-#define CFGCHIP2_FORCE_HOST (1 << 13)
-#define CFGCHIP2_FORCE_DEVICE (2 << 13)
-#define CFGCHIP2_FORCE_HOST_VBUS_LOW (3 << 13)
-#define CFGCHIP2_USB1PHYCLKMUX (1 << 12)
-#define CFGCHIP2_USB2PHYCLKMUX (1 << 11)
-#define CFGCHIP2_PHYPWRDN (1 << 10)
-#define CFGCHIP2_OTGPWRDN (1 << 9)
-#define CFGCHIP2_DATPOL (1 << 8)
-#define CFGCHIP2_USB1SUSPENDM (1 << 7)
-#define CFGCHIP2_PHY_PLLON (1 << 6) /* override PLL suspend */
-#define CFGCHIP2_SESENDEN (1 << 5) /* Vsess_end comparator */
-#define CFGCHIP2_VBDTCTEN (1 << 4) /* Vbus comparator */
-#define CFGCHIP2_REFFREQ (0xf << 0)
-#define CFGCHIP2_REFFREQ_12MHZ (1 << 0)
-#define CFGCHIP2_REFFREQ_24MHZ (2 << 0)
-#define CFGCHIP2_REFFREQ_48MHZ (3 << 0)
-
-#define DA8XX_USB_VBUS_GPIO (1 << 15)
-
-int usb_phy_on(void);
-void usb_phy_off(void);
-
-#endif /* __DA8XX_MUSB_H__ */
+++ /dev/null
-/*
- * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __MISC_H
-#define __MISC_H
-
-/* pin muxer definitions */
-#define PIN_MUX_NUM_FIELDS 8 /* Per register */
-#define PIN_MUX_FIELD_SIZE 4 /* n in bits */
-#define PIN_MUX_FIELD_MASK ((1 << PIN_MUX_FIELD_SIZE) - 1)
-
-/* pin definition */
-struct pinmux_config {
- dv_reg *mux; /* Address of mux register */
- unsigned char value; /* Value to set in field */
- unsigned char field; /* field number */
-};
-
-/* pin table definition */
-struct pinmux_resource {
- const struct pinmux_config *pins;
- const int n_pins;
-};
-
-#define PINMUX_ITEM(item) { \
- .pins = item, \
- .n_pins = ARRAY_SIZE(item) \
- }
-
-struct lpsc_resource {
- const int lpsc_no;
-};
-
-int dvevm_read_mac_address(uint8_t *buf);
-void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr);
-int davinci_configure_pin_mux(const struct pinmux_config *pins, int n_pins);
-int davinci_configure_pin_mux_items(const struct pinmux_resource *item,
- int n_items);
-#if defined(CONFIG_DRIVER_TI_EMAC) && defined(CONFIG_SOC_DA8XX)
-void davinci_emac_mii_mode_sel(int mode_sel);
-#endif
-#if defined(CONFIG_SOC_DA8XX)
-void irq_init(void);
-int da8xx_configure_lpsc_items(const struct lpsc_resource *item,
- const int n_items);
-#endif
-
-#endif /* __MISC_H */
+++ /dev/null
-/*
- * Copyright (C) 2011
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef _DV_DDR2_DEFS_H_
-#define _DV_DDR2_DEFS_H_
-
-/*
- * DDR2 Memory Ctrl Register structure
- * See sprueh7d.pdf for more details.
- */
-struct dv_ddr2_regs_ctrl {
- unsigned char rsvd0[4]; /* 0x00 */
- unsigned int sdrstat; /* 0x04 */
- unsigned int sdbcr; /* 0x08 */
- unsigned int sdrcr; /* 0x0C */
- unsigned int sdtimr; /* 0x10 */
- unsigned int sdtimr2; /* 0x14 */
- unsigned char rsvd1[4]; /* 0x18 */
- unsigned int sdbcr2; /* 0x1C */
- unsigned int pbbpr; /* 0x20 */
- unsigned char rsvd2[156]; /* 0x24 */
- unsigned int irr; /* 0xC0 */
- unsigned int imr; /* 0xC4 */
- unsigned int imsr; /* 0xC8 */
- unsigned int imcr; /* 0xCC */
- unsigned char rsvd3[20]; /* 0xD0 */
- unsigned int ddrphycr; /* 0xE4 */
- unsigned int ddrphycr2; /* 0xE8 */
- unsigned char rsvd4[4]; /* 0xEC */
-};
-
-#define DV_DDR_PHY_PWRDNEN 0x40
-#define DV_DDR_PHY_EXT_STRBEN 0x80
-#define DV_DDR_PHY_RD_LATENCY_SHIFT 0
-
-#define DV_DDR_SDTMR1_RFC_SHIFT 25
-#define DV_DDR_SDTMR1_RP_SHIFT 22
-#define DV_DDR_SDTMR1_RCD_SHIFT 19
-#define DV_DDR_SDTMR1_WR_SHIFT 16
-#define DV_DDR_SDTMR1_RAS_SHIFT 11
-#define DV_DDR_SDTMR1_RC_SHIFT 6
-#define DV_DDR_SDTMR1_RRD_SHIFT 3
-#define DV_DDR_SDTMR1_WTR_SHIFT 0
-
-#define DV_DDR_SDTMR2_RASMAX_SHIFT 27
-#define DV_DDR_SDTMR2_XP_SHIFT 25
-#define DV_DDR_SDTMR2_ODT_SHIFT 23
-#define DV_DDR_SDTMR2_XSNR_SHIFT 16
-#define DV_DDR_SDTMR2_XSRD_SHIFT 8
-#define DV_DDR_SDTMR2_RTP_SHIFT 5
-#define DV_DDR_SDTMR2_CKE_SHIFT 0
-
-#define DV_DDR_SDCR_DDR2TERM1_SHIFT 27
-#define DV_DDR_SDCR_IBANK_POS_SHIFT 26
-#define DV_DDR_SDCR_MSDRAMEN_SHIFT 25
-#define DV_DDR_SDCR_DDRDRIVE1_SHIFT 24
-#define DV_DDR_SDCR_BOOTUNLOCK_SHIFT 23
-#define DV_DDR_SDCR_DDR_DDQS_SHIFT 22
-#define DV_DDR_SDCR_DDR2EN_SHIFT 20
-#define DV_DDR_SDCR_DDRDRIVE0_SHIFT 18
-#define DV_DDR_SDCR_DDREN_SHIFT 17
-#define DV_DDR_SDCR_SDRAMEN_SHIFT 16
-#define DV_DDR_SDCR_TIMUNLOCK_SHIFT 15
-#define DV_DDR_SDCR_BUS_WIDTH_SHIFT 14
-#define DV_DDR_SDCR_CL_SHIFT 9
-#define DV_DDR_SDCR_IBANK_SHIFT 4
-#define DV_DDR_SDCR_PAGESIZE_SHIFT 0
-
-#define DV_DDR_SDRCR_LPMODEN (1 << 31)
-#define DV_DDR_SDRCR_MCLKSTOPEN (1 << 30)
-
-#define DV_DDR_SRCR_LPMODEN_SHIFT 31
-#define DV_DDR_SRCR_MCLKSTOPEN_SHIFT 30
-
-#define DV_DDR_BOOTUNLOCK (1 << DV_DDR_SDCR_BOOTUNLOCK_SHIFT)
-#define DV_DDR_TIMUNLOCK (1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT)
-
-#define dv_ddr2_regs_ctrl \
- ((struct dv_ddr2_regs_ctrl *)DAVINCI_DDR_EMIF_CTRL_BASE)
-
-#endif /* _DV_DDR2_DEFS_H_ */
+++ /dev/null
-/*
- * SoC-specific lowlevel code for tms320dm365 and similar chips
- *
- * Copyright (C) 2011
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef __DM365_LOWLEVEL_H
-#define __DM365_LOWLEVEL_H
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-
-void dm365_waitloop(unsigned long loopcnt);
-int dm365_pll1_init(unsigned long pllmult, unsigned long prediv);
-int dm365_pll2_init(unsigned long pllm, unsigned long prediv);
-int dm365_ddr_setup(void);
-void dm365_psc_init(void);
-void dm365_pinmux_ctl(unsigned long offset, unsigned long mask,
- unsigned long value);
-void dm36x_lowlevel_init(ulong bootflag);
-
-#endif /* #ifndef __DM365_LOWLEVEL_H */
+++ /dev/null
-/*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Based on:
- *
- * ----------------------------------------------------------------------------
- *
- * dm644x_emac.h
- *
- * TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM
- *
- * Copyright (C) 2005 Texas Instruments.
- *
- * ----------------------------------------------------------------------------
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * Modifications:
- * ver. 1.0: Sep 2005, TI PSP Team - Created EMAC version for uBoot.
- */
-
-#ifndef _DM644X_EMAC_H_
-#define _DM644X_EMAC_H_
-
-#include <asm/arch/hardware.h>
-
-#ifdef CONFIG_SOC_DM365
-#define EMAC_BASE_ADDR (0x01d07000)
-#define EMAC_WRAPPER_BASE_ADDR (0x01d0a000)
-#define EMAC_WRAPPER_RAM_ADDR (0x01d08000)
-#define EMAC_MDIO_BASE_ADDR (0x01d0b000)
-#define DAVINCI_EMAC_VERSION2
-#elif defined(CONFIG_SOC_DA8XX)
-#define EMAC_BASE_ADDR DAVINCI_EMAC_CNTRL_REGS_BASE
-#define EMAC_WRAPPER_BASE_ADDR DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE
-#define EMAC_WRAPPER_RAM_ADDR DAVINCI_EMAC_WRAPPER_RAM_BASE
-#define EMAC_MDIO_BASE_ADDR DAVINCI_MDIO_CNTRL_REGS_BASE
-#define DAVINCI_EMAC_VERSION2
-#else
-#define EMAC_BASE_ADDR (0x01c80000)
-#define EMAC_WRAPPER_BASE_ADDR (0x01c81000)
-#define EMAC_WRAPPER_RAM_ADDR (0x01c82000)
-#define EMAC_MDIO_BASE_ADDR (0x01c84000)
-#endif
-
-#ifdef CONFIG_SOC_DM646X
-#define DAVINCI_EMAC_VERSION2
-#define DAVINCI_EMAC_GIG_ENABLE
-#endif
-
-#ifdef CONFIG_SOC_DM646X
-/* MDIO module input frequency */
-#define EMAC_MDIO_BUS_FREQ 76500000
-/* MDIO clock output frequency */
-#define EMAC_MDIO_CLOCK_FREQ 2500000 /* 2.5 MHz */
-#elif defined(CONFIG_SOC_DM365)
-/* MDIO module input frequency */
-#define EMAC_MDIO_BUS_FREQ 121500000
-/* MDIO clock output frequency */
-#define EMAC_MDIO_CLOCK_FREQ 2200000 /* 2.2 MHz */
-#elif defined(CONFIG_SOC_DA8XX)
-/* MDIO module input frequency */
-#define EMAC_MDIO_BUS_FREQ clk_get(DAVINCI_MDIO_CLKID)
-/* MDIO clock output frequency */
-#define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */
-#else
-/* MDIO module input frequency */
-#define EMAC_MDIO_BUS_FREQ 99000000 /* PLL/6 - 99 MHz */
-/* MDIO clock output frequency */
-#define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */
-#endif
-
-#define PHY_KSZ8873 (0x00221450)
-int ksz8873_is_phy_connected(int phy_addr);
-int ksz8873_get_link_speed(int phy_addr);
-int ksz8873_init_phy(int phy_addr);
-int ksz8873_auto_negotiate(int phy_addr);
-
-#define PHY_LXT972 (0x001378e2)
-int lxt972_is_phy_connected(int phy_addr);
-int lxt972_get_link_speed(int phy_addr);
-int lxt972_init_phy(int phy_addr);
-int lxt972_auto_negotiate(int phy_addr);
-
-#define PHY_DP83848 (0x20005c90)
-int dp83848_is_phy_connected(int phy_addr);
-int dp83848_get_link_speed(int phy_addr);
-int dp83848_init_phy(int phy_addr);
-int dp83848_auto_negotiate(int phy_addr);
-
-#define PHY_ET1011C (0x282f013)
-int et1011c_get_link_speed(int phy_addr);
-
-#endif /* _DM644X_EMAC_H_ */
+++ /dev/null
-/*
- * Copyright (C) 2009 Texas Instruments Incorporated
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef _GPIO_DEFS_H_
-#define _GPIO_DEFS_H_
-
-#ifndef CONFIG_SOC_DA8XX
-#define DAVINCI_GPIO_BINTEN 0x01C67008
-#define DAVINCI_GPIO_BANK01 0x01C67010
-#define DAVINCI_GPIO_BANK23 0x01C67038
-#define DAVINCI_GPIO_BANK45 0x01C67060
-#define DAVINCI_GPIO_BANK67 0x01C67088
-
-#else /* CONFIG_SOC_DA8XX */
-#define DAVINCI_GPIO_BINTEN 0x01E26008
-#define DAVINCI_GPIO_BANK01 0x01E26010
-#define DAVINCI_GPIO_BANK23 0x01E26038
-#define DAVINCI_GPIO_BANK45 0x01E26060
-#define DAVINCI_GPIO_BANK67 0x01E26088
-#define DAVINCI_GPIO_BANK8 0x01E260B0
-#endif /* CONFIG_SOC_DA8XX */
-
-struct davinci_gpio {
- unsigned int dir;
- unsigned int out_data;
- unsigned int set_data;
- unsigned int clr_data;
- unsigned int in_data;
- unsigned int set_rising;
- unsigned int clr_rising;
- unsigned int set_falling;
- unsigned int clr_falling;
- unsigned int intstat;
-};
-
-struct davinci_gpio_bank {
- int num_gpio;
- unsigned int irq_num;
- unsigned int irq_mask;
- unsigned long *in_use;
- unsigned long base;
-};
-
-#define davinci_gpio_bank01 ((struct davinci_gpio *)DAVINCI_GPIO_BANK01)
-#define davinci_gpio_bank23 ((struct davinci_gpio *)DAVINCI_GPIO_BANK23)
-#define davinci_gpio_bank45 ((struct davinci_gpio *)DAVINCI_GPIO_BANK45)
-#define davinci_gpio_bank67 ((struct davinci_gpio *)DAVINCI_GPIO_BANK67)
-#define davinci_gpio_bank8 ((struct davinci_gpio *)DAVINCI_GPIO_BANK8)
-
-#define gpio_status() gpio_info()
-#define GPIO_NAME_SIZE 20
-#if defined(CONFIG_SOC_DM644X)
-/* GPIO0 to GPIO53, omit the V3.3 volts one */
-#define MAX_NUM_GPIOS 70
-#elif defined(CONFIG_SOC_DA8XX) && !defined(CONFIG_SOC_DA850)
-#define MAX_NUM_GPIOS 128
-#else
-#define MAX_NUM_GPIOS 144
-#endif
-#define GPIO_BANK(gp) (davinci_gpio_bank01 + ((gp) >> 5))
-#define GPIO_BIT(gp) ((gp) & 0x1F)
-
-void gpio_info(void);
-
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * Based on:
- *
- * -------------------------------------------------------------------------
- *
- * linux/include/asm-arm/arch-davinci/hardware.h
- *
- * Copyright (C) 2006 Texas Instruments.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include <config.h>
-#include <linux/sizes.h>
-
-#define REG(addr) (*(volatile unsigned int *)(addr))
-#define REG_P(addr) ((volatile unsigned int *)(addr))
-
-typedef volatile unsigned int dv_reg;
-typedef volatile unsigned int * dv_reg_p;
-
-/*
- * Base register addresses
- *
- * NOTE: some of these DM6446-specific addresses DO NOT WORK
- * on other DaVinci chips. Double check them before you try
- * using the addresses ... or PSC module identifiers, etc.
- */
-#ifndef CONFIG_SOC_DA8XX
-
-#define DAVINCI_DMA_3PCC_BASE (0x01c00000)
-#define DAVINCI_DMA_3PTC0_BASE (0x01c10000)
-#define DAVINCI_DMA_3PTC1_BASE (0x01c10400)
-#define DAVINCI_UART0_BASE (0x01c20000)
-#define DAVINCI_UART1_BASE (0x01c20400)
-#define DAVINCI_TIMER3_BASE (0x01c20800)
-#define DAVINCI_I2C_BASE (0x01c21000)
-#define DAVINCI_TIMER0_BASE (0x01c21400)
-#define DAVINCI_TIMER1_BASE (0x01c21800)
-#define DAVINCI_WDOG_BASE (0x01c21c00)
-#define DAVINCI_PWM0_BASE (0x01c22000)
-#define DAVINCI_PWM1_BASE (0x01c22400)
-#define DAVINCI_PWM2_BASE (0x01c22800)
-#define DAVINCI_TIMER4_BASE (0x01c23800)
-#define DAVINCI_SYSTEM_MODULE_BASE (0x01c40000)
-#define DAVINCI_PLL_CNTRL0_BASE (0x01c40800)
-#define DAVINCI_PLL_CNTRL1_BASE (0x01c40c00)
-#define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01c41000)
-#define DAVINCI_ARM_INTC_BASE (0x01c48000)
-#define DAVINCI_USB_OTG_BASE (0x01c64000)
-#define DAVINCI_CFC_ATA_BASE (0x01c66000)
-#define DAVINCI_SPI_BASE (0x01c66800)
-#define DAVINCI_GPIO_BASE (0x01c67000)
-#define DAVINCI_VPSS_REGS_BASE (0x01c70000)
-#if !defined(CONFIG_SOC_DM646X)
-#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000)
-#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000)
-#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000)
-#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000)
-#endif
-#define DAVINCI_DDR_BASE (0x80000000)
-
-#ifdef CONFIG_SOC_DM644X
-#define DAVINCI_UART2_BASE 0x01c20800
-#define DAVINCI_UHPI_BASE 0x01c67800
-#define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01c80000
-#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01c81000
-#define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01c82000
-#define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01c84000
-#define DAVINCI_IMCOP_BASE 0x01cc0000
-#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01e00000
-#define DAVINCI_VLYNQ_BASE 0x01e01000
-#define DAVINCI_ASP_BASE 0x01e02000
-#define DAVINCI_MMC_SD_BASE 0x01e10000
-#define DAVINCI_MS_BASE 0x01e20000
-#define DAVINCI_VLYNQ_REMOTE_BASE 0x0c000000
-
-#elif defined(CONFIG_SOC_DM355)
-#define DAVINCI_MMC_SD1_BASE 0x01e00000
-#define DAVINCI_ASP0_BASE 0x01e02000
-#define DAVINCI_ASP1_BASE 0x01e04000
-#define DAVINCI_UART2_BASE 0x01e06000
-#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01e10000
-#define DAVINCI_MMC_SD0_BASE 0x01e11000
-
-#elif defined(CONFIG_SOC_DM365)
-#define DAVINCI_MMC_SD1_BASE 0x01d00000
-#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01d10000
-#define DAVINCI_MMC_SD0_BASE 0x01d11000
-#define DAVINCI_DDR_EMIF_CTRL_BASE 0x20000000
-#define DAVINCI_SPI0_BASE 0x01c66000
-#define DAVINCI_SPI1_BASE 0x01c66800
-
-#elif defined(CONFIG_SOC_DM646X)
-#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x20008000
-#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x42000000
-#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE 0x44000000
-#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x46000000
-#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x48000000
-
-#endif
-
-#else /* CONFIG_SOC_DA8XX */
-
-#define DAVINCI_UART0_BASE 0x01c42000
-#define DAVINCI_UART1_BASE 0x01d0c000
-#define DAVINCI_UART2_BASE 0x01d0d000
-#define DAVINCI_I2C0_BASE 0x01c22000
-#define DAVINCI_I2C1_BASE 0x01e28000
-#define DAVINCI_TIMER0_BASE 0x01c20000
-#define DAVINCI_TIMER1_BASE 0x01c21000
-#define DAVINCI_WDOG_BASE 0x01c21000
-#define DAVINCI_RTC_BASE 0x01c23000
-#define DAVINCI_PLL_CNTRL0_BASE 0x01c11000
-#define DAVINCI_PLL_CNTRL1_BASE 0x01e1a000
-#define DAVINCI_PSC0_BASE 0x01c10000
-#define DAVINCI_PSC1_BASE 0x01e27000
-#define DAVINCI_SPI0_BASE 0x01c41000
-#define DAVINCI_USB_OTG_BASE 0x01e00000
-#define DAVINCI_SPI1_BASE (cpu_is_da830() ? \
- 0x01e12000 : 0x01f0e000)
-#define DAVINCI_GPIO_BASE 0x01e26000
-#define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01e23000
-#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01e22000
-#define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01e20000
-#define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01e24000
-#define DAVINCI_SYSCFG1_BASE 0x01e2c000
-#define DAVINCI_MMC_SD0_BASE 0x01c40000
-#define DAVINCI_MMC_SD1_BASE 0x01e1b000
-#define DAVINCI_TIMER2_BASE 0x01f0c000
-#define DAVINCI_TIMER3_BASE 0x01f0d000
-#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x68000000
-#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x40000000
-#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x60000000
-#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x62000000
-#define DAVINCI_ASYNC_EMIF_DATA_CE4_BASE 0x64000000
-#define DAVINCI_ASYNC_EMIF_DATA_CE5_BASE 0x66000000
-#define DAVINCI_DDR_EMIF_CTRL_BASE 0xb0000000
-#define DAVINCI_DDR_EMIF_DATA_BASE 0xc0000000
-#define DAVINCI_INTC_BASE 0xfffee000
-#define DAVINCI_BOOTCFG_BASE 0x01c14000
-#define DAVINCI_LCD_CNTL_BASE 0x01e13000
-#define DAVINCI_L3CBARAM_BASE 0x80000000
-#define JTAG_ID_REG (DAVINCI_BOOTCFG_BASE + 0x18)
-#define CHIP_REV_ID_REG (DAVINCI_BOOTCFG_BASE + 0x24)
-#define HOST1CFG (DAVINCI_BOOTCFG_BASE + 0x44)
-#define PSC0_MDCTL (DAVINCI_PSC0_BASE + 0xa00)
-
-#define GPIO_BANK0_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x10)
-#define GPIO_BANK0_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x14)
-#define GPIO_BANK0_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x18)
-#define GPIO_BANK0_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x1c)
-#define GPIO_BANK2_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x38)
-#define GPIO_BANK2_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x3c)
-#define GPIO_BANK2_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x40)
-#define GPIO_BANK2_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x44)
-#define GPIO_BANK6_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x88)
-#define GPIO_BANK6_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x8c)
-#define GPIO_BANK6_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x90)
-#define GPIO_BANK6_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x94)
-#endif /* CONFIG_SOC_DA8XX */
-
-/* Power and Sleep Controller (PSC) Domains */
-#define DAVINCI_GPSC_ARMDOMAIN 0
-#define DAVINCI_GPSC_DSPDOMAIN 1
-
-#ifndef CONFIG_SOC_DA8XX
-
-#define DAVINCI_LPSC_VPSSMSTR 0
-#define DAVINCI_LPSC_VPSSSLV 1
-#define DAVINCI_LPSC_TPCC 2
-#define DAVINCI_LPSC_TPTC0 3
-#define DAVINCI_LPSC_TPTC1 4
-#define DAVINCI_LPSC_EMAC 5
-#define DAVINCI_LPSC_EMAC_WRAPPER 6
-#define DAVINCI_LPSC_MDIO 7
-#define DAVINCI_LPSC_IEEE1394 8
-#define DAVINCI_LPSC_USB 9
-#define DAVINCI_LPSC_ATA 10
-#define DAVINCI_LPSC_VLYNQ 11
-#define DAVINCI_LPSC_UHPI 12
-#define DAVINCI_LPSC_DDR_EMIF 13
-#define DAVINCI_LPSC_AEMIF 14
-#define DAVINCI_LPSC_MMC_SD 15
-#define DAVINCI_LPSC_MEMSTICK 16
-#define DAVINCI_LPSC_McBSP 17
-#define DAVINCI_LPSC_I2C 18
-#define DAVINCI_LPSC_UART0 19
-#define DAVINCI_LPSC_UART1 20
-#define DAVINCI_LPSC_UART2 21
-#define DAVINCI_LPSC_SPI 22
-#define DAVINCI_LPSC_PWM0 23
-#define DAVINCI_LPSC_PWM1 24
-#define DAVINCI_LPSC_PWM2 25
-#define DAVINCI_LPSC_GPIO 26
-#define DAVINCI_LPSC_TIMER0 27
-#define DAVINCI_LPSC_TIMER1 28
-#define DAVINCI_LPSC_TIMER2 29
-#define DAVINCI_LPSC_SYSTEM_SUBSYS 30
-#define DAVINCI_LPSC_ARM 31
-#define DAVINCI_LPSC_SCR2 32
-#define DAVINCI_LPSC_SCR3 33
-#define DAVINCI_LPSC_SCR4 34
-#define DAVINCI_LPSC_CROSSBAR 35
-#define DAVINCI_LPSC_CFG27 36
-#define DAVINCI_LPSC_CFG3 37
-#define DAVINCI_LPSC_CFG5 38
-#define DAVINCI_LPSC_GEM 39
-#define DAVINCI_LPSC_IMCOP 40
-#define DAVINCI_LPSC_VPSSMASTER 47
-#define DAVINCI_LPSC_MJCP 50
-#define DAVINCI_LPSC_HDVICP 51
-
-#define DAVINCI_DM646X_LPSC_EMAC 14
-#define DAVINCI_DM646X_LPSC_UART0 26
-#define DAVINCI_DM646X_LPSC_I2C 31
-#define DAVINCI_DM646X_LPSC_TIMER0 34
-
-#else /* CONFIG_SOC_DA8XX */
-
-#define DAVINCI_LPSC_TPCC 0
-#define DAVINCI_LPSC_TPTC0 1
-#define DAVINCI_LPSC_TPTC1 2
-#define DAVINCI_LPSC_AEMIF 3
-#define DAVINCI_LPSC_SPI0 4
-#define DAVINCI_LPSC_MMC_SD 5
-#define DAVINCI_LPSC_AINTC 6
-#define DAVINCI_LPSC_ARM_RAM_ROM 7
-#define DAVINCI_LPSC_SECCTL_KEYMGR 8
-#define DAVINCI_LPSC_UART0 9
-#define DAVINCI_LPSC_SCR0 10
-#define DAVINCI_LPSC_SCR1 11
-#define DAVINCI_LPSC_SCR2 12
-#define DAVINCI_LPSC_DMAX 13
-#define DAVINCI_LPSC_ARM 14
-#define DAVINCI_LPSC_GEM 15
-
-/* for LPSCs in PSC1, offset from 32 for differentiation */
-#define DAVINCI_LPSC_PSC1_BASE 32
-#define DAVINCI_LPSC_USB20 (DAVINCI_LPSC_PSC1_BASE + 1)
-#define DAVINCI_LPSC_USB11 (DAVINCI_LPSC_PSC1_BASE + 2)
-#define DAVINCI_LPSC_GPIO (DAVINCI_LPSC_PSC1_BASE + 3)
-#define DAVINCI_LPSC_UHPI (DAVINCI_LPSC_PSC1_BASE + 4)
-#define DAVINCI_LPSC_EMAC (DAVINCI_LPSC_PSC1_BASE + 5)
-#define DAVINCI_LPSC_DDR_EMIF (DAVINCI_LPSC_PSC1_BASE + 6)
-#define DAVINCI_LPSC_McASP0 (DAVINCI_LPSC_PSC1_BASE + 7)
-#define DAVINCI_LPSC_SPI1 (DAVINCI_LPSC_PSC1_BASE + 10)
-#define DAVINCI_LPSC_I2C1 (DAVINCI_LPSC_PSC1_BASE + 11)
-#define DAVINCI_LPSC_UART1 (DAVINCI_LPSC_PSC1_BASE + 12)
-#define DAVINCI_LPSC_UART2 (DAVINCI_LPSC_PSC1_BASE + 13)
-#define DAVINCI_LPSC_LCDC (DAVINCI_LPSC_PSC1_BASE + 16)
-#define DAVINCI_LPSC_ePWM (DAVINCI_LPSC_PSC1_BASE + 17)
-#define DAVINCI_LPSC_MMCSD1 (DAVINCI_LPSC_PSC1_BASE + 18)
-#define DAVINCI_LPSC_eCAP (DAVINCI_LPSC_PSC1_BASE + 20)
-#define DAVINCI_LPSC_L3_CBA_RAM (DAVINCI_LPSC_PSC1_BASE + 31)
-
-/* DA830-specific peripherals */
-#define DAVINCI_LPSC_McASP1 (DAVINCI_LPSC_PSC1_BASE + 8)
-#define DAVINCI_LPSC_McASP2 (DAVINCI_LPSC_PSC1_BASE + 9)
-#define DAVINCI_LPSC_eQEP (DAVINCI_LPSC_PSC1_BASE + 21)
-#define DAVINCI_LPSC_SCR8 (DAVINCI_LPSC_PSC1_BASE + 24)
-#define DAVINCI_LPSC_SCR7 (DAVINCI_LPSC_PSC1_BASE + 25)
-#define DAVINCI_LPSC_SCR12 (DAVINCI_LPSC_PSC1_BASE + 26)
-
-/* DA850-specific peripherals */
-#define DAVINCI_LPSC_TPCC1 (DAVINCI_LPSC_PSC1_BASE + 0)
-#define DAVINCI_LPSC_SATA (DAVINCI_LPSC_PSC1_BASE + 8)
-#define DAVINCI_LPSC_VPIF (DAVINCI_LPSC_PSC1_BASE + 9)
-#define DAVINCI_LPSC_McBSP0 (DAVINCI_LPSC_PSC1_BASE + 14)
-#define DAVINCI_LPSC_McBSP1 (DAVINCI_LPSC_PSC1_BASE + 15)
-#define DAVINCI_LPSC_MMC_SD1 (DAVINCI_LPSC_PSC1_BASE + 18)
-#define DAVINCI_LPSC_uPP (DAVINCI_LPSC_PSC1_BASE + 19)
-#define DAVINCI_LPSC_TPTC2 (DAVINCI_LPSC_PSC1_BASE + 21)
-#define DAVINCI_LPSC_SCR_F0 (DAVINCI_LPSC_PSC1_BASE + 24)
-#define DAVINCI_LPSC_SCR_F1 (DAVINCI_LPSC_PSC1_BASE + 25)
-#define DAVINCI_LPSC_SCR_F2 (DAVINCI_LPSC_PSC1_BASE + 26)
-#define DAVINCI_LPSC_SCR_F6 (DAVINCI_LPSC_PSC1_BASE + 27)
-#define DAVINCI_LPSC_SCR_F7 (DAVINCI_LPSC_PSC1_BASE + 28)
-#define DAVINCI_LPSC_SCR_F8 (DAVINCI_LPSC_PSC1_BASE + 29)
-#define DAVINCI_LPSC_BR_F7 (DAVINCI_LPSC_PSC1_BASE + 30)
-
-#endif /* CONFIG_SOC_DA8XX */
-
-void lpsc_on(unsigned int id);
-void lpsc_syncreset(unsigned int id);
-void lpsc_disable(unsigned int id);
-void dsp_on(void);
-
-void davinci_enable_uart0(void);
-void davinci_enable_emac(void);
-void davinci_enable_i2c(void);
-void davinci_errata_workarounds(void);
-
-#ifndef CONFIG_SOC_DA8XX
-
-/* Some PSC defines */
-#define PSC_CHP_SHRTSW (0x01c40038)
-#define PSC_GBLCTL (0x01c41010)
-#define PSC_EPCPR (0x01c41070)
-#define PSC_EPCCR (0x01c41078)
-#define PSC_PTCMD (0x01c41120)
-#define PSC_PTSTAT (0x01c41128)
-#define PSC_PDSTAT (0x01c41200)
-#define PSC_PDSTAT1 (0x01c41204)
-#define PSC_PDCTL (0x01c41300)
-#define PSC_PDCTL1 (0x01c41304)
-
-#define PSC_MDCTL_BASE (0x01c41a00)
-#define PSC_MDSTAT_BASE (0x01c41800)
-
-#define VDD3P3V_PWDN (0x01c40048)
-#define UART0_PWREMU_MGMT (0x01c20030)
-
-#define PSC_SILVER_BULLET (0x01c41a20)
-
-#else /* CONFIG_SOC_DA8XX */
-
-#define PSC_ENABLE 0x3
-#define PSC_DISABLE 0x2
-#define PSC_SYNCRESET 0x1
-#define PSC_SWRSTDISABLE 0x0
-
-#define PSC_PSC0_MODULE_ID_CNT 16
-#define PSC_PSC1_MODULE_ID_CNT 32
-
-#define UART0_PWREMU_MGMT (0x01c42030)
-
-struct davinci_psc_regs {
- dv_reg revid;
- dv_reg rsvd0[71];
- dv_reg ptcmd;
- dv_reg rsvd1;
- dv_reg ptstat;
- dv_reg rsvd2[437];
- union {
- struct {
- dv_reg mdstat[PSC_PSC0_MODULE_ID_CNT];
- dv_reg rsvd3[112];
- dv_reg mdctl[PSC_PSC0_MODULE_ID_CNT];
- } psc0;
- struct {
- dv_reg mdstat[PSC_PSC1_MODULE_ID_CNT];
- dv_reg rsvd3[96];
- dv_reg mdctl[PSC_PSC1_MODULE_ID_CNT];
- } psc1;
- };
-};
-
-#define davinci_psc0_regs ((struct davinci_psc_regs *)DAVINCI_PSC0_BASE)
-#define davinci_psc1_regs ((struct davinci_psc_regs *)DAVINCI_PSC1_BASE)
-
-#endif /* CONFIG_SOC_DA8XX */
-
-#define PSC_MDSTAT_STATE 0x3f
-#define PSC_MDCTL_NEXT 0x07
-
-#ifndef CONFIG_SOC_DA8XX
-
-/* Miscellania... */
-#define VBPR (0x20000020)
-
-/* NOTE: system control modules are *highly* chip-specific, both
- * as to register content (e.g. for muxing) and which registers exist.
- */
-#define PINMUX0 0x01c40000
-#define PINMUX1 0x01c40004
-#define PINMUX2 0x01c40008
-#define PINMUX3 0x01c4000c
-#define PINMUX4 0x01c40010
-
-struct davinci_uart_ctrl_regs {
- dv_reg revid1;
- dv_reg res;
- dv_reg pwremu_mgmt;
- dv_reg mdr;
-};
-
-#define DAVINCI_UART_CTRL_BASE 0x28
-
-/* UART PWREMU_MGMT definitions */
-#define DAVINCI_UART_PWREMU_MGMT_FREE (1 << 0)
-#define DAVINCI_UART_PWREMU_MGMT_URRST (1 << 13)
-#define DAVINCI_UART_PWREMU_MGMT_UTRST (1 << 14)
-
-#else /* CONFIG_SOC_DA8XX */
-
-struct davinci_pllc_regs {
- dv_reg revid;
- dv_reg rsvd1[56];
- dv_reg rstype;
- dv_reg rsvd2[6];
- dv_reg pllctl;
- dv_reg ocsel;
- dv_reg rsvd3[2];
- dv_reg pllm;
- dv_reg prediv;
- dv_reg plldiv1;
- dv_reg plldiv2;
- dv_reg plldiv3;
- dv_reg oscdiv;
- dv_reg postdiv;
- dv_reg rsvd4[3];
- dv_reg pllcmd;
- dv_reg pllstat;
- dv_reg alnctl;
- dv_reg dchange;
- dv_reg cken;
- dv_reg ckstat;
- dv_reg systat;
- dv_reg rsvd5[3];
- dv_reg plldiv4;
- dv_reg plldiv5;
- dv_reg plldiv6;
- dv_reg plldiv7;
- dv_reg rsvd6[32];
- dv_reg emucnt0;
- dv_reg emucnt1;
-};
-
-#define davinci_pllc0_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE)
-#define davinci_pllc1_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL1_BASE)
-#define DAVINCI_PLLC_DIV_MASK 0x1f
-
-/*
- * A clock ID is a 32-bit number where bit 16 represents the PLL controller
- * (clear is PLLC0, set is PLLC1) and the low 16 bits represent the divisor,
- * counting from 1. Clock IDs may be passed to clk_get().
- */
-
-/* flags to select PLL controller */
-#define DAVINCI_PLLC0_FLAG (0)
-#define DAVINCI_PLLC1_FLAG (1 << 16)
-
-enum davinci_clk_ids {
- /*
- * Clock IDs for PLL outputs. Each may be switched on/off
- * independently, and each may map to one or more peripherals.
- */
- DAVINCI_PLL0_SYSCLK2 = DAVINCI_PLLC0_FLAG | 2,
- DAVINCI_PLL0_SYSCLK4 = DAVINCI_PLLC0_FLAG | 4,
- DAVINCI_PLL0_SYSCLK6 = DAVINCI_PLLC0_FLAG | 6,
- DAVINCI_PLL1_SYSCLK1 = DAVINCI_PLLC1_FLAG | 1,
- DAVINCI_PLL1_SYSCLK2 = DAVINCI_PLLC1_FLAG | 2,
-
- /* map peripherals to clock IDs */
- DAVINCI_ARM_CLKID = DAVINCI_PLL0_SYSCLK6,
- DAVINCI_DDR_CLKID = DAVINCI_PLL1_SYSCLK1,
- DAVINCI_MDIO_CLKID = DAVINCI_PLL0_SYSCLK4,
- DAVINCI_MMC_CLKID = DAVINCI_PLL0_SYSCLK2,
- DAVINCI_SPI0_CLKID = DAVINCI_PLL0_SYSCLK2,
- DAVINCI_MMCSD_CLKID = DAVINCI_PLL0_SYSCLK2,
-
- /* special clock ID - output of PLL multiplier */
- DAVINCI_PLLM_CLKID = 0x0FF,
-
- /* special clock ID - output of PLL post divisor */
- DAVINCI_PLLC_CLKID = 0x100,
-
- /* special clock ID - PLL bypass */
- DAVINCI_AUXCLK_CLKID = 0x101,
-};
-
-#define DAVINCI_UART2_CLKID (cpu_is_da830() ? DAVINCI_PLL0_SYSCLK2 \
- : get_async3_src())
-
-#define DAVINCI_SPI1_CLKID (cpu_is_da830() ? DAVINCI_PLL0_SYSCLK2 \
- : get_async3_src())
-
-int clk_get(enum davinci_clk_ids id);
-
-/* Boot config */
-struct davinci_syscfg_regs {
- dv_reg revid;
- dv_reg rsvd[13];
- dv_reg kick0;
- dv_reg kick1;
- dv_reg rsvd1[52];
- dv_reg mstpri[3];
- dv_reg rsvd2;
- dv_reg pinmux[20];
- dv_reg suspsrc;
- dv_reg chipsig;
- dv_reg chipsig_clr;
- dv_reg cfgchip0;
- dv_reg cfgchip1;
- dv_reg cfgchip2;
- dv_reg cfgchip3;
- dv_reg cfgchip4;
-};
-
-#define davinci_syscfg_regs \
- ((struct davinci_syscfg_regs *)DAVINCI_BOOTCFG_BASE)
-
-#define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
-
-/* Emulation suspend bits */
-#define DAVINCI_SYSCFG_SUSPSRC_EMAC (1 << 5)
-#define DAVINCI_SYSCFG_SUSPSRC_I2C (1 << 16)
-#define DAVINCI_SYSCFG_SUSPSRC_SPI0 (1 << 21)
-#define DAVINCI_SYSCFG_SUSPSRC_SPI1 (1 << 22)
-#define DAVINCI_SYSCFG_SUSPSRC_UART0 (1 << 18)
-#define DAVINCI_SYSCFG_SUSPSRC_UART2 (1 << 20)
-#define DAVINCI_SYSCFG_SUSPSRC_TIMER0 (1 << 27)
-
-struct davinci_syscfg1_regs {
- dv_reg vtpio_ctl;
- dv_reg ddr_slew;
- dv_reg deepsleep;
- dv_reg pupd_ena;
- dv_reg pupd_sel;
- dv_reg rxactive;
- dv_reg pwrdwn;
-};
-
-#define davinci_syscfg1_regs \
- ((struct davinci_syscfg1_regs *)DAVINCI_SYSCFG1_BASE)
-
-#define DDR_SLEW_CMOSEN_BIT 4
-#define DDR_SLEW_DDR_PDENA_BIT 5
-
-#define VTP_POWERDWN (1 << 6)
-#define VTP_LOCK (1 << 7)
-#define VTP_CLKRZ (1 << 13)
-#define VTP_READY (1 << 15)
-#define VTP_IOPWRDWN (1 << 14)
-
-#define DV_SYSCFG_KICK0_UNLOCK 0x83e70b13
-#define DV_SYSCFG_KICK1_UNLOCK 0x95a4f1e0
-
-/* Interrupt controller */
-struct davinci_aintc_regs {
- dv_reg revid;
- dv_reg cr;
- dv_reg dummy0[2];
- dv_reg ger;
- dv_reg dummy1[219];
- dv_reg ecr1;
- dv_reg ecr2;
- dv_reg ecr3;
- dv_reg dummy2[1117];
- dv_reg hier;
-};
-
-#define davinci_aintc_regs ((struct davinci_aintc_regs *)DAVINCI_INTC_BASE)
-
-struct davinci_uart_ctrl_regs {
- dv_reg revid1;
- dv_reg revid2;
- dv_reg pwremu_mgmt;
- dv_reg mdr;
-};
-
-#define DAVINCI_UART_CTRL_BASE 0x28
-#define DAVINCI_UART0_CTRL_ADDR (DAVINCI_UART0_BASE + DAVINCI_UART_CTRL_BASE)
-#define DAVINCI_UART1_CTRL_ADDR (DAVINCI_UART1_BASE + DAVINCI_UART_CTRL_BASE)
-#define DAVINCI_UART2_CTRL_ADDR (DAVINCI_UART2_BASE + DAVINCI_UART_CTRL_BASE)
-
-#define davinci_uart0_ctrl_regs \
- ((struct davinci_uart_ctrl_regs *)DAVINCI_UART0_CTRL_ADDR)
-#define davinci_uart1_ctrl_regs \
- ((struct davinci_uart_ctrl_regs *)DAVINCI_UART1_CTRL_ADDR)
-#define davinci_uart2_ctrl_regs \
- ((struct davinci_uart_ctrl_regs *)DAVINCI_UART2_CTRL_ADDR)
-
-/* UART PWREMU_MGMT definitions */
-#define DAVINCI_UART_PWREMU_MGMT_FREE (1 << 0)
-#define DAVINCI_UART_PWREMU_MGMT_URRST (1 << 13)
-#define DAVINCI_UART_PWREMU_MGMT_UTRST (1 << 14)
-
-static inline int cpu_is_da830(void)
-{
- unsigned int jtag_id = REG(JTAG_ID_REG);
- unsigned short part_no = (jtag_id >> 12) & 0xffff;
-
- return ((part_no == 0xb7df) ? 1 : 0);
-}
-static inline int cpu_is_da850(void)
-{
- unsigned int jtag_id = REG(JTAG_ID_REG);
- unsigned short part_no = (jtag_id >> 12) & 0xffff;
-
- return ((part_no == 0xb7d1) ? 1 : 0);
-}
-
-static inline enum davinci_clk_ids get_async3_src(void)
-{
- return (REG(&davinci_syscfg_regs->cfgchip3) & 0x10) ?
- DAVINCI_PLL1_SYSCLK2 : DAVINCI_PLL0_SYSCLK2;
-}
-
-#endif /* CONFIG_SOC_DA8XX */
-
-#if defined(CONFIG_SOC_DM365)
-#include <asm/arch/aintc_defs.h>
-#include <asm/arch/ddr2_defs.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/pll_defs.h>
-#include <asm/arch/psc_defs.h>
-#include <asm/arch/syscfg_defs.h>
-#include <asm/arch/timer_defs.h>
-
-#define TMPBUF 0x00017ff8
-#define TMPSTATUS 0x00017ff0
-#define DV_TMPBUF_VAL 0x591b3ed7
-#define FLAG_PORRST 0x00000001
-#define FLAG_WDTRST 0x00000002
-#define FLAG_FLGON 0x00000004
-#define FLAG_FLGOFF 0x00000010
-
-#endif
-
-#endif /* __ASM_ARCH_HARDWARE_H */
+++ /dev/null
-/*
- * (C) Copyright 2004-2014
- * Texas Instruments, <www.ti.com>
- *
- * Some changes copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef _I2C_DEFS_H_
-#define _I2C_DEFS_H_
-
-#ifndef CONFIG_SOC_DA8XX
-#define I2C_BASE 0x01c21000
-#else
-#define I2C_BASE 0x01c22000
-#endif
-
-#endif
+++ /dev/null
-/*
- * Pinmux configurations for the DAxxx SoCs
- *
- * Copyright (C) 2011 OMICRON electronics GmbH
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_PINMUX_DEFS_H
-#define __ASM_ARCH_PINMUX_DEFS_H
-
-#include <asm/arch/davinci_misc.h>
-#include <config.h>
-
-/* SPI0 pin muxer settings */
-extern const struct pinmux_config spi0_pins_base[3];
-extern const struct pinmux_config spi0_pins_scs0[1];
-extern const struct pinmux_config spi0_pins_ena[1];
-
-/* SPI1 pin muxer settings */
-extern const struct pinmux_config spi1_pins_base[3];
-extern const struct pinmux_config spi1_pins_scs0[1];
-
-/* UART pin muxer settings */
-extern const struct pinmux_config uart0_pins_txrx[2];
-extern const struct pinmux_config uart0_pins_rtscts[2];
-extern const struct pinmux_config uart1_pins_txrx[2];
-extern const struct pinmux_config uart2_pins_txrx[2];
-extern const struct pinmux_config uart2_pins_rtscts[2];
-
-/* EMAC pin muxer settings*/
-extern const struct pinmux_config emac_pins_rmii[8];
-extern const struct pinmux_config emac_pins_rmii_clk_source[1];
-extern const struct pinmux_config emac_pins_mii[15];
-extern const struct pinmux_config emac_pins_mdio[2];
-
-/* I2C pin muxer settings */
-extern const struct pinmux_config i2c0_pins[2];
-extern const struct pinmux_config i2c1_pins[2];
-
-/* EMIFA pin muxer settings */
-extern const struct pinmux_config emifa_pins[40];
-extern const struct pinmux_config emifa_pins_cs0[1];
-extern const struct pinmux_config emifa_pins_cs2[1];
-extern const struct pinmux_config emifa_pins_cs3[1];
-extern const struct pinmux_config emifa_pins_cs4[1];
-extern const struct pinmux_config emifa_pins_nand[12];
-extern const struct pinmux_config emifa_pins_nor[43];
-
-/* USB pin mux setting */
-extern const struct pinmux_config usb_pins[1];
-
-/* MMC pin muxer settings */
-extern const struct pinmux_config mmc0_pins_8bit[10];
-extern const struct pinmux_config mmc0_pins[6];
-
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2011
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef _DV_PLL_DEFS_H_
-#define _DV_PLL_DEFS_H_
-
-struct dv_pll_regs {
- unsigned int pid; /* 0x00 */
- unsigned char rsvd0[224]; /* 0x04 */
- unsigned int rstype; /* 0xe4 */
- unsigned char rsvd1[24]; /* 0xe8 */
- unsigned int pllctl; /* 0x100 */
- unsigned char rsvd2[4]; /* 0x104 */
- unsigned int secctl; /* 0x108 */
- unsigned int rv; /* 0x10c */
- unsigned int pllm; /* 0x110 */
- unsigned int prediv; /* 0x114 */
- unsigned int plldiv1; /* 0x118 */
- unsigned int plldiv2; /* 0x11c */
- unsigned int plldiv3; /* 0x120 */
- unsigned int oscdiv1; /* 0x124 */
- unsigned int postdiv; /* 0x128 */
- unsigned int bpdiv; /* 0x12c */
- unsigned char rsvd5[8]; /* 0x130 */
- unsigned int pllcmd; /* 0x138 */
- unsigned int pllstat; /* 0x13c */
- unsigned int alnctl; /* 0x140 */
- unsigned int dchange; /* 0x144 */
- unsigned int cken; /* 0x148 */
- unsigned int ckstat; /* 0x14c */
- unsigned int systat; /* 0x150 */
- unsigned char rsvd6[12]; /* 0x154 */
- unsigned int plldiv4; /* 0x160 */
- unsigned int plldiv5; /* 0x164 */
- unsigned int plldiv6; /* 0x168 */
- unsigned int plldiv7; /* 0x16C */
- unsigned int plldiv8; /* 0x170 */
- unsigned int plldiv9; /* 0x174 */
-};
-
-#define PLL_MASTER_LOCK (1 << 4)
-
-#define PLLCTL_CLOCK_MODE_SHIFT 8
-#define PLLCTL_PLLEN (1 << 0)
-#define PLLCTL_PLLPWRDN (1 << 1)
-#define PLLCTL_PLLRST (1 << 3)
-#define PLLCTL_PLLDIS (1 << 4)
-#define PLLCTL_PLLENSRC (1 << 5)
-#define PLLCTL_RES_9 (1 << 8)
-#define PLLCTL_EXTCLKSRC (1 << 9)
-
-#define PLL_DIVEN (1 << 15)
-#define PLL_POSTDEN PLL_DIVEN
-
-#define PLL_SCSCFG3_DIV45PENA (1 << 2)
-#define PLL_SCSCFG3_EMA_CLKSRC (1 << 1)
-
-#define PLL_RSTYPE_POR (1 << 0)
-#define PLL_RSTYPE_XWRST (1 << 1)
-
-#define PLLSECCTL_TINITZ (1 << 16)
-#define PLLSECCTL_TENABLE (1 << 17)
-#define PLLSECCTL_TENABLEDIV (1 << 18)
-#define PLLSECCTL_STOPMODE (1 << 22)
-
-#define PLLCMD_GOSET (1 << 0)
-#define PLLCMD_GOSTAT (1 << 0)
-
-#define PLL0_LOCK 0x07000000
-#define PLL1_LOCK 0x07000000
-
-#define dv_pll0_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL0_BASE)
-#define dv_pll1_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL1_BASE)
-
-#define ARM_PLLDIV (offsetof(struct dv_pll_regs, plldiv2))
-#define DDR_PLLDIV (offsetof(struct dv_pll_regs, plldiv7))
-#define SPI_PLLDIV (offsetof(struct dv_pll_regs, plldiv4))
-
-unsigned int davinci_clk_get(unsigned int div);
-#endif /* _DV_PLL_DEFS_H_ */
+++ /dev/null
-/*
- * Copyright (C) 2011
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef _DV_PSC_DEFS_H_
-#define _DV_PSC_DEFS_H_
-
-/*
- * Power/Sleep Ctrl Register structure
- * See sprufb3.pdf, Chapter 7
- */
-struct dv_psc_regs {
- unsigned int pid; /* 0x000 */
- unsigned char rsvd0[16]; /* 0x004 */
- unsigned char rsvd1[4]; /* 0x014 */
- unsigned int inteval; /* 0x018 */
- unsigned char rsvd2[36]; /* 0x01C */
- unsigned int merrpr0; /* 0x040 */
- unsigned int merrpr1; /* 0x044 */
- unsigned char rsvd3[8]; /* 0x048 */
- unsigned int merrcr0; /* 0x050 */
- unsigned int merrcr1; /* 0x054 */
- unsigned char rsvd4[8]; /* 0x058 */
- unsigned int perrpr; /* 0x060 */
- unsigned char rsvd5[4]; /* 0x064 */
- unsigned int perrcr; /* 0x068 */
- unsigned char rsvd6[4]; /* 0x06C */
- unsigned int epcpr; /* 0x070 */
- unsigned char rsvd7[4]; /* 0x074 */
- unsigned int epccr; /* 0x078 */
- unsigned char rsvd8[144]; /* 0x07C */
- unsigned char rsvd9[20]; /* 0x10C */
- unsigned int ptcmd; /* 0x120 */
- unsigned char rsvd10[4]; /* 0x124 */
- unsigned int ptstat; /* 0x128 */
- unsigned char rsvd11[212]; /* 0x12C */
- unsigned int pdstat0; /* 0x200 */
- unsigned int pdstat1; /* 0x204 */
- unsigned char rsvd12[248]; /* 0x208 */
- unsigned int pdctl0; /* 0x300 */
- unsigned int pdctl1; /* 0x304 */
- unsigned char rsvd13[536]; /* 0x308 */
- unsigned int mckout0; /* 0x520 */
- unsigned int mckout1; /* 0x524 */
- unsigned char rsvd14[728]; /* 0x528 */
- unsigned int mdstat[52]; /* 0x800 */
- unsigned char rsvd15[304]; /* 0x8D0 */
- unsigned int mdctl[52]; /* 0xA00 */
-};
-
-/* PSC constants */
-#define EMURSTIE_MASK (0x00000200)
-
-#define PD0 (0)
-
-#define PSC_ENABLE (0x3)
-#define PSC_DISABLE (0x2)
-#define PSC_SYNCRESET (0x1)
-#define PSC_SWRSTDISABLE (0x0)
-
-#define PSC_GOSTAT (1 << 0)
-#define PSC_MD_STATE_MSK (0x1f)
-
-#define PSC_CMD_GO (1 << 0)
-
-#define dv_psc_regs ((struct dv_psc_regs *)DAVINCI_PWR_SLEEP_CNTRL_BASE)
-
-#endif /* _DV_PSC_DEFS_H_ */
+++ /dev/null
-/*
- * Davinci MMC Controller Defines - Based on Linux davinci_mmc.c
- *
- * Copyright (C) 2010 Texas Instruments Incorporated
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _SDMMC_DEFS_H_
-#define _SDMMC_DEFS_H_
-
-#include <asm/arch/hardware.h>
-
-/* MMC Control Reg fields */
-#define MMCCTL_DATRST (1 << 0)
-#define MMCCTL_CMDRST (1 << 1)
-#define MMCCTL_WIDTH_4_BIT (1 << 2)
-#define MMCCTL_DATEG_DISABLED (0 << 6)
-#define MMCCTL_DATEG_RISING (1 << 6)
-#define MMCCTL_DATEG_FALLING (2 << 6)
-#define MMCCTL_DATEG_BOTH (3 << 6)
-#define MMCCTL_PERMDR_LE (0 << 9)
-#define MMCCTL_PERMDR_BE (1 << 9)
-#define MMCCTL_PERMDX_LE (0 << 10)
-#define MMCCTL_PERMDX_BE (1 << 10)
-
-/* MMC Clock Control Reg fields */
-#define MMCCLK_CLKEN (1 << 8)
-#define MMCCLK_CLKRT_MASK (0xFF << 0)
-
-/* MMC Status Reg0 fields */
-#define MMCST0_DATDNE (1 << 0)
-#define MMCST0_BSYDNE (1 << 1)
-#define MMCST0_RSPDNE (1 << 2)
-#define MMCST0_TOUTRD (1 << 3)
-#define MMCST0_TOUTRS (1 << 4)
-#define MMCST0_CRCWR (1 << 5)
-#define MMCST0_CRCRD (1 << 6)
-#define MMCST0_CRCRS (1 << 7)
-#define MMCST0_DXRDY (1 << 9)
-#define MMCST0_DRRDY (1 << 10)
-#define MMCST0_DATED (1 << 11)
-#define MMCST0_TRNDNE (1 << 12)
-
-#define MMCST0_ERR_MASK (0x00F8)
-
-/* MMC Status Reg1 fields */
-#define MMCST1_BUSY (1 << 0)
-#define MMCST1_CLKSTP (1 << 1)
-#define MMCST1_DXEMP (1 << 2)
-#define MMCST1_DRFUL (1 << 3)
-#define MMCST1_DAT3ST (1 << 4)
-#define MMCST1_FIFOEMP (1 << 5)
-#define MMCST1_FIFOFUL (1 << 6)
-
-/* MMC INT Mask Reg fields */
-#define MMCIM_EDATDNE (1 << 0)
-#define MMCIM_EBSYDNE (1 << 1)
-#define MMCIM_ERSPDNE (1 << 2)
-#define MMCIM_ETOUTRD (1 << 3)
-#define MMCIM_ETOUTRS (1 << 4)
-#define MMCIM_ECRCWR (1 << 5)
-#define MMCIM_ECRCRD (1 << 6)
-#define MMCIM_ECRCRS (1 << 7)
-#define MMCIM_EDXRDY (1 << 9)
-#define MMCIM_EDRRDY (1 << 10)
-#define MMCIM_EDATED (1 << 11)
-#define MMCIM_ETRNDNE (1 << 12)
-
-#define MMCIM_MASKALL (0xFFFFFFFF)
-
-/* MMC Resp Tout Reg fields */
-#define MMCTOR_TOR_MASK (0xFF) /* dont write to reg, | it */
-#define MMCTOR_TOD_20_16_SHIFT (8)
-
-/* MMC Data Read Tout Reg fields */
-#define MMCTOD_TOD_0_15_MASK (0xFFFF)
-
-/* MMC Block len Reg fields */
-#define MMCBLEN_BLEN_MASK (0xFFF)
-
-/* MMC Num Blocks Reg fields */
-#define MMCNBLK_NBLK_MASK (0xFFFF)
-#define MMCNBLK_NBLK_MAX (0xFFFF)
-
-/* MMC Num Blocks Counter Reg fields */
-#define MMCNBLC_NBLC_MASK (0xFFFF)
-
-/* MMC Cmd Reg fields */
-#define MMCCMD_CMD_MASK (0x3F)
-#define MMCCMD_PPLEN (1 << 7)
-#define MMCCMD_BSYEXP (1 << 8)
-#define MMCCMD_RSPFMT_NONE (0 << 9)
-#define MMCCMD_RSPFMT_R1567 (1 << 9)
-#define MMCCMD_RSPFMT_R2 (2 << 9)
-#define MMCCMD_RSPFMT_R3 (3 << 9)
-#define MMCCMD_DTRW (1 << 11)
-#define MMCCMD_STRMTP (1 << 12)
-#define MMCCMD_WDATX (1 << 13)
-#define MMCCMD_INITCK (1 << 14)
-#define MMCCMD_DCLR (1 << 15)
-#define MMCCMD_DMATRIG (1 << 16)
-
-/* FIFO control Reg fields */
-#define MMCFIFOCTL_FIFORST (1 << 0)
-#define MMCFIFOCTL_FIFODIR (1 << 1)
-#define MMCFIFOCTL_FIFOLEV (1 << 2)
-#define MMCFIFOCTL_ACCWD_4 (0 << 3) /* access width of 4 bytes */
-#define MMCFIFOCTL_ACCWD_3 (1 << 3) /* access width of 3 bytes */
-#define MMCFIFOCTL_ACCWD_2 (2 << 3) /* access width of 2 bytes */
-#define MMCFIFOCTL_ACCWD_1 (3 << 3) /* access width of 1 byte */
-
-/* Davinci MMC Register definitions */
-struct davinci_mmc_regs {
- dv_reg mmcctl;
- dv_reg mmcclk;
- dv_reg mmcst0;
- dv_reg mmcst1;
- dv_reg mmcim;
- dv_reg mmctor;
- dv_reg mmctod;
- dv_reg mmcblen;
- dv_reg mmcnblk;
- dv_reg mmcnblc;
- dv_reg mmcdrr;
- dv_reg mmcdxr;
- dv_reg mmccmd;
- dv_reg mmcarghl;
- dv_reg mmcrsp01;
- dv_reg mmcrsp23;
- dv_reg mmcrsp45;
- dv_reg mmcrsp67;
- dv_reg mmcdrsp;
- dv_reg mmcetok;
- dv_reg mmccidx;
- dv_reg mmcckc;
- dv_reg mmctorc;
- dv_reg mmctodc;
- dv_reg mmcblnc;
- dv_reg sdioctl;
- dv_reg sdiost0;
- dv_reg sdioien;
- dv_reg sdioist;
- dv_reg mmcfifoctl;
-};
-
-/* Davinci MMC board definitions */
-struct davinci_mmc {
- struct davinci_mmc_regs *reg_base; /* Register base address */
- uint input_clk; /* Input clock to MMC controller */
- uint host_caps; /* Host capabilities */
- uint voltages; /* Host supported voltages */
- uint version; /* MMC Controller version */
- struct mmc_config cfg;
-};
-
-enum {
- MMC_CTLR_VERSION_1 = 0, /* DM644x and DM355 */
- MMC_CTLR_VERSION_2, /* DA830 */
-};
-
-int davinci_mmc_init(bd_t *bis, struct davinci_mmc *host);
-
-#endif /* _SDMMC_DEFS_H */
+++ /dev/null
-/*
- * Copyright (C) 2011
- * Heiko Schocher, DENX Software Engineering, hs@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef _DV_SYSCFG_DEFS_H_
-#define _DV_SYSCFG_DEFS_H_
-
-#ifndef CONFIG_SOC_DA8XX
-/* System Control Module register structure for DM365 */
-struct dv_sys_module_regs {
- unsigned int pinmux[5]; /* 0x00 */
- unsigned int bootcfg; /* 0x14 */
- unsigned int arm_intmux; /* 0x18 */
- unsigned int edma_evtmux; /* 0x1C */
- unsigned int ddr_slew; /* 0x20 */
- unsigned int clkout; /* 0x24 */
- unsigned int device_id; /* 0x28 */
- unsigned int vdac_config; /* 0x2C */
- unsigned int timer64_ctl; /* 0x30 */
- unsigned int usbbphy_ctl; /* 0x34 */
- unsigned int misc; /* 0x38 */
- unsigned int mstpri[2]; /* 0x3C */
- unsigned int vpss_clkctl; /* 0x44 */
- unsigned int peri_clkctl; /* 0x48 */
- unsigned int deepsleep; /* 0x4C */
- unsigned int dft_enable; /* 0x50 */
- unsigned int debounce[8]; /* 0x54 */
- unsigned int vtpiocr; /* 0x74 */
- unsigned int pupdctl0; /* 0x78 */
- unsigned int pupdctl1; /* 0x7C */
- unsigned int hdimcopbt; /* 0x80 */
- unsigned int pll0_config; /* 0x84 */
- unsigned int pll1_config; /* 0x88 */
-};
-
-#define VPTIO_RDY (1 << 15)
-#define VPTIO_IOPWRDN (1 << 14)
-#define VPTIO_CLRZ (1 << 13)
-#define VPTIO_LOCK (1 << 7)
-#define VPTIO_PWRDN (1 << 6)
-
-#define VPSS_CLK_CTL_VPSS_CLKMD (1 << 7)
-
-#define dv_sys_module_regs \
- ((struct dv_sys_module_regs *)DAVINCI_SYSTEM_MODULE_BASE)
-
-#endif /* !CONFIG_SOC_DA8XX */
-#endif /* _DV_SYSCFG_DEFS_H_ */
+++ /dev/null
-/*
- * Copyright (C) 2011 DENX Software Engineering GmbH
- * Heiko Schocher <hs@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef _TIMER_DEFS_H_
-#define _TIMER_DEFS_H_
-
-struct davinci_timer {
- u_int32_t pid12;
- u_int32_t emumgt;
- u_int32_t na1;
- u_int32_t na2;
- u_int32_t tim12;
- u_int32_t tim34;
- u_int32_t prd12;
- u_int32_t prd34;
- u_int32_t tcr;
- u_int32_t tgcr;
- u_int32_t wdtcr;
-};
-
-#define DV_TIMER_TCR_ENAMODE_MASK 3
-
-#define DV_TIMER_TCR_ENAMODE12_SHIFT 6
-#define DV_TIMER_TCR_CLKSRC12_SHIFT 8
-#define DV_TIMER_TCR_READRSTMODE12_SHIFT 10
-#define DV_TIMER_TCR_CAPMODE12_SHIFT 11
-#define DV_TIMER_TCR_CAPVTMODE12_SHIFT 12
-#define DV_TIMER_TCR_ENAMODE34_SHIFT 22
-#define DV_TIMER_TCR_CLKSRC34_SHIFT 24
-#define DV_TIMER_TCR_READRSTMODE34_SHIFT 26
-#define DV_TIMER_TCR_CAPMODE34_SHIFT 27
-#define DV_TIMER_TCR_CAPEVTMODE12_SHIFT 28
-
-#define DV_WDT_ENABLE_SYS_RESET 0x00020000
-#define DV_WDT_TRIGGER_SYS_RESET 0x00020002
-
-#ifdef CONFIG_HW_WATCHDOG
-void davinci_hw_watchdog_enable(void);
-void davinci_hw_watchdog_reset(void);
-#endif
-#endif /* _TIMER_DEFS_H_ */
--- /dev/null
+/*
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _DV_AINTC_DEFS_H_
+#define _DV_AINTC_DEFS_H_
+
+struct dv_aintc_regs {
+ unsigned int fiq0; /* 0x00 */
+ unsigned int fiq1; /* 0x04 */
+ unsigned int irq0; /* 0x08 */
+ unsigned int irq1; /* 0x0c */
+ unsigned int fiqentry; /* 0x10 */
+ unsigned int irqentry; /* 0x14 */
+ unsigned int eint0; /* 0x18 */
+ unsigned int eint1; /* 0x1c */
+ unsigned int intctl; /* 0x20 */
+ unsigned int eabase; /* 0x24 */
+ unsigned char rsvd0[8]; /* 0x28 */
+ unsigned int intpri0; /* 0x30 */
+ unsigned int intpri1; /* 0x34 */
+ unsigned int intpri2; /* 0x38 */
+ unsigned int intpri3; /* 0x3c */
+ unsigned int intpri4; /* 0x40 */
+ unsigned int intpri5; /* 0x44 */
+ unsigned int intpri6; /* 0x48 */
+ unsigned int intpri7; /* 0x4c */
+};
+
+#define dv_aintc_regs ((struct dv_aintc_regs *)DAVINCI_ARM_INTC_BASE)
+
+#define DV_AINTC_INTCTL_IDMODE (1 << 2)
+
+#endif /* _DV_AINTC_DEFS_H_ */
--- /dev/null
+/*
+ * SoC-specific lowlevel code for DA850
+ *
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __DA850_LOWLEVEL_H
+#define __DA850_LOWLEVEL_H
+
+#include <asm/arch/pinmux_defs.h>
+
+/* pinmux_resource[] vector is defined in the board specific file */
+extern const struct pinmux_resource pinmuxes[];
+extern const int pinmuxes_size;
+
+extern const struct lpsc_resource lpsc[];
+extern const int lpsc_size;
+
+/* NOR Boot Configuration Word Field Descriptions */
+#define DA850_NORBOOT_COPY_XK(X) ((X - 1) << 8)
+#define DA850_NORBOOT_METHOD_DIRECT (1 << 4)
+#define DA850_NORBOOT_16BIT (1 << 0)
+
+#define dv_maskbits(addr, val) \
+ writel((readl(addr) & val), addr)
+
+void da850_lpc_transition(unsigned char pscnum, unsigned char module,
+ unsigned char domain, unsigned char state);
+void da850_psc_init(void);
+void da850_pinmux_ctl(unsigned long offset, unsigned long mask,
+ unsigned long value);
+
+#endif /* #ifndef __DA850_LOWLEVEL_H */
--- /dev/null
+/*
+ * da8xx-usb.h -- TI's DA8xx platform specific usb wrapper definitions.
+ *
+ * Author: Ajay Kumar Gupta <ajay.gupta@ti.com>
+ *
+ * Based on drivers/usb/musb/davinci.h
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __DA8XX_MUSB_H__
+#define __DA8XX_MUSB_H__
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/gpio.h>
+
+/* Base address of da8xx usb0 wrapper */
+#define DA8XX_USB_OTG_BASE 0x01E00000
+
+/* Base address of da8xx musb core */
+#define DA8XX_USB_OTG_CORE_BASE (DA8XX_USB_OTG_BASE + 0x400)
+
+/* Timeout for DA8xx usb module */
+#define DA8XX_USB_OTG_TIMEOUT 0x3FFFFFF
+
+/*
+ * DA8xx platform USB wrapper register overlay.
+ */
+struct da8xx_usb_regs {
+ dv_reg revision;
+ dv_reg control;
+ dv_reg status;
+ dv_reg emulation;
+ dv_reg mode;
+ dv_reg autoreq;
+ dv_reg srpfixtime;
+ dv_reg teardown;
+ dv_reg intsrc;
+ dv_reg intsrc_set;
+ dv_reg intsrc_clr;
+ dv_reg intmsk;
+ dv_reg intmsk_set;
+ dv_reg intmsk_clr;
+ dv_reg intsrcmsk;
+ dv_reg eoi;
+ dv_reg intvector;
+ dv_reg grndis_size[4];
+};
+
+#define da8xx_usb_regs ((struct da8xx_usb_regs *)DA8XX_USB_OTG_BASE)
+
+/* DA8XX interrupt bits definitions */
+#define DA8XX_USB_TX_ENDPTS_MASK 0x1f /* ep0 + 4 tx */
+#define DA8XX_USB_RX_ENDPTS_MASK 0x1e /* 4 rx */
+#define DA8XX_USB_TXINT_SHIFT 0
+#define DA8XX_USB_RXINT_SHIFT 8
+
+#define DA8XX_USB_USBINT_MASK 0x01ff0000 /* 8 Mentor, DRVVBUS */
+#define DA8XX_USB_TXINT_MASK \
+ (DA8XX_USB_TX_ENDPTS_MASK << DA8XX_USB_TXINT_SHIFT)
+#define DA8XX_USB_RXINT_MASK \
+ (DA8XX_USB_RX_ENDPTS_MASK << DA8XX_USB_RXINT_SHIFT)
+
+/* DA8xx CFGCHIP2 (USB 2.0 PHY Control) register bits */
+#define CFGCHIP2_PHYCLKGD (1 << 17)
+#define CFGCHIP2_VBUSSENSE (1 << 16)
+#define CFGCHIP2_RESET (1 << 15)
+#define CFGCHIP2_OTGMODE (3 << 13)
+#define CFGCHIP2_NO_OVERRIDE (0 << 13)
+#define CFGCHIP2_FORCE_HOST (1 << 13)
+#define CFGCHIP2_FORCE_DEVICE (2 << 13)
+#define CFGCHIP2_FORCE_HOST_VBUS_LOW (3 << 13)
+#define CFGCHIP2_USB1PHYCLKMUX (1 << 12)
+#define CFGCHIP2_USB2PHYCLKMUX (1 << 11)
+#define CFGCHIP2_PHYPWRDN (1 << 10)
+#define CFGCHIP2_OTGPWRDN (1 << 9)
+#define CFGCHIP2_DATPOL (1 << 8)
+#define CFGCHIP2_USB1SUSPENDM (1 << 7)
+#define CFGCHIP2_PHY_PLLON (1 << 6) /* override PLL suspend */
+#define CFGCHIP2_SESENDEN (1 << 5) /* Vsess_end comparator */
+#define CFGCHIP2_VBDTCTEN (1 << 4) /* Vbus comparator */
+#define CFGCHIP2_REFFREQ (0xf << 0)
+#define CFGCHIP2_REFFREQ_12MHZ (1 << 0)
+#define CFGCHIP2_REFFREQ_24MHZ (2 << 0)
+#define CFGCHIP2_REFFREQ_48MHZ (3 << 0)
+
+#define DA8XX_USB_VBUS_GPIO (1 << 15)
+
+int usb_phy_on(void);
+void usb_phy_off(void);
+
+#endif /* __DA8XX_MUSB_H__ */
--- /dev/null
+/*
+ * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __MISC_H
+#define __MISC_H
+
+/* pin muxer definitions */
+#define PIN_MUX_NUM_FIELDS 8 /* Per register */
+#define PIN_MUX_FIELD_SIZE 4 /* n in bits */
+#define PIN_MUX_FIELD_MASK ((1 << PIN_MUX_FIELD_SIZE) - 1)
+
+/* pin definition */
+struct pinmux_config {
+ dv_reg *mux; /* Address of mux register */
+ unsigned char value; /* Value to set in field */
+ unsigned char field; /* field number */
+};
+
+/* pin table definition */
+struct pinmux_resource {
+ const struct pinmux_config *pins;
+ const int n_pins;
+};
+
+#define PINMUX_ITEM(item) { \
+ .pins = item, \
+ .n_pins = ARRAY_SIZE(item) \
+ }
+
+struct lpsc_resource {
+ const int lpsc_no;
+};
+
+int dvevm_read_mac_address(uint8_t *buf);
+void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr);
+int davinci_configure_pin_mux(const struct pinmux_config *pins, int n_pins);
+int davinci_configure_pin_mux_items(const struct pinmux_resource *item,
+ int n_items);
+#if defined(CONFIG_DRIVER_TI_EMAC) && defined(CONFIG_SOC_DA8XX)
+void davinci_emac_mii_mode_sel(int mode_sel);
+#endif
+#if defined(CONFIG_SOC_DA8XX)
+void irq_init(void);
+int da8xx_configure_lpsc_items(const struct lpsc_resource *item,
+ const int n_items);
+#endif
+
+#endif /* __MISC_H */
--- /dev/null
+/*
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _DV_DDR2_DEFS_H_
+#define _DV_DDR2_DEFS_H_
+
+/*
+ * DDR2 Memory Ctrl Register structure
+ * See sprueh7d.pdf for more details.
+ */
+struct dv_ddr2_regs_ctrl {
+ unsigned char rsvd0[4]; /* 0x00 */
+ unsigned int sdrstat; /* 0x04 */
+ unsigned int sdbcr; /* 0x08 */
+ unsigned int sdrcr; /* 0x0C */
+ unsigned int sdtimr; /* 0x10 */
+ unsigned int sdtimr2; /* 0x14 */
+ unsigned char rsvd1[4]; /* 0x18 */
+ unsigned int sdbcr2; /* 0x1C */
+ unsigned int pbbpr; /* 0x20 */
+ unsigned char rsvd2[156]; /* 0x24 */
+ unsigned int irr; /* 0xC0 */
+ unsigned int imr; /* 0xC4 */
+ unsigned int imsr; /* 0xC8 */
+ unsigned int imcr; /* 0xCC */
+ unsigned char rsvd3[20]; /* 0xD0 */
+ unsigned int ddrphycr; /* 0xE4 */
+ unsigned int ddrphycr2; /* 0xE8 */
+ unsigned char rsvd4[4]; /* 0xEC */
+};
+
+#define DV_DDR_PHY_PWRDNEN 0x40
+#define DV_DDR_PHY_EXT_STRBEN 0x80
+#define DV_DDR_PHY_RD_LATENCY_SHIFT 0
+
+#define DV_DDR_SDTMR1_RFC_SHIFT 25
+#define DV_DDR_SDTMR1_RP_SHIFT 22
+#define DV_DDR_SDTMR1_RCD_SHIFT 19
+#define DV_DDR_SDTMR1_WR_SHIFT 16
+#define DV_DDR_SDTMR1_RAS_SHIFT 11
+#define DV_DDR_SDTMR1_RC_SHIFT 6
+#define DV_DDR_SDTMR1_RRD_SHIFT 3
+#define DV_DDR_SDTMR1_WTR_SHIFT 0
+
+#define DV_DDR_SDTMR2_RASMAX_SHIFT 27
+#define DV_DDR_SDTMR2_XP_SHIFT 25
+#define DV_DDR_SDTMR2_ODT_SHIFT 23
+#define DV_DDR_SDTMR2_XSNR_SHIFT 16
+#define DV_DDR_SDTMR2_XSRD_SHIFT 8
+#define DV_DDR_SDTMR2_RTP_SHIFT 5
+#define DV_DDR_SDTMR2_CKE_SHIFT 0
+
+#define DV_DDR_SDCR_DDR2TERM1_SHIFT 27
+#define DV_DDR_SDCR_IBANK_POS_SHIFT 26
+#define DV_DDR_SDCR_MSDRAMEN_SHIFT 25
+#define DV_DDR_SDCR_DDRDRIVE1_SHIFT 24
+#define DV_DDR_SDCR_BOOTUNLOCK_SHIFT 23
+#define DV_DDR_SDCR_DDR_DDQS_SHIFT 22
+#define DV_DDR_SDCR_DDR2EN_SHIFT 20
+#define DV_DDR_SDCR_DDRDRIVE0_SHIFT 18
+#define DV_DDR_SDCR_DDREN_SHIFT 17
+#define DV_DDR_SDCR_SDRAMEN_SHIFT 16
+#define DV_DDR_SDCR_TIMUNLOCK_SHIFT 15
+#define DV_DDR_SDCR_BUS_WIDTH_SHIFT 14
+#define DV_DDR_SDCR_CL_SHIFT 9
+#define DV_DDR_SDCR_IBANK_SHIFT 4
+#define DV_DDR_SDCR_PAGESIZE_SHIFT 0
+
+#define DV_DDR_SDRCR_LPMODEN (1 << 31)
+#define DV_DDR_SDRCR_MCLKSTOPEN (1 << 30)
+
+#define DV_DDR_SRCR_LPMODEN_SHIFT 31
+#define DV_DDR_SRCR_MCLKSTOPEN_SHIFT 30
+
+#define DV_DDR_BOOTUNLOCK (1 << DV_DDR_SDCR_BOOTUNLOCK_SHIFT)
+#define DV_DDR_TIMUNLOCK (1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT)
+
+#define dv_ddr2_regs_ctrl \
+ ((struct dv_ddr2_regs_ctrl *)DAVINCI_DDR_EMIF_CTRL_BASE)
+
+#endif /* _DV_DDR2_DEFS_H_ */
--- /dev/null
+/*
+ * SoC-specific lowlevel code for tms320dm365 and similar chips
+ *
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __DM365_LOWLEVEL_H
+#define __DM365_LOWLEVEL_H
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+
+void dm365_waitloop(unsigned long loopcnt);
+int dm365_pll1_init(unsigned long pllmult, unsigned long prediv);
+int dm365_pll2_init(unsigned long pllm, unsigned long prediv);
+int dm365_ddr_setup(void);
+void dm365_psc_init(void);
+void dm365_pinmux_ctl(unsigned long offset, unsigned long mask,
+ unsigned long value);
+void dm36x_lowlevel_init(ulong bootflag);
+
+#endif /* #ifndef __DM365_LOWLEVEL_H */
--- /dev/null
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Based on:
+ *
+ * ----------------------------------------------------------------------------
+ *
+ * dm644x_emac.h
+ *
+ * TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM
+ *
+ * Copyright (C) 2005 Texas Instruments.
+ *
+ * ----------------------------------------------------------------------------
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Modifications:
+ * ver. 1.0: Sep 2005, TI PSP Team - Created EMAC version for uBoot.
+ */
+
+#ifndef _DM644X_EMAC_H_
+#define _DM644X_EMAC_H_
+
+#include <asm/arch/hardware.h>
+
+#ifdef CONFIG_SOC_DM365
+#define EMAC_BASE_ADDR (0x01d07000)
+#define EMAC_WRAPPER_BASE_ADDR (0x01d0a000)
+#define EMAC_WRAPPER_RAM_ADDR (0x01d08000)
+#define EMAC_MDIO_BASE_ADDR (0x01d0b000)
+#define DAVINCI_EMAC_VERSION2
+#elif defined(CONFIG_SOC_DA8XX)
+#define EMAC_BASE_ADDR DAVINCI_EMAC_CNTRL_REGS_BASE
+#define EMAC_WRAPPER_BASE_ADDR DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE
+#define EMAC_WRAPPER_RAM_ADDR DAVINCI_EMAC_WRAPPER_RAM_BASE
+#define EMAC_MDIO_BASE_ADDR DAVINCI_MDIO_CNTRL_REGS_BASE
+#define DAVINCI_EMAC_VERSION2
+#else
+#define EMAC_BASE_ADDR (0x01c80000)
+#define EMAC_WRAPPER_BASE_ADDR (0x01c81000)
+#define EMAC_WRAPPER_RAM_ADDR (0x01c82000)
+#define EMAC_MDIO_BASE_ADDR (0x01c84000)
+#endif
+
+#ifdef CONFIG_SOC_DM646X
+#define DAVINCI_EMAC_VERSION2
+#define DAVINCI_EMAC_GIG_ENABLE
+#endif
+
+#ifdef CONFIG_SOC_DM646X
+/* MDIO module input frequency */
+#define EMAC_MDIO_BUS_FREQ 76500000
+/* MDIO clock output frequency */
+#define EMAC_MDIO_CLOCK_FREQ 2500000 /* 2.5 MHz */
+#elif defined(CONFIG_SOC_DM365)
+/* MDIO module input frequency */
+#define EMAC_MDIO_BUS_FREQ 121500000
+/* MDIO clock output frequency */
+#define EMAC_MDIO_CLOCK_FREQ 2200000 /* 2.2 MHz */
+#elif defined(CONFIG_SOC_DA8XX)
+/* MDIO module input frequency */
+#define EMAC_MDIO_BUS_FREQ clk_get(DAVINCI_MDIO_CLKID)
+/* MDIO clock output frequency */
+#define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */
+#else
+/* MDIO module input frequency */
+#define EMAC_MDIO_BUS_FREQ 99000000 /* PLL/6 - 99 MHz */
+/* MDIO clock output frequency */
+#define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */
+#endif
+
+#define PHY_KSZ8873 (0x00221450)
+int ksz8873_is_phy_connected(int phy_addr);
+int ksz8873_get_link_speed(int phy_addr);
+int ksz8873_init_phy(int phy_addr);
+int ksz8873_auto_negotiate(int phy_addr);
+
+#define PHY_LXT972 (0x001378e2)
+int lxt972_is_phy_connected(int phy_addr);
+int lxt972_get_link_speed(int phy_addr);
+int lxt972_init_phy(int phy_addr);
+int lxt972_auto_negotiate(int phy_addr);
+
+#define PHY_DP83848 (0x20005c90)
+int dp83848_is_phy_connected(int phy_addr);
+int dp83848_get_link_speed(int phy_addr);
+int dp83848_init_phy(int phy_addr);
+int dp83848_auto_negotiate(int phy_addr);
+
+#define PHY_ET1011C (0x282f013)
+int et1011c_get_link_speed(int phy_addr);
+
+#endif /* _DM644X_EMAC_H_ */
--- /dev/null
+/*
+ * Copyright (C) 2009 Texas Instruments Incorporated
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _GPIO_DEFS_H_
+#define _GPIO_DEFS_H_
+
+#ifndef CONFIG_SOC_DA8XX
+#define DAVINCI_GPIO_BINTEN 0x01C67008
+#define DAVINCI_GPIO_BANK01 0x01C67010
+#define DAVINCI_GPIO_BANK23 0x01C67038
+#define DAVINCI_GPIO_BANK45 0x01C67060
+#define DAVINCI_GPIO_BANK67 0x01C67088
+
+#else /* CONFIG_SOC_DA8XX */
+#define DAVINCI_GPIO_BINTEN 0x01E26008
+#define DAVINCI_GPIO_BANK01 0x01E26010
+#define DAVINCI_GPIO_BANK23 0x01E26038
+#define DAVINCI_GPIO_BANK45 0x01E26060
+#define DAVINCI_GPIO_BANK67 0x01E26088
+#define DAVINCI_GPIO_BANK8 0x01E260B0
+#endif /* CONFIG_SOC_DA8XX */
+
+struct davinci_gpio {
+ unsigned int dir;
+ unsigned int out_data;
+ unsigned int set_data;
+ unsigned int clr_data;
+ unsigned int in_data;
+ unsigned int set_rising;
+ unsigned int clr_rising;
+ unsigned int set_falling;
+ unsigned int clr_falling;
+ unsigned int intstat;
+};
+
+struct davinci_gpio_bank {
+ int num_gpio;
+ unsigned int irq_num;
+ unsigned int irq_mask;
+ unsigned long *in_use;
+ unsigned long base;
+};
+
+#define davinci_gpio_bank01 ((struct davinci_gpio *)DAVINCI_GPIO_BANK01)
+#define davinci_gpio_bank23 ((struct davinci_gpio *)DAVINCI_GPIO_BANK23)
+#define davinci_gpio_bank45 ((struct davinci_gpio *)DAVINCI_GPIO_BANK45)
+#define davinci_gpio_bank67 ((struct davinci_gpio *)DAVINCI_GPIO_BANK67)
+#define davinci_gpio_bank8 ((struct davinci_gpio *)DAVINCI_GPIO_BANK8)
+
+#define gpio_status() gpio_info()
+#define GPIO_NAME_SIZE 20
+#if defined(CONFIG_SOC_DM644X)
+/* GPIO0 to GPIO53, omit the V3.3 volts one */
+#define MAX_NUM_GPIOS 70
+#elif defined(CONFIG_SOC_DA8XX) && !defined(CONFIG_SOC_DA850)
+#define MAX_NUM_GPIOS 128
+#else
+#define MAX_NUM_GPIOS 144
+#endif
+#define GPIO_BANK(gp) (davinci_gpio_bank01 + ((gp) >> 5))
+#define GPIO_BIT(gp) ((gp) & 0x1F)
+
+void gpio_info(void);
+
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Based on:
+ *
+ * -------------------------------------------------------------------------
+ *
+ * linux/include/asm-arm/arch-davinci/hardware.h
+ *
+ * Copyright (C) 2006 Texas Instruments.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <config.h>
+#include <linux/sizes.h>
+
+#define REG(addr) (*(volatile unsigned int *)(addr))
+#define REG_P(addr) ((volatile unsigned int *)(addr))
+
+typedef volatile unsigned int dv_reg;
+typedef volatile unsigned int * dv_reg_p;
+
+/*
+ * Base register addresses
+ *
+ * NOTE: some of these DM6446-specific addresses DO NOT WORK
+ * on other DaVinci chips. Double check them before you try
+ * using the addresses ... or PSC module identifiers, etc.
+ */
+#ifndef CONFIG_SOC_DA8XX
+
+#define DAVINCI_DMA_3PCC_BASE (0x01c00000)
+#define DAVINCI_DMA_3PTC0_BASE (0x01c10000)
+#define DAVINCI_DMA_3PTC1_BASE (0x01c10400)
+#define DAVINCI_UART0_BASE (0x01c20000)
+#define DAVINCI_UART1_BASE (0x01c20400)
+#define DAVINCI_TIMER3_BASE (0x01c20800)
+#define DAVINCI_I2C_BASE (0x01c21000)
+#define DAVINCI_TIMER0_BASE (0x01c21400)
+#define DAVINCI_TIMER1_BASE (0x01c21800)
+#define DAVINCI_WDOG_BASE (0x01c21c00)
+#define DAVINCI_PWM0_BASE (0x01c22000)
+#define DAVINCI_PWM1_BASE (0x01c22400)
+#define DAVINCI_PWM2_BASE (0x01c22800)
+#define DAVINCI_TIMER4_BASE (0x01c23800)
+#define DAVINCI_SYSTEM_MODULE_BASE (0x01c40000)
+#define DAVINCI_PLL_CNTRL0_BASE (0x01c40800)
+#define DAVINCI_PLL_CNTRL1_BASE (0x01c40c00)
+#define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01c41000)
+#define DAVINCI_ARM_INTC_BASE (0x01c48000)
+#define DAVINCI_USB_OTG_BASE (0x01c64000)
+#define DAVINCI_CFC_ATA_BASE (0x01c66000)
+#define DAVINCI_SPI_BASE (0x01c66800)
+#define DAVINCI_GPIO_BASE (0x01c67000)
+#define DAVINCI_VPSS_REGS_BASE (0x01c70000)
+#if !defined(CONFIG_SOC_DM646X)
+#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000)
+#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000)
+#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000)
+#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000)
+#endif
+#define DAVINCI_DDR_BASE (0x80000000)
+
+#ifdef CONFIG_SOC_DM644X
+#define DAVINCI_UART2_BASE 0x01c20800
+#define DAVINCI_UHPI_BASE 0x01c67800
+#define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01c80000
+#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01c81000
+#define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01c82000
+#define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01c84000
+#define DAVINCI_IMCOP_BASE 0x01cc0000
+#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01e00000
+#define DAVINCI_VLYNQ_BASE 0x01e01000
+#define DAVINCI_ASP_BASE 0x01e02000
+#define DAVINCI_MMC_SD_BASE 0x01e10000
+#define DAVINCI_MS_BASE 0x01e20000
+#define DAVINCI_VLYNQ_REMOTE_BASE 0x0c000000
+
+#elif defined(CONFIG_SOC_DM355)
+#define DAVINCI_MMC_SD1_BASE 0x01e00000
+#define DAVINCI_ASP0_BASE 0x01e02000
+#define DAVINCI_ASP1_BASE 0x01e04000
+#define DAVINCI_UART2_BASE 0x01e06000
+#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01e10000
+#define DAVINCI_MMC_SD0_BASE 0x01e11000
+
+#elif defined(CONFIG_SOC_DM365)
+#define DAVINCI_MMC_SD1_BASE 0x01d00000
+#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01d10000
+#define DAVINCI_MMC_SD0_BASE 0x01d11000
+#define DAVINCI_DDR_EMIF_CTRL_BASE 0x20000000
+#define DAVINCI_SPI0_BASE 0x01c66000
+#define DAVINCI_SPI1_BASE 0x01c66800
+
+#elif defined(CONFIG_SOC_DM646X)
+#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x20008000
+#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x42000000
+#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE 0x44000000
+#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x46000000
+#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x48000000
+
+#endif
+
+#else /* CONFIG_SOC_DA8XX */
+
+#define DAVINCI_UART0_BASE 0x01c42000
+#define DAVINCI_UART1_BASE 0x01d0c000
+#define DAVINCI_UART2_BASE 0x01d0d000
+#define DAVINCI_I2C0_BASE 0x01c22000
+#define DAVINCI_I2C1_BASE 0x01e28000
+#define DAVINCI_TIMER0_BASE 0x01c20000
+#define DAVINCI_TIMER1_BASE 0x01c21000
+#define DAVINCI_WDOG_BASE 0x01c21000
+#define DAVINCI_RTC_BASE 0x01c23000
+#define DAVINCI_PLL_CNTRL0_BASE 0x01c11000
+#define DAVINCI_PLL_CNTRL1_BASE 0x01e1a000
+#define DAVINCI_PSC0_BASE 0x01c10000
+#define DAVINCI_PSC1_BASE 0x01e27000
+#define DAVINCI_SPI0_BASE 0x01c41000
+#define DAVINCI_USB_OTG_BASE 0x01e00000
+#define DAVINCI_SPI1_BASE (cpu_is_da830() ? \
+ 0x01e12000 : 0x01f0e000)
+#define DAVINCI_GPIO_BASE 0x01e26000
+#define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01e23000
+#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01e22000
+#define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01e20000
+#define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01e24000
+#define DAVINCI_SYSCFG1_BASE 0x01e2c000
+#define DAVINCI_MMC_SD0_BASE 0x01c40000
+#define DAVINCI_MMC_SD1_BASE 0x01e1b000
+#define DAVINCI_TIMER2_BASE 0x01f0c000
+#define DAVINCI_TIMER3_BASE 0x01f0d000
+#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x68000000
+#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x40000000
+#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x60000000
+#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x62000000
+#define DAVINCI_ASYNC_EMIF_DATA_CE4_BASE 0x64000000
+#define DAVINCI_ASYNC_EMIF_DATA_CE5_BASE 0x66000000
+#define DAVINCI_DDR_EMIF_CTRL_BASE 0xb0000000
+#define DAVINCI_DDR_EMIF_DATA_BASE 0xc0000000
+#define DAVINCI_INTC_BASE 0xfffee000
+#define DAVINCI_BOOTCFG_BASE 0x01c14000
+#define DAVINCI_LCD_CNTL_BASE 0x01e13000
+#define DAVINCI_L3CBARAM_BASE 0x80000000
+#define JTAG_ID_REG (DAVINCI_BOOTCFG_BASE + 0x18)
+#define CHIP_REV_ID_REG (DAVINCI_BOOTCFG_BASE + 0x24)
+#define HOST1CFG (DAVINCI_BOOTCFG_BASE + 0x44)
+#define PSC0_MDCTL (DAVINCI_PSC0_BASE + 0xa00)
+
+#define GPIO_BANK0_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x10)
+#define GPIO_BANK0_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x14)
+#define GPIO_BANK0_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x18)
+#define GPIO_BANK0_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x1c)
+#define GPIO_BANK2_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x38)
+#define GPIO_BANK2_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x3c)
+#define GPIO_BANK2_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x40)
+#define GPIO_BANK2_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x44)
+#define GPIO_BANK6_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x88)
+#define GPIO_BANK6_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x8c)
+#define GPIO_BANK6_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x90)
+#define GPIO_BANK6_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x94)
+#endif /* CONFIG_SOC_DA8XX */
+
+/* Power and Sleep Controller (PSC) Domains */
+#define DAVINCI_GPSC_ARMDOMAIN 0
+#define DAVINCI_GPSC_DSPDOMAIN 1
+
+#ifndef CONFIG_SOC_DA8XX
+
+#define DAVINCI_LPSC_VPSSMSTR 0
+#define DAVINCI_LPSC_VPSSSLV 1
+#define DAVINCI_LPSC_TPCC 2
+#define DAVINCI_LPSC_TPTC0 3
+#define DAVINCI_LPSC_TPTC1 4
+#define DAVINCI_LPSC_EMAC 5
+#define DAVINCI_LPSC_EMAC_WRAPPER 6
+#define DAVINCI_LPSC_MDIO 7
+#define DAVINCI_LPSC_IEEE1394 8
+#define DAVINCI_LPSC_USB 9
+#define DAVINCI_LPSC_ATA 10
+#define DAVINCI_LPSC_VLYNQ 11
+#define DAVINCI_LPSC_UHPI 12
+#define DAVINCI_LPSC_DDR_EMIF 13
+#define DAVINCI_LPSC_AEMIF 14
+#define DAVINCI_LPSC_MMC_SD 15
+#define DAVINCI_LPSC_MEMSTICK 16
+#define DAVINCI_LPSC_McBSP 17
+#define DAVINCI_LPSC_I2C 18
+#define DAVINCI_LPSC_UART0 19
+#define DAVINCI_LPSC_UART1 20
+#define DAVINCI_LPSC_UART2 21
+#define DAVINCI_LPSC_SPI 22
+#define DAVINCI_LPSC_PWM0 23
+#define DAVINCI_LPSC_PWM1 24
+#define DAVINCI_LPSC_PWM2 25
+#define DAVINCI_LPSC_GPIO 26
+#define DAVINCI_LPSC_TIMER0 27
+#define DAVINCI_LPSC_TIMER1 28
+#define DAVINCI_LPSC_TIMER2 29
+#define DAVINCI_LPSC_SYSTEM_SUBSYS 30
+#define DAVINCI_LPSC_ARM 31
+#define DAVINCI_LPSC_SCR2 32
+#define DAVINCI_LPSC_SCR3 33
+#define DAVINCI_LPSC_SCR4 34
+#define DAVINCI_LPSC_CROSSBAR 35
+#define DAVINCI_LPSC_CFG27 36
+#define DAVINCI_LPSC_CFG3 37
+#define DAVINCI_LPSC_CFG5 38
+#define DAVINCI_LPSC_GEM 39
+#define DAVINCI_LPSC_IMCOP 40
+#define DAVINCI_LPSC_VPSSMASTER 47
+#define DAVINCI_LPSC_MJCP 50
+#define DAVINCI_LPSC_HDVICP 51
+
+#define DAVINCI_DM646X_LPSC_EMAC 14
+#define DAVINCI_DM646X_LPSC_UART0 26
+#define DAVINCI_DM646X_LPSC_I2C 31
+#define DAVINCI_DM646X_LPSC_TIMER0 34
+
+#else /* CONFIG_SOC_DA8XX */
+
+#define DAVINCI_LPSC_TPCC 0
+#define DAVINCI_LPSC_TPTC0 1
+#define DAVINCI_LPSC_TPTC1 2
+#define DAVINCI_LPSC_AEMIF 3
+#define DAVINCI_LPSC_SPI0 4
+#define DAVINCI_LPSC_MMC_SD 5
+#define DAVINCI_LPSC_AINTC 6
+#define DAVINCI_LPSC_ARM_RAM_ROM 7
+#define DAVINCI_LPSC_SECCTL_KEYMGR 8
+#define DAVINCI_LPSC_UART0 9
+#define DAVINCI_LPSC_SCR0 10
+#define DAVINCI_LPSC_SCR1 11
+#define DAVINCI_LPSC_SCR2 12
+#define DAVINCI_LPSC_DMAX 13
+#define DAVINCI_LPSC_ARM 14
+#define DAVINCI_LPSC_GEM 15
+
+/* for LPSCs in PSC1, offset from 32 for differentiation */
+#define DAVINCI_LPSC_PSC1_BASE 32
+#define DAVINCI_LPSC_USB20 (DAVINCI_LPSC_PSC1_BASE + 1)
+#define DAVINCI_LPSC_USB11 (DAVINCI_LPSC_PSC1_BASE + 2)
+#define DAVINCI_LPSC_GPIO (DAVINCI_LPSC_PSC1_BASE + 3)
+#define DAVINCI_LPSC_UHPI (DAVINCI_LPSC_PSC1_BASE + 4)
+#define DAVINCI_LPSC_EMAC (DAVINCI_LPSC_PSC1_BASE + 5)
+#define DAVINCI_LPSC_DDR_EMIF (DAVINCI_LPSC_PSC1_BASE + 6)
+#define DAVINCI_LPSC_McASP0 (DAVINCI_LPSC_PSC1_BASE + 7)
+#define DAVINCI_LPSC_SPI1 (DAVINCI_LPSC_PSC1_BASE + 10)
+#define DAVINCI_LPSC_I2C1 (DAVINCI_LPSC_PSC1_BASE + 11)
+#define DAVINCI_LPSC_UART1 (DAVINCI_LPSC_PSC1_BASE + 12)
+#define DAVINCI_LPSC_UART2 (DAVINCI_LPSC_PSC1_BASE + 13)
+#define DAVINCI_LPSC_LCDC (DAVINCI_LPSC_PSC1_BASE + 16)
+#define DAVINCI_LPSC_ePWM (DAVINCI_LPSC_PSC1_BASE + 17)
+#define DAVINCI_LPSC_MMCSD1 (DAVINCI_LPSC_PSC1_BASE + 18)
+#define DAVINCI_LPSC_eCAP (DAVINCI_LPSC_PSC1_BASE + 20)
+#define DAVINCI_LPSC_L3_CBA_RAM (DAVINCI_LPSC_PSC1_BASE + 31)
+
+/* DA830-specific peripherals */
+#define DAVINCI_LPSC_McASP1 (DAVINCI_LPSC_PSC1_BASE + 8)
+#define DAVINCI_LPSC_McASP2 (DAVINCI_LPSC_PSC1_BASE + 9)
+#define DAVINCI_LPSC_eQEP (DAVINCI_LPSC_PSC1_BASE + 21)
+#define DAVINCI_LPSC_SCR8 (DAVINCI_LPSC_PSC1_BASE + 24)
+#define DAVINCI_LPSC_SCR7 (DAVINCI_LPSC_PSC1_BASE + 25)
+#define DAVINCI_LPSC_SCR12 (DAVINCI_LPSC_PSC1_BASE + 26)
+
+/* DA850-specific peripherals */
+#define DAVINCI_LPSC_TPCC1 (DAVINCI_LPSC_PSC1_BASE + 0)
+#define DAVINCI_LPSC_SATA (DAVINCI_LPSC_PSC1_BASE + 8)
+#define DAVINCI_LPSC_VPIF (DAVINCI_LPSC_PSC1_BASE + 9)
+#define DAVINCI_LPSC_McBSP0 (DAVINCI_LPSC_PSC1_BASE + 14)
+#define DAVINCI_LPSC_McBSP1 (DAVINCI_LPSC_PSC1_BASE + 15)
+#define DAVINCI_LPSC_MMC_SD1 (DAVINCI_LPSC_PSC1_BASE + 18)
+#define DAVINCI_LPSC_uPP (DAVINCI_LPSC_PSC1_BASE + 19)
+#define DAVINCI_LPSC_TPTC2 (DAVINCI_LPSC_PSC1_BASE + 21)
+#define DAVINCI_LPSC_SCR_F0 (DAVINCI_LPSC_PSC1_BASE + 24)
+#define DAVINCI_LPSC_SCR_F1 (DAVINCI_LPSC_PSC1_BASE + 25)
+#define DAVINCI_LPSC_SCR_F2 (DAVINCI_LPSC_PSC1_BASE + 26)
+#define DAVINCI_LPSC_SCR_F6 (DAVINCI_LPSC_PSC1_BASE + 27)
+#define DAVINCI_LPSC_SCR_F7 (DAVINCI_LPSC_PSC1_BASE + 28)
+#define DAVINCI_LPSC_SCR_F8 (DAVINCI_LPSC_PSC1_BASE + 29)
+#define DAVINCI_LPSC_BR_F7 (DAVINCI_LPSC_PSC1_BASE + 30)
+
+#endif /* CONFIG_SOC_DA8XX */
+
+void lpsc_on(unsigned int id);
+void lpsc_syncreset(unsigned int id);
+void lpsc_disable(unsigned int id);
+void dsp_on(void);
+
+void davinci_enable_uart0(void);
+void davinci_enable_emac(void);
+void davinci_enable_i2c(void);
+void davinci_errata_workarounds(void);
+
+#ifndef CONFIG_SOC_DA8XX
+
+/* Some PSC defines */
+#define PSC_CHP_SHRTSW (0x01c40038)
+#define PSC_GBLCTL (0x01c41010)
+#define PSC_EPCPR (0x01c41070)
+#define PSC_EPCCR (0x01c41078)
+#define PSC_PTCMD (0x01c41120)
+#define PSC_PTSTAT (0x01c41128)
+#define PSC_PDSTAT (0x01c41200)
+#define PSC_PDSTAT1 (0x01c41204)
+#define PSC_PDCTL (0x01c41300)
+#define PSC_PDCTL1 (0x01c41304)
+
+#define PSC_MDCTL_BASE (0x01c41a00)
+#define PSC_MDSTAT_BASE (0x01c41800)
+
+#define VDD3P3V_PWDN (0x01c40048)
+#define UART0_PWREMU_MGMT (0x01c20030)
+
+#define PSC_SILVER_BULLET (0x01c41a20)
+
+#else /* CONFIG_SOC_DA8XX */
+
+#define PSC_ENABLE 0x3
+#define PSC_DISABLE 0x2
+#define PSC_SYNCRESET 0x1
+#define PSC_SWRSTDISABLE 0x0
+
+#define PSC_PSC0_MODULE_ID_CNT 16
+#define PSC_PSC1_MODULE_ID_CNT 32
+
+#define UART0_PWREMU_MGMT (0x01c42030)
+
+struct davinci_psc_regs {
+ dv_reg revid;
+ dv_reg rsvd0[71];
+ dv_reg ptcmd;
+ dv_reg rsvd1;
+ dv_reg ptstat;
+ dv_reg rsvd2[437];
+ union {
+ struct {
+ dv_reg mdstat[PSC_PSC0_MODULE_ID_CNT];
+ dv_reg rsvd3[112];
+ dv_reg mdctl[PSC_PSC0_MODULE_ID_CNT];
+ } psc0;
+ struct {
+ dv_reg mdstat[PSC_PSC1_MODULE_ID_CNT];
+ dv_reg rsvd3[96];
+ dv_reg mdctl[PSC_PSC1_MODULE_ID_CNT];
+ } psc1;
+ };
+};
+
+#define davinci_psc0_regs ((struct davinci_psc_regs *)DAVINCI_PSC0_BASE)
+#define davinci_psc1_regs ((struct davinci_psc_regs *)DAVINCI_PSC1_BASE)
+
+#endif /* CONFIG_SOC_DA8XX */
+
+#define PSC_MDSTAT_STATE 0x3f
+#define PSC_MDCTL_NEXT 0x07
+
+#ifndef CONFIG_SOC_DA8XX
+
+/* Miscellania... */
+#define VBPR (0x20000020)
+
+/* NOTE: system control modules are *highly* chip-specific, both
+ * as to register content (e.g. for muxing) and which registers exist.
+ */
+#define PINMUX0 0x01c40000
+#define PINMUX1 0x01c40004
+#define PINMUX2 0x01c40008
+#define PINMUX3 0x01c4000c
+#define PINMUX4 0x01c40010
+
+struct davinci_uart_ctrl_regs {
+ dv_reg revid1;
+ dv_reg res;
+ dv_reg pwremu_mgmt;
+ dv_reg mdr;
+};
+
+#define DAVINCI_UART_CTRL_BASE 0x28
+
+/* UART PWREMU_MGMT definitions */
+#define DAVINCI_UART_PWREMU_MGMT_FREE (1 << 0)
+#define DAVINCI_UART_PWREMU_MGMT_URRST (1 << 13)
+#define DAVINCI_UART_PWREMU_MGMT_UTRST (1 << 14)
+
+#else /* CONFIG_SOC_DA8XX */
+
+struct davinci_pllc_regs {
+ dv_reg revid;
+ dv_reg rsvd1[56];
+ dv_reg rstype;
+ dv_reg rsvd2[6];
+ dv_reg pllctl;
+ dv_reg ocsel;
+ dv_reg rsvd3[2];
+ dv_reg pllm;
+ dv_reg prediv;
+ dv_reg plldiv1;
+ dv_reg plldiv2;
+ dv_reg plldiv3;
+ dv_reg oscdiv;
+ dv_reg postdiv;
+ dv_reg rsvd4[3];
+ dv_reg pllcmd;
+ dv_reg pllstat;
+ dv_reg alnctl;
+ dv_reg dchange;
+ dv_reg cken;
+ dv_reg ckstat;
+ dv_reg systat;
+ dv_reg rsvd5[3];
+ dv_reg plldiv4;
+ dv_reg plldiv5;
+ dv_reg plldiv6;
+ dv_reg plldiv7;
+ dv_reg rsvd6[32];
+ dv_reg emucnt0;
+ dv_reg emucnt1;
+};
+
+#define davinci_pllc0_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE)
+#define davinci_pllc1_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL1_BASE)
+#define DAVINCI_PLLC_DIV_MASK 0x1f
+
+/*
+ * A clock ID is a 32-bit number where bit 16 represents the PLL controller
+ * (clear is PLLC0, set is PLLC1) and the low 16 bits represent the divisor,
+ * counting from 1. Clock IDs may be passed to clk_get().
+ */
+
+/* flags to select PLL controller */
+#define DAVINCI_PLLC0_FLAG (0)
+#define DAVINCI_PLLC1_FLAG (1 << 16)
+
+enum davinci_clk_ids {
+ /*
+ * Clock IDs for PLL outputs. Each may be switched on/off
+ * independently, and each may map to one or more peripherals.
+ */
+ DAVINCI_PLL0_SYSCLK2 = DAVINCI_PLLC0_FLAG | 2,
+ DAVINCI_PLL0_SYSCLK4 = DAVINCI_PLLC0_FLAG | 4,
+ DAVINCI_PLL0_SYSCLK6 = DAVINCI_PLLC0_FLAG | 6,
+ DAVINCI_PLL1_SYSCLK1 = DAVINCI_PLLC1_FLAG | 1,
+ DAVINCI_PLL1_SYSCLK2 = DAVINCI_PLLC1_FLAG | 2,
+
+ /* map peripherals to clock IDs */
+ DAVINCI_ARM_CLKID = DAVINCI_PLL0_SYSCLK6,
+ DAVINCI_DDR_CLKID = DAVINCI_PLL1_SYSCLK1,
+ DAVINCI_MDIO_CLKID = DAVINCI_PLL0_SYSCLK4,
+ DAVINCI_MMC_CLKID = DAVINCI_PLL0_SYSCLK2,
+ DAVINCI_SPI0_CLKID = DAVINCI_PLL0_SYSCLK2,
+ DAVINCI_MMCSD_CLKID = DAVINCI_PLL0_SYSCLK2,
+
+ /* special clock ID - output of PLL multiplier */
+ DAVINCI_PLLM_CLKID = 0x0FF,
+
+ /* special clock ID - output of PLL post divisor */
+ DAVINCI_PLLC_CLKID = 0x100,
+
+ /* special clock ID - PLL bypass */
+ DAVINCI_AUXCLK_CLKID = 0x101,
+};
+
+#define DAVINCI_UART2_CLKID (cpu_is_da830() ? DAVINCI_PLL0_SYSCLK2 \
+ : get_async3_src())
+
+#define DAVINCI_SPI1_CLKID (cpu_is_da830() ? DAVINCI_PLL0_SYSCLK2 \
+ : get_async3_src())
+
+int clk_get(enum davinci_clk_ids id);
+
+/* Boot config */
+struct davinci_syscfg_regs {
+ dv_reg revid;
+ dv_reg rsvd[13];
+ dv_reg kick0;
+ dv_reg kick1;
+ dv_reg rsvd1[52];
+ dv_reg mstpri[3];
+ dv_reg rsvd2;
+ dv_reg pinmux[20];
+ dv_reg suspsrc;
+ dv_reg chipsig;
+ dv_reg chipsig_clr;
+ dv_reg cfgchip0;
+ dv_reg cfgchip1;
+ dv_reg cfgchip2;
+ dv_reg cfgchip3;
+ dv_reg cfgchip4;
+};
+
+#define davinci_syscfg_regs \
+ ((struct davinci_syscfg_regs *)DAVINCI_BOOTCFG_BASE)
+
+#define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
+
+/* Emulation suspend bits */
+#define DAVINCI_SYSCFG_SUSPSRC_EMAC (1 << 5)
+#define DAVINCI_SYSCFG_SUSPSRC_I2C (1 << 16)
+#define DAVINCI_SYSCFG_SUSPSRC_SPI0 (1 << 21)
+#define DAVINCI_SYSCFG_SUSPSRC_SPI1 (1 << 22)
+#define DAVINCI_SYSCFG_SUSPSRC_UART0 (1 << 18)
+#define DAVINCI_SYSCFG_SUSPSRC_UART2 (1 << 20)
+#define DAVINCI_SYSCFG_SUSPSRC_TIMER0 (1 << 27)
+
+struct davinci_syscfg1_regs {
+ dv_reg vtpio_ctl;
+ dv_reg ddr_slew;
+ dv_reg deepsleep;
+ dv_reg pupd_ena;
+ dv_reg pupd_sel;
+ dv_reg rxactive;
+ dv_reg pwrdwn;
+};
+
+#define davinci_syscfg1_regs \
+ ((struct davinci_syscfg1_regs *)DAVINCI_SYSCFG1_BASE)
+
+#define DDR_SLEW_CMOSEN_BIT 4
+#define DDR_SLEW_DDR_PDENA_BIT 5
+
+#define VTP_POWERDWN (1 << 6)
+#define VTP_LOCK (1 << 7)
+#define VTP_CLKRZ (1 << 13)
+#define VTP_READY (1 << 15)
+#define VTP_IOPWRDWN (1 << 14)
+
+#define DV_SYSCFG_KICK0_UNLOCK 0x83e70b13
+#define DV_SYSCFG_KICK1_UNLOCK 0x95a4f1e0
+
+/* Interrupt controller */
+struct davinci_aintc_regs {
+ dv_reg revid;
+ dv_reg cr;
+ dv_reg dummy0[2];
+ dv_reg ger;
+ dv_reg dummy1[219];
+ dv_reg ecr1;
+ dv_reg ecr2;
+ dv_reg ecr3;
+ dv_reg dummy2[1117];
+ dv_reg hier;
+};
+
+#define davinci_aintc_regs ((struct davinci_aintc_regs *)DAVINCI_INTC_BASE)
+
+struct davinci_uart_ctrl_regs {
+ dv_reg revid1;
+ dv_reg revid2;
+ dv_reg pwremu_mgmt;
+ dv_reg mdr;
+};
+
+#define DAVINCI_UART_CTRL_BASE 0x28
+#define DAVINCI_UART0_CTRL_ADDR (DAVINCI_UART0_BASE + DAVINCI_UART_CTRL_BASE)
+#define DAVINCI_UART1_CTRL_ADDR (DAVINCI_UART1_BASE + DAVINCI_UART_CTRL_BASE)
+#define DAVINCI_UART2_CTRL_ADDR (DAVINCI_UART2_BASE + DAVINCI_UART_CTRL_BASE)
+
+#define davinci_uart0_ctrl_regs \
+ ((struct davinci_uart_ctrl_regs *)DAVINCI_UART0_CTRL_ADDR)
+#define davinci_uart1_ctrl_regs \
+ ((struct davinci_uart_ctrl_regs *)DAVINCI_UART1_CTRL_ADDR)
+#define davinci_uart2_ctrl_regs \
+ ((struct davinci_uart_ctrl_regs *)DAVINCI_UART2_CTRL_ADDR)
+
+/* UART PWREMU_MGMT definitions */
+#define DAVINCI_UART_PWREMU_MGMT_FREE (1 << 0)
+#define DAVINCI_UART_PWREMU_MGMT_URRST (1 << 13)
+#define DAVINCI_UART_PWREMU_MGMT_UTRST (1 << 14)
+
+static inline int cpu_is_da830(void)
+{
+ unsigned int jtag_id = REG(JTAG_ID_REG);
+ unsigned short part_no = (jtag_id >> 12) & 0xffff;
+
+ return ((part_no == 0xb7df) ? 1 : 0);
+}
+static inline int cpu_is_da850(void)
+{
+ unsigned int jtag_id = REG(JTAG_ID_REG);
+ unsigned short part_no = (jtag_id >> 12) & 0xffff;
+
+ return ((part_no == 0xb7d1) ? 1 : 0);
+}
+
+static inline enum davinci_clk_ids get_async3_src(void)
+{
+ return (REG(&davinci_syscfg_regs->cfgchip3) & 0x10) ?
+ DAVINCI_PLL1_SYSCLK2 : DAVINCI_PLL0_SYSCLK2;
+}
+
+#endif /* CONFIG_SOC_DA8XX */
+
+#if defined(CONFIG_SOC_DM365)
+#include <asm/arch/aintc_defs.h>
+#include <asm/arch/ddr2_defs.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/pll_defs.h>
+#include <asm/arch/psc_defs.h>
+#include <asm/arch/syscfg_defs.h>
+#include <asm/arch/timer_defs.h>
+
+#define TMPBUF 0x00017ff8
+#define TMPSTATUS 0x00017ff0
+#define DV_TMPBUF_VAL 0x591b3ed7
+#define FLAG_PORRST 0x00000001
+#define FLAG_WDTRST 0x00000002
+#define FLAG_FLGON 0x00000004
+#define FLAG_FLGOFF 0x00000010
+
+#endif
+
+#endif /* __ASM_ARCH_HARDWARE_H */
--- /dev/null
+/*
+ * (C) Copyright 2004-2014
+ * Texas Instruments, <www.ti.com>
+ *
+ * Some changes copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _I2C_DEFS_H_
+#define _I2C_DEFS_H_
+
+#ifndef CONFIG_SOC_DA8XX
+#define I2C_BASE 0x01c21000
+#else
+#define I2C_BASE 0x01c22000
+#endif
+
+#endif
--- /dev/null
+/*
+ * Pinmux configurations for the DAxxx SoCs
+ *
+ * Copyright (C) 2011 OMICRON electronics GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_PINMUX_DEFS_H
+#define __ASM_ARCH_PINMUX_DEFS_H
+
+#include <asm/arch/davinci_misc.h>
+#include <config.h>
+
+/* SPI0 pin muxer settings */
+extern const struct pinmux_config spi0_pins_base[3];
+extern const struct pinmux_config spi0_pins_scs0[1];
+extern const struct pinmux_config spi0_pins_ena[1];
+
+/* SPI1 pin muxer settings */
+extern const struct pinmux_config spi1_pins_base[3];
+extern const struct pinmux_config spi1_pins_scs0[1];
+
+/* UART pin muxer settings */
+extern const struct pinmux_config uart0_pins_txrx[2];
+extern const struct pinmux_config uart0_pins_rtscts[2];
+extern const struct pinmux_config uart1_pins_txrx[2];
+extern const struct pinmux_config uart2_pins_txrx[2];
+extern const struct pinmux_config uart2_pins_rtscts[2];
+
+/* EMAC pin muxer settings*/
+extern const struct pinmux_config emac_pins_rmii[8];
+extern const struct pinmux_config emac_pins_rmii_clk_source[1];
+extern const struct pinmux_config emac_pins_mii[15];
+extern const struct pinmux_config emac_pins_mdio[2];
+
+/* I2C pin muxer settings */
+extern const struct pinmux_config i2c0_pins[2];
+extern const struct pinmux_config i2c1_pins[2];
+
+/* EMIFA pin muxer settings */
+extern const struct pinmux_config emifa_pins[40];
+extern const struct pinmux_config emifa_pins_cs0[1];
+extern const struct pinmux_config emifa_pins_cs2[1];
+extern const struct pinmux_config emifa_pins_cs3[1];
+extern const struct pinmux_config emifa_pins_cs4[1];
+extern const struct pinmux_config emifa_pins_nand[12];
+extern const struct pinmux_config emifa_pins_nor[43];
+
+/* USB pin mux setting */
+extern const struct pinmux_config usb_pins[1];
+
+/* MMC pin muxer settings */
+extern const struct pinmux_config mmc0_pins_8bit[10];
+extern const struct pinmux_config mmc0_pins[6];
+
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _DV_PLL_DEFS_H_
+#define _DV_PLL_DEFS_H_
+
+struct dv_pll_regs {
+ unsigned int pid; /* 0x00 */
+ unsigned char rsvd0[224]; /* 0x04 */
+ unsigned int rstype; /* 0xe4 */
+ unsigned char rsvd1[24]; /* 0xe8 */
+ unsigned int pllctl; /* 0x100 */
+ unsigned char rsvd2[4]; /* 0x104 */
+ unsigned int secctl; /* 0x108 */
+ unsigned int rv; /* 0x10c */
+ unsigned int pllm; /* 0x110 */
+ unsigned int prediv; /* 0x114 */
+ unsigned int plldiv1; /* 0x118 */
+ unsigned int plldiv2; /* 0x11c */
+ unsigned int plldiv3; /* 0x120 */
+ unsigned int oscdiv1; /* 0x124 */
+ unsigned int postdiv; /* 0x128 */
+ unsigned int bpdiv; /* 0x12c */
+ unsigned char rsvd5[8]; /* 0x130 */
+ unsigned int pllcmd; /* 0x138 */
+ unsigned int pllstat; /* 0x13c */
+ unsigned int alnctl; /* 0x140 */
+ unsigned int dchange; /* 0x144 */
+ unsigned int cken; /* 0x148 */
+ unsigned int ckstat; /* 0x14c */
+ unsigned int systat; /* 0x150 */
+ unsigned char rsvd6[12]; /* 0x154 */
+ unsigned int plldiv4; /* 0x160 */
+ unsigned int plldiv5; /* 0x164 */
+ unsigned int plldiv6; /* 0x168 */
+ unsigned int plldiv7; /* 0x16C */
+ unsigned int plldiv8; /* 0x170 */
+ unsigned int plldiv9; /* 0x174 */
+};
+
+#define PLL_MASTER_LOCK (1 << 4)
+
+#define PLLCTL_CLOCK_MODE_SHIFT 8
+#define PLLCTL_PLLEN (1 << 0)
+#define PLLCTL_PLLPWRDN (1 << 1)
+#define PLLCTL_PLLRST (1 << 3)
+#define PLLCTL_PLLDIS (1 << 4)
+#define PLLCTL_PLLENSRC (1 << 5)
+#define PLLCTL_RES_9 (1 << 8)
+#define PLLCTL_EXTCLKSRC (1 << 9)
+
+#define PLL_DIVEN (1 << 15)
+#define PLL_POSTDEN PLL_DIVEN
+
+#define PLL_SCSCFG3_DIV45PENA (1 << 2)
+#define PLL_SCSCFG3_EMA_CLKSRC (1 << 1)
+
+#define PLL_RSTYPE_POR (1 << 0)
+#define PLL_RSTYPE_XWRST (1 << 1)
+
+#define PLLSECCTL_TINITZ (1 << 16)
+#define PLLSECCTL_TENABLE (1 << 17)
+#define PLLSECCTL_TENABLEDIV (1 << 18)
+#define PLLSECCTL_STOPMODE (1 << 22)
+
+#define PLLCMD_GOSET (1 << 0)
+#define PLLCMD_GOSTAT (1 << 0)
+
+#define PLL0_LOCK 0x07000000
+#define PLL1_LOCK 0x07000000
+
+#define dv_pll0_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL0_BASE)
+#define dv_pll1_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL1_BASE)
+
+#define ARM_PLLDIV (offsetof(struct dv_pll_regs, plldiv2))
+#define DDR_PLLDIV (offsetof(struct dv_pll_regs, plldiv7))
+#define SPI_PLLDIV (offsetof(struct dv_pll_regs, plldiv4))
+
+unsigned int davinci_clk_get(unsigned int div);
+#endif /* _DV_PLL_DEFS_H_ */
--- /dev/null
+/*
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _DV_PSC_DEFS_H_
+#define _DV_PSC_DEFS_H_
+
+/*
+ * Power/Sleep Ctrl Register structure
+ * See sprufb3.pdf, Chapter 7
+ */
+struct dv_psc_regs {
+ unsigned int pid; /* 0x000 */
+ unsigned char rsvd0[16]; /* 0x004 */
+ unsigned char rsvd1[4]; /* 0x014 */
+ unsigned int inteval; /* 0x018 */
+ unsigned char rsvd2[36]; /* 0x01C */
+ unsigned int merrpr0; /* 0x040 */
+ unsigned int merrpr1; /* 0x044 */
+ unsigned char rsvd3[8]; /* 0x048 */
+ unsigned int merrcr0; /* 0x050 */
+ unsigned int merrcr1; /* 0x054 */
+ unsigned char rsvd4[8]; /* 0x058 */
+ unsigned int perrpr; /* 0x060 */
+ unsigned char rsvd5[4]; /* 0x064 */
+ unsigned int perrcr; /* 0x068 */
+ unsigned char rsvd6[4]; /* 0x06C */
+ unsigned int epcpr; /* 0x070 */
+ unsigned char rsvd7[4]; /* 0x074 */
+ unsigned int epccr; /* 0x078 */
+ unsigned char rsvd8[144]; /* 0x07C */
+ unsigned char rsvd9[20]; /* 0x10C */
+ unsigned int ptcmd; /* 0x120 */
+ unsigned char rsvd10[4]; /* 0x124 */
+ unsigned int ptstat; /* 0x128 */
+ unsigned char rsvd11[212]; /* 0x12C */
+ unsigned int pdstat0; /* 0x200 */
+ unsigned int pdstat1; /* 0x204 */
+ unsigned char rsvd12[248]; /* 0x208 */
+ unsigned int pdctl0; /* 0x300 */
+ unsigned int pdctl1; /* 0x304 */
+ unsigned char rsvd13[536]; /* 0x308 */
+ unsigned int mckout0; /* 0x520 */
+ unsigned int mckout1; /* 0x524 */
+ unsigned char rsvd14[728]; /* 0x528 */
+ unsigned int mdstat[52]; /* 0x800 */
+ unsigned char rsvd15[304]; /* 0x8D0 */
+ unsigned int mdctl[52]; /* 0xA00 */
+};
+
+/* PSC constants */
+#define EMURSTIE_MASK (0x00000200)
+
+#define PD0 (0)
+
+#define PSC_ENABLE (0x3)
+#define PSC_DISABLE (0x2)
+#define PSC_SYNCRESET (0x1)
+#define PSC_SWRSTDISABLE (0x0)
+
+#define PSC_GOSTAT (1 << 0)
+#define PSC_MD_STATE_MSK (0x1f)
+
+#define PSC_CMD_GO (1 << 0)
+
+#define dv_psc_regs ((struct dv_psc_regs *)DAVINCI_PWR_SLEEP_CNTRL_BASE)
+
+#endif /* _DV_PSC_DEFS_H_ */
--- /dev/null
+/*
+ * Davinci MMC Controller Defines - Based on Linux davinci_mmc.c
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SDMMC_DEFS_H_
+#define _SDMMC_DEFS_H_
+
+#include <asm/arch/hardware.h>
+
+/* MMC Control Reg fields */
+#define MMCCTL_DATRST (1 << 0)
+#define MMCCTL_CMDRST (1 << 1)
+#define MMCCTL_WIDTH_4_BIT (1 << 2)
+#define MMCCTL_DATEG_DISABLED (0 << 6)
+#define MMCCTL_DATEG_RISING (1 << 6)
+#define MMCCTL_DATEG_FALLING (2 << 6)
+#define MMCCTL_DATEG_BOTH (3 << 6)
+#define MMCCTL_PERMDR_LE (0 << 9)
+#define MMCCTL_PERMDR_BE (1 << 9)
+#define MMCCTL_PERMDX_LE (0 << 10)
+#define MMCCTL_PERMDX_BE (1 << 10)
+
+/* MMC Clock Control Reg fields */
+#define MMCCLK_CLKEN (1 << 8)
+#define MMCCLK_CLKRT_MASK (0xFF << 0)
+
+/* MMC Status Reg0 fields */
+#define MMCST0_DATDNE (1 << 0)
+#define MMCST0_BSYDNE (1 << 1)
+#define MMCST0_RSPDNE (1 << 2)
+#define MMCST0_TOUTRD (1 << 3)
+#define MMCST0_TOUTRS (1 << 4)
+#define MMCST0_CRCWR (1 << 5)
+#define MMCST0_CRCRD (1 << 6)
+#define MMCST0_CRCRS (1 << 7)
+#define MMCST0_DXRDY (1 << 9)
+#define MMCST0_DRRDY (1 << 10)
+#define MMCST0_DATED (1 << 11)
+#define MMCST0_TRNDNE (1 << 12)
+
+#define MMCST0_ERR_MASK (0x00F8)
+
+/* MMC Status Reg1 fields */
+#define MMCST1_BUSY (1 << 0)
+#define MMCST1_CLKSTP (1 << 1)
+#define MMCST1_DXEMP (1 << 2)
+#define MMCST1_DRFUL (1 << 3)
+#define MMCST1_DAT3ST (1 << 4)
+#define MMCST1_FIFOEMP (1 << 5)
+#define MMCST1_FIFOFUL (1 << 6)
+
+/* MMC INT Mask Reg fields */
+#define MMCIM_EDATDNE (1 << 0)
+#define MMCIM_EBSYDNE (1 << 1)
+#define MMCIM_ERSPDNE (1 << 2)
+#define MMCIM_ETOUTRD (1 << 3)
+#define MMCIM_ETOUTRS (1 << 4)
+#define MMCIM_ECRCWR (1 << 5)
+#define MMCIM_ECRCRD (1 << 6)
+#define MMCIM_ECRCRS (1 << 7)
+#define MMCIM_EDXRDY (1 << 9)
+#define MMCIM_EDRRDY (1 << 10)
+#define MMCIM_EDATED (1 << 11)
+#define MMCIM_ETRNDNE (1 << 12)
+
+#define MMCIM_MASKALL (0xFFFFFFFF)
+
+/* MMC Resp Tout Reg fields */
+#define MMCTOR_TOR_MASK (0xFF) /* dont write to reg, | it */
+#define MMCTOR_TOD_20_16_SHIFT (8)
+
+/* MMC Data Read Tout Reg fields */
+#define MMCTOD_TOD_0_15_MASK (0xFFFF)
+
+/* MMC Block len Reg fields */
+#define MMCBLEN_BLEN_MASK (0xFFF)
+
+/* MMC Num Blocks Reg fields */
+#define MMCNBLK_NBLK_MASK (0xFFFF)
+#define MMCNBLK_NBLK_MAX (0xFFFF)
+
+/* MMC Num Blocks Counter Reg fields */
+#define MMCNBLC_NBLC_MASK (0xFFFF)
+
+/* MMC Cmd Reg fields */
+#define MMCCMD_CMD_MASK (0x3F)
+#define MMCCMD_PPLEN (1 << 7)
+#define MMCCMD_BSYEXP (1 << 8)
+#define MMCCMD_RSPFMT_NONE (0 << 9)
+#define MMCCMD_RSPFMT_R1567 (1 << 9)
+#define MMCCMD_RSPFMT_R2 (2 << 9)
+#define MMCCMD_RSPFMT_R3 (3 << 9)
+#define MMCCMD_DTRW (1 << 11)
+#define MMCCMD_STRMTP (1 << 12)
+#define MMCCMD_WDATX (1 << 13)
+#define MMCCMD_INITCK (1 << 14)
+#define MMCCMD_DCLR (1 << 15)
+#define MMCCMD_DMATRIG (1 << 16)
+
+/* FIFO control Reg fields */
+#define MMCFIFOCTL_FIFORST (1 << 0)
+#define MMCFIFOCTL_FIFODIR (1 << 1)
+#define MMCFIFOCTL_FIFOLEV (1 << 2)
+#define MMCFIFOCTL_ACCWD_4 (0 << 3) /* access width of 4 bytes */
+#define MMCFIFOCTL_ACCWD_3 (1 << 3) /* access width of 3 bytes */
+#define MMCFIFOCTL_ACCWD_2 (2 << 3) /* access width of 2 bytes */
+#define MMCFIFOCTL_ACCWD_1 (3 << 3) /* access width of 1 byte */
+
+/* Davinci MMC Register definitions */
+struct davinci_mmc_regs {
+ dv_reg mmcctl;
+ dv_reg mmcclk;
+ dv_reg mmcst0;
+ dv_reg mmcst1;
+ dv_reg mmcim;
+ dv_reg mmctor;
+ dv_reg mmctod;
+ dv_reg mmcblen;
+ dv_reg mmcnblk;
+ dv_reg mmcnblc;
+ dv_reg mmcdrr;
+ dv_reg mmcdxr;
+ dv_reg mmccmd;
+ dv_reg mmcarghl;
+ dv_reg mmcrsp01;
+ dv_reg mmcrsp23;
+ dv_reg mmcrsp45;
+ dv_reg mmcrsp67;
+ dv_reg mmcdrsp;
+ dv_reg mmcetok;
+ dv_reg mmccidx;
+ dv_reg mmcckc;
+ dv_reg mmctorc;
+ dv_reg mmctodc;
+ dv_reg mmcblnc;
+ dv_reg sdioctl;
+ dv_reg sdiost0;
+ dv_reg sdioien;
+ dv_reg sdioist;
+ dv_reg mmcfifoctl;
+};
+
+/* Davinci MMC board definitions */
+struct davinci_mmc {
+ struct davinci_mmc_regs *reg_base; /* Register base address */
+ uint input_clk; /* Input clock to MMC controller */
+ uint host_caps; /* Host capabilities */
+ uint voltages; /* Host supported voltages */
+ uint version; /* MMC Controller version */
+ struct mmc_config cfg;
+};
+
+enum {
+ MMC_CTLR_VERSION_1 = 0, /* DM644x and DM355 */
+ MMC_CTLR_VERSION_2, /* DA830 */
+};
+
+int davinci_mmc_init(bd_t *bis, struct davinci_mmc *host);
+
+#endif /* _SDMMC_DEFS_H */
--- /dev/null
+/*
+ * Copyright (C) 2011
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _DV_SYSCFG_DEFS_H_
+#define _DV_SYSCFG_DEFS_H_
+
+#ifndef CONFIG_SOC_DA8XX
+/* System Control Module register structure for DM365 */
+struct dv_sys_module_regs {
+ unsigned int pinmux[5]; /* 0x00 */
+ unsigned int bootcfg; /* 0x14 */
+ unsigned int arm_intmux; /* 0x18 */
+ unsigned int edma_evtmux; /* 0x1C */
+ unsigned int ddr_slew; /* 0x20 */
+ unsigned int clkout; /* 0x24 */
+ unsigned int device_id; /* 0x28 */
+ unsigned int vdac_config; /* 0x2C */
+ unsigned int timer64_ctl; /* 0x30 */
+ unsigned int usbbphy_ctl; /* 0x34 */
+ unsigned int misc; /* 0x38 */
+ unsigned int mstpri[2]; /* 0x3C */
+ unsigned int vpss_clkctl; /* 0x44 */
+ unsigned int peri_clkctl; /* 0x48 */
+ unsigned int deepsleep; /* 0x4C */
+ unsigned int dft_enable; /* 0x50 */
+ unsigned int debounce[8]; /* 0x54 */
+ unsigned int vtpiocr; /* 0x74 */
+ unsigned int pupdctl0; /* 0x78 */
+ unsigned int pupdctl1; /* 0x7C */
+ unsigned int hdimcopbt; /* 0x80 */
+ unsigned int pll0_config; /* 0x84 */
+ unsigned int pll1_config; /* 0x88 */
+};
+
+#define VPTIO_RDY (1 << 15)
+#define VPTIO_IOPWRDN (1 << 14)
+#define VPTIO_CLRZ (1 << 13)
+#define VPTIO_LOCK (1 << 7)
+#define VPTIO_PWRDN (1 << 6)
+
+#define VPSS_CLK_CTL_VPSS_CLKMD (1 << 7)
+
+#define dv_sys_module_regs \
+ ((struct dv_sys_module_regs *)DAVINCI_SYSTEM_MODULE_BASE)
+
+#endif /* !CONFIG_SOC_DA8XX */
+#endif /* _DV_SYSCFG_DEFS_H_ */
--- /dev/null
+/*
+ * Copyright (C) 2011 DENX Software Engineering GmbH
+ * Heiko Schocher <hs@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _TIMER_DEFS_H_
+#define _TIMER_DEFS_H_
+
+struct davinci_timer {
+ u_int32_t pid12;
+ u_int32_t emumgt;
+ u_int32_t na1;
+ u_int32_t na2;
+ u_int32_t tim12;
+ u_int32_t tim34;
+ u_int32_t prd12;
+ u_int32_t prd34;
+ u_int32_t tcr;
+ u_int32_t tgcr;
+ u_int32_t wdtcr;
+};
+
+#define DV_TIMER_TCR_ENAMODE_MASK 3
+
+#define DV_TIMER_TCR_ENAMODE12_SHIFT 6
+#define DV_TIMER_TCR_CLKSRC12_SHIFT 8
+#define DV_TIMER_TCR_READRSTMODE12_SHIFT 10
+#define DV_TIMER_TCR_CAPMODE12_SHIFT 11
+#define DV_TIMER_TCR_CAPVTMODE12_SHIFT 12
+#define DV_TIMER_TCR_ENAMODE34_SHIFT 22
+#define DV_TIMER_TCR_CLKSRC34_SHIFT 24
+#define DV_TIMER_TCR_READRSTMODE34_SHIFT 26
+#define DV_TIMER_TCR_CAPMODE34_SHIFT 27
+#define DV_TIMER_TCR_CAPEVTMODE12_SHIFT 28
+
+#define DV_WDT_ENABLE_SYS_RESET 0x00020000
+#define DV_WDT_TRIGGER_SYS_RESET 0x00020002
+
+#ifdef CONFIG_HW_WATCHDOG
+void davinci_hw_watchdog_enable(void);
+void davinci_hw_watchdog_reset(void);
+#endif
+#endif /* _TIMER_DEFS_H_ */
projects / u-boot / commitdiff