ARM: pantheon: add mmc definition

Signed-off-by: Lei Wen <leiwen@marvell.com>

diff --git a/arch/arm/cpu/arm926ejs/pantheon/cpu.c b/arch/arm/cpu/arm926ejs/pantheon/cpu.c
index efc9395b9604fc799581ec39049fc0051c009c38..db9b348ad3bf4f3b25589d5864bc49d314daf786 100644 (file)
--- a/arch/arm/cpu/arm926ejs/pantheon/cpu.c
+++ b/arch/arm/cpu/arm926ejs/pantheon/cpu.c
@@ -42,6 +42,9 @@ int arch_cpu_init(void)
        struct panthmpmu_registers *mpmu =
                (struct panthmpmu_registers*) PANTHEON_MPMU_BASE;
 
+       struct panthapmu_registers *apmu =
+               (struct panthapmu_registers *) PANTHEON_APMU_BASE;
+
        /* set SEL_MRVL_ID bit in PANTHEON_CPU_CONF register */
        val = readl(&cpuregs->cpu_conf);
        val = val | SET_MRVL_ID;
@@ -65,6 +68,14 @@ int arch_cpu_init(void)
        writel(APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi);
 #endif
 
+#ifdef CONFIG_MV_SDHCI
+       /* Enable mmc clock */
+       writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST,
+                       &apmu->sd1);
+       writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST,
+                       &apmu->sd3);
+#endif
+
        icache_enable();
 
        return 0;

diff --git a/arch/arm/include/asm/arch-pantheon/config.h b/arch/arm/include/asm/arch-pantheon/config.h
index fd23c97b37172dae994737def88d9a7a07796c35..d10583dec48c03091558d9f4a6b528995340fc8d 100644 (file)
--- a/arch/arm/include/asm/arch-pantheon/config.h
+++ b/arch/arm/include/asm/arch-pantheon/config.h
@@ -47,4 +47,22 @@
 #define CONFIG_SYS_I2C_SLAVE           0xfe
 #endif
 
+/*
+ * MMC definition
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_CMD_FAT                 1
+#define CONFIG_MMC                     1
+#define CONFIG_GENERIC_MMC             1
+#define CONFIG_SDHCI                   1
+#define CONFIG_MMC_SDHCI_IO_ACCESSORS  1
+#define CONFIG_SYS_MMC_MAX_BLK_COUNT   0x1000
+#define CONFIG_MMC_SDMA                        1
+#define CONFIG_MV_SDHCI                        1
+#define CONFIG_DOS_PARTITION           1
+#define CONFIG_EFI_PARTITION           1
+#define CONFIG_SYS_MMC_NUM             2
+#define CONFIG_SYS_MMC_BASE            {0xD4280000, 0xd4281000}
+#endif
+
 #endif /* _PANTHEON_CONFIG_H */

diff --git a/arch/arm/include/asm/arch-pantheon/cpu.h b/arch/arm/include/asm/arch-pantheon/cpu.h
index 60955c5a55eae50e70b7e885a2c61fd65f90d1e7..94e837133e91ba08a73065bc98d7347a5323e82a 100644 (file)
--- a/arch/arm/include/asm/arch-pantheon/cpu.h
+++ b/arch/arm/include/asm/arch-pantheon/cpu.h
@@ -42,6 +42,17 @@ struct panthmpmu_registers {
        u32 acgr;       /*0x1024*/
 };
 
+/*
+ * Application Power Management (APMU) Registers
+ * Refer Register Datasheet 9.2
+ */
+struct panthapmu_registers {
+       u8 pad0[0x0054];
+       u32 sd1;        /*0x0054*/
+       u8 pad1[0x00e0 - 0x054 - 4];
+       u32 sd3;        /*0x00e0*/
+};
+
 /*
  * APB Clock Reset/Control Registers
  * Refer Register Datasheet 6.14
@@ -77,5 +88,6 @@ struct panthcpu_registers {
  */
 u32 panth_sdram_base(int);
 u32 panth_sdram_size(int);
+int mv_sdh_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks);
 
 #endif /* _PANTHEON_CPU_H */

diff --git a/arch/arm/include/asm/arch-pantheon/mfp.h b/arch/arm/include/asm/arch-pantheon/mfp.h
index e9391961b17cb64a3a10becf9b8fcad50a8e9212..b868ab8f6597a79e5246ff174f4ec769cd21a350 100644 (file)
--- a/arch/arm/include/asm/arch-pantheon/mfp.h
+++ b/arch/arm/include/asm/arch-pantheon/mfp.h
@@ -38,6 +38,18 @@
 #define MFP54_CI2C_SDA         (MFP_REG(0x1b4) | MFP_AF2 | MFP_DRIVE_MEDIUM)
 
 /* More macros can be defined here... */
+#define MFP_MMC1_DAT7          (MFP_REG(0x84) | MFP_AF0 | MFP_DRIVE_MEDIUM)
+#define MFP_MMC1_DAT6          (MFP_REG(0x88) | MFP_AF0 | MFP_DRIVE_MEDIUM)
+#define MFP_MMC1_DAT5          (MFP_REG(0x8c) | MFP_AF0 | MFP_DRIVE_MEDIUM)
+#define MFP_MMC1_DAT4          (MFP_REG(0x90) | MFP_AF0 | MFP_DRIVE_MEDIUM)
+#define MFP_MMC1_DAT3          (MFP_REG(0x94) | MFP_AF0 | MFP_DRIVE_FAST)
+#define MFP_MMC1_DAT2          (MFP_REG(0x98) | MFP_AF0 | MFP_DRIVE_FAST)
+#define MFP_MMC1_DAT1          (MFP_REG(0x9c) | MFP_AF0 | MFP_DRIVE_FAST)
+#define MFP_MMC1_DAT0          (MFP_REG(0xa0) | MFP_AF0 | MFP_DRIVE_FAST)
+#define MFP_MMC1_CMD           (MFP_REG(0xa4) | MFP_AF0 | MFP_DRIVE_FAST)
+#define MFP_MMC1_CLK           (MFP_REG(0xa8) | MFP_AF0 | MFP_DRIVE_FAST)
+#define MFP_MMC1_CD            (MFP_REG(0xac) | MFP_AF0 | MFP_DRIVE_MEDIUM)
+#define MFP_MMC1_WP            (MFP_REG(0xb0) | MFP_AF0 | MFP_DRIVE_MEDIUM)
 
 #define MFP_PIN_MAX    117
 #endif

diff --git a/arch/arm/include/asm/arch-pantheon/pantheon.h b/arch/arm/include/asm/arch-pantheon/pantheon.h
index c7fe646128ec1b8a41137c7f1d0fd8382aa27649..d5e9ba048e43f33a92c3fe5c0cc962a63782c11e 100644 (file)
--- a/arch/arm/include/asm/arch-pantheon/pantheon.h
+++ b/arch/arm/include/asm/arch-pantheon/pantheon.h
@@ -32,6 +32,12 @@
 /* Functional Clock Selection Mask */
 #define APBC_FNCLKSEL(x)        (((x) & 0xf) << 4)
 
+/* Common APMU register bit definitions */
+#define APMU_PERI_CLK  (1<<4)  /* Peripheral Clock Enable */
+#define APMU_AXI_CLK   (1<<3)  /* AXI Clock Enable*/
+#define APMU_PERI_RST  (1<<1)  /* Peripheral Reset */
+#define APMU_AXI_RST   (1<<0)  /* AXI Reset */
+
 /* Register Base Addresses */
 #define PANTHEON_DRAM_BASE     0xB0000000
 #define PANTHEON_TIMER_BASE    0xD4014000
@@ -42,6 +48,7 @@
 #define PANTHEON_GPIO_BASE     0xD4019000
 #define PANTHEON_MFPR_BASE     0xD401E000
 #define PANTHEON_MPMU_BASE     0xD4050000
+#define PANTHEON_APMU_BASE     0xD4282800
 #define PANTHEON_CPU_BASE      0xD4282C00
 
 #endif /* _PANTHEON_H */