mtspr DBCR0,r0
#endif
+/* L1 DCache is used for initial RAM */
+
+ /* Allocate Initial RAM in data cache.
+ */
+ lis r3,CFG_INIT_RAM_ADDR@h
+ ori r3,r3,CFG_INIT_RAM_ADDR@l
+ li r2,512 /* 512*32=16K */
+ mtctr r2
+ li r0,0
+1:
+ dcbz r0,r3
+ dcbtls 0,r0,r3
+ addi r3,r3,32
+ bdnz 1b
+
/* Jump out the last 4K page and continue to 'normal' start */
+#ifdef CFG_RAMBOOT
bl 3f
b _start_cont
+#else
+ /* Calculate absolute address in FLASH and jump there */
+ /*--------------------------------------------------------------*/
+ lis r3,CFG_MONITOR_BASE@h
+ ori r3,r3,CFG_MONITOR_BASE@l
+ addi r3,r3,_start_cont - _start + _START_OFFSET
+ mtlr r3
+#endif
3: li r0,0
mtspr SRR1,r0 /* Keep things disabled for now */
rfi
isync
-
.text
.globl _start
_start:
.align 4
.globl _start_cont
_start_cont:
-
-/* L1 DCache is used for initial RAM */
-
- /* Allocate Initial RAM in data cache.
- */
- lis r3,CFG_INIT_RAM_ADDR@h
- ori r3,r3,CFG_INIT_RAM_ADDR@l
- li r2,512 /* 512*32=16K */
- mtctr r2
- li r0,0
-1:
- dcbz r0,r3
- dcbtls 0,r0,r3
- addi r3,r3,32
- bdnz 1b
-
-#ifndef CFG_RAMBOOT
- /* Calculate absolute address in FLASH and jump there */
- /*--------------------------------------------------------------*/
- lis r3,CFG_MONITOR_BASE@h
- ori r3,r3,CFG_MONITOR_BASE@l
- addi r3,r3,in_flash - _start + _START_OFFSET
- mtlr r3
- blr
- .global in_flash
-in_flash:
-#endif /* CFG_RAMBOOT */
-
/* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
lis r1,CFG_INIT_RAM_ADDR@h
ori r1,r1,CFG_INIT_SP_OFFSET@l