Initial mpc8610hpcd board files.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Mahesh Jade <mahesh.jade@freescale.com>
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>

diff --git a/board/freescale/mpc8610hpcd/Makefile b/board/freescale/mpc8610hpcd/Makefile
new file mode 100644 (file)
index 0000000..6f5a5c1
--- /dev/null
+++ b/board/freescale/mpc8610hpcd/Makefile
@@ -0,0 +1,57 @@
+# Copyright 2007 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
+LIB    = $(obj)lib$(BOARD).a
+
+COBJS  := $(BOARD).o \
+       ../common/sys_eeprom.o \
+       ../common/pixis.o
+
+SOBJS  := init.o
+
+SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS))
+SOBJS  := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):        $(obj).depend $(OBJS) $(SOBJS)
+       $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+       rm -f $(OBJS) $(SOBJS)
+
+.PHONY: distclean
+distclean:     clean
+       rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

diff --git a/board/freescale/mpc8610hpcd/config.mk b/board/freescale/mpc8610hpcd/config.mk
new file mode 100644 (file)
index 0000000..64ac4dc
--- /dev/null
+++ b/board/freescale/mpc8610hpcd/config.mk
@@ -0,0 +1,25 @@
+# Copyright 2007 Freescale Semiconductor.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0xfff00000
+
+PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8610=1 -maltivec -mabi=altivec -msoft-float -O2

diff --git a/board/freescale/mpc8610hpcd/init.S b/board/freescale/mpc8610hpcd/init.S
new file mode 100644 (file)
index 0000000..68797a8
--- /dev/null
+++ b/board/freescale/mpc8610hpcd/init.S
@@ -0,0 +1,147 @@
+/*
+ * Copyright 2007 Freescale Semiconductor.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc86xx.h>
+
+#define LAWAR_TRGT_PCI1                0x00000000
+#define LAWAR_TRGT_PCIE1       0x00200000
+#define LAWAR_TRGT_PCIE2       0x00100000
+#define LAWAR_TRGT_LBC         0x00400000
+#define LAWAR_TRGT_DDR         0x00f00000
+
+#if !defined(CONFIG_SPD_EEPROM)
+#define LAWBAR1 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff)
+#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M))
+#else
+#define LAWBAR1 0
+#define LAWAR1 ((LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN)
+#endif
+
+#define LAWBAR2 ((CFG_PCIE1_MEM_BASE>>12) & 0xffffff)
+#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+#define LAWBAR3 ((CFG_PCIE2_MEM_BASE>>12) & 0xffffff)
+#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+#define LAWBAR4 ((PIXIS_BASE>>12) & 0xffffff)
+#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_2M))
+
+#define LAWBAR5 ((CFG_PCIE1_IO_PHYS>>12) & 0xffffff)
+#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_1M))
+
+#define LAWBAR6 ((CFG_PCIE2_IO_PHYS>>12) & 0xffffff)
+#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_1M))
+
+#define LAWBAR7 ((CFG_FLASH_BASE >>12) & 0xffffff)
+#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+#define LAWBAR8 ((CFG_PCI1_MEM_PHYS>>12) & 0xffffff)
+#define LAWAR8 (LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+#define LAWBAR9 ((CFG_PCI1_IO_PHYS>>12) & 0xffffff)
+#define LAWAR9 (LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M))
+
+
+       .section .bootpg, "ax"
+       .globl  law_entry
+law_entry:
+       lis     r7,CFG_CCSRBAR@h
+       ori     r7,r7,CFG_CCSRBAR@l
+
+       addi    r4,r7,0
+       addi    r5,r7,0
+
+       /* Skip LAWAR0, start at LAWAR1 */
+       lis     r6,LAWBAR1@h
+       ori     r6,r6,LAWBAR1@l
+       stwu    r6, 0xc28(r4)
+
+       lis     r6,LAWAR1@h
+       ori     r6,r6,LAWAR1@l
+       stwu    r6, 0xc30(r5)
+
+       /* LAWBAR2, LAWAR2 */
+       lis     r6,LAWBAR2@h
+       ori     r6,r6,LAWBAR2@l
+       stwu    r6, 0x20(r4)
+
+       lis     r6,LAWAR2@h
+       ori     r6,r6,LAWAR2@l
+       stwu    r6, 0x20(r5)
+
+       /* LAWBAR3, LAWAR3 */
+       lis     r6,LAWBAR3@h
+       ori     r6,r6,LAWBAR3@l
+       stwu    r6, 0x20(r4)
+
+       lis     r6,LAWAR3@h
+       ori     r6,r6,LAWAR3@l
+       stwu    r6, 0x20(r5)
+
+       /* LAWBAR4, LAWAR4 */
+       lis     r6,LAWBAR4@h
+       ori     r6,r6,LAWBAR4@l
+       stwu    r6, 0x20(r4)
+
+       lis     r6,LAWAR4@h
+       ori     r6,r6,LAWAR4@l
+       stwu    r6, 0x20(r5)
+       /* LAWBAR5, LAWAR5 */
+       lis     r6,LAWBAR5@h
+       ori     r6,r6,LAWBAR5@l
+       stwu    r6, 0x20(r4)
+
+       lis     r6,LAWAR5@h
+       ori     r6,r6,LAWAR5@l
+       stwu    r6, 0x20(r5)
+
+       /* LAWBAR6, LAWAR6 */
+       lis     r6,LAWBAR6@h
+       ori     r6,r6,LAWBAR6@l
+       stwu    r6, 0x20(r4)
+
+       lis     r6,LAWAR6@h
+       ori     r6,r6,LAWAR6@l
+       stwu    r6, 0x20(r5)
+
+       /* LAWBAR7, LAWAR7 */
+       lis     r6,LAWBAR7@h
+       ori     r6,r6,LAWBAR7@l
+       stwu    r6, 0x20(r4)
+
+       lis     r6,LAWAR7@h
+       ori     r6,r6,LAWAR7@l
+       stwu    r6, 0x20(r5)
+
+       /* LAWBAR8, LAWAR8 */
+       lis     r6,LAWBAR8@h
+       ori     r6,r6,LAWBAR8@l
+       stwu    r6, 0x20(r4)
+
+       lis     r6,LAWAR8@h
+       ori     r6,r6,LAWAR8@l
+       stwu    r6, 0x20(r5)
+
+       /* LAWBAR9, LAWAR9 */
+       lis     r6,LAWBAR9@h
+       ori     r6,r6,LAWBAR9@l
+       stwu    r6, 0x20(r4)
+
+       lis     r6,LAWAR9@h
+       ori     r6,r6,LAWAR9@l
+       stwu    r6, 0x20(r5)
+
+       blr

diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
new file mode 100644 (file)
index 0000000..63790ca
--- /dev/null
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
@@ -0,0 +1,507 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#define DEBUG
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/immap_86xx.h>
+#include <asm/immap_fsl_pci.h>
+#include <spd.h>
+#include <asm/io.h>
+
+
+#if defined(CONFIG_OF_FLAT_TREE)
+#include <ft_build.h>
+extern void ft_cpu_setup(void *blob, bd_t *bd);
+#endif
+
+#include "../common/pixis.h"
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+extern void ddr_enable_ecc(unsigned int dram_size);
+#endif
+
+#if defined(CONFIG_SPD_EEPROM)
+#include "spd_sdram.h"
+#endif
+
+void sdram_init(void);
+long int fixed_sdram(void);
+
+/* called before any console output */
+int board_early_init_f(void)
+{
+       volatile immap_t *immap = (immap_t *)CFG_IMMR;
+       volatile ccsr_gur_t *gur = &immap->im_gur;
+
+       gur->gpiocr |= 0x888a5500; /* DIU16, IR1, UART0, UART2 */
+
+       return 0;
+}
+
+int checkboard(void)
+{
+       volatile immap_t *immap = (immap_t *)CFG_IMMR;
+       volatile ccsr_lbc_t *memctl = &immap->im_lbc;
+       volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
+
+       puts("Board: MPC8610HPCD\n");
+
+       mcm->abcr |= 0x00010000; /* 0 */
+       mcm->hpmr3 = 0x80000008; /* 4c */
+       mcm->hpmr0 = 0;
+       mcm->hpmr1 = 0;
+       mcm->hpmr2 = 0;
+       mcm->hpmr4 = 0;
+       mcm->hpmr5 = 0;
+
+       return 0;
+}
+
+
+long int
+initdram(int board_type)
+{
+       long dram_size = 0;
+
+#if defined(CONFIG_SPD_EEPROM)
+       dram_size = spd_sdram();
+#else
+       dram_size = fixed_sdram();
+#endif
+
+#if defined(CFG_RAMBOOT)
+       puts(" DDR: ");
+       return dram_size;
+#endif
+
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+       /*
+        * Initialize and enable DDR ECC.
+        */
+       ddr_enable_ecc(dram_size);
+#endif
+
+       puts(" DDR: ");
+       return dram_size;
+}
+
+
+#if defined(CFG_DRAM_TEST)
+int
+testdram(void)
+{
+       uint *pstart = (uint *) CFG_MEMTEST_START;
+       uint *pend = (uint *) CFG_MEMTEST_END;
+       uint *p;
+
+       puts("SDRAM test phase 1:\n");
+       for (p = pstart; p < pend; p++)
+               *p = 0xaaaaaaaa;
+
+       for (p = pstart; p < pend; p++) {
+               if (*p != 0xaaaaaaaa) {
+                       printf("SDRAM test fails at: %08x\n", (uint) p);
+                       return 1;
+               }
+       }
+
+       puts("SDRAM test phase 2:\n");
+       for (p = pstart; p < pend; p++)
+               *p = 0x55555555;
+
+       for (p = pstart; p < pend; p++) {
+               if (*p != 0x55555555) {
+                       printf("SDRAM test fails at: %08x\n", (uint) p);
+                       return 1;
+               }
+       }
+
+       puts("SDRAM test passed.\n");
+       return 0;
+}
+#endif
+
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+
+long int fixed_sdram(void)
+{
+#if !defined(CFG_RAMBOOT)
+       volatile immap_t *immap = (immap_t *)CFG_IMMR;
+       volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
+       uint d_init;
+
+       ddr->cs0_bnds = 0x0000001f;
+       ddr->cs0_config = 0x80010202;
+
+       ddr->ext_refrec = 0x00000000;
+       ddr->timing_cfg_0 = 0x00260802;
+       ddr->timing_cfg_1 = 0x3935d322;
+       ddr->timing_cfg_2 = 0x14904cc8;
+       ddr->sdram_mode_1 = 0x00480432;
+       ddr->sdram_mode_2 = 0x00000000;
+       ddr->sdram_interval = 0x06180fff; /* 0x06180100; */
+       ddr->sdram_data_init = 0xDEADBEEF;
+       ddr->sdram_clk_cntl = 0x03800000;
+       ddr->sdram_cfg_2 = 0x04400010;
+
+#if defined(CONFIG_DDR_ECC)
+       ddr->err_int_en = 0x0000000d;
+       ddr->err_disable = 0x00000000;
+       ddr->err_sbe = 0x00010000;
+#endif
+       asm("sync;isync");
+
+       udelay(500);
+
+       ddr->sdram_cfg_1 = 0xc3000000; /* 0xe3008000;*/
+
+
+#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+       d_init = 1;
+       debug("DDR - 1st controller: memory initializing\n");
+       /*
+        * Poll until memory is initialized.
+        * 512 Meg at 400 might hit this 200 times or so.
+        */
+       while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
+               udelay(1000);
+
+       debug("DDR: memory initialized\n\n");
+       asm("sync; isync");
+       udelay(500);
+#endif
+
+       return 512 * 1024 * 1024;
+#endif
+       return CFG_SDRAM_SIZE * 1024 * 1024;
+}
+
+#endif
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_fsl86xxads_config_table[] = {
+       {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+        PCI_IDSEL_NUMBER, PCI_ANY_ID,
+        pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
+                                PCI_ENET0_MEMADDR,
+                                PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} },
+       {}
+};
+#endif
+
+
+static struct pci_controller pci1_hose = {
+#ifndef CONFIG_PCI_PNP
+config_table:pci_mpc86xxcts_config_table
+#endif
+};
+#endif /* CONFIG_PCI */
+
+#ifdef CONFIG_PCIE1
+static struct pci_controller pcie1_hose;
+#endif
+
+#ifdef CONFIG_PCIE2
+static struct pci_controller pcie2_hose;
+#endif
+
+int first_free_busno = 0;
+
+void pci_init_board(void)
+{
+       volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
+       volatile ccsr_gur_t *gur = &immap->im_gur;
+       uint devdisr = gur->devdisr;
+       uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+       uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
+
+       printf( " pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
+               devdisr, io_sel, host_agent);
+
+
+#ifdef CONFIG_PCIE1
+ {
+       volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
+       extern void fsl_pci_init(struct pci_controller *hose);
+       struct pci_controller *hose = &pcie1_hose;
+       int pcie_configured = (io_sel == 1) || (io_sel == 4);
+       int pcie_ep = (host_agent == 0) || (host_agent == 2) ||
+               (host_agent == 5);
+
+       if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)) {
+               printf(" PCIe 1 connected to Uli as %s (base address %x)\n",
+                       pcie_ep ? "End Point" : "Root Complex",
+                       (uint)pci);
+               if (pci->pme_msg_det)
+                       pci->pme_msg_det = 0xffffffff;
+
+               /* inbound */
+               pci_set_region(hose->regions + 0,
+                        CFG_PCI_MEMORY_BUS,
+                        CFG_PCI_MEMORY_PHYS,
+                        CFG_PCI_MEMORY_SIZE,
+                        PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+               /* outbound memory */
+               pci_set_region(hose->regions + 1,
+                        CFG_PCIE1_MEM_BASE,
+                        CFG_PCIE1_MEM_PHYS,
+                        CFG_PCIE1_MEM_SIZE,
+                        PCI_REGION_MEM);
+
+               /* outbound io */
+               pci_set_region(hose->regions + 2,
+                        CFG_PCIE1_IO_BASE,
+                        CFG_PCIE1_IO_PHYS,
+                        CFG_PCIE1_IO_SIZE,
+                        PCI_REGION_IO);
+
+               hose->region_count = 3;
+
+               hose->first_busno = first_free_busno;
+               pci_setup_indirect(hose, (int)&pci->cfg_addr,
+                                (int)&pci->cfg_data);
+
+               fsl_pci_init(hose);
+
+               first_free_busno = hose->last_busno + 1;
+               printf(" PCI-Express 1 on bus %02x - %02x\n",
+                       hose->first_busno, hose->last_busno);
+
+       } else
+               puts(" PCI-Express 1: Disabled\n");
+ }
+#else
+       puts("PCI-Express 1: Disabled\n");
+#endif /* CONFIG_PCIE1 */
+
+
+#ifdef CONFIG_PCIE2
+ {
+       volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR;
+       extern void fsl_pci_init(struct pci_controller *hose);
+       struct pci_controller *hose = &pcie2_hose;
+
+       int pcie_configured = (io_sel == 0) || (io_sel == 4);
+       int pcie_ep = (host_agent == 0) || (host_agent == 1) ||
+               (host_agent == 4);
+
+       if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)) {
+               printf(" PCI-Express 2 connected to slot as %s" \
+                       " (base address %x)\n",
+                       pcie_ep ? "End Point" : "Root Complex",
+                       (uint)pci);
+               if (pci->pme_msg_det)
+                       pci->pme_msg_det = 0xffffffff;
+
+               /* inbound */
+               pci_set_region(hose->regions + 0,
+                        CFG_PCI_MEMORY_BUS,
+                        CFG_PCI_MEMORY_PHYS,
+                        CFG_PCI_MEMORY_SIZE,
+                        PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+               /* outbound memory */
+               pci_set_region(hose->regions + 1,
+                        CFG_PCIE2_MEM_BASE,
+                        CFG_PCIE2_MEM_PHYS,
+                        CFG_PCIE2_MEM_SIZE,
+                        PCI_REGION_MEM);
+
+               /* outbound io */
+               pci_set_region(hose->regions + 2,
+                        CFG_PCIE2_IO_BASE,
+                        CFG_PCIE2_IO_PHYS,
+                        CFG_PCIE2_IO_SIZE,
+                        PCI_REGION_IO);
+
+               hose->region_count = 3;
+
+               hose->first_busno = first_free_busno;
+               pci_setup_indirect(hose, (int)&pci->cfg_addr,
+                                (int)&pci->cfg_data);
+
+               fsl_pci_init(hose);
+
+               first_free_busno = hose->last_busno + 1;
+               printf(" PCI-Express 2 on bus %02x - %02x\n",
+                       hose->first_busno, hose->last_busno);
+       } else
+               puts(" PCI-Express 2: Disabled\n");
+ }
+#else
+       puts("PCI-Express 2: Disabled\n");
+#endif /* CONFIG_PCIE2 */
+
+
+#ifdef CONFIG_PCI1
+ {
+       volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
+       extern void fsl_pci_init(struct pci_controller *hose);
+       struct pci_controller *hose = &pci1_hose;
+       int pci_agent = (host_agent >= 4) && (host_agent <= 6);
+
+       if ( !(devdisr & MPC86xx_DEVDISR_PCI1)) {
+               printf(" PCI connected to PCI slots as %s" \
+                       " (base address %x)\n",
+                       pci_agent ? "Agent" : "Host",
+                       (uint)pci);
+
+               /* inbound */
+               pci_set_region(hose->regions + 0,
+                        CFG_PCI_MEMORY_BUS,
+                        CFG_PCI_MEMORY_PHYS,
+                        CFG_PCI_MEMORY_SIZE,
+                        PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+               /* outbound memory */
+               pci_set_region(hose->regions + 1,
+                        CFG_PCI1_MEM_BASE,
+                        CFG_PCI1_MEM_PHYS,
+                        CFG_PCI1_MEM_SIZE,
+                        PCI_REGION_MEM);
+
+               /* outbound io */
+               pci_set_region(hose->regions + 2,
+                        CFG_PCI1_IO_BASE,
+                        CFG_PCI1_IO_PHYS,
+                        CFG_PCI1_IO_SIZE,
+                        PCI_REGION_IO);
+
+               hose->region_count = 3;
+
+               hose->first_busno = first_free_busno;
+               pci_setup_indirect(hose, (int) &pci->cfg_addr,
+                                (int) &pci->cfg_data);
+
+               fsl_pci_init(hose);
+
+               first_free_busno = hose->last_busno + 1;
+               printf(" PCI on bus %02x - %02x\n",
+                       hose->first_busno, hose->last_busno);
+
+
+       } else
+               puts(" PCI: Disabled\n");
+ }
+#endif /* CONFIG_PCI1 */
+}
+
+#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_board_setup(void *blob, bd_t *bd)
+{
+       u32 *p;
+       int len;
+
+       ft_cpu_setup(blob, bd);
+
+       p = ft_get_prop(blob, "/memory/reg", &len);
+       if (p != NULL) {
+               *p++ = cpu_to_be32(bd->bi_memstart);
+               *p = cpu_to_be32(bd->bi_memsize);
+       }
+
+#ifdef CONFIG_PCI1
+       p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len);
+       if (p != NULL) {
+               p[0] = 0;
+               p[1] = pci1_hose.last_busno - pci1_hose.first_busno;
+               debug("pci@8000 first_busno=%d last_busno=%d\n",p[0],p[1]);
+       }
+#endif
+#ifdef CONFIG_PCIE1
+       p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@a000/bus-range", &len);
+       if (p != NULL) {
+               p[0] = 0;
+               p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
+               debug("pcie@9000 first_busno=%d last_busno=%d\n",p[0],p[1]);
+       }
+#endif
+#ifdef CONFIG_PCIE2
+       p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pcie@9000/bus-range", &len);
+       if (p != NULL) {
+               p[0] = 0;
+               p[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
+               debug("pcie@9000 first_busno=%d last_busno=%d\n",p[0],p[1]);
+       }
+#endif
+
+}
+#endif
+
+/*
+ * get_board_sys_clk
+ * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
+ */
+
+unsigned long
+get_board_sys_clk(ulong dummy)
+{
+       u8 i, go_bit, rd_clks;
+       ulong val = 0;
+       ulong a;
+
+       a = PIXIS_BASE + PIXIS_SPD;
+       i = in8(a);
+       i &= 0x07;
+
+       switch (i) {
+       case 0:
+               val = 33333000;
+               break;
+       case 1:
+               val = 39999600;
+               break;
+       case 2:
+               val = 49999500;
+               break;
+       case 3:
+               val = 66666000;
+               break;
+       case 4:
+               val = 83332500;
+               break;
+       case 5:
+               val = 99999000;
+               break;
+       case 6:
+               val = 133332000;
+               break;
+       case 7:
+               val = 166665000;
+               break;
+       }
+
+       return val;
+}

diff --git a/board/freescale/mpc8610hpcd/u-boot.lds b/board/freescale/mpc8610hpcd/u-boot.lds
new file mode 100644 (file)
index 0000000..ae9c6c4
--- /dev/null
+++ b/board/freescale/mpc8610hpcd/u-boot.lds
@@ -0,0 +1,135 @@
+/*
+ * Copyright 2007 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+
+SECTIONS
+{
+
+  /* Read-only sections, merged into text segment: */
+  .interp : { *(.interp) }
+  .hash                 : { *(.hash)           }
+  .dynsym       : { *(.dynsym)         }
+  .dynstr       : { *(.dynstr)         }
+  .rel.text     : { *(.rel.text)       }
+  .rela.text    : { *(.rela.text)      }
+  .rel.data     : { *(.rel.data)       }
+  .rela.data    : { *(.rela.data)      }
+  .rel.rodata   : { *(.rel.rodata)     }
+  .rela.rodata  : { *(.rela.rodata)    }
+  .rel.got      : { *(.rel.got)        }
+  .rela.got     : { *(.rela.got)       }
+  .rel.ctors    : { *(.rel.ctors)      }
+  .rela.ctors   : { *(.rela.ctors)     }
+  .rel.dtors    : { *(.rel.dtors)      }
+  .rela.dtors   : { *(.rela.dtors)     }
+  .rel.bss      : { *(.rel.bss)        }
+  .rela.bss     : { *(.rela.bss)       }
+  .rel.plt      : { *(.rel.plt)        }
+  .rela.plt     : { *(.rela.plt)       }
+  .init                 : { *(.init)   }
+  .plt : { *(.plt) }
+  .text :
+  {
+    cpu/mpc86xx/start.o        (.text)
+    board/freescale/mpc8610hpcd/init.o (.bootpg)
+    cpu/mpc86xx/traps.o (.text)
+    cpu/mpc86xx/interrupts.o (.text)
+    cpu/mpc86xx/cpu_init.o (.text)
+    cpu/mpc86xx/cpu.o (.text)
+    cpu/mpc86xx/speed.o (.text)
+    common/dlmalloc.o (.text)
+    lib_generic/crc32.o (.text)
+    lib_ppc/extable.o (.text)
+    lib_generic/zlib.o (.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+   }
+    _etext = .;
+    PROVIDE (etext = .);
+    .rodata    :
+   {
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+    *(.eh_frame)
+  }
+  .fini             : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data           :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss      :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}