fsl-ddr: setup ODT_RD_CFG & ODT_WR_CFG when we interleave

In chip-select interleaving case, we also need set the ODT_RD_CFG
and ODT_WR_CFG in cs1_config register.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c
index 3be7e227108c860042376684301859508162d373..adc4f6ee37ada73ed46d87ee33e085358b372e60 100644 (file)
--- a/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -1197,7 +1197,10 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
                        /* Don't set up boundaries for other CS
                         * other than CS0, if bank interleaving
                         * is enabled and not CS2+CS3 interleaved.
+                        * But we need to set the ODT_RD_CFG and
+                        * ODT_WR_CFG for CS1_CONFIG here.
                         */
+                       set_csn_config(i, ddr, popts, dimm_params);
                        break;
                }