- rpm2cpio
- wget
- device-tree-compiler
+ - lzop
install:
# Clone uboot-test-hooks
depends on !NIOS2 && !XTENSA
depends on !EFI_APP
default 0x80800000 if ARCH_OMAP2PLUS
+ default 0x4a000000 if ARCH_SUNXI && !MACH_SUN9I && !MACH_SUN8I_V3S
+ default 0x2a000000 if ARCH_SUNXI && MACH_SUN9I
+ default 0x42e00000 if ARCH_SUNXI && MACH_SUN8I_V3S
hex "Text Base"
help
The address in memory that U-Boot will be running from, initially.
ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom
endif
+# Build a combined spl + u-boot image for sunxi
+ifeq ($(CONFIG_ARCH_SUNXI)$(CONFIG_SPL),yy)
+ALL-y += u-boot-sunxi-with-spl.bin
+endif
+
# enable combined SPL/u-boot/dtb rules for tegra
ifeq ($(CONFIG_TEGRA)$(CONFIG_SPL),yy)
ALL-y += u-boot-tegra.bin u-boot-nodtb-tegra.bin
endif
ifneq ($(CONFIG_ARCH_SUNXI),)
+ifeq ($(CONFIG_ARM64),)
u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.img u-boot.dtb FORCE
$(call if_changed,binman)
+else
+u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.itb FORCE
+ $(call if_changed,cat)
+endif
endif
ifneq ($(CONFIG_TEGRA),)
be at least 4MB.
- MII/PHY support:
- CONFIG_PHY_ADDR
-
- The address of PHY on MII bus.
-
CONFIG_PHY_CLOCK_FREQ (ppc4xx)
The clock frequency of the MII bus
+++ /dev/null
-# Build a combined spl + u-boot image
-ifdef CONFIG_SPL
-ifndef CONFIG_SPL_BUILD
-ALL-y += u-boot-sunxi-with-spl.bin
-endif
-endif
#include <asm/armv7m_mpu.h>
#include <asm/io.h>
-#define V7M_MPU_CTRL_ENABLE (1 << 0)
+#define V7M_MPU_CTRL_ENABLE BIT(0)
#define V7M_MPU_CTRL_DISABLE (0 << 0)
-#define V7M_MPU_CTRL_HFNMIENA (1 << 1)
-#define VALID_REGION (1 << 4)
+#define V7M_MPU_CTRL_HFNMIENA BIT(1)
+#define V7M_MPU_CTRL_PRIVDEFENA BIT(2)
+#define VALID_REGION BIT(4)
-#define ENABLE_REGION (1 << 0)
+#define ENABLE_REGION BIT(0)
#define AP_SHIFT 24
#define XN_SHIFT 28
void enable_mpu(void)
{
- writel(V7M_MPU_CTRL_ENABLE | V7M_MPU_CTRL_HFNMIENA, &V7M_MPU->ctrl);
+ writel(V7M_MPU_CTRL_ENABLE | V7M_MPU_CTRL_PRIVDEFENA, &V7M_MPU->ctrl);
/* Make sure new mpu config is effective for next memory access */
dsb();
stm32f469-disco.dtb
dtb-$(CONFIG_STM32F7) += stm32f746-disco.dtb \
- stm32f769-disco.dtb
+ stm32f769-disco.dtb \
+ stm32746g-eval.dtb
dtb-$(CONFIG_STM32H7) += stm32h743i-disco.dtb \
stm32h743i-eval.dtb
sun7i-a20-m5.dtb \
sun7i-a20-mk808c.dtb \
sun7i-a20-olimex-som-evb.dtb \
+ sun7i-a20-olimex-som204-evb.dtb \
+ sun7i-a20-olimex-som204-evb-emmc.dtb \
sun7i-a20-olinuxino-lime.dtb \
sun7i-a20-olinuxino-lime2.dtb \
sun7i-a20-olinuxino-lime2-emmc.dtb \
&pcf_hdmi{
u-boot,i2c-offset-len = <0>;
};
+
+&mmc2_pins_default {
+ u-boot,dm-spl;
+};
+
+&mmc2_pins_hs {
+ u-boot,dm-spl;
+};
+
+&mmc2_pins_ddr_rev20 {
+ u-boot,dm-spl;
+};
+
+&mmc2_pins_hs200 {
+ u-boot,dm-spl;
+};
+
+&mmc2_iodelay_hs200_rev20_conf {
+ u-boot,dm-spl;
+};
&cpsw_emac1 {
phy-handle = <&dp83867_1>;
};
+
+&mmc2_pins_default {
+ u-boot,dm-spl;
+};
+
+&mmc2_pins_hs {
+ u-boot,dm-spl;
+};
+
+&mmc2_pins_ddr_rev20 {
+ u-boot,dm-spl;
+};
+
+&mmc2_iodelay_ddr_conf {
+ u-boot,dm-spl;
+};
+
+&mmc2_pins_hs200 {
+ u-boot,dm-spl;
+};
+
+&mmc2_iodelay_hs200_rev20_conf {
+ u-boot,dm-spl;
+};
&cpsw_emac1 {
phy-handle = <&dp83867_1>;
};
+
+&mmc2_pins_default {
+ u-boot,dm-spl;
+};
+
+&mmc2_pins_hs {
+ u-boot,dm-spl;
+};
+
+&mmc2_pins_ddr_rev20 {
+ u-boot,dm-spl;
+};
+
+&mmc2_iodelay_ddr_conf {
+ u-boot,dm-spl;
+};
+
+&mmc2_pins_hs200 {
+ u-boot,dm-spl;
+};
+
+&mmc2_iodelay_hs200_rev20_conf {
+ u-boot,dm-spl;
+};
&cpsw_emac1 {
phy-handle = <&dp83867_1>;
};
+
+&mmc2_pins_default {
+ u-boot,dm-spl;
+};
+
+&mmc2_pins_hs200 {
+ u-boot,dm-spl;
+};
+
+&mmc2_iodelay_hs200_conf {
+ u-boot,dm-spl;
+};
#include "dra76x.dtsi"
#include "dra7-evm-common.dtsi"
+#include "dra76x-mmc-iodelay.dtsi"
#include <dt-bindings/net/ti-dp83867.h>
/ {
};
};
-&dra7_pmx_core {
- mmc1_pins_default: mmc1_pins_default {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
- DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
- DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
- DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
- DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
- DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
- DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
- >;
- };
-
- mmc1_pins_sdr12: pinmux_mmc1_sdr12_pins {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
- DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
- DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
- DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
- DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
- DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
- >;
- };
-
- mmc2_pins_default: mmc2_pins_default {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
- DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
- DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
- DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
- DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
- DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
- DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
- DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
- DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
- DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
- >;
- };
-};
-
&i2c1 {
status = "okay";
clock-frequency = <400000>;
&mmc1 {
status = "okay";
vmmc-supply = <&vio_3v3_sd>;
- vmmc_aux-supply = <&ldo4_reg>;
+ vqmmc-supply = <&ldo4_reg>;
bus-width = <4>;
/*
* SDCD signal is not being used here - using the fact that GPIO mode
* is always hardwired.
*/
cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "hs";
pinctrl-0 = <&mmc1_pins_default>;
+ pinctrl-1 = <&mmc1_pins_hs>;
};
&mmc2 {
status = "okay";
vmmc-supply = <&vio_1v8>;
bus-width = <8>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
pinctrl-0 = <&mmc2_pins_default>;
+ pinctrl-1 = <&mmc2_pins_default>;
+ pinctrl-2 = <&mmc2_pins_default>;
+ pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_conf>;
};
/* No RTC on this device */
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018 Texas Instruments
+// MMC IOdelay values for TI's DRA76x and AM576x SoCs.
+// Author: Sekhar Nori <nsekhar@ti.com>
+
+/*
+ * Rules for modifying this file:
+ * a) Update of this file should typically correspond to a datamanual revision.
+ * Datamanual revision that was used should be updated in comment below.
+ * If there is no update to datamanual, do not update the values. If you
+ * need to use values different from that recommended by the datamanual
+ * for your design, then you should consider adding values to the device-
+ * -tree file for your board directly.
+ * b) We keep the mode names as close to the datamanual as possible. So
+ * if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v,
+ * we follow that in code too.
+ * c) If the values change between multiple revisions of silicon, we add
+ * a revision tag to both the new and old entry. Use 'rev11' for PG 1.1,
+ * 'rev20' for PG 2.0 and so on.
+ * d) The node name and node label should be the exact same string. This is
+ * to curb naming creativity and achieve consistency.
+ *
+ * Datamanual Revisions:
+ *
+ * DRA76x Silicon Revision 1.0: SPRS993A, Revised July 2017
+ *
+ */
+
+&dra7_pmx_core {
+ mmc1_pins_default: mmc1_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc1_pins_hs: mmc1_pins_hs {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc1_pins_sdr50: mmc1_pins_sdr50 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc1_pins_ddr50: mmc1_pins_ddr50 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc2_pins_default: mmc2_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+ >;
+ };
+
+ mmc2_pins_hs200: mmc2_pins_hs200 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+ >;
+ };
+
+ mmc3_pins_default: mmc3_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
+ DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
+ DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
+ DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
+ DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
+ DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
+ >;
+ };
+
+ mmc4_pins_hs: mmc4_pins_hs {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
+ DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
+ DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
+ DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
+ DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
+ DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
+ >;
+ };
+};
+
+&dra7_iodelay_core {
+
+ /* Corresponds to MMC1_DDR_MANUAL1 in datamanual */
+ mmc1_iodelay_ddr_conf: mmc1_iodelay_ddr_conf {
+ pinctrl-pin-array = <
+ 0x618 A_DELAY_PS(489) G_DELAY_PS(0) /* CFG_MMC1_CLK_IN */
+ 0x624 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_IN */
+ 0x630 A_DELAY_PS(374) G_DELAY_PS(0) /* CFG_MMC1_DAT0_IN */
+ 0x63c A_DELAY_PS(31) G_DELAY_PS(0) /* CFG_MMC1_DAT1_IN */
+ 0x648 A_DELAY_PS(56) G_DELAY_PS(0) /* CFG_MMC1_DAT2_IN */
+ 0x654 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_IN */
+ 0x620 A_DELAY_PS(1355) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */
+ 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */
+ 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */
+ 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */
+ 0x638 A_DELAY_PS(0) G_DELAY_PS(4) /* CFG_MMC1_DAT0_OUT */
+ 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */
+ 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */
+ 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */
+ 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */
+ 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */
+ 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */
+ >;
+ };
+
+ /* Corresponds to MMC1_SDR104_MANUAL1 in datamanual */
+ mmc1_iodelay_sdr104_conf: mmc1_iodelay_sdr104_conf {
+ pinctrl-pin-array = <
+ 0x620 A_DELAY_PS(892) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */
+ 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */
+ 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */
+ 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */
+ 0x638 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */
+ 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */
+ 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */
+ 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */
+ 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */
+ 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */
+ 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */
+ >;
+ };
+
+ /* Corresponds to MMC2_HS200_MANUAL1 in datamanual */
+ mmc2_iodelay_hs200_conf: mmc2_iodelay_hs200_conf {
+ pinctrl-pin-array = <
+ 0x190 A_DELAY_PS(384) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */
+ 0x194 A_DELAY_PS(0) G_DELAY_PS(174) /* CFG_GPMC_A19_OUT */
+ 0x1a8 A_DELAY_PS(410) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */
+ 0x1ac A_DELAY_PS(85) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */
+ 0x1b4 A_DELAY_PS(468) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */
+ 0x1b8 A_DELAY_PS(139) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */
+ 0x1c0 A_DELAY_PS(676) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */
+ 0x1c4 A_DELAY_PS(69) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */
+ 0x1d0 A_DELAY_PS(1062) G_DELAY_PS(154) /* CFG_GPMC_A23_OUT */
+ 0x1d8 A_DELAY_PS(640) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */
+ 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */
+ 0x1e4 A_DELAY_PS(356) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */
+ 0x1e8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */
+ 0x1f0 A_DELAY_PS(579) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */
+ 0x1f4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */
+ 0x1fc A_DELAY_PS(435) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */
+ 0x200 A_DELAY_PS(36) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */
+ 0x364 A_DELAY_PS(759) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */
+ 0x368 A_DELAY_PS(72) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */
+ >;
+ };
+
+ /* Corresponds to MMC3_MANUAL1 in datamanual */
+ mmc3_iodelay_manual1_conf: mmc3_iodelay_manual1_conf {
+ pinctrl-pin-array = <
+ 0x678 A_DELAY_PS(0) G_DELAY_PS(386) /* CFG_MMC3_CLK_IN */
+ 0x680 A_DELAY_PS(605) G_DELAY_PS(0) /* CFG_MMC3_CLK_OUT */
+ 0x684 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_IN */
+ 0x688 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OEN */
+ 0x68c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OUT */
+ 0x690 A_DELAY_PS(171) G_DELAY_PS(0) /* CFG_MMC3_DAT0_IN */
+ 0x694 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OEN */
+ 0x698 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OUT */
+ 0x69c A_DELAY_PS(221) G_DELAY_PS(0) /* CFG_MMC3_DAT1_IN */
+ 0x6a0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OEN */
+ 0x6a4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OUT */
+ 0x6a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_IN */
+ 0x6ac A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OEN */
+ 0x6b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OUT */
+ 0x6b4 A_DELAY_PS(474) G_DELAY_PS(0) /* CFG_MMC3_DAT3_IN */
+ 0x6b8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OEN */
+ 0x6bc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OUT */
+ >;
+ };
+
+ /* Corresponds to MMC3_MANUAL2 in datamanual */
+ mmc3_iodelay_sdr50_conf: mmc3_iodelay_sdr50_conf {
+ pinctrl-pin-array = <
+ 0x678 A_DELAY_PS(852) G_DELAY_PS(0) /* CFG_MMC3_CLK_IN */
+ 0x680 A_DELAY_PS(94) G_DELAY_PS(0) /* CFG_MMC3_CLK_OUT */
+ 0x684 A_DELAY_PS(122) G_DELAY_PS(0) /* CFG_MMC3_CMD_IN */
+ 0x688 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OEN */
+ 0x68c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OUT */
+ 0x690 A_DELAY_PS(91) G_DELAY_PS(0) /* CFG_MMC3_DAT0_IN */
+ 0x694 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OEN */
+ 0x698 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OUT */
+ 0x69c A_DELAY_PS(57) G_DELAY_PS(0) /* CFG_MMC3_DAT1_IN */
+ 0x6a0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OEN */
+ 0x6a4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OUT */
+ 0x6a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_IN */
+ 0x6ac A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OEN */
+ 0x6b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OUT */
+ 0x6b4 A_DELAY_PS(375) G_DELAY_PS(0) /* CFG_MMC3_DAT3_IN */
+ 0x6b8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OEN */
+ 0x6bc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OUT */
+ >;
+ };
+
+ /* Corresponds to MMC4_MANUAL1 in datamanual */
+ mmc4_iodelay_manual1_conf: mmc4_iodelay_manual1_conf {
+ pinctrl-pin-array = <
+ 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */
+ 0x848 A_DELAY_PS(1147) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */
+ 0x84c A_DELAY_PS(1834) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */
+ 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */
+ 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */
+ 0x870 A_DELAY_PS(2165) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */
+ 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */
+ 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */
+ 0x87c A_DELAY_PS(1929) G_DELAY_PS(64) /* CFG_UART2_RTSN_IN */
+ 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */
+ 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */
+ 0x888 A_DELAY_PS(1935) G_DELAY_PS(128) /* CFG_UART2_RXD_IN */
+ 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */
+ 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */
+ 0x894 A_DELAY_PS(2172) G_DELAY_PS(44) /* CFG_UART2_TXD_IN */
+ 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */
+ 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */
+ >;
+ };
+
+ /* Corresponds to MMC4_DS_MANUAL1 in datamanual */
+ mmc4_iodelay_default_conf: mmc4_iodelay_default_conf {
+ pinctrl-pin-array = <
+ 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */
+ 0x848 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */
+ 0x84c A_DELAY_PS(307) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */
+ 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */
+ 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */
+ 0x870 A_DELAY_PS(785) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */
+ 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */
+ 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */
+ 0x87c A_DELAY_PS(613) G_DELAY_PS(0) /* CFG_UART2_RTSN_IN */
+ 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */
+ 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */
+ 0x888 A_DELAY_PS(683) G_DELAY_PS(0) /* CFG_UART2_RXD_IN */
+ 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */
+ 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */
+ 0x894 A_DELAY_PS(835) G_DELAY_PS(0) /* CFG_UART2_TXD_IN */
+ 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */
+ 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */
+ >;
+ };
+};
--- /dev/null
+/*
+ * Copyright (C) 2017 Jagan Teki <jagan@amarulasolutions.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+&dmc {
+ rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
+ 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
+ 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
+ 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
+ 0x5 0x0>;
+ rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
+ 0xa60 0x40 0x10 0x0>;
+ /* Add a dummy value to cause of-platdata think this is bytes */
+ rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
+};
+
+&sdmmc {
+ u-boot,dm-pre-reloc;
+};
+
+&emmc {
+ u-boot,dm-pre-reloc;
+};
+
+&uart2 {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+};
};
memory {
+ reg = <0x0 0x0 0x0 0x80000000>;
device_type = "memory";
- reg = <0 0x80000000>;
};
- vcc_sd: sdmmc-regulator {
+ dc12_vbat: dc12-vbat {
compatible = "regulator-fixed";
- gpio = <&gpio7 RK_PB3 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_pwr>;
- regulator-name = "vcc_sd";
+ regulator-name = "dc12_vbat";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vboot_3v3: vboot-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vboot_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- startup-delay-us = <100000>;
- vin-supply = <&vcc_io>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&dc12_vbat>;
};
vcc_sys: vsys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_sys";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&dc12_vbat>;
+ };
+
+ vboot_5v: vboot-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "vboot_sv";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
+ vin-supply = <&dc12_vbat>;
+ };
+
+ v3g_3v3: v3g-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "v3g_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&dc12_vbat>;
+ };
+
+ vsus_5v: vsus-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "vsus_5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc_io>;
+ };
+
+ vusb1_5v: vusb1-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "vusb1_5v";
+ enable-active-high;
+ gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; /* OTG_VBUS_DRV */
+ pinctrl-names = "default";
+ pinctrl-0 = <&otg_vbus_drv>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vsus_5v>;
+ };
+
+ vusb2_5v: vusb2-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "vusb2_5v";
+ enable-active-high;
+ gpio = <&gpio8 RK_PB1 GPIO_ACTIVE_HIGH>; /* USB2_PWR_EN */
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb2_pwr_en>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vsus_5v>;
};
-};
-&dmc {
- rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
- 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
- 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
- 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
- 0x5 0x0>;
- rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
- 0xa60 0x40 0x10 0x0>;
- /* Add a dummy value to cause of-platdata think this is bytes */
- rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>;
+ ext_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ clock-output-names = "ext_gmac";
+ };
};
&cpu0 {
cpu0-supply = <&vdd_cpu>;
};
+&emmc {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ disable-wp;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
+ vmmc-supply = <&vcc_io>;
+ status = "okay";
+};
+
+&gmac {
+ assigned-clocks = <&cru SCLK_MAC>;
+ assigned-clock-parents = <&ext_gmac>;
+ clock_in_out = "input";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>;
+ phy-supply = <&vcc_lan>;
+ phy-mode = "rgmii";
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 1000000>;
+ snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>;
+ tx_delay = <0x30>;
+ rx_delay = <0x10>;
+ status = "okay";
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
+&hdmi {
+ ddc-i2c-bus = <&i2c2>;
+ status = "okay";
+};
+
&i2c0 {
clock-frequency = <400000>;
status = "okay";
reg = <0x1b>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA4 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <1>;
+ clock-output-names = "xin32k", "rk808-clkout2";
pinctrl-names = "default";
pinctrl-0 = <&pmic_int &global_pwroff>;
- wakeup-source;
rockchip,system-power-controller;
- #clock-cells = <1>;
- clock-output-names = "xin32k", "rk808-clkout2";
+ wakeup-source;
vcc1-supply = <&vcc_sys>;
vcc2-supply = <&vcc_sys>;
vcc12-supply = <&vcc_io>;
regulators {
- vdd_cpu: vdd_log: DCDC_REG1 {
- regulator-always-on;
- regulator-boot-on;
+ vdd_cpu: DCDC_REG1 {
+ regulator-name = "vdd_arm";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1350000>;
- regulator-name = "vdd_log";
+ regulator-always-on;
+ regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_gpu: DCDC_REG2 {
- regulator-always-on;
- regulator-boot-on;
+ regulator-name = "vdd_gpu";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1250000>;
- regulator-name = "vdd_gpu";
+ regulator-always-on;
+ regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
- regulator-name = "vcc_ddr";
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_io: DCDC_REG4 {
- regulator-always-on;
- regulator-boot-on;
+ regulator-name = "vcc_io";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- regulator-name = "vcc_io";
+ regulator-always-on;
+ regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
vcca_tp: LDO_REG1 {
- regulator-always-on;
- regulator-boot-on;
+ regulator-name = "vcc_tp";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- regulator-name = "vcc_tp";
+ regulator-always-on;
+ regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
vcc_codec: LDO_REG2 {
- regulator-always-on;
- regulator-boot-on;
+ regulator-name = "vcc_codec";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- regulator-name = "vcc_codec";
+ regulator-always-on;
+ regulator-boot-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_10: LDO_REG3 {
- regulator-always-on;
- regulator-boot-on;
+ regulator-name = "vdd_10";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
- regulator-name = "vdd_10";
+ regulator-always-on;
+ regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
vcc_gps: LDO_REG4 {
- regulator-always-on;
- regulator-boot-on;
+ regulator-name = "vcc_gps";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
- regulator-name = "vcc_gps";
+ regulator-always-on;
+ regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
vccio_sd: LDO_REG5 {
- regulator-always-on;
- regulator-boot-on;
+ regulator-name = "vccio_sd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
- regulator-name = "vccio_sd";
+ regulator-always-on;
+ regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
vcc10_lcd: LDO_REG6 {
- regulator-always-on;
- regulator-boot-on;
+ regulator-name = "vcc10_lcd";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
- regulator-name = "vcc10_lcd";
+ regulator-always-on;
+ regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
vcc_18: LDO_REG7 {
- regulator-always-on;
- regulator-boot-on;
+ regulator-name = "vcc_18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
- regulator-name = "vcc_18";
+ regulator-always-on;
+ regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
vcc18_lcd: LDO_REG8 {
- regulator-always-on;
- regulator-boot-on;
+ regulator-name = "vcc18_lcd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
- regulator-name = "vcc18_lcd";
+ regulator-always-on;
+ regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
- vcc33_sd: SWITCH_REG1 {
- regulator-always-on;
- regulator-boot-on;
+ vcc_sd: SWITCH_REG1 {
+ regulator-name = "vcc_sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- regulator-name = "vcc33_sd";
+ regulator-always-on;
+ regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_lan: SWITCH_REG2 {
- regulator-always-on;
- regulator-boot-on;
+ regulator-name = "vcc_lan";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- regulator-name = "vcc_lan";
+ regulator-always-on;
+ regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
};
};
};
-&sdmmc {
- u-boot,dm-pre-reloc;
+&i2c2 {
status = "okay";
+};
+&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>;
vmmc-supply = <&vcc_sd>;
vqmmc-supply = <&vccio_sd>;
+ status = "okay";
};
&uart2 {
- u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&phy_pwr_en>;
+ status = "okay";
+};
+
+&usb_otg {
+ status = "okay";
+};
+
+&vopb {
+ status = "okay";
+};
+
+&vopb_mmu {
+ status = "okay";
+};
+
+&vopl {
+ status = "okay";
+};
+
+&vopl_mmu {
status = "okay";
};
};
&pinctrl {
- u-boot,dm-pre-reloc;
+ pcfg_output_high: pcfg-output-high {
+ output-high;
+ };
+
+ gmac {
+ phy_int: phy-int {
+ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ phy_pmeb: phy-pmeb {
+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ phy_rst: phy-rst {
+ rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>;
+ };
+ };
+
pmic {
pmic_int: pmic-int {
rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
- sdmmc {
- sdmmc_pwr: sdmmc-pwr {
- rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
+ usb_host {
+ phy_pwr_en: phy-pwr-en {
+ rockchip,pins = <RK_GPIO2 RK_PB1 RK_FUNC_GPIO &pcfg_output_high>;
+ };
+
+ usb2_pwr_en: usb2-pwr-en {
+ rockchip,pins = <8 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb_otg {
+ otg_vbus_drv: otg-vbus-drv {
+ rockchip,pins = <RK_GPIO0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
+
};
};
};
pinctrl-0 = <&sdio_pins>;
pinctrl-1 = <&sdio_pins_od>;
bus-width = <4>;
+ max-frequency = <14000000>;
};
&timers1 {
--- /dev/null
+/*
+ * Copyright 2018 - Christophe Priouzeau <christophe.priouzeau@st.com>
+ *
+ * Based on:
+ * stm32f746-disco.dts from U-boot 2018.01
+ * Copyright 2016 - Lee Jones <lee.jones@linaro.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "stm32f746.dtsi"
+#include <dt-bindings/memory/stm32-sdram.h>
+
+/ {
+ model = "STMicroelectronics STM32F746G-EVAL board";
+ compatible = "st,stm32f746g-eval", "st,stm32f746";
+
+ chosen {
+ bootargs = "root=/dev/mmcblk0p1 rw rootwait";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ reg = <0xC0000000 0x2000000>;
+ };
+
+ aliases {
+ serial0 = &usart1;
+ spi0 = &qspi;
+ mmc0 = &sdio;
+ /* Aliases for gpios so as to use sequence */
+ gpio0 = &gpioa;
+ gpio1 = &gpiob;
+ gpio2 = &gpioc;
+ gpio3 = &gpiod;
+ gpio4 = &gpioe;
+ gpio5 = &gpiof;
+ gpio6 = &gpiog;
+ gpio7 = &gpioh;
+ gpio8 = &gpioi;
+ gpio9 = &gpioj;
+ gpio10 = &gpiok;
+ };
+
+ led1 {
+ compatible = "st,led1";
+ led-gpio = <&gpiof 10 0>;
+ };
+
+ button1 {
+ compatible = "st,button1";
+ button-gpio = <&gpioc 13 0>;
+ };
+};
+
+&clk_hse {
+ clock-frequency = <25000000>;
+};
+
+&pinctrl {
+ usart1_pins_a: usart1@0 {
+ pins1 {
+ pinmux = <STM32F746_PA9_FUNC_USART1_TX>;
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ pins2 {
+ pinmux = <STM32F746_PA10_FUNC_USART1_RX>;
+ bias-disable;
+ };
+ };
+
+ ethernet_mii: mii@0 {
+ pins {
+ pinmux = <STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
+ <STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
+ <STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
+ <STM32F746_PA2_FUNC_ETH_MDIO>,
+ <STM32F746_PC1_FUNC_ETH_MDC>,
+ <STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
+ <STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
+ <STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
+ <STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>;
+ slew-rate = <2>;
+ };
+ };
+
+ fmc_pins: fmc@0 {
+ pins {
+ pinmux = <STM32F746_PI10_FUNC_FMC_D31>, /* FMC_D31 */
+ <STM32F746_PI9_FUNC_FMC_D30>, /* FMC_D30*/
+ <STM32F746_PI7_FUNC_FMC_D29>, /* FMC_D29 */
+ <STM32F746_PI6_FUNC_FMC_D28>, /* FMC_D28 */
+ <STM32F746_PI3_FUNC_FMC_D27>, /* FMC_D27 */
+ <STM32F746_PI2_FUNC_FMC_D26>, /* FMC_D26 */
+ <STM32F746_PI1_FUNC_FMC_D25>, /* FMC_D25 */
+ <STM32F746_PI0_FUNC_FMC_D24>, /* FMC_D24 */
+ <STM32F746_PH15_FUNC_FMC_D23>, /* FMC_D23 */
+ <STM32F746_PH14_FUNC_FMC_D22>, /* FMC_D22 */
+ <STM32F746_PH13_FUNC_FMC_D21>, /* FMC_D21 */
+ <STM32F746_PH12_FUNC_FMC_D20>, /* FMC_D20 */
+ <STM32F746_PH11_FUNC_FMC_D19>, /* FMC_D19 */
+ <STM32F746_PH10_FUNC_FMC_D18>, /* FMC_D18 */
+ <STM32F746_PH9_FUNC_FMC_D17>, /* FMC_D17 */
+ <STM32F746_PH8_FUNC_FMC_D16>, /* FMC_D16 */
+
+ <STM32F746_PD10_FUNC_FMC_D15>, /* FMC_D15 */
+ <STM32F746_PD9_FUNC_FMC_D14>, /* FMC_D14*/
+ <STM32F746_PD8_FUNC_FMC_D13>, /* FMC_D13 */
+ <STM32F746_PE15_FUNC_FMC_D12>,/* FMC_D12 */
+ <STM32F746_PE14_FUNC_FMC_D11>,/* FMC_D11 */
+ <STM32F746_PE13_FUNC_FMC_D10>,/* FMC_D10 */
+ <STM32F746_PE12_FUNC_FMC_D9>, /* FMC_D9 */
+ <STM32F746_PE11_FUNC_FMC_D8>, /* FMC_D8 */
+ <STM32F746_PE10_FUNC_FMC_D7>, /* FMC_D7 */
+ <STM32F746_PE9_FUNC_FMC_D6>, /* FMC_D6 */
+ <STM32F746_PE8_FUNC_FMC_D5>, /* FMC_D5*/
+ <STM32F746_PE7_FUNC_FMC_D4>, /* FMC_D4 */
+ <STM32F746_PD1_FUNC_FMC_D3>, /* FMC_D3 */
+ <STM32F746_PD0_FUNC_FMC_D2>, /* FMC_D2 */
+ <STM32F746_PD15_FUNC_FMC_D1>, /* FMC_D1 */
+ <STM32F746_PD14_FUNC_FMC_D0>, /* FMC_D0 */
+
+ <STM32F746_PI5_FUNC_FMC_NBL3>, /* FMC_NBL3 */
+ <STM32F746_PI4_FUNC_FMC_NBL2>, /* FMC_NBL2 */
+ <STM32F746_PE1_FUNC_FMC_NBL1>, /* FMC_NBL1 */
+ <STM32F746_PE0_FUNC_FMC_NBL0>, /* FMC_NBL0 */
+
+ <STM32F746_PG5_FUNC_FMC_A15_FMC_BA1>, /* FMC_A15 FMC_BA1 */
+ <STM32F746_PG4_FUNC_FMC_A14_FMC_BA0>, /* FMC_A14 FMC_BA0*/
+
+ <STM32F746_PG1_FUNC_FMC_A11>, /* FMC_A11 */
+ <STM32F746_PG0_FUNC_FMC_A10>, /* FMC_A10 */
+ <STM32F746_PF15_FUNC_FMC_A9>, /* FMC_A9 */
+ <STM32F746_PF14_FUNC_FMC_A8>, /* FMC_A8 */
+ <STM32F746_PF13_FUNC_FMC_A7>, /* FMC_A7 */
+ <STM32F746_PF12_FUNC_FMC_A6>, /* FMC_A6 */
+ <STM32F746_PF5_FUNC_FMC_A5>, /* FUNC_FMC_A5 */
+ <STM32F746_PF4_FUNC_FMC_A4>, /* FMC_A4 */
+ <STM32F746_PF3_FUNC_FMC_A3>, /* FMC_A3 */
+ <STM32F746_PF2_FUNC_FMC_A2>, /* FMC_A2 */
+ <STM32F746_PF1_FUNC_FMC_A1>, /* FMC_A1 */
+ <STM32F746_PF0_FUNC_FMC_A0>, /* FMC_A0 */
+
+ <STM32F746_PH3_FUNC_FMC_SDNE0>,/* FMC_SDNE0 */
+ <STM32F746_PH5_FUNC_FMC_SDNWE>, /* FMC_SDNWE */
+ <STM32F746_PF11_FUNC_FMC_SDNRAS>, /* FMC_SDNRAS */
+ <STM32F746_PG15_FUNC_FMC_SDNCAS>, /* FMC_SDNCAS */
+ <STM32F746_PH2_FUNC_FMC_SDCKE0>, /* FMC_SDCKE0 */
+ <STM32F746_PG8_FUNC_FMC_SDCLK>; /* FMC_SDCLK */
+ slew-rate = <2>;
+ };
+ };
+};
+
+&usart1 {
+ pinctrl-0 = <&usart1_pins_a>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&mac {
+ status = "okay";
+ pinctrl-0 = <ðernet_mii>;
+ phy-mode = "rmii";
+ phy-handle = <&phy0>;
+
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+};
+
+&fmc {
+ pinctrl-0 = <&fmc_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ /*
+ * Memory configuration from sdram datasheet IS42S32800G-6BLI
+ */
+ bank1: bank@0 {
+ st,sdram-control = /bits/ 8 <NO_COL_9 NO_ROW_12 MWIDTH_32 BANKS_4
+ CAS_2 SDCLK_3 RD_BURST_EN RD_PIPE_DL_0>;
+ st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_1 TRAS_1 TRC_6 TRP_2
+ TWR_1 TRCD_1>;
+ st,sdram-refcount = <1539>;
+ };
+};
+
+&sdio {
+ status = "okay";
+ pinctrl-names = "default", "opendrain";
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-1 = <&sdio_pins_od>;
+ bus-width = <4>;
+ max-frequency = <25000000>;
+};
+/{
+ soc {
+ timer5: timer@40000c00 {
+ u-boot,dm-pre-reloc;
+ };
+ };
+};
+
&pinctrl {
usart1_pins_a: usart1@0 {
u-boot,dm-pre-reloc;
pinctrl-names = "default", "opendrain";
max-frequency = <48000000>;
};
+
+ timer5: timer@40000c00 {
+ compatible = "st,stm32-timer";
+ reg = <0x40000c00 0x400>;
+ interrupts = <50>;
+ clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
+ };
};
};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree Source for A20-SOM204-EVB-eMMC Board
+ *
+ * Copyright (C) 2018 Olimex Ltd.
+ * Author: Stefan Mavrodiev <stefan@olimex.com>
+ */
+
+/dts-v1/;
+#include "sun7i-a20-olimex-som204-evb.dts"
+
+/ {
+ model = "Olimex A20-SOM204-EVB-eMMC";
+ compatible = "olimex,a20-olimex-som204-evb-emmc", "allwinner,sun7i-a20";
+
+ mmc2_pwrseq: mmc2_pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&pio 2 16 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins_a>;
+ vmmc-supply = <®_vcc3v3>;
+ mmc-pwrseq = <&mmc2_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ emmc: emmc@0 {
+ reg = <0>;
+ compatible = "mmc-card";
+ broken-hpi;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree Source for A20-SOM204-EVB Board
+ *
+ * Copyright (C) 2018 Olimex Ltd.
+ * Author: Stefan Mavrodiev <stefan@olimex.com>
+ */
+
+/dts-v1/;
+#include "sun7i-a20.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+ model = "Olimex A20-SOM204-EVB";
+ compatible = "olimex,a20-olimex-som204-evb", "allwinner,sun7i-a20";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart4;
+ serial2 = &uart7;
+ spi0 = &spi1;
+ spi1 = &spi2;
+ ethernet1 = &rtl8723bs;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ stat {
+ label = "a20-som204-evb:green:stat";
+ gpios = <&pio 8 0 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ led1 {
+ label = "a20-som204-evb:green:led1";
+ gpios = <&pio 8 10 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ led2 {
+ label = "a20-som204-evb:yellow:led2";
+ gpios = <&pio 8 11 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+ };
+
+ rtl_pwrseq: rtl_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&pio 6 9 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&ahci {
+ target-supply = <®_ahci_5v>;
+ status = "okay";
+};
+
+&codec {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <®_dcdc2>;
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&gmac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_pins_rgmii_a>;
+ phy = <&phy3>;
+ phy-mode = "rgmii";
+ phy-supply = <®_vcc3v3>;
+
+ snps,reset-gpio = <&pio 0 17 GPIO_ACTIVE_HIGH>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 1000000>;
+ status = "okay";
+
+ phy3: ethernet-phy@3 {
+ reg = <3>;
+ };
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ reg = <0x34>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+/* Exposed to UEXT1 */
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+
+ eeprom: eeprom@50 {
+ compatible = "atmel,24c16";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+};
+
+/* Exposed to UEXT2 */
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_a>;
+ status = "okay";
+};
+
+&ir0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir0_rx_pins_a>;
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+ status = "okay";
+};
+
+&mmc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc3_pins_a>;
+ vmmc-supply = <®_vcc3v3>;
+ mmc-pwrseq = <&rtl_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ rtl8723bs: sdio_wifi@1 {
+ reg = <1>;
+ };
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&otg_sram {
+ status = "okay";
+};
+
+&pio {
+ bt_uart_pins: bt_uart_pins@0 {
+ pins = "PG6", "PG7", "PG8";
+ function = "uart3";
+ };
+};
+
+#include "axp209.dtsi"
+
+®_ahci_5v {
+ gpio = <&pio 2 3 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-int-dll";
+};
+
+®_ldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-name = "vdd-rtc";
+};
+
+®_ldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
+®_ldo4 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pg";
+};
+
+®_usb0_vbus {
+ gpio = <&pio 2 17 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+®_usb1_vbus {
+ status = "okay";
+};
+
+®_usb2_vbus {
+ status = "okay";
+};
+
+/* Exposed to UEXT1 */
+&spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_pins_a>,
+ <&spi1_cs0_pins_a>;
+ status = "okay";
+};
+
+/* Exposed to UEXT2 */
+&spi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2_pins_a>,
+ <&spi2_cs0_pins_a>;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+/* Used for RTL8723BS bluetooth */
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_uart_pins>;
+ status = "okay";
+};
+
+/* Exposed to UEXT1 */
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pins_a>;
+ status = "okay";
+};
+
+/* Exposed to UEXT2 */
+&uart7 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart7_pins_a>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usb_power_supply {
+ status = "okay";
+};
+
+&usbphy {
+ usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+ usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+ usb0_vbus_power-supply = <&usb_power_supply>;
+ usb0_vbus-supply = <®_usb0_vbus>;
+ usb1_vbus-supply = <®_usb1_vbus>;
+ usb2_vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
usb_otg: usb@01c19000 {
compatible = "allwinner,sun8i-a33-musb";
+ reg = <0x01c19000 0x400>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mc";
status = "disabled";
--- /dev/null
+/*
+ * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
+ * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _GPIO_H_
+#define _GPIO_H_
+
+enum stm32_gpio_port {
+ STM32_GPIO_PORT_A = 0,
+ STM32_GPIO_PORT_B,
+ STM32_GPIO_PORT_C,
+ STM32_GPIO_PORT_D,
+ STM32_GPIO_PORT_E,
+ STM32_GPIO_PORT_F,
+ STM32_GPIO_PORT_G,
+ STM32_GPIO_PORT_H,
+ STM32_GPIO_PORT_I
+};
+
+enum stm32_gpio_pin {
+ STM32_GPIO_PIN_0 = 0,
+ STM32_GPIO_PIN_1,
+ STM32_GPIO_PIN_2,
+ STM32_GPIO_PIN_3,
+ STM32_GPIO_PIN_4,
+ STM32_GPIO_PIN_5,
+ STM32_GPIO_PIN_6,
+ STM32_GPIO_PIN_7,
+ STM32_GPIO_PIN_8,
+ STM32_GPIO_PIN_9,
+ STM32_GPIO_PIN_10,
+ STM32_GPIO_PIN_11,
+ STM32_GPIO_PIN_12,
+ STM32_GPIO_PIN_13,
+ STM32_GPIO_PIN_14,
+ STM32_GPIO_PIN_15
+};
+
+enum stm32_gpio_mode {
+ STM32_GPIO_MODE_IN = 0,
+ STM32_GPIO_MODE_OUT,
+ STM32_GPIO_MODE_AF,
+ STM32_GPIO_MODE_AN
+};
+
+enum stm32_gpio_otype {
+ STM32_GPIO_OTYPE_PP = 0,
+ STM32_GPIO_OTYPE_OD
+};
+
+enum stm32_gpio_speed {
+ STM32_GPIO_SPEED_2M = 0,
+ STM32_GPIO_SPEED_25M,
+ STM32_GPIO_SPEED_50M,
+ STM32_GPIO_SPEED_100M
+};
+
+enum stm32_gpio_pupd {
+ STM32_GPIO_PUPD_NO = 0,
+ STM32_GPIO_PUPD_UP,
+ STM32_GPIO_PUPD_DOWN
+};
+
+enum stm32_gpio_af {
+ STM32_GPIO_AF0 = 0,
+ STM32_GPIO_AF1,
+ STM32_GPIO_AF2,
+ STM32_GPIO_AF3,
+ STM32_GPIO_AF4,
+ STM32_GPIO_AF5,
+ STM32_GPIO_AF6,
+ STM32_GPIO_AF7,
+ STM32_GPIO_AF8,
+ STM32_GPIO_AF9,
+ STM32_GPIO_AF10,
+ STM32_GPIO_AF11,
+ STM32_GPIO_AF12,
+ STM32_GPIO_AF13,
+ STM32_GPIO_AF14,
+ STM32_GPIO_AF15
+};
+
+struct stm32_gpio_dsc {
+ enum stm32_gpio_port port;
+ enum stm32_gpio_pin pin;
+};
+
+struct stm32_gpio_ctl {
+ enum stm32_gpio_mode mode;
+ enum stm32_gpio_otype otype;
+ enum stm32_gpio_speed speed;
+ enum stm32_gpio_pupd pupd;
+ enum stm32_gpio_af af;
+};
+
+struct stm32_gpio_regs {
+ u32 moder; /* GPIO port mode */
+ u32 otyper; /* GPIO port output type */
+ u32 ospeedr; /* GPIO port output speed */
+ u32 pupdr; /* GPIO port pull-up/pull-down */
+ u32 idr; /* GPIO port input data */
+ u32 odr; /* GPIO port output data */
+ u32 bsrr; /* GPIO port bit set/reset */
+ u32 lckr; /* GPIO port configuration lock */
+ u32 afr[2]; /* GPIO alternate function */
+};
+
+struct stm32_gpio_priv {
+ struct stm32_gpio_regs *regs;
+};
+
+#endif /* _GPIO_H_ */
--- /dev/null
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_STM32F_H
+#define _ASM_ARCH_STM32F_H
+
+#define STM32_PERIPH_BASE 0x40000000UL
+
+#define STM32_APB2_PERIPH_BASE (STM32_PERIPH_BASE + 0x00010000)
+#define STM32_AHB1_PERIPH_BASE (STM32_PERIPH_BASE + 0x00020000)
+
+#define STM32_SYSCFG_BASE (STM32_APB2_PERIPH_BASE + 0x3800)
+#define STM32_FLASH_CNTL_BASE (STM32_AHB1_PERIPH_BASE + 0x3C00)
+
+void stm32_flash_latency_cfg(int latency);
+
+#endif /* _ASM_ARCH_STM32F_H */
+
+++ /dev/null
-/*
- * (C) Copyright 2013
- * Pavel Boldin, Emcraft Systems, paboldin@emcraft.com
- *
- * (C) Copyright 2015
- * Kamil Lulko, <kamil.lulko@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _MACH_FMC_H_
-#define _MACH_FMC_H_
-
-struct stm32_fmc_regs {
- u32 sdcr1; /* Control register 1 */
- u32 sdcr2; /* Control register 2 */
- u32 sdtr1; /* Timing register 1 */
- u32 sdtr2; /* Timing register 2 */
- u32 sdcmr; /* Mode register */
- u32 sdrtr; /* Refresh timing register */
- u32 sdsr; /* Status register */
-};
-
-/*
- * FMC registers base
- */
-#define STM32_SDRAM_FMC_BASE 0xA0000140
-#define STM32_SDRAM_FMC ((struct stm32_fmc_regs *)STM32_SDRAM_FMC_BASE)
-
-/* Control register SDCR */
-#define FMC_SDCR_RPIPE_SHIFT 13 /* RPIPE bit shift */
-#define FMC_SDCR_RBURST_SHIFT 12 /* RBURST bit shift */
-#define FMC_SDCR_SDCLK_SHIFT 10 /* SDRAM clock divisor shift */
-#define FMC_SDCR_WP_SHIFT 9 /* Write protection shift */
-#define FMC_SDCR_CAS_SHIFT 7 /* CAS latency shift */
-#define FMC_SDCR_NB_SHIFT 6 /* Number of banks shift */
-#define FMC_SDCR_MWID_SHIFT 4 /* Memory width shift */
-#define FMC_SDCR_NR_SHIFT 2 /* Number of row address bits shift */
-#define FMC_SDCR_NC_SHIFT 0 /* Number of col address bits shift */
-
-/* Timings register SDTR */
-#define FMC_SDTR_TMRD_SHIFT 0 /* Load mode register to active */
-#define FMC_SDTR_TXSR_SHIFT 4 /* Exit self-refresh time */
-#define FMC_SDTR_TRAS_SHIFT 8 /* Self-refresh time */
-#define FMC_SDTR_TRC_SHIFT 12 /* Row cycle delay */
-#define FMC_SDTR_TWR_SHIFT 16 /* Recovery delay */
-#define FMC_SDTR_TRP_SHIFT 20 /* Row precharge delay */
-#define FMC_SDTR_TRCD_SHIFT 24 /* Row-to-column delay */
-
-
-#define FMC_SDCMR_NRFS_SHIFT 5
-
-#define FMC_SDCMR_MODE_NORMAL 0
-#define FMC_SDCMR_MODE_START_CLOCK 1
-#define FMC_SDCMR_MODE_PRECHARGE 2
-#define FMC_SDCMR_MODE_AUTOREFRESH 3
-#define FMC_SDCMR_MODE_WRITE_MODE 4
-#define FMC_SDCMR_MODE_SELFREFRESH 5
-#define FMC_SDCMR_MODE_POWERDOWN 6
-
-#define FMC_SDCMR_BANK_1 (1 << 4)
-#define FMC_SDCMR_BANK_2 (1 << 3)
-
-#define FMC_SDCMR_MODE_REGISTER_SHIFT 9
-
-#define FMC_SDSR_BUSY (1 << 5)
-
-#define FMC_BUSY_WAIT() do { \
- __asm__ __volatile__ ("dsb" : : : "memory"); \
- while (STM32_SDRAM_FMC->sdsr & FMC_SDSR_BUSY) \
- ; \
- } while (0)
-
-
-#endif /* _MACH_FMC_H_ */
#ifndef _STM32_GPIO_H_
#define _STM32_GPIO_H_
-#if (CONFIG_STM32_USART == 1)
-#define STM32_GPIO_PORT_X STM32_GPIO_PORT_A
-#define STM32_GPIO_PIN_TX STM32_GPIO_PIN_9
-#define STM32_GPIO_PIN_RX STM32_GPIO_PIN_10
-#define STM32_GPIO_USART STM32_GPIO_AF7
-
-#elif (CONFIG_STM32_USART == 2)
-#define STM32_GPIO_PORT_X STM32_GPIO_PORT_D
-#define STM32_GPIO_PIN_TX STM32_GPIO_PIN_5
-#define STM32_GPIO_PIN_RX STM32_GPIO_PIN_6
-#define STM32_GPIO_USART STM32_GPIO_AF7
-
-#elif (CONFIG_STM32_USART == 3)
-#define STM32_GPIO_PORT_X STM32_GPIO_PORT_C
-#define STM32_GPIO_PIN_TX STM32_GPIO_PIN_10
-#define STM32_GPIO_PIN_RX STM32_GPIO_PIN_11
-#define STM32_GPIO_USART STM32_GPIO_AF7
-
-#elif (CONFIG_STM32_USART == 6)
-#define STM32_GPIO_PORT_X STM32_GPIO_PORT_G
-#define STM32_GPIO_PIN_TX STM32_GPIO_PIN_14
-#define STM32_GPIO_PIN_RX STM32_GPIO_PIN_9
-#define STM32_GPIO_USART STM32_GPIO_AF8
-
-#else
-#define STM32_GPIO_PORT_X STM32_GPIO_PORT_A
-#define STM32_GPIO_PIN_TX STM32_GPIO_PIN_9
-#define STM32_GPIO_PIN_RX STM32_GPIO_PIN_10
-#define STM32_GPIO_USART STM32_GPIO_AF7
-
-#endif
-
-enum stm32_gpio_port {
- STM32_GPIO_PORT_A = 0,
- STM32_GPIO_PORT_B,
- STM32_GPIO_PORT_C,
- STM32_GPIO_PORT_D,
- STM32_GPIO_PORT_E,
- STM32_GPIO_PORT_F,
- STM32_GPIO_PORT_G,
- STM32_GPIO_PORT_H,
- STM32_GPIO_PORT_I
-};
-
-enum stm32_gpio_pin {
- STM32_GPIO_PIN_0 = 0,
- STM32_GPIO_PIN_1,
- STM32_GPIO_PIN_2,
- STM32_GPIO_PIN_3,
- STM32_GPIO_PIN_4,
- STM32_GPIO_PIN_5,
- STM32_GPIO_PIN_6,
- STM32_GPIO_PIN_7,
- STM32_GPIO_PIN_8,
- STM32_GPIO_PIN_9,
- STM32_GPIO_PIN_10,
- STM32_GPIO_PIN_11,
- STM32_GPIO_PIN_12,
- STM32_GPIO_PIN_13,
- STM32_GPIO_PIN_14,
- STM32_GPIO_PIN_15
-};
-
-enum stm32_gpio_mode {
- STM32_GPIO_MODE_IN = 0,
- STM32_GPIO_MODE_OUT,
- STM32_GPIO_MODE_AF,
- STM32_GPIO_MODE_AN
-};
-
-enum stm32_gpio_otype {
- STM32_GPIO_OTYPE_PP = 0,
- STM32_GPIO_OTYPE_OD
-};
-
-enum stm32_gpio_speed {
- STM32_GPIO_SPEED_2M = 0,
- STM32_GPIO_SPEED_25M,
- STM32_GPIO_SPEED_50M,
- STM32_GPIO_SPEED_100M
-};
-
-enum stm32_gpio_pupd {
- STM32_GPIO_PUPD_NO = 0,
- STM32_GPIO_PUPD_UP,
- STM32_GPIO_PUPD_DOWN
-};
-
-enum stm32_gpio_af {
- STM32_GPIO_AF0 = 0,
- STM32_GPIO_AF1,
- STM32_GPIO_AF2,
- STM32_GPIO_AF3,
- STM32_GPIO_AF4,
- STM32_GPIO_AF5,
- STM32_GPIO_AF6,
- STM32_GPIO_AF7,
- STM32_GPIO_AF8,
- STM32_GPIO_AF9,
- STM32_GPIO_AF10,
- STM32_GPIO_AF11,
- STM32_GPIO_AF12,
- STM32_GPIO_AF13,
- STM32_GPIO_AF14,
- STM32_GPIO_AF15
-};
-
-struct stm32_gpio_dsc {
- enum stm32_gpio_port port;
- enum stm32_gpio_pin pin;
-};
-
-struct stm32_gpio_ctl {
- enum stm32_gpio_mode mode;
- enum stm32_gpio_otype otype;
- enum stm32_gpio_speed speed;
- enum stm32_gpio_pupd pupd;
- enum stm32_gpio_af af;
-};
-
-struct stm32_gpio_regs {
- u32 moder; /* GPIO port mode */
- u32 otyper; /* GPIO port output type */
- u32 ospeedr; /* GPIO port output speed */
- u32 pupdr; /* GPIO port pull-up/pull-down */
- u32 idr; /* GPIO port input data */
- u32 odr; /* GPIO port output data */
- u32 bsrr; /* GPIO port bit set/reset */
- u32 lckr; /* GPIO port configuration lock */
- u32 afr[2]; /* GPIO alternate function */
-};
-
-struct stm32_gpio_priv {
- struct stm32_gpio_regs *regs;
-};
-
-static inline unsigned stm32_gpio_to_port(unsigned gpio)
-{
- return gpio / 16;
-}
-
-static inline unsigned stm32_gpio_to_pin(unsigned gpio)
-{
- return gpio % 16;
-}
+#include <asm/arch-stm32/gpio.h>
#endif /* _STM32_GPIO_H_ */
#ifndef _MACH_STM32_H_
#define _MACH_STM32_H_
+#include <asm/arch-stm32/stm32f.h>
+
/*
* Peripheral memory map
*/
#define STM32_SYSMEM_BASE 0x1FFF0000
-#define STM32_PERIPH_BASE 0x40000000
-#define STM32_APB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00000000)
-#define STM32_APB2PERIPH_BASE (STM32_PERIPH_BASE + 0x00010000)
-#define STM32_AHB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00020000)
-#define STM32_AHB2PERIPH_BASE (STM32_PERIPH_BASE + 0x10000000)
-
-#define STM32_BUS_MASK 0xFFFF0000
/*
* Register maps
*/
#define STM32_U_ID_BASE (STM32_SYSMEM_BASE + 0x7A10)
#define STM32_U_ID ((struct stm32_u_id_regs *)STM32_U_ID_BASE)
-
-#define STM32_RCC_BASE (STM32_AHB1PERIPH_BASE + 0x3800)
-#define STM32_RCC ((struct stm32_rcc_regs *)STM32_RCC_BASE)
-
-#define FLASH_CNTL_BASE (STM32_AHB1PERIPH_BASE + 0x3C00)
-
static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
[0 ... 3] = 16 * 1024,
[4] = 64 * 1024,
[5 ... 11] = 128 * 1024
};
-void stm32_flash_latency_cfg(int latency);
-
#endif /* _MACH_STM32_H_ */
+++ /dev/null
-/*
- * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
- * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __STM32_DEFS_H__
-#define __STM32_DEFS_H__
-#include <asm/arch/stm32_periph.h>
-
-int clock_setup(enum periph_clock);
-
-#endif
-
+++ /dev/null
-/*
- * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
- * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARM_ARCH_PERIPH_H
-#define __ASM_ARM_ARCH_PERIPH_H
-
-/*
- * Peripherals required for pinmux configuration. List will
- * grow with support for more devices getting added.
- * Numbering based on interrupt table.
- *
- */
-enum periph_id {
- UART1_GPIOA_9_10 = 0,
- UART2_GPIOD_5_6,
-};
-
-enum periph_clock {
- USART1_CLOCK_CFG = 0,
- USART2_CLOCK_CFG,
- GPIO_A_CLOCK_CFG,
- GPIO_B_CLOCK_CFG,
- GPIO_C_CLOCK_CFG,
- GPIO_D_CLOCK_CFG,
- GPIO_E_CLOCK_CFG,
- GPIO_F_CLOCK_CFG,
- GPIO_G_CLOCK_CFG,
- GPIO_H_CLOCK_CFG,
- GPIO_I_CLOCK_CFG,
- GPIO_J_CLOCK_CFG,
- GPIO_K_CLOCK_CFG,
-};
-
-#endif /* __ASM_ARM_ARCH_PERIPH_H */
#ifndef _STM32_GPIO_H_
#define _STM32_GPIO_H_
-#include <asm/gpio.h>
-enum stm32_gpio_port {
- STM32_GPIO_PORT_A = 0,
- STM32_GPIO_PORT_B,
- STM32_GPIO_PORT_C,
- STM32_GPIO_PORT_D,
- STM32_GPIO_PORT_E,
- STM32_GPIO_PORT_F,
- STM32_GPIO_PORT_G,
- STM32_GPIO_PORT_H,
- STM32_GPIO_PORT_I
-};
-
-enum stm32_gpio_pin {
- STM32_GPIO_PIN_0 = 0,
- STM32_GPIO_PIN_1,
- STM32_GPIO_PIN_2,
- STM32_GPIO_PIN_3,
- STM32_GPIO_PIN_4,
- STM32_GPIO_PIN_5,
- STM32_GPIO_PIN_6,
- STM32_GPIO_PIN_7,
- STM32_GPIO_PIN_8,
- STM32_GPIO_PIN_9,
- STM32_GPIO_PIN_10,
- STM32_GPIO_PIN_11,
- STM32_GPIO_PIN_12,
- STM32_GPIO_PIN_13,
- STM32_GPIO_PIN_14,
- STM32_GPIO_PIN_15
-};
-
-enum stm32_gpio_mode {
- STM32_GPIO_MODE_IN = 0,
- STM32_GPIO_MODE_OUT,
- STM32_GPIO_MODE_AF,
- STM32_GPIO_MODE_AN
-};
-
-enum stm32_gpio_otype {
- STM32_GPIO_OTYPE_PP = 0,
- STM32_GPIO_OTYPE_OD
-};
-
-enum stm32_gpio_speed {
- STM32_GPIO_SPEED_2M = 0,
- STM32_GPIO_SPEED_25M,
- STM32_GPIO_SPEED_50M,
- STM32_GPIO_SPEED_100M
-};
-
-enum stm32_gpio_pupd {
- STM32_GPIO_PUPD_NO = 0,
- STM32_GPIO_PUPD_UP,
- STM32_GPIO_PUPD_DOWN
-};
-
-enum stm32_gpio_af {
- STM32_GPIO_AF0 = 0,
- STM32_GPIO_AF1,
- STM32_GPIO_AF2,
- STM32_GPIO_AF3,
- STM32_GPIO_AF4,
- STM32_GPIO_AF5,
- STM32_GPIO_AF6,
- STM32_GPIO_AF7,
- STM32_GPIO_AF8,
- STM32_GPIO_AF9,
- STM32_GPIO_AF10,
- STM32_GPIO_AF11,
- STM32_GPIO_AF12,
- STM32_GPIO_AF13,
- STM32_GPIO_AF14,
- STM32_GPIO_AF15
-};
-
-struct stm32_gpio_dsc {
- enum stm32_gpio_port port;
- enum stm32_gpio_pin pin;
-};
-
-struct stm32_gpio_ctl {
- enum stm32_gpio_mode mode;
- enum stm32_gpio_otype otype;
- enum stm32_gpio_speed speed;
- enum stm32_gpio_pupd pupd;
- enum stm32_gpio_af af;
-};
-
-struct stm32_gpio_regs {
- u32 moder; /* GPIO port mode */
- u32 otyper; /* GPIO port output type */
- u32 ospeedr; /* GPIO port output speed */
- u32 pupdr; /* GPIO port pull-up/pull-down */
- u32 idr; /* GPIO port input data */
- u32 odr; /* GPIO port output data */
- u32 bsrr; /* GPIO port bit set/reset */
- u32 lckr; /* GPIO port configuration lock */
- u32 afr[2]; /* GPIO alternate function */
-};
-
-struct stm32_gpio_priv {
- struct stm32_gpio_regs *regs;
-};
-
-static inline unsigned stm32_gpio_to_port(unsigned gpio)
-{
- return gpio / 16;
-}
-
-static inline unsigned stm32_gpio_to_pin(unsigned gpio)
-{
- return gpio % 16;
-}
+#include <asm/arch-stm32/gpio.h>
#endif /* _STM32_GPIO_H_ */
+++ /dev/null
-/*
- * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
- * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _STM32_GPT_H
-#define _STM32_GPT_H
-
-#include <asm/arch/stm32.h>
-
-struct gpt_regs {
- u32 cr1;
- u32 cr2;
- u32 smcr;
- u32 dier;
- u32 sr;
- u32 egr;
- u32 ccmr1;
- u32 ccmr2;
- u32 ccer;
- u32 cnt;
- u32 psc;
- u32 arr;
- u32 reserved;
- u32 ccr1;
- u32 ccr2;
- u32 ccr3;
- u32 ccr4;
- u32 reserved1;
- u32 dcr;
- u32 dmar;
- u32 tim2_5_or;
-};
-
-struct gpt_regs *const gpt1_regs_ptr =
- (struct gpt_regs *)TIM2_BASE;
-
-/* Timer control1 register */
-#define GPT_CR1_CEN BIT(0)
-#define GPT_MODE_AUTO_RELOAD BIT(7)
-
-/* Auto reload register for free running config */
-#define GPT_FREE_RUNNING 0xFFFFFFFF
-
-/* Timer, HZ specific defines */
-#define CONFIG_STM32_HZ 1000
-
-/* Timer Event Generation registers */
-#define TIM_EGR_UG BIT(0)
-
-#endif
#ifndef _ASM_ARCH_HARDWARE_H
#define _ASM_ARCH_HARDWARE_H
-/* STM32F746 */
-#define ITCM_FLASH_BASE 0x00200000UL
-#define AXIM_FLASH_BASE 0x08000000UL
-
-#define ITCM_SRAM_BASE 0x00000000UL
-#define DTCM_SRAM_BASE 0x20000000UL
-#define SRAM1_BASE 0x20010000UL
-#define SRAM2_BASE 0x2004C000UL
-
-#define PERIPH_BASE 0x40000000UL
-
-#define APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000)
-#define APB2_PERIPH_BASE (PERIPH_BASE + 0x00010000)
-#define AHB1_PERIPH_BASE (PERIPH_BASE + 0x00020000)
-#define AHB2_PERIPH_BASE (PERIPH_BASE + 0x10000000)
-#define AHB3_PERIPH_BASE (PERIPH_BASE + 0x20000000)
-
-#define TIM2_BASE (APB1_PERIPH_BASE + 0x0000)
-#define USART2_BASE (APB1_PERIPH_BASE + 0x4400)
-#define USART3_BASE (APB1_PERIPH_BASE + 0x4800)
-#define PWR_BASE (APB1_PERIPH_BASE + 0x7000)
-
-#define USART1_BASE (APB2_PERIPH_BASE + 0x1000)
-#define USART6_BASE (APB2_PERIPH_BASE + 0x1400)
-#define STM32_SYSCFG_BASE (APB2_PERIPH_BASE + 0x3800)
-
-#define STM32_GPIOA_BASE (AHB1_PERIPH_BASE + 0x0000)
-#define STM32_GPIOB_BASE (AHB1_PERIPH_BASE + 0x0400)
-#define STM32_GPIOC_BASE (AHB1_PERIPH_BASE + 0x0800)
-#define STM32_GPIOD_BASE (AHB1_PERIPH_BASE + 0x0C00)
-#define STM32_GPIOE_BASE (AHB1_PERIPH_BASE + 0x1000)
-#define STM32_GPIOF_BASE (AHB1_PERIPH_BASE + 0x1400)
-#define STM32_GPIOG_BASE (AHB1_PERIPH_BASE + 0x1800)
-#define STM32_GPIOH_BASE (AHB1_PERIPH_BASE + 0x1C00)
-#define STM32_GPIOI_BASE (AHB1_PERIPH_BASE + 0x2000)
-#define STM32_GPIOJ_BASE (AHB1_PERIPH_BASE + 0x2400)
-#define STM32_GPIOK_BASE (AHB1_PERIPH_BASE + 0x2800)
-#define RCC_BASE (AHB1_PERIPH_BASE + 0x3800)
-#define FLASH_CNTL_BASE (AHB1_PERIPH_BASE + 0x3C00)
-
-
-#define SDRAM_FMC_BASE (AHB3_PERIPH_BASE + 0x40000140)
+#include <asm/arch-stm32/stm32f.h>
static const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
[0 ... 3] = 32 * 1024,
[5 ... 7] = 256 * 1024
};
-#define STM32_BUS_MASK GENMASK(31, 16)
-
-#define STM32_RCC ((struct stm32_rcc_regs *)RCC_BASE)
-
-
-void stm32_flash_latency_cfg(int latency);
-
#endif /* _ASM_ARCH_HARDWARE_H */
+++ /dev/null
-/*
- * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
- * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __STM32_DEFS_H__
-#define __STM32_DEFS_H__
-#include <asm/arch/stm32_periph.h>
-
-int clock_setup(enum periph_clock);
-
-#endif
-
+++ /dev/null
-/*
- * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
- * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARM_ARCH_PERIPH_H
-#define __ASM_ARM_ARCH_PERIPH_H
-
-/*
- * Peripherals required for pinmux configuration. List will
- * grow with support for more devices getting added.
- * Numbering based on interrupt table.
- *
- */
-enum periph_id {
- PERIPH_ID_USART1 = 37,
-
- PERIPH_ID_QUADSPI = 92,
-};
-
-enum periph_clock {
- TIMER2_CLOCK_CFG,
-};
-
-#endif /* __ASM_ARM_ARCH_PERIPH_H */
*/
#define STM32_SYSCFG ((struct stm32_syscfg_regs *)STM32_SYSCFG_BASE)
-/* SYSCFG memory remap register */
-#define SYSCFG_MEMRMP_MEM_BOOT BIT(0)
-#define SYSCFG_MEMRMP_SWP_FMC BIT(10)
-
/* SYSCFG peripheral mode configuration register */
-#define SYSCFG_PMC_ADCXDC2 BIT(16)
#define SYSCFG_PMC_MII_RMII_SEL BIT(23)
-/* Compensation cell control register */
-#define SYSCFG_CMPCR_CMP_PD BIT(0)
-#define SYSCFG_CMPCR_READY BIT(8)
-
#endif
#ifndef _STM32_GPIO_H_
#define _STM32_GPIO_H_
-#include <asm/gpio.h>
-enum stm32_gpio_port {
- STM32_GPIO_PORT_A = 0,
- STM32_GPIO_PORT_B,
- STM32_GPIO_PORT_C,
- STM32_GPIO_PORT_D,
- STM32_GPIO_PORT_E,
- STM32_GPIO_PORT_F,
- STM32_GPIO_PORT_G,
- STM32_GPIO_PORT_H,
- STM32_GPIO_PORT_I
-};
-
-enum stm32_gpio_pin {
- STM32_GPIO_PIN_0 = 0,
- STM32_GPIO_PIN_1,
- STM32_GPIO_PIN_2,
- STM32_GPIO_PIN_3,
- STM32_GPIO_PIN_4,
- STM32_GPIO_PIN_5,
- STM32_GPIO_PIN_6,
- STM32_GPIO_PIN_7,
- STM32_GPIO_PIN_8,
- STM32_GPIO_PIN_9,
- STM32_GPIO_PIN_10,
- STM32_GPIO_PIN_11,
- STM32_GPIO_PIN_12,
- STM32_GPIO_PIN_13,
- STM32_GPIO_PIN_14,
- STM32_GPIO_PIN_15
-};
-
-enum stm32_gpio_mode {
- STM32_GPIO_MODE_IN = 0,
- STM32_GPIO_MODE_OUT,
- STM32_GPIO_MODE_AF,
- STM32_GPIO_MODE_AN
-};
-
-enum stm32_gpio_otype {
- STM32_GPIO_OTYPE_PP = 0,
- STM32_GPIO_OTYPE_OD
-};
-
-enum stm32_gpio_speed {
- STM32_GPIO_SPEED_2M = 0,
- STM32_GPIO_SPEED_25M,
- STM32_GPIO_SPEED_50M,
- STM32_GPIO_SPEED_100M
-};
-
-enum stm32_gpio_pupd {
- STM32_GPIO_PUPD_NO = 0,
- STM32_GPIO_PUPD_UP,
- STM32_GPIO_PUPD_DOWN
-};
-
-enum stm32_gpio_af {
- STM32_GPIO_AF0 = 0,
- STM32_GPIO_AF1,
- STM32_GPIO_AF2,
- STM32_GPIO_AF3,
- STM32_GPIO_AF4,
- STM32_GPIO_AF5,
- STM32_GPIO_AF6,
- STM32_GPIO_AF7,
- STM32_GPIO_AF8,
- STM32_GPIO_AF9,
- STM32_GPIO_AF10,
- STM32_GPIO_AF11,
- STM32_GPIO_AF12,
- STM32_GPIO_AF13,
- STM32_GPIO_AF14,
- STM32_GPIO_AF15
-};
-
-struct stm32_gpio_dsc {
- enum stm32_gpio_port port;
- enum stm32_gpio_pin pin;
-};
-
-struct stm32_gpio_ctl {
- enum stm32_gpio_mode mode;
- enum stm32_gpio_otype otype;
- enum stm32_gpio_speed speed;
- enum stm32_gpio_pupd pupd;
- enum stm32_gpio_af af;
-};
-
-struct stm32_gpio_regs {
- u32 moder; /* GPIO port mode */
- u32 otyper; /* GPIO port output type */
- u32 ospeedr; /* GPIO port output speed */
- u32 pupdr; /* GPIO port pull-up/pull-down */
- u32 idr; /* GPIO port input data */
- u32 odr; /* GPIO port output data */
- u32 bsrr; /* GPIO port bit set/reset */
- u32 lckr; /* GPIO port configuration lock */
- u32 afr[2]; /* GPIO alternate function */
-};
-
-struct stm32_gpio_priv {
- struct stm32_gpio_regs *regs;
-};
-
-static inline unsigned stm32_gpio_to_port(unsigned gpio)
-{
- return gpio / 16;
-}
-
-static inline unsigned stm32_gpio_to_pin(unsigned gpio)
-{
- return gpio % 16;
-}
+#include <asm/arch-stm32/gpio.h>
#endif /* _STM32_GPIO_H_ */
#include <common.h>
#include <asm/setup.h>
#include <asm/arch/sys_proto.h>
+#include <asm/omap_common.h>
+
static void do_cancel_out(u32 *num, u32 *den, u32 factor)
{
while (1) {
select STM32_RCC
select STM32_RESET
select STM32_SERIAL
+ select STM32_TIMER
+ select TIMER
config STM32F7
bool "stm32f7 family"
select STM32_RCC
select STM32_RESET
select STM32_SERIAL
+ select STM32_TIMER
+ select TIMER
select SUPPORT_SPL
select SPL
select SPL_BOARD_INIT
select SPL_RAM
select SPL_SERIAL_SUPPORT
select SPL_SYS_MALLOC_SIMPLE
+ select SPL_TIMER
select SPL_XIP_SUPPORT
config STM32H7
select STM32_RCC
select STM32_RESET
select STM32_SERIAL
+ select STM32_TIMER
select SYSCON
+ select TIMER
source "arch/arm/mach-stm32/stm32f4/Kconfig"
source "arch/arm/mach-stm32/stm32f7/Kconfig"
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += soc.o
-obj-$(CONFIG_STM32F4) += stm32f4/
-obj-$(CONFIG_STM32F7) += stm32f7/
struct mpu_region_config stm32_region_config[] = {
/*
- * Make all 4GB cacheable & executable. We are overriding it
- * with next region for any requirement. e.g. below region1,
- * 2 etc.
- * In other words, the area not coming in following
- * regions configuration is the one configured here in region_0
- * (cacheable & executable).
+ * Make SDRAM area cacheable & executable.
*/
+#if defined(CONFIG_STM32F4)
{ 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW,
- O_I_WB_RD_WR_ALLOC, REGION_4GB },
-
- /* armv7m code area */
- { 0x00000000, REGION_1, XN_DIS, PRIV_RW_USR_RW,
- STRONG_ORDER, REGION_512MB },
-
- /* Device area : Not executable */
- { 0x40000000, REGION_2, XN_EN, PRIV_RW_USR_RW,
- DEVICE_NON_SHARED, REGION_512MB },
+ O_I_WB_RD_WR_ALLOC, REGION_16MB },
+#endif
- /*
- * Armv7m fixed configuration: strongly ordered & not
- * executable, not cacheable
- */
- { 0xE0000000, REGION_3, XN_EN, PRIV_RW_USR_RW,
- STRONG_ORDER, REGION_512MB },
+#if defined(CONFIG_STM32F7)
+ { 0xC0000000, REGION_0, XN_DIS, PRIV_RW_USR_RW,
+ O_I_WB_RD_WR_ALLOC, REGION_16MB },
+#endif
-#if !defined(CONFIG_STM32H7)
- /* Device area : Not executable */
- { 0xA0000000, REGION_4, XN_EN, PRIV_RW_USR_RW,
- DEVICE_NON_SHARED, REGION_512MB },
+#if defined(CONFIG_STM32H7)
+ { 0xD0000000, REGION_0, XN_DIS, PRIV_RW_USR_RW,
+ O_I_WB_RD_WR_ALLOC, REGION_32MB },
#endif
};
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2015
-# Kamil Lulko, <kamil.lulko@gmail.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += timer.o
+++ /dev/null
-/*
- * (C) Copyright 2015
- * Kamil Lulko, <kamil.lulko@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <stm32_rcc.h>
-#include <asm/io.h>
-#include <asm/armv7m.h>
-#include <asm/arch/stm32.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define STM32_TIM2_BASE (STM32_APB1PERIPH_BASE + 0x0000)
-
-#define RCC_APB1ENR_TIM2EN (1 << 0)
-
-struct stm32_tim2_5 {
- u32 cr1;
- u32 cr2;
- u32 smcr;
- u32 dier;
- u32 sr;
- u32 egr;
- u32 ccmr1;
- u32 ccmr2;
- u32 ccer;
- u32 cnt;
- u32 psc;
- u32 arr;
- u32 reserved1;
- u32 ccr1;
- u32 ccr2;
- u32 ccr3;
- u32 ccr4;
- u32 reserved2;
- u32 dcr;
- u32 dmar;
- u32 or;
-};
-
-#define TIM_CR1_CEN (1 << 0)
-
-#define TIM_EGR_UG (1 << 0)
-
-int timer_init(void)
-{
- struct stm32_tim2_5 *tim = (struct stm32_tim2_5 *)STM32_TIM2_BASE;
-
- setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN);
-
- writel(((CONFIG_SYS_CLK_FREQ / 2) / CONFIG_SYS_HZ_CLOCK) - 1,
- &tim->psc);
-
- writel(0xFFFFFFFF, &tim->arr);
- writel(TIM_CR1_CEN, &tim->cr1);
- setbits_le32(&tim->egr, TIM_EGR_UG);
-
- gd->arch.tbl = 0;
- gd->arch.tbu = 0;
- gd->arch.lastinc = 0;
-
- return 0;
-}
-
-ulong get_timer(ulong base)
-{
- return (get_ticks() / (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)) - base;
-}
-
-unsigned long long get_ticks(void)
-{
- struct stm32_tim2_5 *tim = (struct stm32_tim2_5 *)STM32_TIM2_BASE;
- u32 now;
-
- now = readl(&tim->cnt);
-
- if (now >= gd->arch.lastinc)
- gd->arch.tbl += (now - gd->arch.lastinc);
- else
- gd->arch.tbl += (0xFFFFFFFF - gd->arch.lastinc) + now;
-
- gd->arch.lastinc = now;
-
- return gd->arch.tbl;
-}
-
-void reset_timer(void)
-{
- struct stm32_tim2_5 *tim = (struct stm32_tim2_5 *)STM32_TIM2_BASE;
-
- gd->arch.lastinc = readl(&tim->cnt);
- gd->arch.tbl = 0;
-}
-
-/* delay x useconds */
-void __udelay(ulong usec)
-{
- unsigned long long start;
-
- start = get_ticks(); /* get current timestamp */
- while ((get_ticks() - start) < usec)
- ; /* loop till time has passed */
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
- return CONFIG_SYS_HZ_CLOCK;
-}
+++ /dev/null
-#
-# Copyright (C) 2016, STMicroelectronics - All Rights Reserved
-# Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += timer.o
+++ /dev/null
-/*
- * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
- * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <stm32_rcc.h>
-#include <asm/io.h>
-#include <asm/arch/stm32.h>
-#include <asm/arch/stm32_defs.h>
-#include <asm/arch/gpt.h>
-
-#define READ_TIMER() (readl(&gpt1_regs_ptr->cnt) & GPT_FREE_RUNNING)
-#define GPT_RESOLUTION (CONFIG_SYS_HZ_CLOCK/CONFIG_STM32_HZ)
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define timestamp gd->arch.tbl
-#define lastdec gd->arch.lastinc
-
-int timer_init(void)
-{
- /* Timer2 clock configuration */
- clock_setup(TIMER2_CLOCK_CFG);
- /* Stop the timer */
- writel(readl(&gpt1_regs_ptr->cr1) & ~GPT_CR1_CEN, &gpt1_regs_ptr->cr1);
-
- writel((CONFIG_SYS_CLK_FREQ / 2 / CONFIG_SYS_HZ_CLOCK) - 1,
- &gpt1_regs_ptr->psc);
-
- /* Configure timer for auto-reload */
- writel(readl(&gpt1_regs_ptr->cr1) | GPT_MODE_AUTO_RELOAD,
- &gpt1_regs_ptr->cr1);
-
- /* load value for free running */
- writel(GPT_FREE_RUNNING, &gpt1_regs_ptr->arr);
-
- /* start timer */
- writel(readl(&gpt1_regs_ptr->cr1) | GPT_CR1_CEN, &gpt1_regs_ptr->cr1);
-
- writel(readl(&gpt1_regs_ptr->egr) | TIM_EGR_UG, &gpt1_regs_ptr->egr);
-
- /* Reset the timer */
- lastdec = READ_TIMER();
- timestamp = 0;
-
- return 0;
-}
-
-/*
- * timer without interrupts
- */
-ulong get_timer(ulong base)
-{
- return (get_timer_masked() / GPT_RESOLUTION) - base;
-}
-
-void __udelay(unsigned long usec)
-{
- ulong tmo;
- ulong start = get_timer_masked();
- ulong tenudelcnt = CONFIG_SYS_HZ_CLOCK / (1000 * 100);
- ulong rndoff;
-
- rndoff = (usec % 10) ? 1 : 0;
-
- /* tenudelcnt timer tick gives 10 microsecconds delay */
- tmo = ((usec / 10) + rndoff) * tenudelcnt;
-
- while ((ulong) (get_timer_masked() - start) < tmo)
- ;
-}
-
-ulong get_timer_masked(void)
-{
- ulong now = READ_TIMER();
-
- if (now >= lastdec) {
- /* normal mode */
- timestamp += now - lastdec;
- } else {
- /* we have an overflow ... */
- timestamp += now + GPT_FREE_RUNNING - lastdec;
- }
- lastdec = now;
-
- return timestamp;
-}
-
-void udelay_masked(unsigned long usec)
-{
- return udelay(usec);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
- return CONFIG_STM32_HZ;
-}
F: board/amarula/vyasa-rk3288
F: include/configs/vyasa-rk3288.h
F: configs/vyasa-rk3288_defconfig
+F: arch/arm/dts/rk3288-vyasa.dts
+F: arch/arm/dts/rk3288-vyasa-u-boot.dtsi
#ifndef CONFIG_TPL_BUILD
#include <spl.h>
+void board_boot_order(u32 *spl_boot_list)
+{
+ /* eMMC prior to sdcard. */
+ spl_boot_list[0] = BOOT_DEVICE_MMC2;
+ spl_boot_list[1] = BOOT_DEVICE_MMC1;
+}
+
int spl_start_uboot(void)
{
/* break into full u-boot on 'c' */
#include <asm/armv7m.h>
#include <asm/arch/stm32.h>
#include <asm/arch/gpio.h>
-#include <asm/arch/stm32_periph.h>
-#include <asm/arch/stm32_defs.h>
#include <asm/arch/syscfg.h>
#include <asm/gpio.h>
S: Maintained
F: configs/Nintendo_NES_Classic_Edition_defconfig
+OLIMEX A20-SOM204 BOARD
+M: Stefan Mavrodiev <stefan@olimex.com>
+S: Maintained
+F: configs/A20-Olimex-SOM204-EVB_defconfig
+F: configs/A20-Olimex-SOM204-EVB-eMMC_defconfig
+
ORANGEPI WIN/WIN PLUS BOARD
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
(replace /dev/sdx with you SD card device file name, which could be
/dev/mmcblk[x] as well).
-Alternatively you can concatenate the SPL and the U-Boot FIT image into a
+Alternatively you can use the SPL and the U-Boot FIT image combined into a
single file and transfer that instead:
-$ cat spl/sunxi-spl.bin u-boot.itb > u-boot-sunxi-with-spl.bin
# dd if=u-boot-sunxi-with-spl.bin of=/dev/sdx bs=8k seek=1
You can partition the microSD card, but leave the first MB unallocated (most
if (generate_fake_mac)
omap_die_id_usbethaddr();
+#if defined(CONFIG_MTDIDS_DEFAULT) && defined(CONFIG_MTDPARTS_DEFAULT)
+ if (strlen(CONFIG_MTDIDS_DEFAULT))
+ env_set("mtdids", CONFIG_MTDIDS_DEFAULT);
+
+ if (strlen(CONFIG_MTDPARTS_DEFAULT))
+ env_set("mtdparts", CONFIG_MTDPARTS_DEFAULT);
+#endif
+
return 0;
}
#include <part.h>
#include <vsprintf.h>
+enum cmd_part_info {
+ CMD_PART_INFO_START = 0,
+ CMD_PART_INFO_SIZE,
+};
+
static int do_part_uuid(int argc, char * const argv[])
{
int part;
return 0;
}
-static int do_part_start(int argc, char * const argv[])
+static int do_part_info(int argc, char * const argv[], enum cmd_part_info param)
{
struct blk_desc *desc;
disk_partition_t info;
char buf[512] = { 0 };
+ char *endp;
int part;
int err;
int ret;
if (argc > 4)
return CMD_RET_USAGE;
- part = simple_strtoul(argv[2], NULL, 0);
-
ret = blk_get_device_by_str(argv[0], argv[1], &desc);
if (ret < 0)
return 1;
- err = part_get_info(desc, part, &info);
- if (err)
- return 1;
+ part = simple_strtoul(argv[2], &endp, 0);
+ if (*endp == '\0') {
+ err = part_get_info(desc, part, &info);
+ if (err)
+ return 1;
+ } else {
+ part = part_get_info_by_name(desc, argv[2], &info);
+ if (part == -1)
+ return 1;
+ }
- snprintf(buf, sizeof(buf), LBAF, info.start);
+ switch (param) {
+ case CMD_PART_INFO_START:
+ snprintf(buf, sizeof(buf), LBAF, info.start);
+ break;
+ case CMD_PART_INFO_SIZE:
+ snprintf(buf, sizeof(buf), LBAF, info.size);
+ break;
+ default:
+ printf("** Unknown cmd_part_info value: %d\n", param);
+ return 1;
+ }
if (argc > 3)
env_set(argv[3], buf);
return 0;
}
-static int do_part_size(int argc, char * const argv[])
+static int do_part_start(int argc, char * const argv[])
{
- struct blk_desc *desc;
- disk_partition_t info;
- char buf[512] = { 0 };
- int part;
- int err;
- int ret;
-
- if (argc < 3)
- return CMD_RET_USAGE;
- if (argc > 4)
- return CMD_RET_USAGE;
-
- part = simple_strtoul(argv[2], NULL, 0);
-
- ret = blk_get_device_by_str(argv[0], argv[1], &desc);
- if (ret < 0)
- return 1;
-
- err = part_get_info(desc, part, &info);
- if (err)
- return 1;
-
- snprintf(buf, sizeof(buf), LBAF, info.size);
-
- if (argc > 3)
- env_set(argv[3], buf);
- else
- printf("%s\n", buf);
+ return do_part_info(argc, argv, CMD_PART_INFO_START);
+}
- return 0;
+static int do_part_size(int argc, char * const argv[])
+{
+ return do_part_info(argc, argv, CMD_PART_INFO_SIZE);
}
static int do_part(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
" flags can be -bootable (list only bootable partitions)\n"
"part start <interface> <dev> <part> <varname>\n"
" - set environment variable to the start of the partition (in blocks)\n"
+ " part can be either partition number or partition name\n"
"part size <interface> <dev> <part> <varname>\n"
- " - set environment variable to the size of the partition (in blocks)"
+ " - set environment variable to the size of the partition (in blocks)\n"
+ " part can be either partition number or partition name"
);
long get_ram_size(long *base, long maxsize)
{
volatile long *addr;
- long save[32];
+ long save[31];
+ long save_base;
long cnt;
long val;
long size;
addr = base;
sync();
- save[i] = *addr;
+ save_base = *addr;
sync();
*addr = 0;
if ((val = *addr) != 0) {
/* Restore the original data before leaving the function. */
sync();
- *addr = save[i];
+ *base = save_base;
for (cnt = 1; cnt < maxsize / sizeof(long); cnt <<= 1) {
addr = base + cnt;
sync();
addr = base + cnt;
*addr = save[--i];
}
+ /* warning: don't restore save_base in this case,
+ * it is already done in the loop because
+ * base and base+size share the same physical memory
+ * and *base is saved after *(base+size) modification
+ * in first loop
+ */
return (size);
}
}
+ *base = save_base;
return (maxsize);
}
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=480
CONFIG_DRAM_EMR1=4
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=432
CONFIG_MMC0_CD_PIN="PG1"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_EMR1=0
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_EMR1=0
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_MMC0_CD_PIN="PH1"
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=384
+CONFIG_MMC0_CD_PIN="PH1"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_USB0_VBUS_PIN="PC17"
+CONFIG_USB0_VBUS_DET="PH5"
+CONFIG_I2C1_ENABLE=y
+CONFIG_SATAPWR="PC3"
+CONFIG_GMAC_TX_DELAY=4
+CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olimex-som204-evb-emmc"
+CONFIG_AHCI=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_PARTITION_UUIDS is not set
+CONFIG_SCSI_AHCI=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_ADDR=3
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_RGMII=y
+CONFIG_SUN7I_GMAC=y
+CONFIG_AXP_ALDO3_VOLT=2800
+CONFIG_AXP_ALDO4_VOLT=2800
+CONFIG_SCSI=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_MUSB_GADGET=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
--- /dev/null
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN7I=y
+CONFIG_DRAM_CLK=384
+CONFIG_MMC0_CD_PIN="PH1"
+CONFIG_USB0_VBUS_PIN="PC17"
+CONFIG_USB0_VBUS_DET="PH5"
+CONFIG_I2C1_ENABLE=y
+CONFIG_SATAPWR="PC3"
+CONFIG_GMAC_TX_DELAY=4
+CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-olimex-som204-evb"
+CONFIG_AHCI=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+CONFIG_SPL_I2C_SUPPORT=y
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_ISO_PARTITION is not set
+# CONFIG_SPL_PARTITION_UUIDS is not set
+CONFIG_SCSI_AHCI=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_PHY_ADDR=3
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_RGMII=y
+CONFIG_SUN7I_GMAC=y
+CONFIG_AXP_ALDO3_VOLT=2800
+CONFIG_AXP_ALDO4_VOLT=2800
+CONFIG_SCSI=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_MUSB_GADGET=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_CONS_INDEX=1
CONFIG_MACH_SUN8I_A33=y
CONFIG_DRAM_CLK=432
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_ZQ=123
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=432
CONFIG_MMC0_CD_PIN="PG0"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_EMR1=0
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=432
CONFIG_USB1_VBUS_PIN="PG13"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN8I_R40=y
CONFIG_DRAM_CLK=576
CONFIG_DRAM_ZQ=3881979
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_MACPWR="PH23"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_CONS_INDEX=1
CONFIG_MACH_SUN8I_A33=y
CONFIG_DRAM_CLK=600
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_MACPWR="PH23"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y
CONFIG_USB0_VBUS_PIN="PB10"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_CLK=432
CONFIG_USB1_VBUS_PIN=""
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_EMR1=4
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_CLK=240
CONFIG_DRAM_ZQ=251
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=480
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x2a000000
CONFIG_MACH_SUN9I=y
CONFIG_DRAM_CLK=672
CONFIG_MMC0_CD_PIN="PH18"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=480
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN8I_A83T=y
CONFIG_DRAM_CLK=672
CONFIG_DRAM_ZQ=15355
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_EMR1=0
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=408
CONFIG_MMC0_CD_PIN="PG0"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_ZQ=251
CONFIG_USB1_VBUS_PIN="PH24"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_EMR1=4
CONFIG_USB0_VBUS_PIN="PB09"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=480
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_MACPWR="PH23"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x42e00000
CONFIG_MACH_SUN8I_V3S=y
CONFIG_DRAM_CLK=360
CONFIG_DRAM_ZQ=14779
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_ZQ=122
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=480
CONFIG_DRAM_ZQ=122
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN4I=y
CONFIG_USB1_VBUS_PIN=""
CONFIG_USB2_VBUS_PIN=""
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-mk808c"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:60000,le:60,ri:160,up:13,lo:12,hs:100,vs:10,sync:3,vmode:0"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_CLK=360
CONFIG_DRAM_ZQ=122
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN4I=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-marsboard"
CONFIG_AHCI=y
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_ZQ=120
CONFIG_INITIAL_USB_SCAN_DELAY=2000
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN4I=y
CONFIG_MACPWR="PH15"
CONFIG_VIDEO_VGA=y
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_ZQ=120
CONFIG_USB1_VBUS_PIN="PC27"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_ZQ=122
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_ZQ=120
CONFIG_USB1_VBUS_PIN="PC27"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x2a000000
CONFIG_MACH_SUN9I=y
CONFIG_DRAM_CLK=672
CONFIG_MMC0_CD_PIN="PH18"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN4I=y
CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_VIDEO_COMPOSITE=y
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN8I_A33=y
CONFIG_DRAM_CLK=600
CONFIG_DRAM_ZQ=15291
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_MACPWR="PH23"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_MACPWR="PH23"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_ZQ=251
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_CONS_INDEX=1
CONFIG_MACH_SUN8I_A33=y
CONFIG_DRAM_CLK=552
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=672
CONFIG_DRAM_ZQ=3881979
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_CLK=432
CONFIG_USB1_VBUS_PIN=""
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN8I_A83T=y
CONFIG_DRAM_TYPE=7
CONFIG_DRAM_CLK=480
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x2a000000
CONFIG_MACH_SUN9I=y
CONFIG_DRAM_CLK=600
CONFIG_DRAM_ZQ=3881915
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_EMR1=0
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_VIDEO_VGA=y
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=432
CONFIG_MMC0_CD_PIN="PB3"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=408
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_CLK=420
CONFIG_DRAM_ZQ=251
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN50I=y
CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_AUTOBOOT_DELAY_STR="d"
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
CONFIG_CMD_SPL=y
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=384
CONFIG_DRAM_EMR1=4
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=432
CONFIG_MACPWR="PH23"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN50I=y
CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
CONFIG_MMC0_CD_PIN="PH13"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_ZQ=251
CONFIG_NAND=y
CONFIG_SPL_NAND_SIMPLE=y
CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR=31
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_LPC32XX_SSP=y
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=408
CONFIG_MMC0_CD_PIN="PG0"
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc dra71-evm dra76-evm"
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_OF_SPL_REMOVE_PROPS="clocks clock-names interrupt-parent"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_SPL_MMC_HS200_SUPPORT=y
CONFIG_MMC_OMAP_HS=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN4I=y
CONFIG_MMC0_CD_PIN="PH1"
CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN8I_A33=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_ZQ=15291
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN8I_A23=y
CONFIG_DRAM_CLK=480
CONFIG_DRAM_ZQ=32767
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN8I_A83T=y
CONFIG_DRAM_CLK=480
CONFIG_DRAM_ZQ=15355
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_MACPWR="PH21"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_EMR1=4
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_ZQ=127
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=408
CONFIG_USB0_VBUS_PIN="PG12"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN8I_A33=y
CONFIG_DRAM_CLK=456
CONFIG_DRAM_ZQ=15291
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN7I=y
CONFIG_DRAM_CLK=384
CONFIG_OLD_SUNXI_KERNEL_COMPAT=y
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_EMR1=4
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN8I_A23=y
CONFIG_DRAM_CLK=552
CONFIG_DRAM_ZQ=63351
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_EMR1=4
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=432
CONFIG_MMC0_CD_PIN="PG0"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_EMR1=4
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_CLK=384
CONFIG_DRAM_ZQ=251
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=312
CONFIG_MACPWR="PH19"
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
+CONFIG_PHY_ADDR=8
CONFIG_PHY_MESON_GXL=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
+CONFIG_PHY_ADDR=8
CONFIG_PHY_MESON_GXL=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=672
CONFIG_DRAM_ZQ=3881979
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN6I=y
CONFIG_DRAM_ZQ=251
CONFIG_MACPWR="PA21"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_EMR1=0
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN4I=y
CONFIG_USB2_VBUS_PIN="PH12"
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN4I=y
CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802ii"
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN50I=y
CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-nanopi-a64"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_ZQ=3881979
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_ZQ=3881979
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN50I_H5=y
CONFIG_DRAM_CLK=672
CONFIG_DRAM_ZQ=3881977
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_ZQ=3881979
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_ZQ=3881979
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN50I_H5=y
CONFIG_DRAM_CLK=408
CONFIG_DRAM_ZQ=3881977
CONFIG_TARGET_OMAP3_BEAGLE=y
CONFIG_DEFAULT_DEVICE_TREE="omap3-beagle"
CONFIG_DISTRO_DEFAULTS=y
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DEFAULT_FDT_FILE="omap3-beagle.dtb"
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
+# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
+CONFIG_SYS_PROMPT="BeagleBoard # "
CONFIG_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x82000000
CONFIG_CMD_SPL=y
-CONFIG_CMD_SPL_NAND_OFS=0x240000
+CONFIG_CMD_SPL_NAND_OFS=0x280000
+CONFIG_CMD_SPL_WRITE_SIZE=0x20000
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nand0=nand"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=nand:512k(x-loader),1920k(u-boot),128k(u-boot-env),4m(kernel),-(fs)"
+CONFIG_CMD_FS_UUID=y
+CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(spl),1920k(u-boot),128k(u-boot-env),128k(dtb),6m(kernel),-(rootfs)"
+CONFIG_CMD_UBI=y
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+CONFIG_SPL_PARTITION_UUIDS=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_NAND=y
+CONFIG_SPL_DM=y
CONFIG_LED_STATUS=y
CONFIG_LED_STATUS0=y
CONFIG_LED_STATUS_BIT=1
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
CONFIG_SPL_NAND_SIMPLE=y
+CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OMAP3=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_OMAP2PLUS=y
CONFIG_TWL4030_USB=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_FAT_WRITE=y
CONFIG_BCH=y
+CONFIG_SPL_OF_LIBFDT=y
+# CONFIG_EFI_LOADER is not set
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80100000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SYS_MPUCLK=720
CONFIG_TARGET_OMAP3_EVM=y
CONFIG_DEFAULT_DEVICE_TREE="omap3-evm"
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_DEFAULT_FDT_FILE="omap3-evm.dtb"
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
-CONFIG_SPL_SYS_MALLOC_SIMPLE=y
-CONFIG_SPL_ENV_SUPPORT=y
# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_PROMPT="OMAP3_EVM # "
-# CONFIG_CMD_IMI is not set
+CONFIG_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82000000
+CONFIG_CMD_SPL=y
+CONFIG_CMD_SPL_NAND_OFS=0x280000
+CONFIG_CMD_SPL_WRITE_SIZE=0x20000
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FS_UUID=y
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(spl),1792k(u-boot),128k(dtb),128k(u-boot-env),6m(kernel),-(rootfs)"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(spl),1920k(u-boot),128k(u-boot-env),128k(dtb),6m(kernel),-(rootfs)"
CONFIG_CMD_UBI=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SPL_DM=y
CONFIG_MMC_OMAP_HS=y
-CONFIG_MTD=y
CONFIG_NAND=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
+CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
CONFIG_SPL_NAND_SIMPLE=y
CONFIG_NETDEVICES=y
CONFIG_SMC911X=y
CONFIG_SMC911X_BASE=0x2C000000
CONFIG_SMC911X_32_BIT=y
+CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_OMAP3=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_OMAP2PLUS=y
+CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_USB_GADGET_PRODUCT_NUM=0x5678
-CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_ETHER=y
CONFIG_FAT_WRITE=y
CONFIG_BCH=y
-CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SPL_OF_LIBFDT=y
# CONFIG_EFI_LOADER is not set
CONFIG_ARM=y
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=672
CONFIG_DRAM_ZQ=3881979
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=672
CONFIG_DRAM_ZQ=3881979
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=672
CONFIG_DRAM_ZQ=3881979
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN50I_H5=y
CONFIG_DRAM_CLK=672
CONFIG_DRAM_ZQ=3881977
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=624
CONFIG_DRAM_ZQ=3881979
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=624
CONFIG_DRAM_ZQ=3881979
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=672
CONFIG_DRAM_ZQ=3881979
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=672
CONFIG_DRAM_ZQ=3881979
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN50I_H5=y
CONFIG_DRAM_CLK=672
CONFIG_DRAM_ZQ=3881977
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN50I=y
CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-orangepi-win"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN8I_H3=y
CONFIG_DRAM_CLK=624
CONFIG_DRAM_ZQ=3881979
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN50I_H5=y
CONFIG_DRAM_CLK=672
CONFIG_DRAM_ZQ=3881977
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
+CONFIG_PHY_ADDR=8
CONFIG_PHY_MESON_GXL=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN8I_A33=y
CONFIG_DRAM_CLK=600
CONFIG_DRAM_ZQ=15291
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN50I=y
CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-plus"
# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_OF_LIST="sun50i-a64-pine64 sun50i-a64-pine64-plus"
CONFIG_SUN8I_EMAC=y
CONFIG_USB_EHCI_HCD=y
CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN8I_A23=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_ZQ=63351
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN8I_A23=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_ZQ=63351
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=432
CONFIG_USB0_VBUS_PIN="PB9"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=384
CONFIG_MMC0_CD_PIN="PG0"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN8I_A23=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_ZQ=63306
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN8I_A33=y
CONFIG_DRAM_CLK=456
CONFIG_DRAM_ZQ=15291
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN8I_A33=y
CONFIG_DRAM_CLK=456
CONFIG_DRAM_ZQ=15291
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN5I=y
CONFIG_DRAM_CLK=384
CONFIG_USB1_VBUS_PIN="PG13"
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN50I=y
CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
-# CONFIG_DOS_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
# CONFIG_BLK is not set
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
-# CONFIG_DOS_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_OF_EMBED=y
# CONFIG_BLK is not set
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
-# CONFIG_DOS_PARTITION is not set
+# CONFIG_SPL_DOS_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN8I_A23=y
CONFIG_DRAM_CLK=552
CONFIG_DRAM_ZQ=63351
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN4I=y
CONFIG_DRAM_CLK=432
CONFIG_DRAM_EMR1=4
CONFIG_ARM=y
CONFIG_ARCH_SUNXI=y
-CONFIG_SYS_TEXT_BASE=0x4a000000
CONFIG_MACH_SUN8I_A83T=y
CONFIG_DRAM_TYPE=7
CONFIG_DRAM_CLK=648
CONFIG_LED_GPIO=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_GMAC_ROCKCHIP=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
# CONFIG_SPL_PINCTRL_FULL is not set
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_HAVE_BLOCK_DEVICE
-static struct part_driver *part_driver_lookup_type(int part_type)
+static struct part_driver *part_driver_lookup_type(struct blk_desc *dev_desc)
{
struct part_driver *drv =
ll_entry_start(struct part_driver, part_driver);
const int n_ents = ll_entry_count(struct part_driver, part_driver);
struct part_driver *entry;
- for (entry = drv; entry != drv + n_ents; entry++) {
- if (part_type == entry->part_type)
- return entry;
+ if (dev_desc->part_type == PART_TYPE_UNKNOWN) {
+ for (entry = drv; entry != drv + n_ents; entry++) {
+ int ret;
+
+ ret = entry->test(dev_desc);
+ if (!ret) {
+ dev_desc->part_type = entry->part_type;
+ return entry;
+ }
+ }
+ } else {
+ for (entry = drv; entry != drv + n_ents; entry++) {
+ if (dev_desc->part_type == entry->part_type)
+ return entry;
+ }
}
/* Not found */
return NULL;
}
+#ifdef CONFIG_HAVE_BLOCK_DEVICE
static struct blk_desc *get_dev_hwpart(const char *ifname, int dev, int hwpart)
{
struct blk_desc *dev_desc;
{
struct part_driver *drv;
- drv = part_driver_lookup_type(dev_desc->part_type);
+ drv = part_driver_lookup_type(dev_desc);
if (!drv) {
printf("## Unknown partition table type %x\n",
dev_desc->part_type);
info->type_guid[0] = 0;
#endif
- drv = part_driver_lookup_type(dev_desc->part_type);
+ drv = part_driver_lookup_type(dev_desc);
if (!drv) {
debug("## Unknown partition table type %x\n",
dev_desc->part_type);
int part_get_info_by_name_type(struct blk_desc *dev_desc, const char *name,
disk_partition_t *info, int part_type)
{
- struct part_driver *first_drv =
- ll_entry_start(struct part_driver, part_driver);
- const int n_drvs = ll_entry_count(struct part_driver, part_driver);
struct part_driver *part_drv;
-
- for (part_drv = first_drv; part_drv != first_drv + n_drvs; part_drv++) {
- int ret;
- int i;
- for (i = 1; i < part_drv->max_entries; i++) {
- if (part_type >= 0 && part_type != part_drv->part_type)
- break;
- ret = part_drv->get_info(dev_desc, i, info);
- if (ret != 0) {
- /* no more entries in table */
- break;
- }
- if (strcmp(name, (const char *)info->name) == 0) {
- /* matched */
- return i;
- }
+ int ret;
+ int i;
+
+ part_drv = part_driver_lookup_type(dev_desc);
+ if (!part_drv)
+ return -1;
+ for (i = 1; i < part_drv->max_entries; i++) {
+ ret = part_drv->get_info(dev_desc, i, info);
+ if (ret != 0) {
+ /* no more entries in table */
+ break;
+ }
+ if (strcmp(name, (const char *)info->name) == 0) {
+ /* matched */
+ return i;
}
}
+
return -1;
}
#define RCC_CFGR_PPRE1_SHIFT 10
#define RCC_CFGR_PPRE2_SHIFT 13
-#define RCC_PLLCFGR_PLLSAIN_MASK GENMASK(14, 6)
-#define RCC_PLLCFGR_PLLSAIP_MASK GENMASK(17, 16)
+#define RCC_PLLSAICFGR_PLLSAIN_MASK GENMASK(14, 6)
+#define RCC_PLLSAICFGR_PLLSAIP_MASK GENMASK(17, 16)
+#define RCC_PLLSAICFGR_PLLSAIQ_MASK GENMASK(27, 24)
+#define RCC_PLLSAICFGR_PLLSAIR_MASK GENMASK(30, 28)
#define RCC_PLLSAICFGR_PLLSAIN_SHIFT 6
#define RCC_PLLSAICFGR_PLLSAIP_SHIFT 16
+#define RCC_PLLSAICFGR_PLLSAIQ_SHIFT 24
+#define RCC_PLLSAICFGR_PLLSAIR_SHIFT 28
#define RCC_PLLSAICFGR_PLLSAIP_4 BIT(16)
#define RCC_PLLSAICFGR_PLLSAIQ_4 BIT(26)
-#define RCC_PLLSAICFGR_PLLSAIR_2 BIT(29)
+#define RCC_PLLSAICFGR_PLLSAIR_3 BIT(29) | BIT(28)
+#define RCC_DCKCFGRX_TIMPRE BIT(24)
#define RCC_DCKCFGRX_CK48MSEL BIT(27)
#define RCC_DCKCFGRX_SDMMC1SEL BIT(28)
#define RCC_DCKCFGR2_SDMMC2SEL BIT(29)
+#define RCC_DCKCFGR_PLLSAIDIVR_SHIFT 16
+#define RCC_DCKCFGR_PLLSAIDIVR_MASK GENMASK(17, 16)
+#define RCC_DCKCFGR_PLLSAIDIVR_2 0
+
/*
* RCC AHB1ENR specific definitions
*/
#define RCC_APB2ENR_SYSCFGEN BIT(14)
#define RCC_APB2ENR_SAI1EN BIT(22)
-enum periph_clock {
- TIMER2_CLOCK_CFG,
+enum pllsai_div {
+ PLLSAIP,
+ PLLSAIQ,
+ PLLSAIR,
};
static const struct stm32_clk_info stm32f4_clk_info = {
unsigned long hse_rate;
};
+#ifdef CONFIG_VIDEO_STM32
+static const u8 plldivr_table[] = { 0, 0, 2, 3, 4, 5, 6, 7 };
+#endif
+static const u8 pllsaidivr_table[] = { 2, 4, 8, 16 };
+
static int configure_clocks(struct udevice *dev)
{
struct stm32_clk *priv = dev_get_priv(dev);
struct stm32_rcc_regs *regs = priv->base;
struct stm32_pwr_regs *pwr = priv->pwr_regs;
struct pll_psc *sys_pll_psc = &priv->info.sys_pll_psc;
- u32 pllsaicfgr = 0;
/* Reset RCC configuration */
setbits_le32(®s->cr, RCC_CR_HSION);
clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLQ_MASK,
sys_pll_psc->pll_q << RCC_PLLCFGR_PLLQ_SHIFT);
- /* Configure the SAI PLL to get a 48 MHz source */
- pllsaicfgr = RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIQ_4 |
- RCC_PLLSAICFGR_PLLSAIP_4;
- pllsaicfgr |= 192 << RCC_PLLSAICFGR_PLLSAIN_SHIFT;
- writel(pllsaicfgr, ®s->pllsaicfgr);
-
- /* Enable the main PLL */
- setbits_le32(®s->cr, RCC_CR_PLLON);
- while (!(readl(®s->cr) & RCC_CR_PLLRDY))
- ;
-
+ /* configure SDMMC clock */
if (priv->info.v2) { /*stm32f7 case */
- /* select PLLSAI as 48MHz clock source */
- setbits_le32(®s->dckcfgr2, RCC_DCKCFGRX_CK48MSEL);
+ /* select PLLQ as 48MHz clock source */
+ clrbits_le32(®s->dckcfgr2, RCC_DCKCFGRX_CK48MSEL);
/* select 48MHz as SDMMC1 clock source */
clrbits_le32(®s->dckcfgr2, RCC_DCKCFGRX_SDMMC1SEL);
/* select 48MHz as SDMMC2 clock source */
clrbits_le32(®s->dckcfgr2, RCC_DCKCFGR2_SDMMC2SEL);
} else { /* stm32f4 case */
- /* select PLLSAI as 48MHz clock source */
- setbits_le32(®s->dckcfgr, RCC_DCKCFGRX_CK48MSEL);
+ /* select PLLQ as 48MHz clock source */
+ clrbits_le32(®s->dckcfgr, RCC_DCKCFGRX_CK48MSEL);
/* select 48MHz as SDMMC1 clock source */
clrbits_le32(®s->dckcfgr, RCC_DCKCFGRX_SDMMC1SEL);
}
- /* Enable the SAI PLL */
+#ifdef CONFIG_VIDEO_STM32
+ /*
+ * Configure the SAI PLL to generate LTDC pixel clock
+ */
+ clrsetbits_le32(®s->pllsaicfgr, RCC_PLLSAICFGR_PLLSAIR_MASK,
+ RCC_PLLSAICFGR_PLLSAIR_3);
+ clrsetbits_le32(®s->pllsaicfgr, RCC_PLLSAICFGR_PLLSAIN_MASK,
+ 195 << RCC_PLLSAICFGR_PLLSAIN_SHIFT);
+
+ clrsetbits_le32(®s->dckcfgr, RCC_DCKCFGR_PLLSAIDIVR_MASK,
+ RCC_DCKCFGR_PLLSAIDIVR_2 << RCC_DCKCFGR_PLLSAIDIVR_SHIFT);
+#endif
+ /* Enable the main PLL */
+ setbits_le32(®s->cr, RCC_CR_PLLON);
+ while (!(readl(®s->cr) & RCC_CR_PLLRDY))
+ ;
+
+#ifdef CONFIG_VIDEO_STM32
+/* Enable the SAI PLL */
setbits_le32(®s->cr, RCC_CR_PLLSAION);
while (!(readl(®s->cr) & RCC_CR_PLLSAIRDY))
;
-
+#endif
setbits_le32(®s->apb1enr, RCC_APB1ENR_PWREN);
if (priv->info.has_overdrive) {
while ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) !=
RCC_CFGR_SWS_PLL)
;
- /* gate the SAI clock, needed for MMC 1&2 clocks */
- setbits_le32(®s->apb2enr, RCC_APB2ENR_SAI1EN);
#ifdef CONFIG_ETH_DESIGNWARE
/* gate the SYSCFG clock, needed to set RMII ethernet interface */
return 0;
}
-static unsigned long stm32_clk_pll48clk_rate(struct stm32_clk *priv,
- u32 sysclk)
+static bool stm32_clk_get_ck48msel(struct stm32_clk *priv)
{
struct stm32_rcc_regs *regs = priv->base;
- u16 pllq, pllm, pllsain, pllsaip;
- bool pllsai;
-
- pllq = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLQ_MASK)
- >> RCC_PLLCFGR_PLLQ_SHIFT;
if (priv->info.v2) /*stm32f7 case */
- pllsai = readl(®s->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL;
+ return readl(®s->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL;
else
- pllsai = readl(®s->dckcfgr) & RCC_DCKCFGRX_CK48MSEL;
- if (pllsai) {
- /* PLL48CLK is selected from PLLSAI, get PLLSAI value */
- pllm = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
- pllsain = ((readl(®s->pllsaicfgr) & RCC_PLLCFGR_PLLSAIN_MASK)
- >> RCC_PLLSAICFGR_PLLSAIN_SHIFT);
- pllsaip = ((((readl(®s->pllsaicfgr) & RCC_PLLCFGR_PLLSAIP_MASK)
- >> RCC_PLLSAICFGR_PLLSAIP_SHIFT) + 1) << 1);
- return ((priv->hse_rate / pllm) * pllsain) / pllsaip;
+ return readl(®s->dckcfgr) & RCC_DCKCFGRX_CK48MSEL;
+}
+
+static unsigned long stm32_clk_get_pllsai_vco_rate(struct stm32_clk *priv)
+{
+ struct stm32_rcc_regs *regs = priv->base;
+ u16 pllm, pllsain;
+
+ pllm = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
+ pllsain = ((readl(®s->pllsaicfgr) & RCC_PLLSAICFGR_PLLSAIN_MASK)
+ >> RCC_PLLSAICFGR_PLLSAIN_SHIFT);
+
+ return ((priv->hse_rate / pllm) * pllsain);
+}
+
+static unsigned long stm32_clk_get_pllsai_rate(struct stm32_clk *priv,
+ enum pllsai_div output)
+{
+ struct stm32_rcc_regs *regs = priv->base;
+ u16 pll_div_output;
+
+ switch (output) {
+ case PLLSAIP:
+ pll_div_output = ((((readl(®s->pllsaicfgr)
+ & RCC_PLLSAICFGR_PLLSAIP_MASK)
+ >> RCC_PLLSAICFGR_PLLSAIP_SHIFT) + 1) << 1);
+ break;
+ case PLLSAIQ:
+ pll_div_output = (readl(®s->pllsaicfgr)
+ & RCC_PLLSAICFGR_PLLSAIQ_MASK)
+ >> RCC_PLLSAICFGR_PLLSAIQ_SHIFT;
+ break;
+ case PLLSAIR:
+ pll_div_output = (readl(®s->pllsaicfgr)
+ & RCC_PLLSAICFGR_PLLSAIR_MASK)
+ >> RCC_PLLSAICFGR_PLLSAIR_SHIFT;
+ break;
+ default:
+ pr_err("incorrect PLLSAI output %d\n", output);
+ return -EINVAL;
}
- /* PLL48CLK is selected from PLLQ */
- return sysclk / pllq;
+
+ return (stm32_clk_get_pllsai_vco_rate(priv) / pll_div_output);
}
-static unsigned long stm32_clk_get_rate(struct clk *clk)
+static bool stm32_get_timpre(struct stm32_clk *priv)
{
- struct stm32_clk *priv = dev_get_priv(clk->dev);
struct stm32_rcc_regs *regs = priv->base;
- u32 sysclk = 0;
- u32 shift = 0;
- u16 pllm, plln, pllp;
+ u32 val;
+
+ if (priv->info.v2) /*stm32f7 case */
+ val = readl(®s->dckcfgr2);
+ else
+ val = readl(®s->dckcfgr);
+ /* get timer prescaler */
+ return !!(val & RCC_DCKCFGRX_TIMPRE);
+}
+
+static u32 stm32_get_hclk_rate(struct stm32_rcc_regs *regs, u32 sysclk)
+{
+ u8 shift;
/* Prescaler table lookups for clock computation */
u8 ahb_psc_table[16] = {
0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
};
+
+ shift = ahb_psc_table[(
+ (readl(®s->cfgr) & RCC_CFGR_AHB_PSC_MASK)
+ >> RCC_CFGR_HPRE_SHIFT)];
+
+ return sysclk >> shift;
+};
+
+static u8 stm32_get_apb_shift(struct stm32_rcc_regs *regs, enum apb apb)
+{
+ /* Prescaler table lookups for clock computation */
u8 apb_psc_table[8] = {
0, 0, 0, 0, 1, 2, 3, 4
};
+ if (apb == APB1)
+ return apb_psc_table[(
+ (readl(®s->cfgr) & RCC_CFGR_APB1_PSC_MASK)
+ >> RCC_CFGR_PPRE1_SHIFT)];
+ else /* APB2 */
+ return apb_psc_table[(
+ (readl(®s->cfgr) & RCC_CFGR_APB2_PSC_MASK)
+ >> RCC_CFGR_PPRE2_SHIFT)];
+};
+
+static u32 stm32_get_timer_rate(struct stm32_clk *priv, u32 sysclk,
+ enum apb apb)
+{
+ struct stm32_rcc_regs *regs = priv->base;
+ u8 shift = stm32_get_apb_shift(regs, apb);
+
+ if (stm32_get_timpre(priv))
+ /*
+ * if APB prescaler is configured to a
+ * division factor of 1, 2 or 4
+ */
+ switch (shift) {
+ case 0:
+ case 1:
+ case 2:
+ return stm32_get_hclk_rate(regs, sysclk);
+ default:
+ return (sysclk >> shift) * 4;
+ }
+ else
+ /*
+ * if APB prescaler is configured to a
+ * division factor of 1
+ */
+ if (shift == 0)
+ return sysclk;
+ else
+ return (sysclk >> shift) * 2;
+};
+
+static ulong stm32_clk_get_rate(struct clk *clk)
+{
+ struct stm32_clk *priv = dev_get_priv(clk->dev);
+ struct stm32_rcc_regs *regs = priv->base;
+ u32 sysclk = 0;
+ u32 vco;
+ u32 sdmmcxsel_bit;
+ u32 saidivr;
+ u32 pllsai_rate;
+ u16 pllm, plln, pllp, pllq;
+
if ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) ==
RCC_CFGR_SWS_PLL) {
pllm = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
>> RCC_PLLCFGR_PLLN_SHIFT);
pllp = ((((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
>> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
- sysclk = ((priv->hse_rate / pllm) * plln) / pllp;
+ pllq = ((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLQ_MASK)
+ >> RCC_PLLCFGR_PLLQ_SHIFT);
+ vco = (priv->hse_rate / pllm) * plln;
+ sysclk = vco / pllp;
} else {
return -EINVAL;
}
* AHB1, AHB2 and AHB3
*/
case STM32F7_AHB1_CLOCK(GPIOA) ... STM32F7_AHB3_CLOCK(QSPI):
- shift = ahb_psc_table[(
- (readl(®s->cfgr) & RCC_CFGR_AHB_PSC_MASK)
- >> RCC_CFGR_HPRE_SHIFT)];
- return sysclk >>= shift;
+ return stm32_get_hclk_rate(regs, sysclk);
/* APB1 CLOCK */
case STM32F7_APB1_CLOCK(TIM2) ... STM32F7_APB1_CLOCK(UART8):
- shift = apb_psc_table[(
- (readl(®s->cfgr) & RCC_CFGR_APB1_PSC_MASK)
- >> RCC_CFGR_PPRE1_SHIFT)];
- return sysclk >>= shift;
+ /* For timer clock, an additionnal prescaler is used*/
+ switch (clk->id) {
+ case STM32F7_APB1_CLOCK(TIM2):
+ case STM32F7_APB1_CLOCK(TIM3):
+ case STM32F7_APB1_CLOCK(TIM4):
+ case STM32F7_APB1_CLOCK(TIM5):
+ case STM32F7_APB1_CLOCK(TIM6):
+ case STM32F7_APB1_CLOCK(TIM7):
+ case STM32F7_APB1_CLOCK(TIM12):
+ case STM32F7_APB1_CLOCK(TIM13):
+ case STM32F7_APB1_CLOCK(TIM14):
+ return stm32_get_timer_rate(priv, sysclk, APB1);
+ }
+ return (sysclk >> stm32_get_apb_shift(regs, APB1));
+
/* APB2 CLOCK */
- case STM32F7_APB2_CLOCK(TIM1) ... STM32F7_APB2_CLOCK(LTDC):
+ case STM32F7_APB2_CLOCK(TIM1) ... STM32F7_APB2_CLOCK(DSI):
+ switch (clk->id) {
/*
* particular case for SDMMC1 and SDMMC2 :
* 48Mhz source clock can be from main PLL or from
- * SAI PLL
+ * PLLSAIP
*/
- switch (clk->id) {
case STM32F7_APB2_CLOCK(SDMMC1):
- if (readl(®s->dckcfgr2) & RCC_DCKCFGRX_SDMMC1SEL)
- /* System clock is selected as SDMMC1 clock */
- return sysclk;
- else
- return stm32_clk_pll48clk_rate(priv, sysclk);
- break;
case STM32F7_APB2_CLOCK(SDMMC2):
- if (readl(®s->dckcfgr2) & RCC_DCKCFGR2_SDMMC2SEL)
- /* System clock is selected as SDMMC2 clock */
+ if (clk->id == STM32F7_APB2_CLOCK(SDMMC1))
+ sdmmcxsel_bit = RCC_DCKCFGRX_SDMMC1SEL;
+ else
+ sdmmcxsel_bit = RCC_DCKCFGR2_SDMMC2SEL;
+
+ if (readl(®s->dckcfgr2) & sdmmcxsel_bit)
+ /* System clock is selected as SDMMC1 clock */
return sysclk;
+ /*
+ * 48 MHz can be generated by either PLLSAIP
+ * or by PLLQ depending of CK48MSEL bit of RCC_DCKCFGR
+ */
+ if (stm32_clk_get_ck48msel(priv))
+ return stm32_clk_get_pllsai_rate(priv, PLLSAIP);
else
- return stm32_clk_pll48clk_rate(priv, sysclk);
+ return (vco / pllq);
break;
+
+ /* For timer clock, an additionnal prescaler is used*/
+ case STM32F7_APB2_CLOCK(TIM1):
+ case STM32F7_APB2_CLOCK(TIM8):
+ case STM32F7_APB2_CLOCK(TIM9):
+ case STM32F7_APB2_CLOCK(TIM10):
+ case STM32F7_APB2_CLOCK(TIM11):
+ return stm32_get_timer_rate(priv, sysclk, APB2);
+ break;
+
+ /* particular case for LTDC clock */
+ case STM32F7_APB2_CLOCK(LTDC):
+ saidivr = readl(®s->dckcfgr);
+ saidivr = (saidivr & RCC_DCKCFGR_PLLSAIDIVR_MASK)
+ >> RCC_DCKCFGR_PLLSAIDIVR_SHIFT;
+ pllsai_rate = stm32_clk_get_pllsai_rate(priv, PLLSAIR);
+
+ return pllsai_rate / pllsaidivr_table[saidivr];
}
+ return (sysclk >> stm32_get_apb_shift(regs, APB2));
- shift = apb_psc_table[(
- (readl(®s->cfgr) & RCC_CFGR_APB2_PSC_MASK)
- >> RCC_CFGR_PPRE2_SHIFT)];
- return sysclk >>= shift;
default:
pr_err("clock index %ld out of range\n", clk->id);
return -EINVAL;
static ulong stm32_set_rate(struct clk *clk, ulong rate)
{
+#ifdef CONFIG_VIDEO_STM32
+ struct stm32_clk *priv = dev_get_priv(clk->dev);
+ struct stm32_rcc_regs *regs = priv->base;
+ u32 pllsair_rate, pllsai_vco_rate, current_rate;
+ u32 best_div, best_diff, diff;
+ u16 div;
+ u8 best_plldivr, best_pllsaidivr;
+ u8 i, j;
+ bool found = false;
+
+ /* Only set_rate for LTDC clock is implemented */
+ if (clk->id != STM32F7_APB2_CLOCK(LTDC)) {
+ pr_err("set_rate not implemented for clock index %ld\n",
+ clk->id);
+ return 0;
+ }
+
+ if (rate == stm32_clk_get_rate(clk))
+ /* already set to requested rate */
+ return rate;
+
+ /* get the current PLLSAIR output freq */
+ pllsair_rate = stm32_clk_get_pllsai_rate(priv, PLLSAIR);
+ best_div = pllsair_rate / rate;
+
+ /* look into pllsaidivr_table if this divider is available*/
+ for (i = 0 ; i < sizeof(pllsaidivr_table); i++)
+ if (best_div == pllsaidivr_table[i]) {
+ /* set pll_saidivr with found value */
+ clrsetbits_le32(®s->dckcfgr,
+ RCC_DCKCFGR_PLLSAIDIVR_MASK,
+ pllsaidivr_table[i]);
+ return rate;
+ }
+
+ /*
+ * As no pllsaidivr value is suitable to obtain requested freq,
+ * test all combination of pllsaidivr * pllsair and find the one
+ * which give freq closest to requested rate.
+ */
+
+ pllsai_vco_rate = stm32_clk_get_pllsai_vco_rate(priv);
+ best_diff = ULONG_MAX;
+ best_pllsaidivr = 0;
+ best_plldivr = 0;
+ /*
+ * start at index 2 of plldivr_table as divider value at index 0
+ * and 1 are 0)
+ */
+ for (i = 2; i < sizeof(plldivr_table); i++) {
+ for (j = 0; j < sizeof(pllsaidivr_table); j++) {
+ div = plldivr_table[i] * pllsaidivr_table[j];
+ current_rate = pllsai_vco_rate / div;
+ /* perfect combination is found ? */
+ if (current_rate == rate) {
+ best_pllsaidivr = j;
+ best_plldivr = i;
+ found = true;
+ break;
+ }
+
+ diff = (current_rate > rate) ?
+ current_rate - rate : rate - current_rate;
+
+ /* found a better combination ? */
+ if (diff < best_diff) {
+ best_diff = diff;
+ best_pllsaidivr = j;
+ best_plldivr = i;
+ }
+ }
+
+ if (found)
+ break;
+ }
+
+ /* Disable the SAI PLL */
+ clrbits_le32(®s->cr, RCC_CR_PLLSAION);
+
+ /* set pll_saidivr with found value */
+ clrsetbits_le32(®s->dckcfgr, RCC_DCKCFGR_PLLSAIDIVR_MASK,
+ best_pllsaidivr << RCC_DCKCFGR_PLLSAIDIVR_SHIFT);
+
+ /* set pllsair with found value */
+ clrsetbits_le32(®s->pllsaicfgr, RCC_PLLSAICFGR_PLLSAIR_MASK,
+ plldivr_table[best_plldivr]
+ << RCC_PLLSAICFGR_PLLSAIR_SHIFT);
+
+ /* Enable the SAI PLL */
+ setbits_le32(®s->cr, RCC_CR_PLLSAION);
+ while (!(readl(®s->cr) & RCC_CR_PLLSAIRDY))
+ ;
+
+ div = plldivr_table[best_plldivr] * pllsaidivr_table[best_pllsaidivr];
+ return pllsai_vco_rate / div;
+#else
return 0;
+#endif
}
static int stm32_clk_enable(struct clk *clk)
return 0;
}
-void clock_setup(int peripheral)
-{
- switch (peripheral) {
- case TIMER2_CLOCK_CFG:
- setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN);
- break;
- default:
- break;
- }
-}
-
static int stm32_clk_probe(struct udevice *dev)
{
struct ofnode_phandle_args args;
#define RCC_CFGR_SW_CSI 1
#define RCC_CFGR_SW_HSE 2
#define RCC_CFGR_SW_PLL1 3
+#define RCC_CFGR_TIMPRE BIT(15)
#define RCC_PLLCKSELR_PLLSRC_HSI 0
#define RCC_PLLCKSELR_PLLSRC_CSI 1
.divr = 2,
};
+enum apb {
+ APB1,
+ APB2,
+};
+
int configure_clocks(struct udevice *dev)
{
struct stm32_clk *priv = dev_get_priv(dev);
return -EINVAL;
}
+static u32 stm32_get_apb_psc(struct stm32_rcc_regs *regs, enum apb apb)
+{
+ u16 prescaler_table[8] = {2, 4, 8, 16, 64, 128, 256, 512};
+ u32 d2cfgr = readl(®s->d2cfgr);
+
+ if (apb == APB1) {
+ if (d2cfgr & RCC_D2CFGR_D2PPRE1_DIVIDED)
+ /* get D2 domain APB1 prescaler */
+ return prescaler_table[
+ ((d2cfgr & RCC_D2CFGR_D2PPRE1_DIVIDER)
+ >> RCC_D2CFGR_D2PPRE1_SHIFT)];
+ } else { /* APB2 */
+ if (d2cfgr & RCC_D2CFGR_D2PPRE2_DIVIDED)
+ /* get D2 domain APB2 prescaler */
+ return prescaler_table[
+ ((d2cfgr & RCC_D2CFGR_D2PPRE2_DIVIDER)
+ >> RCC_D2CFGR_D2PPRE2_SHIFT)];
+ }
+
+ return 1;
+};
+
+static u32 stm32_get_timer_rate(struct stm32_clk *priv, u32 sysclk,
+ enum apb apb)
+{
+ struct stm32_rcc_regs *regs = priv->rcc_base;
+u32 psc = stm32_get_apb_psc(regs, apb);
+
+ if (readl(®s->cfgr) & RCC_CFGR_TIMPRE)
+ /*
+ * if APB prescaler is configured to a
+ * division factor of 1, 2 or 4
+ */
+ switch (psc) {
+ case 1:
+ case 2:
+ case 4:
+ return sysclk;
+ case 8:
+ return sysclk / 2;
+ case 16:
+ return sysclk / 4;
+ default:
+ pr_err("unexpected prescaler value (%d)\n", psc);
+ return 0;
+ }
+ else
+ switch (psc) {
+ case 1:
+ return sysclk;
+ case 2:
+ case 4:
+ case 8:
+ case 16:
+ return sysclk / psc;
+ default:
+ pr_err("unexpected prescaler value (%d)\n", psc);
+ return 0;
+ }
+};
+
static ulong stm32_clk_get_rate(struct clk *clk)
{
struct stm32_clk *priv = dev_get_priv(clk->dev);
struct stm32_rcc_regs *regs = priv->rcc_base;
ulong sysclk = 0;
u32 gate_offset;
- u32 d1cfgr;
+ u32 d1cfgr, d3cfgr;
/* prescaler table lookups for clock computation */
u16 prescaler_table[8] = {2, 4, 8, 16, 64, 128, 256, 512};
u8 source, idx;
break;
case RCC_APB4ENR:
- if (d1cfgr & RCC_D3CFGR_D3PPRE_DIVIDED) {
+ d3cfgr = readl(®s->d3cfgr);
+ if (d3cfgr & RCC_D3CFGR_D3PPRE_DIVIDED) {
/* get D3 domain APB4 prescaler */
- idx = (d1cfgr & RCC_D3CFGR_D3PPRE_DIVIDER) >>
+ idx = (d3cfgr & RCC_D3CFGR_D3PPRE_DIVIDER) >>
RCC_D3CFGR_D3PPRE_SHIFT;
sysclk = sysclk / prescaler_table[idx];
}
case RCC_APB1LENR:
case RCC_APB1HENR:
- if (d1cfgr & RCC_D2CFGR_D2PPRE1_DIVIDED) {
- /* get D2 domain APB1 prescaler */
- idx = (d1cfgr & RCC_D2CFGR_D2PPRE1_DIVIDER) >>
- RCC_D2CFGR_D2PPRE1_SHIFT;
- sysclk = sysclk / prescaler_table[idx];
+ /* special case for GPT timers */
+ switch (clk->id) {
+ case TIM14_CK:
+ case TIM13_CK:
+ case TIM12_CK:
+ case TIM7_CK:
+ case TIM6_CK:
+ case TIM5_CK:
+ case TIM4_CK:
+ case TIM3_CK:
+ case TIM2_CK:
+ return stm32_get_timer_rate(priv, sysclk, APB1);
}
debug("%s system clock: freq after APB1 prescaler = %ld\n",
__func__, sysclk);
- return sysclk;
+ return (sysclk / stm32_get_apb_psc(regs, APB1));
break;
case RCC_APB2ENR:
- if (d1cfgr & RCC_D2CFGR_D2PPRE2_DIVIDED) {
- /* get D2 domain APB1 prescaler */
- idx = (d1cfgr & RCC_D2CFGR_D2PPRE2_DIVIDER) >>
- RCC_D2CFGR_D2PPRE2_SHIFT;
- sysclk = sysclk / prescaler_table[idx];
+ /* special case for timers */
+ switch (clk->id) {
+ case TIM17_CK:
+ case TIM16_CK:
+ case TIM15_CK:
+ case TIM8_CK:
+ case TIM1_CK:
+ return stm32_get_timer_rate(priv, sysclk, APB2);
}
debug("%s system clock: freq after APB2 prescaler = %ld\n",
__func__, sysclk);
- return sysclk;
+ return (sysclk / stm32_get_apb_psc(regs, APB2));
+
break;
default:
{
struct rk3036_clk_priv *priv = dev_get_priv(dev);
- priv->cru = (struct rk3036_cru *)devfdt_get_addr(dev);
+ priv->cru = dev_read_addr_ptr(dev);
rkclk_init(priv->cru);
return 0;
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct rk3188_clk_priv *priv = dev_get_priv(dev);
- priv->cru = (struct rk3188_cru *)devfdt_get_addr(dev);
+ priv->cru = dev_read_addr_ptr(dev);
#endif
return 0;
{
struct rk322x_clk_priv *priv = dev_get_priv(dev);
- priv->cru = (struct rk322x_cru *)devfdt_get_addr(dev);
+ priv->cru = dev_read_addr_ptr(dev);
return 0;
}
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct rk3288_clk_priv *priv = dev_get_priv(dev);
- priv->cru = (struct rk3288_cru *)devfdt_get_addr(dev);
+ priv->cru = dev_read_addr_ptr(dev);
#endif
return 0;
{
struct rk3328_clk_priv *priv = dev_get_priv(dev);
- priv->cru = (struct rk3328_cru *)devfdt_get_addr(dev);
+ priv->cru = dev_read_addr_ptr(dev);
return 0;
}
{
struct rv1108_clk_priv *priv = dev_get_priv(dev);
- priv->cru = (struct rv1108_cru *)devfdt_get_addr(dev);
+ priv->cru = dev_read_addr_ptr(dev);
rkclk_init(priv->cru);
#define SDMMC_CLKCR_HWFC_EN BIT(17)
#define SDMMC_CLKCR_DDR BIT(18)
#define SDMMC_CLKCR_BUSSPEED BIT(19)
-#define SDMMC_CLKCR_SELCLKRX GENMASK(21, 20)
+#define SDMMC_CLKCR_SELCLKRX_MASK GENMASK(21, 20)
+#define SDMMC_CLKCR_SELCLKRX_CK 0
+#define SDMMC_CLKCR_SELCLKRX_CKIN BIT(20)
+#define SDMMC_CLKCR_SELCLKRX_FBCK BIT(21)
/* SDMMC_CMD register */
#define SDMMC_CMD_CMDINDEX GENMASK(5, 0)
if (mmc->bus_width == 8)
clk |= SDMMC_CLKCR_WIDBUS_8;
- writel(clk | priv->clk_reg_msk, priv->base + SDMMC_CLKCR);
+ writel(clk | priv->clk_reg_msk | SDMMC_CLKCR_HWFC_EN,
+ priv->base + SDMMC_CLKCR);
return 0;
}
priv->clk_reg_msk |= SDMMC_CLKCR_NEGEDGE;
if (dev_read_bool(dev, "st,dirpol"))
priv->pwr_reg_msk |= SDMMC_POWER_DIRPOL;
+ if (dev_read_bool(dev, "st,pin-ckin"))
+ priv->clk_reg_msk |= SDMMC_CLKCR_SELCLKRX_CKIN;
ret = clk_get_by_index(dev, 0, &priv->clk);
if (ret)
uint32_t *mclkreg;
unsigned fatal_err;
struct gpio_desc cd_gpio; /* Change Detect GPIO */
+ int cd_inverted; /* Inverted Card Detect */
struct sunxi_mmc *reg;
struct mmc_config cfg;
};
{
struct sunxi_mmc_priv *priv = dev_get_priv(dev);
- if (dm_gpio_is_valid(&priv->cd_gpio))
- return dm_gpio_get_value(&priv->cd_gpio);
+ if (dm_gpio_is_valid(&priv->cd_gpio)) {
+ int cd_state = dm_gpio_get_value(&priv->cd_gpio);
+ return cd_state ^ priv->cd_inverted;
+ }
return 1;
}
sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP);
}
+ /* Check if card detect is inverted */
+ priv->cd_inverted = dev_read_bool(dev, "cd-inverted");
+
upriv->mmc = &plat->mmc;
/* Reset controller */
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-#define STM32_FLASH ((struct stm32_flash_regs *)FLASH_CNTL_BASE)
+#define STM32_FLASH ((struct stm32_flash_regs *)STM32_FLASH_CNTL_BASE)
void stm32_flash_latency_cfg(int latency)
{
if PHYLIB
+config PHY_ADDR
+ int "PHY address"
+ default 1 if ARCH_SUNXI
+ default 0
+ help
+ The address of PHY on MII bus. Usually in range of 0 to 31.
+
config B53_SWITCH
bool "Broadcom BCM53xx (RoboSwitch) Ethernet switch PHY support."
help
tx_descs_init(priv);
/* PHY Start Up */
- genphy_parse_link(priv->phydev);
+ phy_startup(priv->phydev);
sun8i_adjust_link(priv, priv->phydev);
{
struct rk_pwm_priv *priv = dev_get_priv(dev);
- priv->regs = (struct rk3288_pwm *)devfdt_get_addr(dev);
+ priv->regs = (struct rk3288_pwm *)dev_read_addr(dev);
return 0;
}
#include <dm.h>
#include <errno.h>
#include <asm/arch/stm32.h>
-#include <asm/arch/stm32_defs.h>
#include <clk.h>
DECLARE_GLOBAL_DATA_PTR;
Select this to enable support for the timer found on
Rockchip devices.
+config STM32_TIMER
+ bool "STM32 timer support"
+ depends on TIMER
+ help
+ Select this to enable support for the timer found on
+ STM32 devices.
+
endmenu
obj-$(CONFIG_ATCPIT100_TIMER) += atcpit100_timer.o
obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o
obj-$(CONFIG_ATMEL_PIT_TIMER) += atmel_pit_timer.o
+obj-$(CONFIG_STM32_TIMER) += stm32_timer.o
--- /dev/null
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <timer.h>
+
+#include <asm/io.h>
+
+/* Timer control1 register */
+#define CR1_CEN BIT(0)
+#define CR1_ARPE BIT(7)
+
+/* Event Generation Register register */
+#define EGR_UG BIT(0)
+
+/* Auto reload register for free running config */
+#define GPT_FREE_RUNNING 0xFFFFFFFF
+
+struct stm32_timer_regs {
+ u32 cr1;
+ u32 cr2;
+ u32 smcr;
+ u32 dier;
+ u32 sr;
+ u32 egr;
+ u32 ccmr1;
+ u32 ccmr2;
+ u32 ccer;
+ u32 cnt;
+ u32 psc;
+ u32 arr;
+ u32 reserved;
+ u32 ccr1;
+ u32 ccr2;
+ u32 ccr3;
+ u32 ccr4;
+ u32 reserved1;
+ u32 dcr;
+ u32 dmar;
+ u32 tim2_5_or;
+};
+
+struct stm32_timer_priv {
+ struct stm32_timer_regs *base;
+};
+
+static int stm32_timer_get_count(struct udevice *dev, u64 *count)
+{
+ struct stm32_timer_priv *priv = dev_get_priv(dev);
+ struct stm32_timer_regs *regs = priv->base;
+
+ *count = readl(®s->cnt);
+
+ return 0;
+}
+
+static int stm32_timer_probe(struct udevice *dev)
+{
+ struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct stm32_timer_priv *priv = dev_get_priv(dev);
+ struct stm32_timer_regs *regs;
+ struct clk clk;
+ fdt_addr_t addr;
+ int ret;
+ u32 rate, psc;
+
+ addr = dev_read_addr(dev);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ priv->base = (struct stm32_timer_regs *)addr;
+
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_enable(&clk);
+ if (ret) {
+ dev_err(dev, "failed to enable clock\n");
+ return ret;
+ }
+
+ regs = priv->base;
+
+ /* Stop the timer */
+ clrbits_le32(®s->cr1, CR1_CEN);
+
+ /* get timer clock */
+ rate = clk_get_rate(&clk);
+
+ /* we set timer prescaler to obtain a 1MHz timer counter frequency */
+ psc = (rate / CONFIG_SYS_HZ_CLOCK) - 1;
+ writel(psc, ®s->psc);
+
+ /* Set timer frequency to 1MHz */
+ uc_priv->clock_rate = CONFIG_SYS_HZ_CLOCK;
+
+ /* Configure timer for auto-reload */
+ setbits_le32(®s->cr1, CR1_ARPE);
+
+ /* load value for auto reload */
+ writel(GPT_FREE_RUNNING, ®s->arr);
+
+ /* start timer */
+ setbits_le32(®s->cr1, CR1_CEN);
+
+ /* Update generation */
+ setbits_le32(®s->egr, EGR_UG);
+
+ return 0;
+}
+
+static const struct timer_ops stm32_timer_ops = {
+ .get_count = stm32_timer_get_count,
+};
+
+static const struct udevice_id stm32_timer_ids[] = {
+ { .compatible = "st,stm32-timer" },
+ {}
+};
+
+U_BOOT_DRIVER(stm32_timer) = {
+ .name = "stm32_timer",
+ .id = UCLASS_TIMER,
+ .of_match = stm32_timer_ids,
+ .priv_auto_alloc_size = sizeof(struct stm32_timer_priv),
+ .probe = stm32_timer_probe,
+ .ops = &stm32_timer_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
uint duty_cycle;
int ret;
- plat = dev_get_uclass_platdata(priv->reg);
- debug("%s: Enable '%s', regulator '%s'/'%s'\n", __func__, dev->name,
- priv->reg->name, plat->name);
- ret = regulator_set_enable(priv->reg, true);
- if (ret) {
- debug("%s: Cannot enable regulator for PWM '%s'\n", __func__,
- dev->name);
- return ret;
+ if (priv->reg) {
+ plat = dev_get_uclass_platdata(priv->reg);
+ debug("%s: Enable '%s', regulator '%s'/'%s'\n", __func__,
+ dev->name, priv->reg->name, plat->name);
+ ret = regulator_set_enable(priv->reg, true);
+ if (ret) {
+ debug("%s: Cannot enable regulator for PWM '%s'\n",
+ __func__, dev->name);
+ return ret;
+ }
+ mdelay(120);
}
- mdelay(120);
duty_cycle = priv->period_ns * (priv->default_level - priv->min_level) /
(priv->max_level - priv->min_level + 1);
debug("%s: start\n", __func__);
ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev,
"power-supply", &priv->reg);
- if (ret) {
+ if (ret)
debug("%s: Cannot get power supply: ret=%d\n", __func__, ret);
- return ret;
- }
ret = gpio_request_by_name(dev, "enable-gpios", 0, &priv->enable,
GPIOD_IS_OUT);
if (ret) {
*/
#include <common.h>
+#include <efi_loader.h>
#include <asm/arch/clock.h>
#include <asm/arch/display.h>
gd->bd->bi_dram[0].size - sunxi_display.fb_size;
sunxi_engines_init();
+#ifdef CONFIG_EFI_LOADER
+ efi_add_memory_map(gd->fb_base,
+ ALIGN(sunxi_display.fb_size, EFI_PAGE_SIZE) >>
+ EFI_PAGE_SHIFT,
+ EFI_RESERVED_MEMORY_TYPE, false);
+#endif
+
fb_dma_addr = gd->fb_base - CONFIG_SYS_SDRAM_BASE;
sunxi_display.fb_addr = gd->fb_base;
if (overscan_offset) {
#include <dm.h>
#include <video.h>
#include <video_console.h>
-#include <video_font.h> /* Get font data, width and height */
+#include <video_font.h> /* Bitmap font for code page 437 */
+
+/*
+ * Structure to describe a console color
+ */
+struct vid_rgb {
+ u32 r;
+ u32 g;
+ u32 b;
+};
/* By default we scroll by a single line */
#ifndef CONFIG_CONSOLE_SCROLL_LINES
video_sync(dev->parent);
}
-static const struct {
- unsigned r;
- unsigned g;
- unsigned b;
-} colors[] = {
+static const struct vid_rgb colors[VID_COLOR_COUNT] = {
{ 0x00, 0x00, 0x00 }, /* black */
- { 0xff, 0x00, 0x00 }, /* red */
- { 0x00, 0xff, 0x00 }, /* green */
+ { 0xc0, 0x00, 0x00 }, /* red */
+ { 0x00, 0xc0, 0x00 }, /* green */
+ { 0xc0, 0x60, 0x00 }, /* brown */
+ { 0x00, 0x00, 0xc0 }, /* blue */
+ { 0xc0, 0x00, 0xc0 }, /* magenta */
+ { 0x00, 0xc0, 0xc0 }, /* cyan */
+ { 0xc0, 0xc0, 0xc0 }, /* light gray */
+ { 0x80, 0x80, 0x80 }, /* gray */
+ { 0xff, 0x00, 0x00 }, /* bright red */
+ { 0x00, 0xff, 0x00 }, /* bright green */
{ 0xff, 0xff, 0x00 }, /* yellow */
- { 0x00, 0x00, 0xff }, /* blue */
- { 0xff, 0x00, 0xff }, /* magenta */
- { 0x00, 0xff, 0xff }, /* cyan */
+ { 0x00, 0x00, 0xff }, /* bright blue */
+ { 0xff, 0x00, 0xff }, /* bright magenta */
+ { 0x00, 0xff, 0xff }, /* bright cyan */
{ 0xff, 0xff, 0xff }, /* white */
};
-static void set_color(struct video_priv *priv, unsigned idx, unsigned *c)
+u32 vid_console_color(struct video_priv *priv, unsigned int idx)
{
switch (priv->bpix) {
case VIDEO_BPP16:
- *c = ((colors[idx].r >> 3) << 0) |
- ((colors[idx].g >> 2) << 5) |
- ((colors[idx].b >> 3) << 11);
- break;
+ return ((colors[idx].r >> 3) << 11) |
+ ((colors[idx].g >> 2) << 5) |
+ ((colors[idx].b >> 3) << 0);
case VIDEO_BPP32:
- *c = 0xff000000 |
- (colors[idx].r << 0) |
- (colors[idx].g << 8) |
- (colors[idx].b << 16);
- break;
+ return (colors[idx].r << 16) |
+ (colors[idx].g << 8) |
+ (colors[idx].b << 0);
default:
- /* unsupported, leave current color in place */
- break;
+ /*
+ * For unknown bit arrangements just support
+ * black and white.
+ */
+ if (idx)
+ return 0xffffff; /* white */
+ else
+ return 0x000000; /* black */
}
}
s++;
switch (val) {
+ case 0:
+ /* all attributes off */
+ video_set_default_colors(vid_priv);
+ break;
+ case 1:
+ /* bold */
+ vid_priv->fg_col_idx |= 8;
+ vid_priv->colour_fg = vid_console_color(
+ vid_priv, vid_priv->fg_col_idx);
+ break;
case 30 ... 37:
- /* fg color */
- set_color(vid_priv, val - 30,
- (unsigned *)&vid_priv->colour_fg);
+ /* foreground color */
+ vid_priv->fg_col_idx &= ~7;
+ vid_priv->fg_col_idx |= val - 30;
+ vid_priv->colour_fg = vid_console_color(
+ vid_priv, vid_priv->fg_col_idx);
break;
case 40 ... 47:
- /* bg color */
- set_color(vid_priv, val - 40,
- (unsigned *)&vid_priv->colour_bg);
+ /* background color */
+ vid_priv->colour_bg = vid_console_color(
+ vid_priv, val - 40);
break;
default:
- /* unknown/unsupported */
+ /* ignore unsupported SGR parameter */
break;
}
}
{
struct video_priv *priv = dev_get_uclass_priv(dev);
- if (priv->bpix == VIDEO_BPP32) {
+ switch (priv->bpix) {
+ case VIDEO_BPP16: {
+ u16 *ppix = priv->fb;
+ u16 *end = priv->fb + priv->fb_size;
+
+ while (ppix < end)
+ *ppix++ = priv->colour_bg;
+ break;
+ }
+ case VIDEO_BPP32: {
u32 *ppix = priv->fb;
u32 *end = priv->fb + priv->fb_size;
while (ppix < end)
*ppix++ = priv->colour_bg;
- } else {
+ break;
+ }
+ default:
memset(priv->fb, priv->colour_bg, priv->fb_size);
+ break;
}
}
+void video_set_default_colors(struct video_priv *priv)
+{
+#ifdef CONFIG_SYS_WHITE_ON_BLACK
+ /* White is used when switching to bold, use light gray here */
+ priv->fg_col_idx = VID_LIGHT_GRAY;
+ priv->colour_fg = vid_console_color(priv, VID_LIGHT_GRAY);
+ priv->colour_bg = vid_console_color(priv, VID_BLACK);
+#else
+ priv->fg_col_idx = VID_BLACK;
+ priv->colour_fg = vid_console_color(priv, VID_BLACK);
+ priv->colour_bg = vid_console_color(priv, VID_WHITE);
+#endif
+}
+
/* Flush video activity to the caches */
void video_sync(struct udevice *vid)
{
priv->line_length = priv->xsize * VNBYTES(priv->bpix);
priv->fb_size = priv->line_length * priv->ysize;
- /* Set up colours - we could in future support other colours */
-#ifdef CONFIG_SYS_WHITE_ON_BLACK
- priv->colour_fg = 0xffffff;
-#else
- priv->colour_bg = 0xffffff;
-#endif
+ /* Set up colors */
+ video_set_default_colors(priv);
if (!CONFIG_IS_ENABLED(NO_FB_CLEAR))
video_clear(dev);
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 10
-#define CONFIG_PHY_ADDR 0
#define CONFIG_PHY_SMSC
/* I2C configuration */
#endif
/* Network. */
-#define CONFIG_PHY_ADDR 0
#define CONFIG_PHY_SMSC
#define CONFIG_MII
#define CONFIG_PHY_ATHEROS
#define CONFIG_RMII
#define CONFIG_PHY_SMSC
#define CONFIG_LPC32XX_ETH
-#define CONFIG_PHY_ADDR 0x1F
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
/*
#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
#define CONFIG_PHY_MARVELL /* there is a marvell phy */
-#define CONFIG_PHY_ADDR { 0x1, 0x0 }
#define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII
#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_DRIVER_EP93XX_MAC
#define CONFIG_MII_SUPPRESS_PREAMBLE
#define CONFIG_MII
-#define CONFIG_PHY_ADDR 1
#undef CONFIG_NETCONSOLE
/* SDRAM configuration */
#define CONFIG_MISC_INIT_R
-#define CONFIG_PHY_ADDR 8
-
#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxl-s905x-khadas-vim.dtb\0"
#include <configs/meson-gxbb-common.h>
#define CONFIG_MISC_INIT_R
-#define CONFIG_PHY_ADDR 8
-
#define MESON_FDTFILE_SETTING "fdtfile=amlogic/meson-gxl-s905x-libretech-cc.dtb\0"
#include <configs/meson-gxbb-common.h>
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
+#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
#include <configs/ti_omap3_common.h>
#define CONFIG_SYS_NAND_ECCBYTES 3
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
-#define CONFIG_ENV_IS_IN_NAND 1
-#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
-#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
+#define CONFIG_SYS_ENV_SECT_SIZE SZ_128K
#define CONFIG_ENV_OFFSET 0x260000
#define CONFIG_ENV_ADDR 0x260000
#define CONFIG_ENV_OVERWRITE
#define CONFIG_MTD_PARTITIONS /* required for UBI partition support */
/* NAND: SPL falcon mode configs */
#if defined(CONFIG_SPL_OS_BOOT)
-#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x2a0000
#endif /* CONFIG_SPL_OS_BOOT */
#endif /* CONFIG_NAND */
-/* MUSB */
-#define CONFIG_USB_OMAP3
-
/* USB EHCI */
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 147
/* TWL4030 LED Support */
#define CONFIG_TWL4030_LED
+/* Environment */
+#define CONFIG_ENV_SIZE SZ_128K
+
+#define CONFIG_PREBOOT "usb start"
+
+#define MEM_LAYOUT_ENV_SETTINGS \
+ DEFAULT_LINUX_BOOT_ENV
+
+#define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \
+ "bootcmd_" #devtypel #instance "=" \
+ "setenv mmcdev " #instance "; " \
+ "run mmcboot\0"
+#define BOOTENV_DEV_NAME_LEGACY_MMC(devtypeu, devtypel, instance) \
+ #devtypel #instance " "
+
+#if defined(CONFIG_NAND)
+
+#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \
+ "bootcmd_" #devtypel #instance "=" \
+ "if test ${mtdids} = '' || test ${mtdparts} = '' ; then " \
+ "echo NAND boot disabled: No mtdids and/or mtdparts; " \
+ "else " \
+ "run nandboot; " \
+ "fi\0"
+#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \
+ #devtypel #instance " "
+
#define BOOT_TARGET_DEVICES(func) \
- func(MMC, mmc, 0)
-
-#define CONFIG_BOOTCOMMAND \
- "run findfdt; " \
- "run distro_bootcmd; " \
- "mmc dev ${mmcdev}; if mmc rescan; then " \
- "if run userbutton; then " \
- "setenv bootenv uEnv.txt;" \
- "else " \
- "setenv bootenv user.txt;" \
- "fi;" \
- "echo SD/MMC found on device ${mmcdev};" \
- "if run loadbootenv; then " \
- "echo Loaded environment from ${bootenv};" \
- "run importbootenv;" \
- "fi;" \
- "if test -n $uenvcmd; then " \
- "echo Running uenvcmd ...;" \
- "run uenvcmd;" \
- "fi;" \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run loadimage; then " \
- "run loadfdt;" \
- "run mmcboot;" \
- "fi;" \
- "fi; " \
- "fi;" \
- "run nandboot;" \
- "setenv bootfile zImage;" \
- "if run loadimage; then " \
- "run loadfdt;" \
- "run mmcbootz; " \
- "fi; " \
+ func(MMC, mmc, 0) \
+ func(LEGACY_MMC, legacy_mmc, 0) \
+ func(UBIFS, ubifs, 0) \
+ func(NAND, nand, 0)
+
+#else /* !CONFIG_NAND */
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0) \
+ func(LEGACY_MMC, legacy_mmc, 0)
+
+#endif /* CONFIG_NAND */
#include <config_distro_bootcmd.h>
#define CONFIG_EXTRA_ENV_SETTINGS \
- DEFAULT_LINUX_BOOT_ENV \
+ MEM_LAYOUT_ENV_SETTINGS \
+ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
"fdt_high=0xffffffff\0" \
- "usbtty=cdc_acm\0" \
- "bootfile=uImage\0" \
- "ramdisk=ramdisk.gz\0" \
+ "console=ttyO2,115200n8\0" \
"bootdir=/boot\0" \
+ "bootenv=uEnv.txt\0" \
+ "bootfile=zImage\0" \
"bootpart=0:2\0" \
- "console=ttyO2,115200n8\0" \
+ "bootubivol=rootfs\0" \
+ "bootubipart=rootfs\0" \
+ "usbtty=cdc_acm\0" \
"mpurate=auto\0" \
"buddy=none\0" \
- "optargs=\0" \
"camera=none\0" \
"vram=12M\0" \
"dvimode=640x480MR-16@60\0" \
"defaultdisplay=dvi\0" \
- "mmcdev=0\0" \
- "mmcroot=/dev/mmcblk0p2 rw\0" \
- "mmcrootfstype=ext4 rootwait\0" \
- "nandroot=ubi0:rootfs ubi.mtd=4\0" \
- "nandrootfstype=ubifs\0" \
- "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=0x81000000,64M\0" \
- "ramrootfstype=ext2\0" \
- "mmcargs=setenv bootargs console=${console} " \
- "${optargs} " \
- "mpurate=${mpurate} " \
- "buddy=${buddy} "\
- "camera=${camera} "\
- "vram=${vram} " \
- "omapfb.mode=dvi:${dvimode} " \
- "omapdss.def_disp=${defaultdisplay} " \
- "root=${mmcroot} " \
- "rootfstype=${mmcrootfstype}\0" \
- "nandargs=setenv bootargs console=${console} " \
- "${optargs} " \
+ "defaultargs=setenv defargs " \
"mpurate=${mpurate} " \
"buddy=${buddy} "\
"camera=${camera} "\
"vram=${vram} " \
"omapfb.mode=dvi:${dvimode} " \
- "omapdss.def_disp=${defaultdisplay} " \
- "root=${nandroot} " \
- "rootfstype=${nandrootfstype}\0" \
+ "omapdss.def_disp=${defaultdisplay}\0" \
+ "optargs=\0" \
"findfdt=" \
"if test $beaglerev = AxBx; then " \
"setenv fdtfile omap3-beagle.dtb; fi; " \
"if test $beaglerev = xMC; then " \
"setenv fdtfile omap3-beagle-xm.dtb; fi; " \
"if test $fdtfile = undefined; then " \
- "echo WARNING: Could not determine device tree to use; fi; \0" \
+ "echo WARNING: Could not determine device tree to use; fi\0" \
+ "mmcdev=0\0" \
+ "mmcpart=2\0" \
+ "mmcroot=/dev/mmcblk0p2 rw\0" \
+ "mmcrootfstype=ext4 rootwait\0" \
+ "mmcargs=run defaultargs; setenv bootargs console=${console} " \
+ "${mtdparts} " \
+ "${defargs} " \
+ "${optargs} " \
+ "root=${mmcroot} " \
+ "rootfstype=${mmcrootfstype}\0" \
+ "userbutton_xm=gpio input 4;\0" \
+ "userbutton_nonxm=gpio input 7;\0" \
+ "userbutton=if gpio input 173; then " \
+ "run userbutton_xm; " \
+ "else " \
+ "run userbutton_nonxm; " \
+ "fi;\0" \
+ "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
+ "ext4bootenv=ext4load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootenv}\0" \
+ "importbootenv=echo Importing environment from mmc${mmcdev} ...; " \
+ "env import -t ${loadaddr} ${filesize}\0" \
+ "mmcbootenv=setenv bootpart ${mmcdev}:${mmcpart}; " \
+ "mmc dev ${mmcdev}; " \
+ "if mmc rescan; then " \
+ "if run userbutton; then " \
+ "setenv bootenv uEnv.txt;" \
+ "else " \
+ "setenv bootenv user.txt;" \
+ "fi;" \
+ "run loadbootenv && run importbootenv; " \
+ "run ext4bootenv && run importbootenv; " \
+ "if test -n $uenvcmd; then " \
+ "echo Running uenvcmd ...; " \
+ "run uenvcmd; " \
+ "fi; " \
+ "fi\0" \
"validatefdt=" \
"if test $beaglerev = xMAB; then " \
"if test ! -e mmc ${bootpart} ${bootdir}/${fdtfile}; then " \
"setenv fdtfile omap3-beagle-xm.dtb; " \
"fi; " \
"fi; \0" \
- "bootenv=uEnv.txt\0" \
- "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
- "importbootenv=echo Importing environment from mmc ...; " \
- "env import -t -r $loadaddr $filesize\0" \
- "ramargs=setenv bootargs console=${console} " \
+ "loadimage=ext4load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
+ "loaddtb=run validatefdt; ext4load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
+ "mmcboot=run mmcbootenv; " \
+ "if run loadimage && run loaddtb; then " \
+ "echo Booting ${bootdir}/${bootfile} from mmc ${bootpart} ...; " \
+ "run mmcargs; " \
+ "if test ${bootfile} = uImage; then " \
+ "bootm ${loadaddr} - ${fdtaddr}; " \
+ "fi; " \
+ "if test ${bootfile} = zImage; then " \
+ "bootz ${loadaddr} - ${fdtaddr}; " \
+ "fi; " \
+ "fi\0" \
+ "nandroot=ubi0:rootfs ubi.mtd=rootfs rw\0" \
+ "nandrootfstype=ubifs rootwait\0" \
+ "nandargs=run defaultargs; setenv bootargs console=${console} " \
+ "${mtdparts} " \
+ "${defargs} " \
"${optargs} " \
- "mpurate=${mpurate} " \
- "buddy=${buddy} "\
- "vram=${vram} " \
- "omapfb.mode=dvi:${dvimode} " \
- "omapdss.def_disp=${defaultdisplay} " \
- "root=${ramroot} " \
- "rootfstype=${ramrootfstype}\0" \
- "loadramdisk=load mmc ${bootpart} ${rdaddr} ${bootdir}/${ramdisk}\0" \
- "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
- "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \
- "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
- "source ${loadaddr}\0" \
- "loadfdt=run validatefdt; load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
- "mmcboot=echo Booting ${bootfile} with DT from mmc${mmcdev} ...; " \
- "run mmcargs; " \
- "bootm ${loadaddr} - ${fdtaddr}\0" \
- "mmcbootz=echo Booting ${bootfile} with DT from mmc${mmcdev} ...; " \
- "run mmcargs; " \
- "bootz ${loadaddr} - ${fdtaddr}\0" \
- "nandboot=echo Booting from nand ...; " \
- "run nandargs; " \
- "nand read ${loadaddr} 280000 400000; " \
- "bootm ${loadaddr}\0" \
- "ramboot=echo Booting from ramdisk ...; " \
- "run ramargs; " \
- "bootm ${loadaddr}\0" \
- "userbutton=if gpio input 173; then run userbutton_xm; " \
- "else run userbutton_nonxm; fi;\0" \
- "userbutton_xm=gpio input 4;\0" \
- "userbutton_nonxm=gpio input 7;\0" \
+ "root=${nandroot} " \
+ "rootfstype=${nandrootfstype}\0" \
+ "nandboot=if nand read ${loadaddr} kernel && nand read ${fdtaddr} dtb; then " \
+ "echo Booting uImage from NAND MTD 'kernel' partition ...; " \
+ "run nandargs; " \
+ "bootm ${loadaddr} - ${fdtaddr}; " \
+ "fi\0" \
+ "loadramdisk=ext4load mmc ${bootpart} ${rdaddr} ${bootdir}/${ramdisk}\0" \
+ "ramdisk=rootfs.ext2.gz.uboot\0" \
+ "ramdisk_size=16384\0" \
+ "ramroot=/dev/ram rw\0" \
+ "ramrootfstype=ext2\0" \
+ "ramargs=run defaultargs; setenv bootargs console=${console} " \
+ "${mtdparts} " \
+ "${defargs} " \
+ "${optargs} " \
+ "root=${ramroot} ramdisk_size=${ramdisk_size} " \
+ "rootfstype=${ramrootfstype}\0" \
+ "ramboot=run mmcbootenv; " \
+ "if run loadimage && run loaddtb && run loadramdisk; then " \
+ "echo Booting ${bootdir}/${bootfile} from mmc ${bootpart} w/ramdisk ...; " \
+ "run ramargs; " \
+ "bootz ${loadaddr} ${rdaddr} ${fdtaddr}; " \
+ "fi\0" \
BOOTENV
#endif /* __CONFIG_H */
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 3
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
-#define CONFIG_ENV_IS_IN_NAND 1
-#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
-#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
+#define CONFIG_SYS_ENV_SECT_SIZE SZ_128K
#define CONFIG_ENV_OFFSET 0x260000
#define CONFIG_ENV_ADDR 0x260000
#define CONFIG_ENV_OVERWRITE
#define CONFIG_MTD_PARTITIONS /* required for UBI partition support */
/* NAND: SPL falcon mode configs */
#if defined(CONFIG_SPL_OS_BOOT)
-#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x2a0000
#endif /* CONFIG_SPL_OS_BOOT */
#endif /* CONFIG_NAND */
-/* MUSB */
-
-/* USB EHCI */
-#define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1
-
/* Environment */
+#define CONFIG_ENV_SIZE SZ_128K
+
#define CONFIG_PREBOOT "usb start"
#define MEM_LAYOUT_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV
-#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \
- "bootcmd_" #devtypel #instance "=" \
- "run nandboot\0"
-#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \
- #devtypel #instance " "
-
#define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \
"bootcmd_" #devtypel #instance "=" \
"setenv mmcdev " #instance "; " \
- "setenv bootpart " #instance ":${mmcpart} ; " \
"run mmcboot\0"
#define BOOTENV_DEV_NAME_LEGACY_MMC(devtypeu, devtypel, instance) \
#devtypel #instance " "
+#if defined(CONFIG_NAND)
+
+#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \
+ "bootcmd_" #devtypel #instance "=" \
+ "if test ${mtdids} = '' || test ${mtdparts} = '' ; then " \
+ "echo NAND boot disabled: No mtdids and/or mtdparts; " \
+ "else " \
+ "run nandboot; " \
+ "fi\0"
+#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \
+ #devtypel #instance " "
+
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
func(LEGACY_MMC, legacy_mmc, 0) \
func(UBIFS, ubifs, 0) \
func(NAND, nand, 0)
+#else /* !CONFIG_NAND */
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0) \
+ func(LEGACY_MMC, legacy_mmc, 0)
+
+#endif /* CONFIG_NAND */
+
#include <config_distro_bootcmd.h>
#define CONFIG_EXTRA_ENV_SETTINGS \
"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
"fdt_high=0xffffffff\0" \
+ "console=ttyO0,115200n8\0" \
"bootdir=/boot\0" \
"bootenv=uEnv.txt\0" \
"bootfile=zImage\0" \
+ "bootpart=0:2\0" \
"bootubivol=rootfs\0" \
"bootubipart=rootfs\0" \
"optargs=\0" \
"mmcdev=0\0" \
"mmcpart=2\0" \
- "bootpart=${mmcdev}:${mmcpart}\0" \
- "console=ttyO0,115200n8\0" \
+ "mmcroot=/dev/mmcblk0p2 rw\0" \
+ "mmcrootfstype=ext4 rootwait\0" \
"mmcargs=setenv bootargs console=${console} " \
"${mtdparts} " \
"${optargs} " \
- "root=/dev/mmcblk0p2 rw " \
- "rootfstype=ext4 rootwait\0" \
- "nandargs=setenv bootargs console=${console} " \
- "${mtdparts} " \
- "${optargs} " \
- "root=ubi0:rootfs rw ubi.mtd=rootfs noinitrd " \
- "rootfstype=ubifs rootwait\0" \
+ "root=${mmcroot} " \
+ "rootfstype=${mmcrootfstype}\0" \
"loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
"ext4bootenv=ext4load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootenv}\0" \
- "importbootenv=echo Importing environment from mmc ...; " \
+ "importbootenv=echo Importing environment from mmc${mmcdev} ...; " \
"env import -t ${loadaddr} ${filesize}\0" \
- "mmcbootenv=mmc dev ${mmcdev}; " \
+ "mmcbootenv=setenv bootpart ${mmcdev}:${mmcpart}; " \
+ "mmc dev ${mmcdev}; " \
"if mmc rescan; then " \
"run loadbootenv && run importbootenv; " \
"run ext4bootenv && run importbootenv; " \
"bootz ${loadaddr} - ${fdtaddr}; " \
"fi; " \
"fi\0" \
- "nandboot=" \
- "if nand read ${loadaddr} kernel && nand read ${fdtaddr} dtb; then " \
+ "nandroot=ubi0:rootfs ubi.mtd=rootfs rw noinitrd\0" \
+ "nandrootfstype=ubifs rootwait\0" \
+ "nandargs=setenv bootargs console=${console} " \
+ "${mtdparts} " \
+ "${optargs} " \
+ "root=${nandroot} " \
+ "rootfstype=${nandrootfstype}\0" \
+ "nandboot=if nand read ${loadaddr} kernel && nand read ${fdtaddr} dtb; then " \
"echo Booting uImage from NAND MTD 'kernel' partition ...; " \
"run nandargs; " \
"bootm ${loadaddr} - ${fdtaddr}; " \
#define CONFIG_MISC_INIT_R
-#define CONFIG_PHY_ADDR 8
-
/* Serial setup */
#define CONFIG_CONS_INDEX 0
#define CONFIG_SYS_NS16550_COM1 0x44e09000
/* Ethernet support */
-#define CONFIG_PHY_ADDR 0
#define CONFIG_PHY_RESET_DELAY 1000
/* SPL */
"scriptaddr=0x00500000\0" \
"pxefile_addr_r=0x00600000\0" \
"fdt_addr_r=0x01f00000\0" \
- "kernel_addr_r=0x02000000\0" \
+ "kernel_addr_r=0x02080000\0" \
"ramdisk_addr_r=0x04000000\0"
#include <config_distro_bootcmd.h>
"scriptaddr=0x00500000\0" \
"pxefile_addr_r=0x00600000\0" \
"fdt_addr_r=0x01f00000\0" \
- "kernel_addr_r=0x02000000\0" \
+ "kernel_addr_r=0x02080000\0" \
"ramdisk_addr_r=0x04000000\0"
#include <config_distro_bootcmd.h>
#define CONFIG_ENV_SIZE (8 << 10)
-#define CONFIG_SYS_ARCH_TIMER
-#define CONFIG_SYS_HZ_CLOCK 250000000
+#define CONFIG_SYS_HZ_CLOCK 1000000
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_ENV_SIZE (8 << 10)
-#define CONFIG_SYS_ARCH_TIMER
-#define CONFIG_SYS_HZ_CLOCK 250000000
+#define CONFIG_SYS_HZ_CLOCK 1000000
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
/* Ethernet support */
#ifdef CONFIG_SUN4I_EMAC
-#define CONFIG_PHY_ADDR 1
#define CONFIG_MII /* MII PHY management */
#endif
#ifdef CONFIG_SUN7I_GMAC
-#define CONFIG_PHY_ADDR 1
#define CONFIG_MII /* MII PHY management */
#define CONFIG_PHY_REALTEK
#endif
#define CONFIG_PHY_SMSC
#define CONFIG_LPC32XX_ETH
-#define CONFIG_PHY_ADDR 0
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
/* FIXME: remove "Waiting for PHY auto negotiation to complete..." message */
/* Ethernet config options */
#define CONFIG_MII
#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
-#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_SPEAR_GPIO
#define STM32F7_RCC_APB2_SAI1 22
#define STM32F7_RCC_APB2_SAI2 23
#define STM32F7_RCC_APB2_LTDC 26
+#define STM32F7_RCC_APB2_DSI 27
#define STM32F7_APB2_RESET(bit) (STM32F7_RCC_APB2_##bit + (0x24 * 8))
#define STM32F7_APB2_CLOCK(bit) (STM32F7_RCC_APB2_##bit + 0xA0)
"setenv eval_bootargs setenv bootargs $bootargs; " \
"run eval_bootargs; " \
"setenv mmcdev 1; " \
- "setenv fdt_part 3; " \
- "setenv boot_part 9; " \
"setenv machid fe6; " \
"mmc dev $mmcdev; " \
"mmc rescan; " \
- "part start mmc ${mmcdev} ${fdt_part} fdt_start; " \
- "part size mmc ${mmcdev} ${fdt_part} fdt_size; " \
- "part start mmc ${mmcdev} ${boot_part} boot_start; " \
- "part size mmc ${mmcdev} ${boot_part} boot_size; " \
+ "part start mmc ${mmcdev} environment fdt_start; " \
+ "part size mmc ${mmcdev} environment fdt_size; " \
+ "part start mmc ${mmcdev} boot boot_start; " \
+ "part size mmc ${mmcdev} boot boot_size; " \
"mmc read ${fdtaddr} ${fdt_start} ${fdt_size}; " \
"mmc read ${loadaddr} ${boot_start} ${boot_size}; " \
"bootm $loadaddr $loadaddr $fdtaddr;\0"
STM32F7,
};
+enum apb {
+ APB1,
+ APB2,
+};
+
struct stm32_rcc_clk {
char *drv_name;
enum soc_family soc;
* @flush_dcache: true to enable flushing of the data cache after
* the LCD is updated
* @cmap: Colour map for 8-bit-per-pixel displays
+ * @fg_col_idx: Foreground color code (bit 3 = bold, bit 0-2 = color)
*/
struct video_priv {
/* Things set up by the driver: */
void *fb;
int fb_size;
int line_length;
- int colour_fg;
- int colour_bg;
+ u32 colour_fg;
+ u32 colour_bg;
bool flush_dcache;
ushort *cmap;
+ u8 fg_col_idx;
};
/* Placeholder - there are no video operations at present */
*/
void video_set_flush_dcache(struct udevice *dev, bool flush);
+/**
+ * Set default colors and attributes
+ *
+ * @priv device information
+ */
+void video_set_default_colors(struct video_priv *priv);
+
#endif /* CONFIG_DM_VIDEO */
#ifndef CONFIG_DM_VIDEO
#ifndef __video_console_h
#define __video_console_h
+#include <video.h>
+
#define VID_FRAC_DIV 256
#define VID_TO_PIXEL(x) ((x) / VID_FRAC_DIV)
#define VID_TO_POS(x) ((x) * VID_FRAC_DIV)
+/*
+ * The 16 colors supported by the console
+ */
+enum color_idx {
+ VID_BLACK = 0,
+ VID_RED,
+ VID_GREEN,
+ VID_BROWN,
+ VID_BLUE,
+ VID_MAGENTA,
+ VID_CYAN,
+ VID_LIGHT_GRAY,
+ VID_GRAY,
+ VID_LIGHT_RED,
+ VID_LIGTH_GREEN,
+ VID_YELLOW,
+ VID_LIGHT_BLUE,
+ VID_LIGHT_MAGENTA,
+ VID_LIGHT_CYAN,
+ VID_WHITE,
+
+ VID_COLOR_COUNT
+};
+
/**
* struct vidconsole_priv - uclass-private data about a console device
*
void vidconsole_position_cursor(struct udevice *dev, unsigned col,
unsigned row);
+#ifdef CONFIG_DM_VIDEO
+
+/**
+ * vid_console_color() - convert a color code to a pixel's internal
+ * representation
+ *
+ * The caller has to guarantee that the color index is less than
+ * VID_COLOR_COUNT.
+ *
+ * @priv private data of the console device
+ * @idx color index
+ * @return color value
+ */
+u32 vid_console_color(struct video_priv *priv, unsigned int idx);
+
+#endif
+
#endif
-/* Hand composed "Minuscule" 4x6 font, with binary data generated using
- * Perl stub.
+/* Hand composed "Minuscule" 4x6 font for code page 437, with binary data
+ * generated using Perl stub.
*
* Use 'perl -x mini_4x6.c < mini_4x6.c > new_version.c' to regenerate
* binary data.
* Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
*
* SPDX-License-Identifier: GPL-2.0+
+ *
+ * This file contains an 8x16 bitmap font for code page 437.
*/
#ifndef _VIDEO_FONT_DATA_
CONFIG_PERIF3_FREQ
CONFIG_PERIF4_FREQ
CONFIG_PHYSMEM
-CONFIG_PHY_ADDR
CONFIG_PHY_BASE_ADR
CONFIG_PHY_BCM5421S
CONFIG_PHY_ET1011C_TX_CLK_FIX
/* test colors (30-37 fg color, 40-47 bg color) */
vidconsole_put_string(con, ANSI_ESC"[30;41mfoo"); /* black on red */
vidconsole_put_string(con, ANSI_ESC"[33;44mbar"); /* yellow on blue */
- ut_asserteq(268, compress_frame_buffer(dev));
+ ut_asserteq(265, compress_frame_buffer(dev));
return 0;
}
tests_xpassed = []
tests_xfailed = []
tests_skipped = []
+tests_warning = []
tests_passed = []
def pytest_itemcollected(item):
if log:
with log.section('Status Report', 'status_report'):
log.status_pass('%d passed' % len(tests_passed))
+ if tests_warning:
+ log.status_warning('%d passed with warning' % len(tests_warning))
+ for test in tests_warning:
+ anchor = anchors.get(test, None)
+ log.status_warning('... ' + test, anchor)
if tests_skipped:
log.status_skipped('%d skipped' % len(tests_skipped))
for test in tests_skipped:
A list of pytest reports (test result data).
"""
+ log.get_and_reset_warning()
reports = runtestprotocol(item, nextitem=nextitem)
+ was_warning = log.get_and_reset_warning()
# In pytest 3, runtestprotocol() may not call pytest_runtest_setup() if
# the test is skipped. That call is required to create the test's section
start_test_section(item)
failure_cleanup = False
- test_list = tests_passed
- msg = 'OK'
- msg_log = log.status_pass
+ if not was_warning:
+ test_list = tests_passed
+ msg = 'OK'
+ msg_log = log.status_pass
+ else:
+ test_list = tests_warning
+ msg = 'OK (with warning)'
+ msg_log = log.status_warning
for report in reports:
if report.outcome == 'failed':
if hasattr(report, 'wasxfail'):
color: #00ff00
}
+.status-warning {
+ color: #ffff00
+}
+
.status-skipped {
color: #ffff00
}
self.timestamp_start = self._get_time()
self.timestamp_prev = self.timestamp_start
self.timestamp_blocks = []
+ self.seen_warning = False
shutil.copy(mod_dir + '/multiplexed_log.css', os.path.dirname(fn))
self.f.write('''\
passed_bcs = passed_bcs.not(":has(.status-xfail)");
passed_bcs = passed_bcs.not(":has(.status-xpass)");
passed_bcs = passed_bcs.not(":has(.status-skipped)");
+ passed_bcs = passed_bcs.not(":has(.status-warning)");
// Hide the passed blocks
passed_bcs.addClass("hidden");
// Flip the expand/contract button hiding for those blocks.
Nothing.
"""
+ self.seen_warning = True
self._note("warning", msg)
+ def get_and_reset_warning(self):
+ """Get and reset the log warning flag.
+
+ Args:
+ None
+
+ Returns:
+ Whether a warning was seen since the last call.
+ """
+
+ ret = self.seen_warning
+ self.seen_warning = False
+ return ret
+
def info(self, msg):
"""Write an informational note to the log file.
self._note("status-pass", msg, anchor)
+ def status_warning(self, msg, anchor=None):
+ """Write a note to the log file describing test(s) which passed.
+
+ Args:
+ msg: A message describing the passed test(s).
+ anchor: Optional internal link target.
+
+ Returns:
+ Nothing.
+ """
+
+ self._note("status-warning", msg, anchor)
+
def status_skipped(self, msg, anchor=None):
"""Write a note to the log file describing skipped test(s).
--- /dev/null
+# Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
+#
+# SPDX-License-Identifier: GPL-2.0
+
+# Test U-Boot's "mmc read" command. The test reads data from the eMMC or SD
+# card, and validates the no errors occurred, and that the expected data was
+# read if the test configuration contains a CRC of the expected data.
+
+import pytest
+import u_boot_utils
+
+"""
+This test relies on boardenv_* to containing configuration values to define
+which MMC devices should be tested. For example:
+
+env__mmc_rd_configs = (
+ {
+ "fixture_id": "emmc-boot0",
+ "is_emmc": True,
+ "devid": 0,
+ "partid": 1,
+ "sector": 0x10,
+ "count": 1,
+ },
+ {
+ "fixture_id": "emmc-boot1",
+ "is_emmc": True,
+ "devid": 0,
+ "partid": 2,
+ "sector": 0x10,
+ "count": 1,
+ },
+ {
+ "fixture_id": "emmc-data",
+ "is_emmc": True,
+ "devid": 0,
+ "partid": 0,
+ "sector": 0x10,
+ "count": 0x1000,
+ },
+ {
+ "fixture_id": "sd-mbr",
+ "is_emmc": False,
+ "devid": 1,
+ "partid": None,
+ "sector": 0,
+ "count": 1,
+ "crc32": "8f6ecf0d",
+ },
+ {
+ "fixture_id": "sd-large",
+ "is_emmc": False,
+ "devid": 1,
+ "partid": None,
+ "sector": 0x10,
+ "count": 0x1000,
+ },
+)
+"""
+
+@pytest.mark.buildconfigspec('cmd_mmc')
+def test_mmc_rd(u_boot_console, env__mmc_rd_config):
+ """Test the "mmc read" command.
+
+ Args:
+ u_boot_console: A U-Boot console connection.
+ env__mmc_rd_config: The single MMC configuration on which
+ to run the test. See the file-level comment above for details
+ of the format.
+
+ Returns:
+ Nothing.
+ """
+
+ is_emmc = env__mmc_rd_config['is_emmc']
+ devid = env__mmc_rd_config['devid']
+ partid = env__mmc_rd_config.get('partid', 0)
+ sector = env__mmc_rd_config.get('sector', 0)
+ count_sectors = env__mmc_rd_config.get('count', 1)
+ expected_crc32 = env__mmc_rd_config.get('crc32', None)
+
+ count_bytes = count_sectors * 512
+ bcfg = u_boot_console.config.buildconfig
+ has_cmd_memory = bcfg.get('config_cmd_memory', 'n') == 'y'
+ has_cmd_crc32 = bcfg.get('config_cmd_crc32', 'n') == 'y'
+ ram_base = u_boot_utils.find_ram_base(u_boot_console)
+ addr = '0x%08x' % ram_base
+
+ # Select MMC device
+ cmd = 'mmc dev %d' % devid
+ if is_emmc:
+ cmd += ' %d' % partid
+ response = u_boot_console.run_command(cmd)
+ assert 'no card present' not in response
+ if is_emmc:
+ partid_response = "(part %d)" % partid
+ else:
+ partid_response = ""
+ good_response = 'mmc%d%s is current device' % (devid, partid_response)
+ assert good_response in response
+
+ # Clear target RAM
+ if expected_crc32:
+ if has_cmd_memory and has_cmd_crc32:
+ cmd = 'mw.b %s 0 0x%x' % (addr, count_bytes)
+ u_boot_console.run_command(cmd)
+
+ cmd = 'crc32 %s 0x%x' % (addr, count_bytes)
+ response = u_boot_console.run_command(cmd)
+ assert expected_crc32 not in response
+ else:
+ u_boot_console.log.warning(
+ 'CONFIG_CMD_MEMORY or CONFIG_CMD_CRC32 != y: Skipping RAM clear')
+
+ # Read data
+ cmd = 'mmc read %s %x %x' % (addr, sector, count_sectors)
+ response = u_boot_console.run_command(cmd)
+ good_response = 'MMC read: dev # %d, block # %d, count %d ... %d blocks read: OK' % (
+ devid, sector, count_sectors, count_sectors)
+ assert good_response in response
+
+ # Check target RAM
+ if expected_crc32:
+ if has_cmd_crc32:
+ cmd = 'crc32 %s 0x%x' % (addr, count_bytes)
+ response = u_boot_console.run_command(cmd)
+ assert expected_crc32 in response
+ else:
+ u_boot_console.log.warning('CONFIG_CMD_CRC32 != y: Skipping check')
projects / u-boot / commitdiff