It looks that x86 chipset always contains a host bridge at pci
b.d.f 0.0.0, so enable this for all boards.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
#define CONFIG_SYS_MONITOR_LEN (1 << 20)
#define CONFIG_ARCH_MISC_INIT
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE
#define CONFIG_SYS_EARLY_PCI_INIT
#define CONFIG_PCI_PNP
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE 0xe000
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE
#define CONFIG_SYS_EARLY_PCI_INIT
#define CONFIG_PCI_PNP
#define CONFIG_SMSC_LPC47M
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE
#define CONFIG_SYS_EARLY_PCI_INIT
#define CONFIG_PCI_PNP
#define CONFIG_RTL8169
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE 0xe000
-#define CONFIG_PCI_CONFIG_HOST_BRIDGE
#define CONFIG_PCI_PNP
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,vga\0" \
* PCI configuration
*/
#define CONFIG_PCI
+#define CONFIG_PCI_CONFIG_HOST_BRIDGE
/*-----------------------------------------------------------------------
* USB configuration