{
clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
- debug("Enable clock domain - 0x%08x\n", clkctrl_reg);
+ debug("Enable clock domain - %p\n", clkctrl_reg);
}
static inline void wait_for_clk_enable(u32 *clkctrl_addr)
{
clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
- debug("Enable clock module - 0x%08x\n", clkctrl_addr);
+ debug("Enable clock module - %p\n", clkctrl_addr);
if (wait_for_enable)
wait_for_clk_enable(clkctrl_addr);
}