]> git.sur5r.net Git - u-boot/commitdiff
mips: ath79: Add support for TPLink WDR4300
authorMarek Vasut <marex@denx.de>
Fri, 6 May 2016 18:10:41 +0000 (20:10 +0200)
committerDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
Fri, 20 May 2016 23:36:39 +0000 (01:36 +0200)
Add support for the TPLink WDR4300 router, which is based on the
AR9344 MIPS 74Kc CPU and has 128 MiB of RAM. The USB is supported
on this system as well.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Wills Wang <wills.wang@live.com>
arch/mips/dts/Makefile
arch/mips/dts/tplink_wdr4300.dts [new file with mode: 0644]
arch/mips/mach-ath79/Kconfig
board/tplink/wdr4300/Kconfig [new file with mode: 0644]
board/tplink/wdr4300/MAINTAINERS [new file with mode: 0644]
board/tplink/wdr4300/Makefile [new file with mode: 0644]
board/tplink/wdr4300/wdr4300.c [new file with mode: 0644]
configs/tplink_wdr4300_defconfig [new file with mode: 0644]
include/configs/tplink_wdr4300.h [new file with mode: 0644]

index bd87ead9723a6b6cab4b88ebf8ec986de883356f..a94b74555073d5c0c59bfdaae1f07e1a0e13f542 100644 (file)
@@ -5,6 +5,7 @@
 dtb-$(CONFIG_TARGET_AP121) += ap121.dtb
 dtb-$(CONFIG_TARGET_AP143) += ap143.dtb
 dtb-$(CONFIG_TARGET_PIC32MZDASK) += pic32mzda_sk.dtb
+dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
 
 targets += $(dtb-y)
 
diff --git a/arch/mips/dts/tplink_wdr4300.dts b/arch/mips/dts/tplink_wdr4300.dts
new file mode 100644 (file)
index 0000000..cfda4df
--- /dev/null
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2016 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+#include "ar934x.dtsi"
+
+/ {
+       model = "TP-Link WDR4300 Board";
+       compatible = "tplink,wdr4300", "qca,ar934x";
+
+       aliases {
+               serial0 = &uart0;
+               spi0 = &spi0;
+       };
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+};
+
+&ehci0 {
+       status = "okay";
+};
+
+&gmac0 {
+       phy-mode = "rgmii";
+       status = "okay";
+};
+
+&spi0 {
+       spi-max-frequency = <25000000>;
+       status = "okay";
+       spi-flash@0 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "spi-flash";
+               memory-map = <0x1e000000 0x00800000>;
+               spi-max-frequency = <25000000>;
+               reg = <0>;
+       };
+};
+
+&uart0 {
+       clock-frequency = <40000000>;
+       status = "okay";
+};
+
+&xtal {
+       clock-frequency = <40000000>;
+};
index 527960f4eb7fb65c6948ab7d5a9d497d2a7f1bff..7d483aa8dce398754df81efdba157d69e179cb75 100644 (file)
@@ -42,9 +42,14 @@ config TARGET_AP143
        bool "AP143 Reference Board"
        select SOC_QCA953X
 
+config BOARD_TPLINK_WDR4300
+       bool "TP-Link WDR4300 Board"
+       select SOC_AR934X
+
 endchoice
 
 source "board/qca/ap121/Kconfig"
 source "board/qca/ap143/Kconfig"
+source "board/tplink/wdr4300/Kconfig"
 
 endmenu
diff --git a/board/tplink/wdr4300/Kconfig b/board/tplink/wdr4300/Kconfig
new file mode 100644 (file)
index 0000000..902abf5
--- /dev/null
@@ -0,0 +1,15 @@
+if BOARD_TPLINK_WDR4300
+
+config SYS_VENDOR
+       default "tplink"
+
+config SYS_SOC
+       default "ath79"
+
+config SYS_BOARD
+       default "wdr4300"
+
+config SYS_CONFIG_NAME
+       default "tplink_wdr4300"
+
+endif
diff --git a/board/tplink/wdr4300/MAINTAINERS b/board/tplink/wdr4300/MAINTAINERS
new file mode 100644 (file)
index 0000000..db239c2
--- /dev/null
@@ -0,0 +1,6 @@
+TPLINK_WDR4300 BOARD
+M:     Marek Vasut <marex@denx.de>
+S:     Maintained
+F:     board/tplink/wdr4300/
+F:     include/configs/tplink_wdr4300.h
+F:     configs/tplink_wdr4300_defconfig
diff --git a/board/tplink/wdr4300/Makefile b/board/tplink/wdr4300/Makefile
new file mode 100644 (file)
index 0000000..4f0c296
--- /dev/null
@@ -0,0 +1,5 @@
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y  = wdr4300.o
diff --git a/board/tplink/wdr4300/wdr4300.c b/board/tplink/wdr4300/wdr4300.c
new file mode 100644 (file)
index 0000000..6e070fd
--- /dev/null
@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2016 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/addrspace.h>
+#include <asm/types.h>
+#include <mach/ath79.h>
+#include <mach/ar71xx_regs.h>
+#include <mach/ddr.h>
+#include <debug_uart.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_USB
+static void wdr4300_usb_start(void)
+{
+       void __iomem *gpio_regs = map_physmem(AR71XX_GPIO_BASE,
+                                             AR71XX_GPIO_SIZE, MAP_NOCACHE);
+       if (!gpio_regs)
+               return;
+
+       /* Power up the USB HUB. */
+       clrbits_be32(gpio_regs + AR71XX_GPIO_REG_OE, BIT(21) | BIT(22));
+       writel(BIT(21) | BIT(22), gpio_regs + AR71XX_GPIO_REG_SET);
+       mdelay(1);
+
+       ath79_usb_reset();
+}
+#else
+static inline void wdr4300_usb_start(void) {}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+       void __iomem *regs;
+
+       regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE,
+                          MAP_NOCACHE);
+
+       /* Assure JTAG is not disconnected. */
+       writel(0x40, regs + AR934X_GPIO_REG_FUNC);
+
+       /* Configure default GPIO input/output regs. */
+       writel(0x3031b, regs + AR71XX_GPIO_REG_OE);
+       writel(0x0f804, regs + AR71XX_GPIO_REG_OUT);
+
+       /* Configure pin multiplexing. */
+       writel(0x00000000, regs + AR934X_GPIO_REG_OUT_FUNC0);
+       writel(0x0b0a0980, regs + AR934X_GPIO_REG_OUT_FUNC1);
+       writel(0x00180000, regs + AR934X_GPIO_REG_OUT_FUNC2);
+       writel(0x00000000, regs + AR934X_GPIO_REG_OUT_FUNC3);
+       writel(0x0000004d, regs + AR934X_GPIO_REG_OUT_FUNC4);
+       writel(0x00000000, regs + AR934X_GPIO_REG_OUT_FUNC5);
+
+#ifdef CONFIG_DEBUG_UART
+       debug_uart_init();
+#endif
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+       ar934x_pll_init(560, 480, 240);
+       ar934x_ddr_init(560, 480, 240);
+#endif
+
+       wdr4300_usb_start();
+       ath79_eth_reset();
+
+       return 0;
+}
+#endif
diff --git a/configs/tplink_wdr4300_defconfig b/configs/tplink_wdr4300_defconfig
new file mode 100644 (file)
index 0000000..b1af2f6
--- /dev/null
@@ -0,0 +1,43 @@
+CONFIG_MIPS=y
+CONFIG_ARCH_ATH79=y
+CONFIG_BOARD_TPLINK_WDR4300=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SYS_NS16550=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEFAULT_DEVICE_TREE="tplink_wdr4300"
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_NET=y
+CONFIG_CMD_NFS=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM_ETH=y
+CONFIG_AG7XXX=y
+CONFIG_CLK=y
+CONFIG_CMD_USB=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_STORAGE=y
+CONFIG_ATH79_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_DATAFLASH=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PINCTRL=y
diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h
new file mode 100644 (file)
index 0000000..2b9e92e
--- /dev/null
@@ -0,0 +1,93 @@
+/*
+ * Copyright (C) 2016 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_TEXT_BASE           0xa1000000
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_SYS_HZ                  1000
+#define CONFIG_SYS_MHZ                 280
+#define CONFIG_SYS_MIPS_TIMER_FREQ     (CONFIG_SYS_MHZ * 1000000)
+
+/* Cache Configuration */
+#define CONFIG_SYS_DCACHE_SIZE         0x8000
+#define CONFIG_SYS_ICACHE_SIZE         0x10000
+#define CONFIG_SYS_CACHELINE_SIZE      32
+
+#define CONFIG_SYS_MONITOR_BASE                CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_MALLOC_LEN          0x40000
+#define CONFIG_SYS_BOOTPARAMS_LEN      0x20000
+
+#define CONFIG_SYS_SDRAM_BASE          0xa0000000
+#define CONFIG_SYS_LOAD_ADDR           0xa1000000
+#define CONFIG_LOADADDR                        CONFIG_SYS_LOAD_ADDR
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_SYS_INIT_RAM_ADDR       0xbd000000
+#define CONFIG_SYS_INIT_RAM_SIZE       0x8000
+#define CONFIG_SYS_INIT_SP_ADDR                \
+       (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
+
+/*
+ * Serial Port
+ */
+#define CONFIG_SYS_NS16550_CLK         40000000
+#define CONFIG_BAUDRATE                        115200
+#define CONFIG_SYS_BAUDRATE_TABLE \
+       {9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_BOOTDELAY               3
+#define CONFIG_BOOTARGS                        \
+       "console=ttyS0,115200 root=/dev/mtdblock2 rootfstype=squashfs"
+#define CONFIG_BOOTCOMMAND             \
+       "dhcp 192.168.1.1:wdr4300.fit && bootm $loadaddr"
+#define CONFIG_LZMA
+
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE                        0x10000
+
+/*
+ * Command
+ */
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_CBSIZE      1024            /* Console I/O buffer size */
+#define CONFIG_SYS_MAXARGS     32              /* Max number of command args */
+#define CONFIG_SYS_BARGSIZE    CONFIG_SYS_CBSIZE
+                                               /* Boot argument buffer size */
+#define CONFIG_VERSION_VARIABLE                        /* U-BOOT version */
+#define CONFIG_AUTO_COMPLETE                   /* Command auto complete */
+#define CONFIG_CMDLINE_EDITING                 /* Command history etc */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
+
+/* USB, USB storage, USB ethernet */
+#define CONFIG_EHCI_MMIO_BIG_ENDIAN
+#define CONFIG_EHCI_DESC_BIG_ENDIAN
+#define CONFIG_EHCI_IS_TDI
+
+#define CONFIG_DOS_PARTITION
+
+/*
+ * Diagnostics
+ */
+#define CONFIG_SYS_MEMTEST_START       0x80100000
+#define CONFIG_SYS_MEMTEST_END         0x83f00000
+#define CONFIG_CMD_MEMTEST
+
+#define CONFIG_USE_PRIVATE_LIBGCC
+
+#define CONFIG_CMD_MII
+#define CONFIG_PHY_GIGE
+
+#endif  /* __CONFIG_H */