arch/arm, arch/powerpc: add # of SEC engines on the SOC

Some SOCs, specifically the ones in the C29x familiy can have
multiple security engines. This patch adds a system configuration
define which indicates the maximum number of SEC engines that
can be found on a SoC.

Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 6529281c94d1dce8bdb2042a0901bb48a80969e3..34b15007ea5e9f534345b915b1c901fa491b807f 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -144,6 +144,7 @@
 #define CONFIG_ARM_ERRATA_829520
 #define CONFIG_ARM_ERRATA_833471
 
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC          1
 #elif defined(CONFIG_LS1043A)
 #define CONFIG_MAX_CPUS                                4
 #define CONFIG_SYS_CACHELINE_SIZE              64
@@ -197,6 +198,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A009929
 #define CONFIG_SYS_FSL_ERRATUM_A009942
 #define CONFIG_SYS_FSL_ERRATUM_A009660
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC          1
 #else
 #error SoC not defined
 #endif

diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index 92f30e28aaaca1ebe163f446139fefd93e039e13..139a6235645cc678b0518502432b8548f49912c2 100644 (file)
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -132,6 +132,7 @@
 #define CONFIG_USB_MAX_CONTROLLER_COUNT                1
 #define CONFIG_SYS_FSL_ERRATUM_A008378
 #define CONFIG_SYS_FSL_ERRATUM_A009663
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC          1
 #else
 #error SoC not defined
 #endif

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index eccc146daedc1433ddce538dac49f4a12bef1aac..505d355bc8c2dc062bcd5758928233ba4ab6410f 100644 (file)
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -928,6 +928,8 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT  8
 #define CONFIG_SYS_CCSRBAR_DEFAULT     0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_A005125
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC  3
+#define CONFIG_SYS_FSL_SEC_IDX_OFFSET  0x20000
 
 #elif defined(CONFIG_QEMU_E500)
 #define CONFIG_MAX_CPUS                        1
@@ -954,4 +956,8 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
 #define CONFIG_SYS_FSL_DDRC_GEN3
 #endif
 
+#if !defined(CONFIG_PPC_C29X)
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC  1
+#endif
+
 #endif /* _ASM_MPC85xx_CONFIG_H_ */

diff --git a/board/freescale/c29xpcie/c29xpcie.c b/board/freescale/c29xpcie/c29xpcie.c
index e325b4db4af9362fbe41dbedb24f07b00348a8af..45f463f01f38134ca38e0793f3b83170b95e1f5f 100644 (file)
--- a/board/freescale/c29xpcie/c29xpcie.c
+++ b/board/freescale/c29xpcie/c29xpcie.c
@@ -122,7 +122,7 @@ void fdt_del_sec(void *blob, int offset)
 
        while ((nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,sec-v6.0",
                        CONFIG_SYS_CCSRBAR_PHYS + CONFIG_SYS_FSL_SEC_OFFSET
-                       + offset * 0x20000)) >= 0) {
+                       + offset * CONFIG_SYS_FSL_SEC_IDX_OFFSET)) >= 0) {
                fdt_del_node(blob, nodeoff);
                offset++;
        }