(pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
-#if defined CONFIG_MX6SL
+#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)
/* Check whether LVE bit needs to be set */
if (pad_ctrl & PAD_CTL_LVE) {
pad_ctrl &= ~PAD_CTL_LVE;
sel_input_ofs += IOMUX_LPSR_SEL_INPUT_OFS;
}
#else
- if (is_mx6ull()) {
+ if (is_mx6ull() || is_mx6sll()) {
if (lpsr == IOMUX_CONFIG_LPSR) {
base = (void *)IOMUXC_SNVS_BASE_ADDR;
mux_mode &= ~IOMUX_CONFIG_LPSR;
#endif
#endif
- if (is_soc_type(MXC_SOC_MX7) || is_cpu_type(MXC_CPU_MX6ULL) || mux_ctrl_ofs)
+ if (is_mx7() || is_mx6ull() || is_mx6sll() || mux_ctrl_ofs)
__raw_writel(mux_mode, base + mux_ctrl_ofs);
if (sel_input_ofs)
#else
if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
__raw_writel(pad_ctrl, base + pad_ctrl_ofs);
+#if defined(CONFIG_MX6SLL)
+ else if ((pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
+ clrbits_le32(base + pad_ctrl_ofs, PAD_CTL_IPD_BIT);
+#endif
#endif
#ifdef CONFIG_IOMUX_LPSR
#define PAD_CTL_DSE_40ohm (6 << 3)
#define PAD_CTL_DSE_34ohm (7 << 3)
-#if defined CONFIG_MX6SL
+/* i.MX6SL/SLL */
#define PAD_CTL_LVE (1 << 1)
#define PAD_CTL_LVE_BIT (1 << 22)
-#endif
+
+/* i.MX6SLL */
+#define PAD_CTL_IPD_BIT (1 << 27)
#elif defined(CONFIG_VF610)