CLKF_MASK = 0x1fff << CLKF_SHIFT,
};
+/* CRU_GLB_RST_ST */
+enum {
+ GLB_POR_RST,
+ FST_GLB_RST_ST = BIT(0),
+ SND_GLB_RST_ST = BIT(1),
+ FST_GLB_TSADC_RST_ST = BIT(2),
+ SND_GLB_TSADC_RST_ST = BIT(3),
+ FST_GLB_WDT_RST_ST = BIT(4),
+ SND_GLB_WDT_RST_ST = BIT(5),
+ GLB_RST_ST_MASK = GENMASK(5, 0),
+};
+
#endif
#include <syscon.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3288.h>
#include <asm/arch/periph.h>
#include <asm/arch/pmu_rk3288.h>
#include <asm/arch/qos_rk3288.h>
return 0;
}
+static void rk3288_detect_reset_reason(void)
+{
+ struct rk3288_cru *cru = rockchip_get_cru();
+ const char *reason;
+
+ if (IS_ERR(cru))
+ return;
+
+ switch (cru->cru_glb_rst_st) {
+ case GLB_POR_RST:
+ reason = "POR";
+ break;
+ case FST_GLB_RST_ST:
+ case SND_GLB_RST_ST:
+ reason = "RST";
+ break;
+ case FST_GLB_TSADC_RST_ST:
+ case SND_GLB_TSADC_RST_ST:
+ reason = "THERMAL";
+ break;
+ case FST_GLB_WDT_RST_ST:
+ case SND_GLB_WDT_RST_ST:
+ reason = "WDOG";
+ break;
+ default:
+ reason = "unknown reset";
+ }
+
+ env_set("reset_reason", reason);
+
+ /*
+ * Clear cru_glb_rst_st, so we can determine the last reset cause
+ * for following resets.
+ */
+ rk_clrreg(&cru->cru_glb_rst_st, GLB_RST_ST_MASK);
+}
+
int board_late_init(void)
{
setup_boot_mode();
rk3288_qos_init();
+ rk3288_detect_reset_reason();
return rk_board_late_init();
}