*/
#define NON_SECURE_SRAM_START 0x40304000
#define NON_SECURE_SRAM_END 0x4030E000 /* Not inclusive */
+#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START
/* base address for indirect vectors (internal boot mode) */
#define SRAM_ROM_VECT_BASE 0x4030D000
+
+ /* ABB settings */
+ #define OMAP_ABB_SETTLING_TIME 50
+ #define OMAP_ABB_CLOCK_CYCLES 16
+
+ /* ABB tranxdone mask */
+ #define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 7)
+
#endif
#define EFUSE_4 0x45145100
#endif /* __ASSEMBLY__ */
- /*
- * Non-secure SRAM Addresses
- * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE
- * at 0x40304000(EMU base) so that our code works for both EMU and GP
- */
+ #ifdef CONFIG_DRA7XX
+ #define NON_SECURE_SRAM_START 0x40300000
+ #define NON_SECURE_SRAM_END 0x40380000 /* Not inclusive */
+ #else
#define NON_SECURE_SRAM_START 0x40300000
#define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */
+ #endif
+#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START
+
/* base address for indirect vectors (internal boot mode) */
#define SRAM_ROM_VECT_BASE 0x4031F000