mx51: Fix USB PHY clocks

The i.MX51 has a single USB PHY clock, while the i.MX53 has two. These 3 clocks
have different clock gate control bit-fields.

The existing code was correct only for i.MX53, so this patch fixes the i.MX51
use case.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Jana Rapava <fermata7@gmail.com>
Cc: Wolfgang Grandegger <wg@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>

diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
index 171d7629ef17e96cdc5e16f2bc7f663df34a342b..4e10d81c9820b0be1447e4d7aa078b8e7370cfb6 100644 (file)
--- a/arch/arm/cpu/armv7/mx5/clock.c
+++ b/arch/arm/cpu/armv7/mx5/clock.c
@@ -126,23 +126,33 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 }
 #endif
 
-void set_usb_phy1_clk(void)
+void set_usb_phy_clk(void)
 {
        clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
 }
 
+#if defined(CONFIG_MX51)
 void enable_usb_phy1_clk(unsigned char enable)
 {
        unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
 
-       clrsetbits_le32(&mxc_ccm->CCGR4,
-                       MXC_CCM_CCGR4_USB_PHY1(MXC_CCM_CCGR_CG_MASK),
-                       MXC_CCM_CCGR4_USB_PHY1(cg));
+       clrsetbits_le32(&mxc_ccm->CCGR2,
+                       MXC_CCM_CCGR2_USB_PHY(MXC_CCM_CCGR_CG_MASK),
+                       MXC_CCM_CCGR2_USB_PHY(cg));
 }
 
-void set_usb_phy2_clk(void)
+void enable_usb_phy2_clk(unsigned char enable)
 {
-       clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
+       /* i.MX51 has a single USB PHY clock, so do nothing here. */
+}
+#elif defined(CONFIG_MX53)
+void enable_usb_phy1_clk(unsigned char enable)
+{
+       unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
+
+       clrsetbits_le32(&mxc_ccm->CCGR4,
+                       MXC_CCM_CCGR4_USB_PHY1(MXC_CCM_CCGR_CG_MASK),
+                       MXC_CCM_CCGR4_USB_PHY1(cg));
 }
 
 void enable_usb_phy2_clk(unsigned char enable)
@@ -153,6 +163,7 @@ void enable_usb_phy2_clk(unsigned char enable)
                        MXC_CCM_CCGR4_USB_PHY2(MXC_CCM_CCGR_CG_MASK),
                        MXC_CCM_CCGR4_USB_PHY2(cg));
 }
+#endif
 
 /*
  * Calculate the frequency of PLLn.
@@ -804,7 +815,7 @@ void mxc_set_sata_internal_clock(void)
        u32 *tmp_base =
                (u32 *)(IIM_BASE_ADDR + 0x180c);
 
-       set_usb_phy1_clk();
+       set_usb_phy_clk();
 
        clrsetbits_le32(tmp_base, 0x6, 0x4);
 }

diff --git a/arch/arm/include/asm/arch-mx5/clock.h b/arch/arm/include/asm/arch-mx5/clock.h
index 82c5b1a0fe5b2915d86f27944b79b8a93d4e265d..83fb87763892a7fc0d5939e33fd03880ab410d5b 100644 (file)
--- a/arch/arm/include/asm/arch-mx5/clock.h
+++ b/arch/arm/include/asm/arch-mx5/clock.h
@@ -57,7 +57,8 @@ u32 imx_get_uartclk(void);
 u32 imx_get_fecclk(void);
 unsigned int mxc_get_clock(enum mxc_clock clk);
 int mxc_set_clock(u32 ref, u32 freq, u32 clk_type);
-void set_usb_phy2_clk(void);
+void set_usb_phy_clk(void);
+void enable_usb_phy1_clk(unsigned char enable);
 void enable_usb_phy2_clk(unsigned char enable);
 void set_usboh3_clk(void);
 void enable_usboh3_clk(unsigned char enable);

diff --git a/drivers/usb/host/ehci-mx5.c b/drivers/usb/host/ehci-mx5.c
index 9c3477304a8b24e3ee5ed8bcb207f1009524947d..9a2c295ec560ea5085163ba62638c3a8aa9b29e6 100644 (file)
--- a/drivers/usb/host/ehci-mx5.c
+++ b/drivers/usb/host/ehci-mx5.c
@@ -220,7 +220,8 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 
        set_usboh3_clk();
        enable_usboh3_clk(1);
-       set_usb_phy2_clk();
+       set_usb_phy_clk();
+       enable_usb_phy1_clk(1);
        enable_usb_phy2_clk(1);
        mdelay(1);