x86: Rename coreboot-serial to x86-serial

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/x86/dts/coreboot.dtsi b/arch/x86/dts/coreboot.dtsi
index c8dc4cec3c99aac8edf1cbd9186ca900223bc241..65a93acd3d56a10b07ab14bf6bdaf7ba51827feb 100644 (file)
--- a/arch/x86/dts/coreboot.dtsi
+++ b/arch/x86/dts/coreboot.dtsi
@@ -6,7 +6,7 @@
        };
 
        serial {
-               compatible = "coreboot-uart";
+               compatible = "x86-uart";
                reg = <0x3f8 0x10>;
                reg-shift = <0>;
                io-mapped = <1>;

diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 8c8494276116360d5340d669c7e7e7130a6e1549..4cc00cd2f84ef2c8cfff3e5c2c0a022d870ceaea 100644 (file)
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -43,7 +43,7 @@ obj-$(CONFIG_ARC_SERIAL) += serial_arc.o
 obj-$(CONFIG_TEGRA_SERIAL) += serial_tegra.o
 obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o
 obj-$(CONFIG_OMAP_SERIAL) += serial_omap.o
-obj-$(CONFIG_COREBOOT_SERIAL) += serial_coreboot.o
+obj-$(CONFIG_X86_SERIAL) += serial_x86.o
 
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_USB_TTY) += usbtty.o

diff --git a/drivers/serial/serial_coreboot.c b/drivers/serial/serial_coreboot.c
deleted file mode 100644 (file)
index 5c6a76c..0000000
--- a/drivers/serial/serial_coreboot.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Copyright (c) 2014 Google, Inc
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <ns16550.h>
-#include <serial.h>
-
-static const struct udevice_id coreboot_serial_ids[] = {
-       { .compatible = "coreboot-uart" },
-       { }
-};
-
-static int coreboot_serial_ofdata_to_platdata(struct udevice *dev)
-{
-       struct ns16550_platdata *plat = dev_get_platdata(dev);
-       int ret;
-
-       ret = ns16550_serial_ofdata_to_platdata(dev);
-       if (ret)
-               return ret;
-       plat->clock = 1843200;
-
-       return 0;
-}
-U_BOOT_DRIVER(serial_ns16550) = {
-       .name   = "serial_coreboot",
-       .id     = UCLASS_SERIAL,
-       .of_match = coreboot_serial_ids,
-       .ofdata_to_platdata = coreboot_serial_ofdata_to_platdata,
-       .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
-       .priv_auto_alloc_size = sizeof(struct NS16550),
-       .probe = ns16550_serial_probe,
-       .ops    = &ns16550_serial_ops,
-};

diff --git a/drivers/serial/serial_x86.c b/drivers/serial/serial_x86.c
new file mode 100644 (file)
index 0000000..e81e035
--- /dev/null
+++ b/drivers/serial/serial_x86.c
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <ns16550.h>
+#include <serial.h>
+
+static const struct udevice_id x86_serial_ids[] = {
+       { .compatible = "x86-uart" },
+       { }
+};
+
+static int x86_serial_ofdata_to_platdata(struct udevice *dev)
+{
+       struct ns16550_platdata *plat = dev_get_platdata(dev);
+       int ret;
+
+       ret = ns16550_serial_ofdata_to_platdata(dev);
+       if (ret)
+               return ret;
+       plat->clock = 1843200;
+
+       return 0;
+}
+U_BOOT_DRIVER(serial_ns16550) = {
+       .name   = "serial_x86",
+       .id     = UCLASS_SERIAL,
+       .of_match = x86_serial_ids,
+       .ofdata_to_platdata = x86_serial_ofdata_to_platdata,
+       .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
+       .priv_auto_alloc_size = sizeof(struct NS16550),
+       .probe = ns16550_serial_probe,
+       .ops    = &ns16550_serial_ops,
+};

diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h
index b311f4c5e6f51d40b1bf9ddd33719c43d42d0b69..8930210908f648170dd6b97a14172f7280f48546 100644 (file)
--- a/include/configs/chromebook_link.h
+++ b/include/configs/chromebook_link.h
@@ -28,7 +28,7 @@
 #define CONFIG_X86_MRC_ADDR                    0xfffa0000
 #define CONFIG_CACHE_MRC_SIZE_KB               512
 
-#define CONFIG_COREBOOT_SERIAL
+#define CONFIG_X86_SERIAL
 
 #define CONFIG_SCSI_DEV_LIST           {PCI_VENDOR_ID_INTEL, \
                        PCI_DEVICE_ID_INTEL_NM10_AHCI},       \

diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h
index 25813804834088219d2f376a2ec68e8f9c9b10a4..990a2d186e3e30456408c5b82cb3ee089c21a849 100644 (file)
--- a/include/configs/coreboot.h
+++ b/include/configs/coreboot.h
@@ -49,7 +49,7 @@
        {PCI_VENDOR_ID_INTEL,           \
                        PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
 
-#define CONFIG_COREBOOT_SERIAL
+#define CONFIG_X86_SERIAL
 
 #define CONFIG_STD_DEVICES_SETTINGS     "stdin=usbkbd,vga,serial\0" \
                                        "stdout=vga,serial,cbmem\0" \

diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h
index b9db6b7649efc0404ca9be9e5249c74646912365..eadb339a0f0473750a163b76d5a4157d5c181857 100644 (file)
--- a/include/configs/crownbay.h
+++ b/include/configs/crownbay.h
@@ -20,7 +20,7 @@
 #define CONFIG_X86_RESET_VECTOR
 #define CONFIG_NR_DRAM_BANKS           1
 
-#define CONFIG_COREBOOT_SERIAL
+#define CONFIG_X86_SERIAL
 #define CONFIG_SMSC_LPC47M
 
 #define CONFIG_PCI_MEM_BUS             0x40000000