ppc4xx: Add USB OHCI support to AMCC Canyonlands 460EX eval board

This patch adds USB OHCI support to the Canyonlands board port. It also
enables EXT2 support.

Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c
index 35514296961720a079efdae763600d7faaba3451..36779f576f2b650ba693f434cad916657410eb02 100644 (file)
--- a/board/amcc/canyonlands/canyonlands.c
+++ b/board/amcc/canyonlands/canyonlands.c
@@ -26,6 +26,7 @@
 #include <asm/io.h>
 #include <asm/mmu.h>
 #include <asm/4xx_pcie.h>
+#include <asm/gpio.h>
 
 extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
 
@@ -100,6 +101,19 @@ int board_early_init_f(void)
 
        mtsdr(SDR0_SRST1, 0);   /* Pull AHB out of reset default=1 */
 
+       /* Setup PLB4-AHB bridge based on the system address map */
+       mtdcr(AHB_TOP, 0x8000004B);
+       mtdcr(AHB_BOT, 0x8000004B);
+
+       /*
+        * Configure USB-STP pins as alternate and not GPIO
+        * It seems to be neccessary to configure the STP pins as GPIO
+        * input at powerup (perhaps while USB reset is asserted). So
+        * we configure those pins to their "real" function now.
+        */
+       gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
+       gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
+
        return 0;
 }
 

diff --git a/board/amcc/canyonlands/init.S b/board/amcc/canyonlands/init.S
index b7cac23cc4d1519808d1e15f9b1606d71f9351ae..bd4cab56d8bbd6e598d228c731be912f5c9d00f6 100644 (file)
--- a/board/amcc/canyonlands/init.S
+++ b/board/amcc/canyonlands/init.S
@@ -88,6 +88,9 @@ tlbtab:
        /* TLB-entry for Local Configuration registers => peripherals */
        tlbentry(CFG_LOCAL_CONF_REGS, SZ_16M, CFG_LOCAL_CONF_REGS, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
 
+       /* AHB: Internal USB Peripherals (USB, SATA) */
+       tlbentry(CFG_AHB_BASE, SZ_1M, 0xbff00000, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
+
        tlbtab_end
 
 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)

diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h
index b1b470987e252d3830c7025e78e7d717c4f9636f..a4bcc655ee2bab8bd6b5cf1d28f80a2fd9f9fc27 100644 (file)
--- a/include/configs/canyonlands.h
+++ b/include/configs/canyonlands.h
@@ -79,6 +79,8 @@
 
 #define CFG_PERIPHERAL_BASE    0xEF600000      /* internal peripherals */
 
+#define CFG_AHB_BASE           0xE2000000      /* internal AHB peripherals     */
+
 #define CFG_MONITOR_BASE       TEXT_BASE
 #define CFG_MONITOR_LEN                (384 * 1024)    /* Reserve 384 kB for Monitor */
 #define CFG_MALLOC_LEN         (512 * 1024)    /* Reserve 512 kB for malloc()*/
@@ -270,6 +272,21 @@
 
 #define CFG_RX_ETH_BUFFER      32      /* Number of ethernet rx buffers & descriptors */
 
+/*-----------------------------------------------------------------------
+ * USB-OHCI
+ *----------------------------------------------------------------------*/
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_USB_STORAGE
+#undef CFG_OHCI_BE_CONTROLLER          /* 460EX has little endian descriptors  */
+#define CFG_OHCI_SWAP_REG_ACCESS       /* 460EX has little endian register     */
+#define CFG_OHCI_USE_NPS               /* force NoPowerSwitching mode          */
+#define CFG_USB_OHCI_REGS_BASE (CFG_AHB_BASE | 0xd0000)
+#define CFG_USB_OHCI_SLOT_NAME "ppc440"
+#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
+
+/*-----------------------------------------------------------------------
+ * Default environment
+ *----------------------------------------------------------------------*/
 #define CONFIG_PREBOOT "echo;" \
        "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
        "echo"
@@ -344,6 +361,7 @@
 #define CONFIG_CMD_DIAG
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_ELF
+#define CONFIG_CMD_EXT2
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_IRQ
@@ -355,6 +373,12 @@
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_USB
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
 
 /*-----------------------------------------------------------------------
  * Miscellaneous configurable options
@@ -466,28 +490,28 @@
 #define CFG_4xx_GPIO_TABLE { /*          Out             GPIO  Alternate1      Alternate2      Alternate3 */ \
 {                                                                                      \
 /* GPIO Core 0 */                                                                      \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO0        GMC1TxD(0)      USB2HostD(0)    */      \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO1        GMC1TxD(1)      USB2HostD(1)    */      \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO2        GMC1TxD(2)      USB2HostD(2)    */      \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO3        GMC1TxD(3)      USB2HostD(3)    */      \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO4        GMC1TxD(4)      USB2HostD(4)    */      \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO5        GMC1TxD(5)      USB2HostD(5)    */      \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO6        GMC1TxD(6)      USB2HostD(6)    */      \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO7        GMC1TxD(7)      USB2HostD(7)    */      \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO8        GMC1RxD(0)      USB2OTGD(0)     */      \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO9        GMC1RxD(1)      USB2OTGD(1)     */      \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2)    USB2OTGD(2)     */      \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3)    USB2OTGD(3)     */      \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4)    USB2OTGD(4)     */      \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5)    USB2OTGD(5)     */      \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6)    USB2OTGD(6)     */      \
-{GPIO0_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7)    USB2OTGD(7)     */      \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO16 GMC1TxER      USB2HostStop    */      \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO17 GMC1CD                USB2HostNext    */      \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO18 GMC1RxER      USB2HostDir     */      \
-{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO19 GMC1TxEN      USB2OTGStop     */      \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO20 GMC1CRS       USB2OTGNext     */      \
-{GPIO0_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO21 GMC1RxDV      USB2OTGDir      */      \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0        GMC1TxD(0)      USB2HostD(0)    */      \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1        GMC1TxD(1)      USB2HostD(1)    */      \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2        GMC1TxD(2)      USB2HostD(2)    */      \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO3        GMC1TxD(3)      USB2HostD(3)    */      \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO4        GMC1TxD(4)      USB2HostD(4)    */      \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO5        GMC1TxD(5)      USB2HostD(5)    */      \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO6        GMC1TxD(6)      USB2HostD(6)    */      \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO7        GMC1TxD(7)      USB2HostD(7)    */      \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8        GMC1RxD(0)      USB2OTGD(0)     */      \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9        GMC1RxD(1)      USB2OTGD(1)     */      \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2)    USB2OTGD(2)     */      \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3)    USB2OTGD(3)     */      \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4)    USB2OTGD(4)     */      \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5)    USB2OTGD(5)     */      \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6)    USB2OTGD(6)     */      \
+{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7)    USB2OTGD(7)     */      \
+{GPIO0_BASE, GPIO_IN , GPIO_SEL,  GPIO_OUT_0}, /* GPIO16 GMC1TxER      USB2HostStop    */      \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD                USB2HostNext    */      \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER      USB2HostDir     */      \
+{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO19 GMC1TxEN      USB2OTGStop     */      \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS       USB2OTGNext     */      \
+{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV      USB2OTGDir      */      \
 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY                         */      \
 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN                         */      \
 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN                         */      \

diff --git a/include/ppc440.h b/include/ppc440.h
index cf29fe7065f09a331754014b817e90b78f20f44c..80dd33235c761f37ab1b109247172b84e01d402a 100644 (file)
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -3355,6 +3355,9 @@
 #define SDR0_DDR0_DDRM_DECODE(n)       ((((unsigned long)(n))>>29)&0x03)
 #define SDR0_DDR0_TUNE_ENCODE(n)       ((((unsigned long)(n))&0x2FF)<<0)
 #define SDR0_DDR0_TUNE_DECODE(n)       ((((unsigned long)(n))>>0)&0x2FF)
+
+#define AHB_TOP                        0xA4
+#define AHB_BOT                        0xA5
 #endif /* CONFIG_460EX || CONFIG_460GT */
 
 #define SDR0_SDCS_SDD                  (0x80000000 >> 31)