*/
int board_early_init_f(void)
{
- writeb(0x01, &sc520_mmcr->gpcsrt); /* GP Chip Select Recovery Time */
- writeb(0x07, &sc520_mmcr->gpcspw); /* GP Chip Select Pulse Width */
- writeb(0x00, &sc520_mmcr->gpcsoff); /* GP Chip Select Offset */
- writeb(0x05, &sc520_mmcr->gprdw); /* GP Read pulse width */
- writeb(0x01, &sc520_mmcr->gprdoff); /* GP Read offset */
- writeb(0x05, &sc520_mmcr->gpwrw); /* GP Write pulse width */
- writeb(0x01, &sc520_mmcr->gpwroff); /* GP Write offset */
-
- writew(0x0630, &sc520_mmcr->piodata15_0); /* PIO15_PIO0 Data */
- writew(0x2000, &sc520_mmcr->piodata31_16); /* PIO31_PIO16 Data */
- writew(0x2000, &sc520_mmcr->piodir31_16); /* GPIO Direction */
- writew(0x87b5, &sc520_mmcr->piodir15_0); /* GPIO Direction */
- writew(0x0dfe, &sc520_mmcr->piopfs31_16); /* GPIO pin function 31-16 reg */
- writew(0x200a, &sc520_mmcr->piopfs15_0); /* GPIO pin function 15-0 reg */
- writeb(0xf8, &sc520_mmcr->cspfs); /* Chip Select Pin Function Select */
-
- writel(0x200713f8, &sc520_mmcr->par[2]); /* Uart A (GPCS0, 0x013f8, 8 Bytes) */
- writel(0x2c0712f8, &sc520_mmcr->par[3]); /* Uart B (GPCS3, 0x012f8, 8 Bytes) */
- writel(0x300711f8, &sc520_mmcr->par[4]); /* Uart C (GPCS4, 0x011f8, 8 Bytes) */
- writel(0x340710f8, &sc520_mmcr->par[5]); /* Uart D (GPCS5, 0x010f8, 8 Bytes) */
- writel(0xe3ffc000, &sc520_mmcr->par[6]); /* SDRAM (0x00000000, 128MB) */
- writel(0xaa3fd000, &sc520_mmcr->par[7]); /* StrataFlash (ROMCS1, 0x10000000, 16MB) */
- writel(0xca3fd100, &sc520_mmcr->par[8]); /* StrataFlash (ROMCS2, 0x11000000, 16MB) */
- writel(0x4203d900, &sc520_mmcr->par[9]); /* SRAM (GPCS0, 0x19000000, 1MB) */
- writel(0x4e03d910, &sc520_mmcr->par[10]); /* SRAM (GPCS3, 0x19100000, 1MB) */
- writel(0x50018100, &sc520_mmcr->par[11]); /* DP-RAM (GPCS4, 0x18100000, 4kB) */
- writel(0x54020000, &sc520_mmcr->par[12]); /* CFLASH1 (0x200000000, 4kB) */
- writel(0x5c020001, &sc520_mmcr->par[13]); /* CFLASH2 (0x200010000, 4kB) */
-/* writel(0x8bfff800, &sc520_mmcr->par14); */ /* BOOTCS at 0x18000000 */
-/* writel(0x38201000, &sc520_mmcr->par15); */ /* LEDs etc (GPCS6, 0x1000, 20 Bytes */
+ u16 pio_out_cfg = 0x0000;
+
+ /* Configure General Purpose Bus timing */
+ writeb(CONFIG_SYS_SC520_GPCSRT, &sc520_mmcr->gpcsrt);
+ writeb(CONFIG_SYS_SC520_GPCSPW, &sc520_mmcr->gpcspw);
+ writeb(CONFIG_SYS_SC520_GPCSOFF, &sc520_mmcr->gpcsoff);
+ writeb(CONFIG_SYS_SC520_GPRDW, &sc520_mmcr->gprdw);
+ writeb(CONFIG_SYS_SC520_GPRDOFF, &sc520_mmcr->gprdoff);
+ writeb(CONFIG_SYS_SC520_GPWRW, &sc520_mmcr->gpwrw);
+ writeb(CONFIG_SYS_SC520_GPWROFF, &sc520_mmcr->gpwroff);
+
+ /* Configure Programmable Input/Output Pins */
+ writew(CONFIG_SYS_SC520_PIODIR15_0, &sc520_mmcr->piodir15_0);
+ writew(CONFIG_SYS_SC520_PIODIR31_16, &sc520_mmcr->piodir31_16);
+ writew(CONFIG_SYS_SC520_PIOPFS31_16, &sc520_mmcr->piopfs31_16);
+ writew(CONFIG_SYS_SC520_PIOPFS15_0, &sc520_mmcr->piopfs15_0);
+ writeb(CONFIG_SYS_SC520_CSPFS, &sc520_mmcr->cspfs);
+ writeb(CONFIG_SYS_SC520_CLKSEL, &sc520_mmcr->clksel);
+
+ /*
+ * Turn off top board
+ * Set StrataFlash chips to 16-bit width
+ * Set StrataFlash chips to normal (non reset/power down) mode
+ */
+ pio_out_cfg |= CONFIG_SYS_ENET_TOP_BRD_PWR;
+ pio_out_cfg |= CONFIG_SYS_ENET_SF_WIDTH;
+ pio_out_cfg |= CONFIG_SYS_ENET_SF1_MODE;
+ pio_out_cfg |= CONFIG_SYS_ENET_SF2_MODE;
+ writew(pio_out_cfg, &sc520_mmcr->pioset15_0);
+
+ /* Turn off auxiliary power output */
+ writew(CONFIG_SYS_ENET_AUX_PWR, &sc520_mmcr->pioclr15_0);
+
+ /* Clear FPGA program mode */
+ writew(CONFIG_SYS_ENET_FPGA_PROG, &sc520_mmcr->pioset31_16);
+
+ /* Configure Programmable Address Regions */
+ writel(CONFIG_SYS_SC520_UARTA_PAR, &sc520_mmcr->par[2]);
+ writel(CONFIG_SYS_SC520_UARTB_PAR, &sc520_mmcr->par[3]);
+ writel(CONFIG_SYS_SC520_UARTC_PAR, &sc520_mmcr->par[4]);
+ writel(CONFIG_SYS_SC520_UARTD_PAR, &sc520_mmcr->par[5]);
+ writel(CONFIG_SYS_SC520_SDRAM_PAR, &sc520_mmcr->par[6]);
+ writel(CONFIG_SYS_SC520_SF1_PAR, &sc520_mmcr->par[7]);
+ writel(CONFIG_SYS_SC520_SF2_PAR, &sc520_mmcr->par[8]);
+ writel(CONFIG_SYS_SC520_SRAM1_PAR, &sc520_mmcr->par[9]);
+ writel(CONFIG_SYS_SC520_SRAM2_PAR, &sc520_mmcr->par[10]);
+ writel(CONFIG_SYS_SC520_DPRAM_PAR, &sc520_mmcr->par[11]);
+ writel(CONFIG_SYS_SC520_CF1_PAR, &sc520_mmcr->par[12]);
+ writel(CONFIG_SYS_SC520_CF2_PAR, &sc520_mmcr->par[13]);
+/* writel(CONFIG_SYS_SC520_BOOTCS_PAR, &sc520_mmcr->par14); */
+/* writel(CONFIG_SYS_SC520_LLIO_PAR, &sc520_mmcr->par15); */
/* Disable Watchdog */
writew(0x3333, &sc520_mmcr->wdtmrctl);
writew(0x0000, &sc520_mmcr->wdtmrctl);
/* Chip Select Configuration */
- writew(0x0033, &sc520_mmcr->bootcsctl);
- writew(0x0615, &sc520_mmcr->romcs1ctl);
- writew(0x0615, &sc520_mmcr->romcs2ctl);
+ writew(CONFIG_SYS_SC520_BOOTCS_CTRL, &sc520_mmcr->bootcsctl);
+ writew(CONFIG_SYS_SC520_ROMCS1_CTRL, &sc520_mmcr->romcs1ctl);
+ writew(CONFIG_SYS_SC520_ROMCS2_CTRL, &sc520_mmcr->romcs2ctl);
- /*
- * Set the timer pin mapping
- * no clock frequency selected, use 1.1892MHz
- */
- writeb(0x72, &sc520_mmcr->clksel);
+ writeb(CONFIG_SYS_SC520_ADDDECCTL, &sc520_mmcr->adddecctl);
+ writeb(CONFIG_SYS_SC520_UART1CTL, &sc520_mmcr->uart1ctl);
+ writeb(CONFIG_SYS_SC520_UART2CTL, &sc520_mmcr->uart2ctl);
- writeb(0x00, &sc520_mmcr->adddecctl);
- writeb(0x07, &sc520_mmcr->uart1ctl);
- writeb(0x07, &sc520_mmcr->uart2ctl);
- writeb(0x06, &sc520_mmcr->sysarbctl);
- writew(0x0003, &sc520_mmcr->sysarbmenb);
+ writeb(CONFIG_SYS_SC520_SYSARBCTL, &sc520_mmcr->sysarbctl);
+ writew(CONFIG_SYS_SC520_SYSARBMENB, &sc520_mmcr->sysarbmenb);
/* enable posted-writes */
- writeb(0x04, &sc520_mmcr->hbctl);
+ writeb(CONFIG_SYS_SC520_HBCTL, &sc520_mmcr->hbctl);
return 0;
}
#define CONFIG_SYS_FPGA_MAX_FINALISE_TIME 10 /* milliseconds */
#define CONFIG_SYS_FPGA_SSI_DATA_RATE 8333 /* kHz (33.3333MHz xtal) */
+/*-----------------------------------------------------------------------
+ * BOOTCS Control (for AM29LV040B-120JC)
+ *
+ * 000 0 00 0 000 11 0 011 }- 0x0033
+ * \ / | \| | \ / \| | \ /
+ * | | | | | | | |
+ * | | | | | | | +---- 3 Wait States (First Access)
+ * | | | | | | +------- Reserved
+ * | | | | | +--------- 3 Wait States (Subsequent Access)
+ * | | | | +------------- Reserved
+ * | | | +---------------- Non-Paged Mode
+ * | | +------------------ 8 Bit Wide
+ * | +--------------------- GP Bus
+ * +------------------------ Reserved
+ */
+#define CONFIG_SYS_SC520_BOOTCS_CTRL 0x0033
+
+/*-----------------------------------------------------------------------
+ * ROMCS Control (for E28F128J3A-150 StrataFlash)
+ *
+ * 000 0 01 1 000 01 0 101 }- 0x0615
+ * \ / | \| | \ / \| | \ /
+ * | | | | | | | |
+ * | | | | | | | +---- 5 Wait States (First Access)
+ * | | | | | | +------- Reserved
+ * | | | | | +--------- 1 Wait State (Subsequent Access)
+ * | | | | +------------- Reserved
+ * | | | +---------------- Paged Mode
+ * | | +------------------ 16 Bit Wide
+ * | +--------------------- GP Bus
+ * +------------------------ Reserved
+ */
+#define CONFIG_SYS_SC520_ROMCS1_CTRL 0x0615
+#define CONFIG_SYS_SC520_ROMCS2_CTRL 0x0615
+
+/*-----------------------------------------------------------------------
+ * SC520 General Purpose Bus configuration
+ *
+ * Chip Select Offset 1 Clock Cycle
+ * Chip Select Pulse Width 8 Clock Cycles
+ * Chip Select Read Offset 2 Clock Cycles
+ * Chip Select Read Width 6 Clock Cycles
+ * Chip Select Write Offset 2 Clock Cycles
+ * Chip Select Write Width 6 Clock Cycles
+ * Chip Select Recovery Time 2 Clock Cycles
+ *
+ * Timing Diagram (from SC520 Register Set Manual - Order #22005B)
+ *
+ * |<-------------General Purpose Bus Cycle---------------->|
+ * | |
+ * ----------------------\__________________/------------------
+ * |<--(GPCSOFF + 1)-->|<--(GPCSPW + 1)-->|<-(GPCSRT + 1)-> |
+ *
+ * ------------------------\_______________/-------------------
+ * |<---(GPRDOFF + 1)--->|<-(GPRDW + 1)->|
+ *
+ * --------------------------\_______________/-----------------
+ * |<----(GPWROFF + 1)---->|<-(GPWRW + 1)->|
+ *
+ * ________/-----------\_______________________________________
+ * |<--->|<--------->|
+ * ^ ^
+ * (GPALEOFF + 1) |
+ * |
+ * (GPALEW + 1)
+ */
+#define CONFIG_SYS_SC520_GPCSOFF 0x00
+#define CONFIG_SYS_SC520_GPCSPW 0x07
+#define CONFIG_SYS_SC520_GPRDOFF 0x01
+#define CONFIG_SYS_SC520_GPRDW 0x05
+#define CONFIG_SYS_SC520_GPWROFF 0x01
+#define CONFIG_SYS_SC520_GPWRW 0x05
+#define CONFIG_SYS_SC520_GPCSRT 0x01
+
+/*-----------------------------------------------------------------------
+ * SC520 Programmable I/O configuration
+ *
+ * Pin Mode Dir. Description
+ * ----------------------------------------------------------------------
+ * PIO0 PIO Output Unused
+ * PIO1 GPBHE# Output GP Bus Byte High Enable (active low)
+ * PIO2 PIO Output Auxiliary power output enable
+ * PIO3 GPAEN Output GP Bus Address Enable
+ * PIO4 PIO Output Top Board Enable (active low)
+ * PIO5 PIO Output StrataFlash 16 bit mode (low = 8 bit mode)
+ * PIO6 PIO Input Data output of Power Supply ADC
+ * PIO7 PIO Output Clock input to Power Supply ADC
+ * PIO8 PIO Output Chip Select input of Power Supply ADC
+ * PIO9 PIO Output StrataFlash 1 Reset / Power Down (active low)
+ * PIO10 PIO Output StrataFlash 2 Reset / Power Down (active low)
+ * PIO11 PIO Input StrataFlash 1 Status
+ * PIO12 PIO Input StrataFlash 2 Status
+ * PIO13 GPIRQ10# Input Can Bus / I2C IRQ (active low)
+ * PIO14 PIO Input Low Input Voltage Warning (active low)
+ * PIO15 PIO Output Watchdog (must toggle at least every 1.6s)
+ * PIO16 PIO Input Power Fail
+ * PIO17 GPIRQ6 Input Compact Flash 1 IRQ (active low)
+ * PIO18 GPIRQ5 Input Compact Flash 2 IRQ (active low)
+ * PIO19 GPIRQ4# Input Dual-Port RAM IRQ (active low)
+ * PIO20 GPIRQ3 Input UART D IRQ
+ * PIO21 GPIRQ2 Input UART C IRQ
+ * PIO22 GPIRQ1 Input UART B IRQ
+ * PIO23 GPIRQ0 Input UART A IRQ
+ * PIO24 GPDBUFOE# Output GP Bus Data Bus Buffer Output Enable
+ * PIO25 PIO Input Battery OK Indication
+ * PIO26 GPMEMCS16# Input GP Bus Memory Chip-Select 16-bit access
+ * PIO27 GPCS0# Output SRAM 1 Chip Select
+ * PIO28 PIO Input Top Board UART CTS
+ * PIO29 PIO Output FPGA Program Mode (active low)
+ * PIO30 PIO Input FPGA Initialised (active low)
+ * PIO31 PIO Input FPGA Done (active low)
+ */
+#define CONFIG_SYS_SC520_PIOPFS15_0 0x200a
+#define CONFIG_SYS_SC520_PIOPFS31_16 0x0dfe
+#define CONFIG_SYS_SC520_PIODIR15_0 0x87bf
+#define CONFIG_SYS_SC520_PIODIR31_16 0x2900
+
+/*-----------------------------------------------------------------------
+ * PIO Pin defines
+ */
+#define CONFIG_SYS_ENET_AUX_PWR 0x0004
+#define CONFIG_SYS_ENET_TOP_BRD_PWR 0x0010
+#define CONFIG_SYS_ENET_SF_WIDTH 0x0020
+#define CONFIG_SYS_ENET_PWR_ADC_DATA 0x0040
+#define CONFIG_SYS_ENET_PWR_ADC_CLK 0x0080
+#define CONFIG_SYS_ENET_PWR_ADC_CS 0x0100
+#define CONFIG_SYS_ENET_SF1_MODE 0x0200
+#define CONFIG_SYS_ENET_SF2_MODE 0x0400
+#define CONFIG_SYS_ENET_SF1_STATUS 0x0800
+#define CONFIG_SYS_ENET_SF2_STATUS 0x1000
+#define CONFIG_SYS_ENET_PWR_STATUS 0x4000
+#define CONFIG_SYS_ENET_WATCHDOG 0x8000
+
+#define CONFIG_SYS_ENET_PWR_FAIL 0x0001
+#define CONFIG_SYS_ENET_BAT_OK 0x0200
+#define CONFIG_SYS_ENET_TOP_BRD_CTS 0x1000
+#define CONFIG_SYS_ENET_FPGA_PROG 0x2000
+#define CONFIG_SYS_ENET_FPGA_INIT 0x4000
+#define CONFIG_SYS_ENET_FPGA_DONE 0x8000
+
+/*-----------------------------------------------------------------------
+ * Chip Select Pin Function Select
+ *
+ * 1 1 1 1 1 0 0 0 }- 0xf8
+ * | | | | | | | |
+ * | | | | | | | +--- Reserved
+ * | | | | | | +----- GPCS1_SEL = ROMCS1#
+ * | | | | | +------- GPCS2_SEL = ROMCS2#
+ * | | | | +--------- GPCS3_SEL = GPCS3
+ * | | | +----------- GPCS4_SEL = GPCS4
+ * | | +------------- GPCS5_SEL = GPCS5
+ * | +--------------- GPCS6_SEL = GPCS6
+ * +----------------- GPCS7_SEL = GPCS7
+ */
+#define CONFIG_SYS_SC520_CSPFS 0xf8
+
+/*-----------------------------------------------------------------------
+ * Clock Select (CLKTIMER[CLKTEST] pin)
+ *
+ * 0 111 00 1 0 }- 0x72
+ * | \ / \| | |
+ * | | | | +--- Pin Disabled
+ * | | | +----- Pin is an output
+ * | | +------- Reserved
+ * | +----------- Disabled (pin stays Low)
+ * +-------------- Reserved
+ */
+#define CONFIG_SYS_SC520_CLKSEL 0x72
+
+/*-----------------------------------------------------------------------
+ * Address Decode Control
+ *
+ * 0 00 0 0 0 0 0 }- 0x00
+ * | \| | | | | |
+ * | | | | | | +--- Integrated UART 1 is enabled
+ * | | | | | +----- Integrated UART 2 is enabled
+ * | | | | +------- Integrated RTC is enabled
+ * | | | +--------- Reserved
+ * | | +----------- I/O Hole accesses are forwarded to the external GP bus
+ * | +------------- Reserved
+ * +---------------- Write-protect violations do not generate an IRQ
+ */
+#define CONFIG_SYS_SC520_ADDDECCTL 0x00
+
+/*-----------------------------------------------------------------------
+ * UART Control
+ *
+ * 00000 1 1 1 }- 0x07
+ * \___/ | | |
+ * | | | +--- Transmit TC interrupt enable
+ * | | +----- Receive TC interrupt enable
+ * | +------- 1.8432 MHz
+ * +----------- Reserved
+ */
+#define CONFIG_SYS_SC520_UART1CTL 0x07
+#define CONFIG_SYS_SC520_UART2CTL 0x07
+
+/*-----------------------------------------------------------------------
+ * System Arbiter Control
+ *
+ * 00000 1 1 0 }- 0x06
+ * \___/ | | |
+ * | | | +--- Disable PCI Bus Arbiter Grant Time-Out Interrupt
+ * | | +----- The system arbiter operates in concurrent mode
+ * | +------- Park the PCI bus on the last master that acquired the bus
+ * +----------- Reserved
+ */
+#define CONFIG_SYS_SC520_SYSARBCTL 0x06
+
+/*-----------------------------------------------------------------------
+ * System Arbiter Master Enable
+ *
+ * 00000000000 0 0 0 1 1 }- 0x06
+ * \_________/ | | | | |
+ * | | | | | +--- PCI master REQ0 enabled (Ethernet 1)
+ * | | | | +----- PCI master REQ1 enabled (Ethernet 2)
+ * | | | +------- PCI master REQ2 disabled
+ * | | +--------- PCI master REQ3 disabled
+ * | +----------- PCI master REQ4 disabled
+ * +------------------ Reserved
+ */
+#define CONFIG_SYS_SC520_SYSARBMENB 0x0003
+
+/*-----------------------------------------------------------------------
+ * System Arbiter Master Enable
+ *
+ * 0 0000 0 00 0000 1 000 }- 0x06
+ * | \__/ | \| \__/ | \_/
+ * | | | | | | +---- Reserved
+ * | | | | | +------- Enable CPU-to-PCI bus write posting
+ * | | | | +---------- Reserved
+ * | | | +-------------- PCI bus reads to SDRAM are not automatically
+ * | | | retried
+ * | | +----------------- Target read FIFOs are not snooped during write
+ * | | transactions
+ * | +-------------------- Reserved
+ * +------------------------ Deassert the PCI bus reset signal
+ */
+#define CONFIG_SYS_SC520_HBCTL 0x08
+
+/*-----------------------------------------------------------------------
+ * PAR for Boot Flash - 512kB @ 0x38000000, BOOTCS
+ * 100 0 1 0 1 00000000111 11100000000000 }- 0x8a01f800
+ * \ / | | | | \----+----/ \-----+------/
+ * | | | | | | +---------- Start at 0x38000000
+ * | | | | | +----------------------- 512kB Region Size
+ * | | | | | ((7 + 1) * 64kB)
+ * | | | | +------------------------------ 64kB Page Size
+ * | | | +-------------------------------- Writes Enabled (So it can be
+ * | | | reprogrammed!)
+ * | | +---------------------------------- Caching Disabled
+ * | +------------------------------------ Execution Enabled
+ * +--------------------------------------- BOOTCS
+ */
+#define CONFIG_SYS_SC520_BOOTCS_PAR 0x8a01f800
+
+/*-----------------------------------------------------------------------
+ * PAR for Low Level I/O (LEDs, Hex Switches etc) - 33 Bytes @ 0x1000, GPCS6
+ *
+ * 001 110 0 000100000 0001000000000000 }- 0x38201000
+ * \ / \ / | \---+---/ \------+-------/
+ * | | | | +----------- Start at 0x00001000
+ * | | | +------------------------ 33 Bytes (0x20 + 1)
+ * | | +------------------------------ Ignored
+ * | +--------------------------------- GPCS6
+ * +------------------------------------- GP Bus I/O
+ */
+#define CONFIG_SYS_SC520_LLIO_PAR 0x38201000
+
+/*-----------------------------------------------------------------------
+ * PAR for Compact Flash Port #1 - 4kB @ 0x200000000, CS5
+ * PAR for Compact Flash Port #2 - 4kB @ 0x200010000, CS7
+ *
+ * 010 101 0 0000000 100000000000000000 }- 0x54020000
+ * 010 111 0 0000000 100000000000000001 }- 0x5c020001
+ * \ / \ / | \--+--/ \-------+--------/
+ * | | | | +------------ Start at 0x200000000
+ * | | | | 0x200010000
+ * | | | +------------------------- 4kB Region Size
+ * | | | ((0 + 1) * 4kB)
+ * | | +------------------------------ 4k Page Size
+ * | +--------------------------------- GPCS5
+ * | GPCS7
+ * +------------------------------------- GP Bus Memory
+ */
+#define CONFIG_SYS_SC520_CF1_PAR 0x54020000
+#define CONFIG_SYS_SC520_CF2_PAR 0x5c020001
+
+/*-----------------------------------------------------------------------
+ * PAR for Extra 16550 UART A - 8 bytes @ 0x013f8, GPCS0
+ * PAR for Extra 16550 UART B - 8 bytes @ 0x012f8, GPCS3
+ * PAR for Extra 16550 UART C - 8 bytes @ 0x011f8, GPCS4
+ * PAR for Extra 16550 UART D - 8 bytes @ 0x010f8, GPCS5
+ *
+ * 001 000 0 000000111 0001001111111000 }- 0x200713f8
+ * 001 011 0 000000111 0001001011111000 }- 0x2c0712f8
+ * 001 011 0 000000111 0001001011111000 }- 0x300711f8
+ * 001 011 0 000000111 0001001011111000 }- 0x340710f8
+ * \ / \ / | \---+---/ \------+-------/
+ * | | | | +----------- Start at 0x013f8
+ * | | | | 0x012f8
+ * | | | | 0x011f8
+ * | | | | 0x010f8
+ * | | | +------------------------ 33 Bytes (32 + 1)
+ * | | +------------------------------ Ignored
+ * | +--------------------------------- GPCS6
+ * +------------------------------------- GP Bus I/O
+ */
+#define CONFIG_SYS_SC520_UARTA_PAR 0x200713f8
+#define CONFIG_SYS_SC520_UARTB_PAR 0x2c0712f8
+#define CONFIG_SYS_SC520_UARTC_PAR 0x300711f8
+#define CONFIG_SYS_SC520_UARTD_PAR 0x340710f8
+
+/*-----------------------------------------------------------------------
+ * PAR for StrataFlash #1 - 16MB @ 0x10000000, ROMCS1
+ * PAR for StrataFlash #2 - 16MB @ 0x11000000, ROMCS2
+ *
+ * 101 0 1 0 1 00011111111 01000000000000 }- 0xaa3fd000
+ * 110 0 1 0 1 00011111111 01000100000000 }- 0xca3fd100
+ * \ / | | | | \----+----/ \-----+------/
+ * | | | | | | +---------- Start at 0x10000000
+ * | | | | | | 0x11000000
+ * | | | | | +----------------------- 16MB Region Size
+ * | | | | | ((255 + 1) * 64kB)
+ * | | | | +------------------------------ 64kB Page Size
+ * | | | +-------------------------------- Writes Enabled
+ * | | +---------------------------------- Caching Disabled
+ * | +------------------------------------ Execution Enabled
+ * +--------------------------------------- ROMCS1
+ * ROMCS2
+ */
+#define CONFIG_SYS_SC520_SF1_PAR 0xaa3fd000
+#define CONFIG_SYS_SC520_SF2_PAR 0xca3fd100
+
+/*-----------------------------------------------------------------------
+ * PAR for SRAM #1 - 1MB @ 0x19000000, GPCS0
+ * PAR for SRAM #2 - 1MB @ 0x19100000, GPCS3
+ *
+ * 010 000 1 00000001111 01100100000000 }- 0x4203d900
+ * 010 011 1 00000001111 01100100010000 }- 0x4e03d910
+ * \ / \ / | \----+----/ \-----+------/
+ * | | | | +---------- Start at 0x19000000
+ * | | | | 0x19100000
+ * | | | +----------------------- 1MB Region Size
+ * | | | ((15 + 1) * 64kB)
+ * | | +------------------------------ 64kB Page Size
+ * | +--------------------------------- GPCS0
+ * | GPCS3
+ * +------------------------------------- GP Bus Memory
+ */
+#define CONFIG_SYS_SC520_SRAM1_PAR 0x4203d900
+#define CONFIG_SYS_SC520_SRAM2_PAR 0x4e03d910
+
+/*-----------------------------------------------------------------------
+ * PAR for Dual-Port RAM - 4kB @ 0x18100000, GPCS4
+ *
+ * 010 100 0 00000000 11000000100000000 }- 0x50018100
+ * \ / \ / | \---+--/ \-------+-------/
+ * | | | | +----------- Start at 0x18100000
+ * | | | +------------------------ 4kB Region Size
+ * | | | ((0 + 1) * 4kB)
+ * | | +------------------------------ 4kB Page Size
+ * | +--------------------------------- GPCS4
+ * +------------------------------------- GP Bus Memory
+ */
+#define CONFIG_SYS_SC520_DPRAM_PAR 0x50018100
+
+/*-----------------------------------------------------------------------
+ * PAR for SDRAM - 128MB @ 0x00000000
+ * 111 0 0 0 1 11111111111 00000000000000 }- 0xe3ffc000
+ * \ / | | | | \----+----/ \-----+------/
+ * | | | | | | +---------- Start at 0x00000000
+ * | | | | | +----------------------- 128MB Region Size
+ * | | | | | ((2047 + 1) * 64kB)
+ * | | | | +------------------------------ 64kB Page Size
+ * | | | +-------------------------------- Writes Enabled
+ * | | +---------------------------------- Caching Enabled
+ * | +------------------------------------ Execution Enabled
+ * +--------------------------------------- SDRAM
+ */
+#define CONFIG_SYS_SC520_SDRAM_PAR 0xe3ffc000
+
#ifndef __ASSEMBLER__
extern unsigned long ip;
projects / u-boot / commitdiff