OMAP3: Remove legacy NAND defines

Remove remaining legacy NAND defines for Beagle, EVM, Overo and Pandora.

Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>

diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index 3bfc0a21d6ac2c2017776d7021435eeae8ddbb87..d8c328f1b419eed5367383005f9cbbe5058a30f1 100644 (file)
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -141,18 +141,6 @@
 
 #define CONFIG_SYS_MAX_NAND_DEVICE     1               /* Max number of NAND */
                                                        /* devices */
-#define SECTORSIZE                     512
-
-#define NAND_ALLOW_ERASE_ALL
-#define ADDR_COLUMN                    1
-#define ADDR_PAGE                      2
-#define ADDR_COLUMN_PAGE               3
-
-#define NAND_ChipID_UNKNOWN            0x00
-#define NAND_MAX_FLOORS                        1
-#define NAND_MAX_CHIPS                 1
-#define NAND_NO_RB                     1
-#define CONFIG_SYS_NAND_WP
 
 #define CONFIG_JFFS2_NAND
 /* nand device jffs2 lives on */
@@ -312,21 +300,4 @@ extern unsigned int boot_flash_sec;
 extern unsigned int boot_flash_type;
 #endif
 
-
-#define WRITE_NAND_COMMAND(d, adr)\
-                       writel(d, &nand_cs_base->nand_cmd)
-#define WRITE_NAND_ADDRESS(d, adr)\
-                       writel(d, &nand_cs_base->nand_adr)
-#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat)
-#define READ_NAND(adr) readl(&nand_cs_base->nand_dat)
-
-/* Other NAND Access APIs */
-#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \
-                       while (0)
-#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \
-                       while (0)
-#define NAND_DISABLE_CE(nand)
-#define NAND_ENABLE_CE(nand)
-#define NAND_WAIT_READY(nand)  udelay(10)
-
 #endif /* __CONFIG_H */

diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index 1b309504051a4be5ebcd5536cf482710c38dd9fa..ab014e9502120a3651f6dc43d579fc76b1281ea2 100644 (file)
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -138,18 +138,6 @@
 
 #define CONFIG_SYS_MAX_NAND_DEVICE     1               /* Max number of */
                                                        /* NAND devices */
-#define SECTORSIZE                     512
-
-#define NAND_ALLOW_ERASE_ALL
-#define ADDR_COLUMN                    1
-#define ADDR_PAGE                      2
-#define ADDR_COLUMN_PAGE               3
-
-#define NAND_ChipID_UNKNOWN            0x00
-#define NAND_MAX_FLOORS                        1
-#define NAND_MAX_CHIPS                 1
-#define NAND_NO_RB                     1
-#define CONFIG_SYS_NAND_WP
 
 #define CONFIG_JFFS2_NAND
 /* nand device jffs2 lives on */
@@ -304,23 +292,6 @@ extern unsigned int boot_flash_sec;
 extern unsigned int boot_flash_type;
 #endif
 
-
-#define WRITE_NAND_COMMAND(d, adr)\
-                       writel(d, &nand_cs_base->nand_cmd)
-#define WRITE_NAND_ADDRESS(d, adr)\
-                       writel(d, &nand_cs_base->nand_adr)
-#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat)
-#define READ_NAND(adr) readl(&nand_cs_base->nand_dat)
-
-/* Other NAND Access APIs */
-#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \
-                       while (0)
-#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \
-                       while (0)
-#define NAND_DISABLE_CE(nand)
-#define NAND_ENABLE_CE(nand)
-#define NAND_WAIT_READY(nand)  udelay(10)
-
 /*----------------------------------------------------------------------------
  * SMSC9115 Ethernet from SMSC9118 family
  *----------------------------------------------------------------------------

diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
index a8be4e697c42a4ba80dc8c1389a5a7996bf03877..d941497827bdf387446d9ef3150a36a307e7ddef 100644 (file)
--- a/include/configs/omap3_overo.h
+++ b/include/configs/omap3_overo.h
@@ -128,19 +128,6 @@
 
 #define CONFIG_SYS_MAX_NAND_DEVICE     1       /* Max number of NAND */
                                                /* devices */
-#define SECTORSIZE                     512
-
-#define NAND_ALLOW_ERASE_ALL
-#define ADDR_COLUMN                    1
-#define ADDR_PAGE                      2
-#define ADDR_COLUMN_PAGE               3
-
-#define NAND_ChipID_UNKNOWN            0x00
-#define NAND_MAX_FLOORS                        1
-#define NAND_MAX_CHIPS                 1
-#define NAND_NO_RB                     1
-#define CONFIG_SYS_NAND_WP
-
 #define CONFIG_JFFS2_NAND
 /* nand device jffs2 lives on */
 #define CONFIG_JFFS2_DEV               "nand0"
@@ -299,21 +286,4 @@ extern unsigned int boot_flash_sec;
 extern unsigned int boot_flash_type;
 #endif
 
-
-#define WRITE_NAND_COMMAND(d, adr)\
-                       writel(d, &nand_cs_base->nand_cmd)
-#define WRITE_NAND_ADDRESS(d, adr)\
-                       writel(d, &nand_cs_base->nand_adr)
-#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat)
-#define READ_NAND(adr) readl(&nand_cs_base->nand_dat)
-
-/* Other NAND Access APIs */
-#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \
-                       while (0)
-#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \
-                       while (0)
-#define NAND_DISABLE_CE(nand)
-#define NAND_ENABLE_CE(nand)
-#define NAND_WAIT_READY(nand)  udelay(10)
-
 #endif                         /* __CONFIG_H */

diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h
index b8cb42e5057077975087ad12e7bc75108155ea73..f9f6480df609657d03e9122c738a5bf0eac6b46c 100644 (file)
--- a/include/configs/omap3_pandora.h
+++ b/include/configs/omap3_pandora.h
@@ -131,18 +131,6 @@
 
 #define CONFIG_SYS_MAX_NAND_DEVICE     1       /* Max number of NAND */
                                                /* devices */
-#define SECTORSIZE                     512
-
-#define NAND_ALLOW_ERASE_ALL
-#define ADDR_COLUMN                    1
-#define ADDR_PAGE                      2
-#define ADDR_COLUMN_PAGE               3
-
-#define NAND_ChipID_UNKNOWN            0x00
-#define NAND_MAX_FLOORS                        1
-#define NAND_MAX_CHIPS                 1
-#define NAND_NO_RB                     1
-#define CONFIG_SYS_NAND_WP
 
 #define CONFIG_JFFS2_NAND
 /* nand device jffs2 lives on */
@@ -301,21 +289,4 @@ extern unsigned int boot_flash_sec;
 extern unsigned int boot_flash_type;
 #endif
 
-
-#define WRITE_NAND_COMMAND(d, adr)\
-                       writel(d, &nand_cs_base->nand_cmd)
-#define WRITE_NAND_ADDRESS(d, adr)\
-                       writel(d, &nand_cs_base->nand_adr)
-#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat)
-#define READ_NAND(adr) readl(&nand_cs_base->nand_dat)
-
-/* Other NAND Access APIs */
-#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \
-                       while (0)
-#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \
-                       while (0)
-#define NAND_DISABLE_CE(nand)
-#define NAND_ENABLE_CE(nand)
-#define NAND_WAIT_READY(nand)  udelay(10)
-
 #endif                         /* __CONFIG_H */