Changes for U-Boot 1.0.0:
======================================================================
+* Patches by Xianghua Xiao, 15 Oct 2003:
+
+ - Added Motorola CPU 8540/8560 support (cpu/85xx)
+ - Added Motorola MPC8540ADS board support (board/mpc8540ads)
+ - Added Motorola MPC8560ADS board support (board/mpc8560ads)
+
+* Fix flash timings on TRAB board
+
* Make sure HUSH is initialized for running auto-update scripts
* Make 5200 reset command _really_ reset the board, without running
* Patch by Martin Krause, 09 Oct 2003:
Fixes for TRAB board
- /board/trab/rs485.c: correct baudrate
- - /board/trab/cmd_trab.c: bug fix for problem with timer overflow in
+ - /board/trab/cmd_trab.c: bug fix for problem with timer overflow in
udelay(); fix some timing problems with adc controller
- /board/trab/trab_fkt.c: add new commands: gain, eeprom and power;
modify commands: touch and buzzer
link state to the fault LED.
- In NetLoop, make the Fault LED reflect the link status. The link
status gets updated on entry, and on timeouts.
-
+
* Patch by Anders Larsen, 18 Sep 2003:
allow mkimage to build and run on Cygwin-hosted systems
E: bruno@exet-ag.de
D: Support for NetBSD (both as host and target system)
-N: Swen Anderson
-E: sand@peppercon.de
-D: ERIC Support
-
N: Guillaume Alexandre
E: guillaume.alexandre@gespac.ch
D: Add PCIPPC6 configuration
+N: Swen Anderson
+E: sand@peppercon.de
+D: ERIC Support
+
N: Pantelis Antoniou
E: panto@intracom.gr
D: NETVIA board support, ARTOS support.
E: tkoeller@gmx.net
D: Port to Motorola Sandpoint 3 (MPC8240)
+N: Raghu Krishnaprasad
+E: Raghu.Krishnaprasad@fci.com
+D: Support for Adder-II MPC852T evaluation board
+W: http://www.forcecomputers.com
+
N: Thomas Lange
E: thomas@corelatus.se
D: Support for GTH and dbau1x00 boards; lots of PCMCIA fixes
D: Overall improvements on StrongARM, ARM720TDMI; Support for Tuxscreen; initial PCMCIA support for ARM
W: www.elinos.com
-N: Pantelis Antoniou
-E: panto@intracom.gr
-D: NETVIA board support, ARTOS support.
-
-N: Raghu Krishnaprasad
-E: Raghu.Krishnaprasad@fci.com
-D: Support for Adder-II MPC852T evaluation board
-W: http://www.forcecomputers.com
-
+N: Xianghua Xiao
+E: x.xiao@motorola.com
+D: Support for Motorola 85xx(PowerQUICC III) chip, MPC8540ADS and MPC8560ADS boards.
SXNI855T MPC8xx
-Raghu Krishnaprasad <raghu.krishnaprasad@fci.com>
-
- ADDERII MPC852T
-
Thomas Frieden <ThomasF@hyperion-entertainment.com>
AmigaOneG3SE MPC7xx
debris MPC8245
+Raghu Krishnaprasad <raghu.krishnaprasad@fci.com>
+
+ ADDERII MPC852T
+
Nye Liu <nyet@zumanetworks.com>
ZUMA MPC7xx_74xx
svm_sc8xx MPC8xx
+Xianghua Xiao <x.xiao@motorola.com>
+
+ MPC8540ADS MPC8540
+ MPC8560ADS MPC8560
+
-------------------------------------------------------------------------
Unknown / orphaned boards:
TQM8260_AC TQM8260_AD TQM8260_AE ZPC1900 \
"
+#########################################################################
+## MPC85xx Systems (includes 8540, 8560 etc.)
+#########################################################################
+
+LIST_85xx=" \
+ MPC8540ADS MPC8560ADS \
+"
+
#########################################################################
## 74xx/7xx Systems
#########################################################################
LIST_ppc="${LIST_5xx} ${LIST_5xxx} \
${LIST_8xx} \
${LIST_824x} ${LIST_8260} \
+ ${LIST_85xx} \
${LIST_4xx} \
${LIST_74xx} ${LIST_7xx}"
for arg in $@
do
case "$arg" in
- ppc|5xx|5xxx|8xx|824x|8260|4xx|7xx|74xx| \
+ ppc|5xx|5xxx|8xx|824x|8260|85xx|4xx|7xx|74xx| \
arm|SA|ARM7|ARM9|pxa|ixp| \
mips| \
x86|I486)
ifeq ($(CPU),ppc4xx)
OBJS += cpu/$(CPU)/resetvec.o
endif
+ifeq ($(CPU),mpc85xx)
+OBJS += cpu/$(CPU)/resetvec.o
+endif
LIBS = board/$(BOARDDIR)/lib$(BOARD).a
LIBS += cpu/$(CPU)/lib$(CPU).a
ZPC1900_config: unconfig
@./mkconfig $(@:_config=) ppc mpc8260 zpc1900
+#########################################################################
+## MPC85xx Systems
+#########################################################################
+
+MPC8540ADS_config: unconfig
+ @./mkconfig $(@:_config=) ppc mpc85xx mpc8540ads
+
+MPC8560ADS_config: unconfig
+ @./mkconfig $(@:_config=) ppc mpc85xx mpc8560ads
+
#########################################################################
## 74xx/7xx Systems
#########################################################################
- cpu/mpc8xx Files specific to Motorola MPC8xx CPUs
- cpu/mpc824x Files specific to Motorola MPC824x CPUs
- cpu/mpc8260 Files specific to Motorola MPC8260 CPU
+- cpu/mpc85xx Files specific to Motorola MPC85xx CPUs
- cpu/ppc4xx Files specific to IBM 4xx CPUs
- board/mbx8xx Files specific to MBX boards
- board/mpc8260ads
Files specific to MPC8260ADS and PQ2FADS-ZU boards
+- board/mpc8540ads
+ Files specific to MPC8540ADS boards
+- board/mpc8560ads
+ Files specific to MPC8560ADS boards
- board/mpl/ Files specific to boards manufactured by MPL
- board/mpl/common Common files for MPL boards
- board/mpl/pip405 Files specific to PIP405 boards
- board/oxc Files specific to OXC boards
- board/omap1510inn
Files specific to OMAP 1510 Innovator boards
-- board/omap1610inn
+- board/omap1610inn
Files specific to OMAP 1610 Innovator boards
- board/pcippc2 Files specific to PCIPPC2/PCIPPC6 boards
- board/pm826 Files specific to PM826 boards
CONFIG_MPC823, CONFIG_MPC850, CONFIG_MPC855, CONFIG_MPC860
or CONFIG_MPC5xx
or CONFIG_MPC824X, CONFIG_MPC8260
+ or CONFIG_MPC85xx
or CONFIG_IOP480
or CONFIG_405GP
or CONFIG_405EP
CONFIG_IAD210, CONFIG_RPXlite, CONFIG_sbc8260,
CONFIG_EBONY, CONFIG_sacsng, CONFIG_FPS860L,
CONFIG_V37, CONFIG_ELPT860, CONFIG_CMI,
- CONFIG_NETVIA, CONFIG_RBC823, CONFIG_ZPC1900
+ CONFIG_NETVIA, CONFIG_RBC823, CONFIG_ZPC1900,
+ CONFIG_MPC8540ADS, CONFIG_MPC8560ADS
ARM based boards:
-----------------
CFG_CMD_DHCP DHCP support
CFG_CMD_DIAG * Diagnostics
CFG_CMD_DOC * Disk-On-Chip Support
- CFG_CMD_DTT Digital Therm and Thermostat
+ CFG_CMD_DTT Digital Therm and Thermostat
CFG_CMD_ECHO * echo arguments
CFG_CMD_EEPROM * EEPROM read/write support
CFG_CMD_ELF bootelf, bootvx
images is included. If not, only uncompressed and gzip
compressed images are supported.
- NOTE: the bzip2 algorithm requires a lot of RAM, so
- the malloc area (as defined by CFG_MALLOC_LEN) should
- be at least 4MB.
+ NOTE: the bzip2 algorithm requires a lot of RAM, so
+ the malloc area (as defined by CFG_MALLOC_LEN) should
+ be at least 4MB.
- Ethernet address:
CONFIG_ETHADDR
use the "saveenv" command to store a valid environment.
- CFG_FAULT_ECHO_LINK_DOWN:
- Echo the inverted Ethernet link state to the fault LED.
+ Echo the inverted Ethernet link state to the fault LED.
Note: If this option is active, then CFG_FAULT_MII_ADDR
also needs to be defined.
- CFG_FAULT_MII_ADDR:
- MII address of the PHY to check for the Ethernet link state.
+ MII address of the PHY to check for the Ethernet link state.
Low Level (hardware related) configuration options:
---------------------------------------------------
- CFG_DEFAULT_IMMR:
Default address of the IMMR after system reset.
- Needed on some 8260 systems (MPC8260ADS, PQ2FADS-ZU,
- and RPXsuper) to be able to adjust the position of
- the IMMR register after a reset.
+ Needed on some 8260 systems (MPC8260ADS, PQ2FADS-ZU,
+ and RPXsuper) to be able to adjust the position of
+ the IMMR register after a reset.
- Floppy Disk Support:
CFG_FDC_DRIVE_NUMBER
GEN860T_config EBONY_config FPS860L_config
ELPT860_config cmi_mpc5xx_config NETVIA_config
at91rm9200dk_config omap1510inn_config MPC8260ADS_config
- omap1610inn_config ZPC1900_config
+ omap1610inn_config ZPC1900_config MPC8540ADS_config
+ MPC8560ADS_config
Note: for some board special configuration names may exist; check if
additional information is available from the board vendor; for
* | |
* | ... |
*****************************************************************************/
-
-
#
TEXT_BASE = 0xFE000000
-
_end = . ;
PROVIDE (end = .);
}
-
int board_pre_init (void)
{
out32(GPIO0_OR, CFG_NAND0_CE); /* set initial outputs */
- out32(GPIO0_OR, CFG_NAND1_CE); /* set initial outputs */
+ out32(GPIO0_OR, CFG_NAND1_CE); /* set initial outputs */
/*
* IRQ 0-15 405GP internally generated; active high; level sensitive
#else
unsigned long size_b0;
int i;
- uint pbcr;
- unsigned long base_b0;
+ uint pbcr;
+ unsigned long base_b0;
int size_val = 0;
/* Init: no FLASHes known */
size_b0, size_b0<<20);
}
- /* Setup offsets */
- flash_get_offsets (-size_b0, &flash_info[0]);
+ /* Setup offsets */
+ flash_get_offsets (-size_b0, &flash_info[0]);
- /* Re-do sizing to get full correct info */
- mtdcr(ebccfga, pb0cr);
- pbcr = mfdcr(ebccfgd);
- mtdcr(ebccfga, pb0cr);
- base_b0 = -size_b0;
+ /* Re-do sizing to get full correct info */
+ mtdcr(ebccfga, pb0cr);
+ pbcr = mfdcr(ebccfgd);
+ mtdcr(ebccfga, pb0cr);
+ base_b0 = -size_b0;
switch (size_b0) {
case 1 << 20:
size_val = 0;
break;
}
pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
- mtdcr(ebccfgd, pbcr);
+ mtdcr(ebccfgd, pbcr);
- /* Monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- -CFG_MONITOR_LEN,
- 0xffffffff,
- &flash_info[0]);
+ /* Monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ -CFG_MONITOR_LEN,
+ 0xffffffff,
+ &flash_info[0]);
- flash_info[0].size = size_b0;
+ flash_info[0].size = size_b0;
return (size_b0);
#endif
short n;
/* set up sector start address table */
- if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+ if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) {
for (i = 0; i < info->sector_count; i++)
info->start[i] = base + (i * 0x00010000);
- } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
+ } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
base += 64 << 10;
++i;
}
- } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
+ } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
--i;
info->start[i] = base;
}
- } else {
+ } else {
if (info->flash_id & FLASH_BTYPE) {
/* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
void flash_print_info (flash_info_t *info)
{
int i;
- int k;
- int size;
- int erased;
- volatile unsigned long *flash;
+ int k;
+ int size;
+ int erased;
+ volatile unsigned long *flash;
if (info->flash_id == FLASH_UNKNOWN) {
printf ("missing or unknown FLASH type\n");
printf (" Sector Start Addresses:");
for (i=0; i<info->sector_count; ++i) {
#ifdef CFG_FLASH_EMPTY_INFO
- /*
- * Check if whole sector is erased
- */
- if (i != (info->sector_count-1))
- size = info->start[i+1] - info->start[i];
- else
- size = info->start[0] + info->size - info->start[i];
- erased = 1;
- flash = (volatile unsigned long *)info->start[i];
- size = size >> 2; /* divide by 4 for longword access */
- for (k=0; k<size; k++)
- {
- if (*flash++ != 0xffffffff)
- {
- erased = 0;
- break;
- }
- }
+ /*
+ * Check if whole sector is erased
+ */
+ if (i != (info->sector_count-1))
+ size = info->start[i+1] - info->start[i];
+ else
+ size = info->start[0] + info->size - info->start[i];
+ erased = 1;
+ flash = (volatile unsigned long *)info->start[i];
+ size = size >> 2; /* divide by 4 for longword access */
+ for (k=0; k<size; k++)
+ {
+ if (*flash++ != 0xffffffff)
+ {
+ erased = 0;
+ break;
+ }
+ }
if ((i % 5) == 0)
printf ("\n ");
- /* print empty and read-only info */
+ /* print empty and read-only info */
printf (" %08lX%s%s",
info->start[i],
erased ? " E" : " ",
short n;
CFG_FLASH_WORD_SIZE value;
ulong base = (ulong)addr;
- volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)addr;
+ volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)addr;
/* Write auto select command: read Manufacturer ID */
addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
break; /* => 2 MB */
case (CFG_FLASH_WORD_SIZE)STM_ID_29W320DT:
- info->flash_id += FLASH_STMW320DT;
- info->sector_count = 67;
+ info->flash_id += FLASH_STMW320DT;
+ info->sector_count = 67;
info->size = 0x00400000; break; /* => 4 MB */
case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T:
- info->flash_id += FLASH_AM320T;
- info->sector_count = 71;
+ info->flash_id += FLASH_AM320T;
+ info->sector_count = 71;
info->size = 0x00400000; break; /* => 4 MB */
case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B:
- info->flash_id += FLASH_AM320B;
+ info->flash_id += FLASH_AM320B;
info->sector_count = 71;
info->size = 0x00400000; break; /* => 4 MB */
case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322T:
- info->flash_id += FLASH_AMDL322T;
- info->sector_count = 71;
+ info->flash_id += FLASH_AMDL322T;
+ info->sector_count = 71;
info->size = 0x00400000; break; /* => 4 MB */
case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322B:
- info->flash_id += FLASH_AMDL322B;
+ info->flash_id += FLASH_AMDL322B;
info->sector_count = 71;
info->size = 0x00400000; break; /* => 4 MB */
case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323T:
- info->flash_id += FLASH_AMDL323T;
+ info->flash_id += FLASH_AMDL323T;
info->sector_count = 71;
info->size = 0x00400000; break; /* => 4 MB */
case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323B:
- info->flash_id += FLASH_AMDL323B;
+ info->flash_id += FLASH_AMDL323B;
info->sector_count = 71;
info->size = 0x00400000; break; /* => 4 MB */
case (CFG_FLASH_WORD_SIZE)AMD_ID_LV640U:
- info->flash_id += FLASH_AM640U;
+ info->flash_id += FLASH_AM640U;
info->sector_count = 128;
info->size = 0x00800000; break; /* => 8 MB */
}
/* set up sector start address table */
- if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
+ if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U)) {
for (i = 0; i < info->sector_count; i++)
info->start[i] = base + (i * 0x00010000);
- } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
+ } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
base += 64 << 10;
++i;
}
- } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
+ } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
--i;
info->start[i] = base;
}
- } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) {
+ } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) {
/* set sector offsets for top boot block type */
base += info->size;
i = info->sector_count;
- /* 1 x 16k boot sector */
+ /* 1 x 16k boot sector */
base -= 16 << 10;
- --i;
+ --i;
info->start[i] = base;
/* 2 x 8k boot sectors */
for (n=0; n<2; ++n) {
--i;
info->start[i] = base;
}
- /* 1 x 32k boot sector */
+ /* 1 x 32k boot sector */
base -= 32 << 10;
- --i;
+ --i;
info->start[i] = base;
while (i > 0) { /* 64k regular sectors */
--i;
info->start[i] = base;
}
- } else {
+ } else {
if (info->flash_id & FLASH_BTYPE) {
/* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
/* D0 = 1 if protected */
addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
- info->protect[i] = 0;
- else
- info->protect[i] = addr2[CFG_FLASH_READ2] & 1;
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
+ info->protect[i] = 0;
+ else
+ info->protect[i] = addr2[CFG_FLASH_READ2] & 1;
}
/*
volatile CFG_FLASH_WORD_SIZE *addr2;
int flag, prot, sect, l_sect;
ulong start, now, last;
- int i;
+ int i;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
for (sect = s_first; sect<=s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[sect]);
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
- addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
- addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
- addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;
- addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
- addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
- addr2[0] = (CFG_FLASH_WORD_SIZE)0x00500050; /* block erase */
- for (i=0; i<50; i++)
- udelay(1000); /* wait 1 ms */
- } else {
- if (sect == s_first) {
- addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
- addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
- addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;
- addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
- addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
- }
- addr2[0] = (CFG_FLASH_WORD_SIZE)0x00300030; /* sector erase */
- }
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+ addr2[0] = (CFG_FLASH_WORD_SIZE)0x00500050; /* block erase */
+ for (i=0; i<50; i++)
+ udelay(1000); /* wait 1 ms */
+ } else {
+ if (sect == s_first) {
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;
+ addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+ addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+ }
+ addr2[0] = (CFG_FLASH_WORD_SIZE)0x00300030; /* sector erase */
+ }
l_sect = sect;
}
}
*/
static int write_word (flash_info_t *info, ulong dest, ulong data)
{
- volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[0]);
- volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *)dest;
- volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *)&data;
+ volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[0]);
+ volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *)dest;
+ volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *)&data;
ulong start;
int flag;
- int i;
+ int i;
/* Check if Flash is (sufficiently) erased */
if ((*((volatile CFG_FLASH_WORD_SIZE *)dest) &
- (CFG_FLASH_WORD_SIZE)data) != (CFG_FLASH_WORD_SIZE)data) {
+ (CFG_FLASH_WORD_SIZE)data) != (CFG_FLASH_WORD_SIZE)data) {
return (2);
}
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
- for (i=0; i<4/sizeof(CFG_FLASH_WORD_SIZE); i++)
- {
- addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
- addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
- addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00A000A0;
-
- dest2[i] = data2[i];
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((dest2[i] & (CFG_FLASH_WORD_SIZE)0x00800080) !=
- (data2[i] & (CFG_FLASH_WORD_SIZE)0x00800080)) {
- if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- }
+ for (i=0; i<4/sizeof(CFG_FLASH_WORD_SIZE); i++)
+ {
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
+ addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+ addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00A000A0;
+
+ dest2[i] = data2[i];
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer (0);
+ while ((dest2[i] & (CFG_FLASH_WORD_SIZE)0x00800080) !=
+ (data2[i] & (CFG_FLASH_WORD_SIZE)0x00800080)) {
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ return (1);
+ }
+ }
+ }
return (0);
}
#define SET_FPGA(data) out32(GPIO0_OR, data)
#define FPGA_WRITE_1 { \
- SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \
- SET_FPGA(FPGA_PRG | FPGA_DATA); /* set data to 1 */ \
- SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set clock to 1 */ \
- SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */
+ SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \
+ SET_FPGA(FPGA_PRG | FPGA_DATA); /* set data to 1 */ \
+ SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set clock to 1 */ \
+ SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */
#define FPGA_WRITE_0 { \
- SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \
- SET_FPGA(FPGA_PRG); /* set data to 0 */ \
- SET_FPGA(FPGA_PRG | FPGA_CLK); /* set clock to 1 */ \
- SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */
+ SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \
+ SET_FPGA(FPGA_PRG); /* set data to 0 */ \
+ SET_FPGA(FPGA_PRG | FPGA_CLK); /* set clock to 1 */ \
+ SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */
#if 0
static int fpga_boot (unsigned char *fpgadata, int size)
memsetup:
/* First setup pll:s to make serial work ok */
/* We have a 12 MHz crystal */
- li t0, SYS_CPUPLL
- li t1, 0x21 /* 396 MHz */
- sw t1, 0(t0)
- sync
- nop
+ li t0, SYS_CPUPLL
+ li t1, 0x21 /* 396 MHz */
+ sw t1, 0(t0)
+ sync
+ nop
- /* Setup AUX PLL */
+ /* Setup AUX PLL */
li t0, SYS_AUXPLL
li t1, 8 /* 96 MHz */
- sw t1, 0(t0) /* aux pll */
- sync
+ sw t1, 0(t0) /* aux pll */
+ sync
/* SDCS 0,1 SDRAM */
li t0, MEM_SDMODE0
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
endif
-
cpu/nios/start.o (.text)
*(.text)
}
- __text_end = .;
+ __text_end = .;
- . = ALIGN(4);
- .rodata :
+ . = ALIGN(4);
+ .rodata :
{
*(.rodata)
}
__rodata_end = .;
- . = ALIGN(4);
- .data :
+ . = ALIGN(4);
+ .data :
{
*(.data)
}
__u_boot_cmd_end = .;
__bss_start = .;
- . = ALIGN(4);
- .bss :
+ . = ALIGN(4);
+ .bss :
{
*(.bss)
}
. = ALIGN(4);
__bss_end = .;
}
-
.long _def_xhandler@h /* Vector 61 */
.long _def_xhandler@h /* Vector 62 */
.long _def_xhandler@h /* Vector 63 */
-
-
* Returns: void.
*****************************************************************************/
void initLenVal( lenVal* plv,
- long lValue )
+ long lValue )
{
plv->len = 1;
plv->val[0] = (unsigned char)lValue;
* Returns: short - 0 = mismatch; 1 = equal.
*****************************************************************************/
short EqualLenVal( lenVal* plvTdoExpected,
- lenVal* plvTdoCaptured,
- lenVal* plvTdoMask )
+ lenVal* plvTdoCaptured,
+ lenVal* plvTdoMask )
{
short sEqual;
short sIndex;
* Returns: short - the bit value.
*****************************************************************************/
short RetBit( lenVal* plv,
- int iByte,
- int iBit )
+ int iByte,
+ int iBit )
{
/* assert( ( iByte >= 0 ) && ( iByte < plv->len ) ); */
/* assert( ( iBit >= 0 ) && ( iBit < 8 ) ); */
* Returns: void.
*****************************************************************************/
void SetBit( lenVal* plv,
- int iByte,
- int iBit,
- short sVal )
+ int iByte,
+ int iBit,
+ short sVal )
{
unsigned char ucByteVal;
unsigned char ucBitMask;
* Returns: void.
*****************************************************************************/
void addVal( lenVal* plvResVal,
- lenVal* plvVal1,
- lenVal* plvVal2 )
+ lenVal* plvVal1,
+ lenVal* plvVal2 )
{
unsigned char ucCarry;
unsigned short usSum;
* Returns: void.
*****************************************************************************/
void readVal( lenVal* plv,
- short sNumBytes )
+ short sNumBytes )
{
unsigned char* pucVal;
#ifdef DEBUG_MODE
#define XSVFDBG_PRINTF(iDebugLevel,pzFormat) \
- { if ( xsvf_iDebugLevel >= iDebugLevel ) \
- printf( pzFormat ); }
+ { if ( xsvf_iDebugLevel >= iDebugLevel ) \
+ printf( pzFormat ); }
#define XSVFDBG_PRINTF1(iDebugLevel,pzFormat,arg1) \
- { if ( xsvf_iDebugLevel >= iDebugLevel ) \
- printf( pzFormat, arg1 ); }
+ { if ( xsvf_iDebugLevel >= iDebugLevel ) \
+ printf( pzFormat, arg1 ); }
#define XSVFDBG_PRINTF2(iDebugLevel,pzFormat,arg1,arg2) \
- { if ( xsvf_iDebugLevel >= iDebugLevel ) \
- printf( pzFormat, arg1, arg2 ); }
+ { if ( xsvf_iDebugLevel >= iDebugLevel ) \
+ printf( pzFormat, arg1, arg2 ); }
#define XSVFDBG_PRINTF3(iDebugLevel,pzFormat,arg1,arg2,arg3) \
- { if ( xsvf_iDebugLevel >= iDebugLevel ) \
- printf( pzFormat, arg1, arg2, arg3 ); }
+ { if ( xsvf_iDebugLevel >= iDebugLevel ) \
+ printf( pzFormat, arg1, arg2, arg3 ); }
#define XSVFDBG_PRINTLENVAL(iDebugLevel,plenVal) \
- { if ( xsvf_iDebugLevel >= iDebugLevel ) \
- xsvfPrintLenVal(plenVal); }
+ { if ( xsvf_iDebugLevel >= iDebugLevel ) \
+ xsvfPrintLenVal(plenVal); }
#else /* !DEBUG_MODE */
#define XSVFDBG_PRINTF(iDebugLevel,pzFormat)
#define XSVFDBG_PRINTF1(iDebugLevel,pzFormat,arg1)
#ifdef DEBUG_MODE
char* xsvf_pzCommandName[] =
{
- "XCOMPLETE",
- "XTDOMASK",
- "XSIR",
- "XSDR",
- "XRUNTEST",
- "Reserved5",
- "Reserved6",
- "XREPEAT",
- "XSDRSIZE",
- "XSDRTDO",
- "XSETSDRMASKS",
- "XSDRINC",
- "XSDRB",
- "XSDRC",
- "XSDRE",
- "XSDRTDOB",
- "XSDRTDOC",
- "XSDRTDOE",
- "XSTATE",
- "XENDIR",
- "XENDDR",
- "XSIR2",
- "XCOMMENT",
- "XWAIT"
+ "XCOMPLETE",
+ "XTDOMASK",
+ "XSIR",
+ "XSDR",
+ "XRUNTEST",
+ "Reserved5",
+ "Reserved6",
+ "XREPEAT",
+ "XSDRSIZE",
+ "XSDRTDO",
+ "XSETSDRMASKS",
+ "XSDRINC",
+ "XSDRB",
+ "XSDRC",
+ "XSDRE",
+ "XSDRTDOB",
+ "XSDRTDOC",
+ "XSDRTDOE",
+ "XSTATE",
+ "XENDIR",
+ "XENDDR",
+ "XSIR2",
+ "XCOMMENT",
+ "XWAIT"
};
char* xsvf_pzErrorName[] =
{
- "No error",
- "ERROR: Unknown",
- "ERROR: TDO mismatch",
- "ERROR: TDO mismatch and exceeded max retries",
- "ERROR: Unsupported XSVF command",
- "ERROR: Illegal state specification",
- "ERROR: Data overflows allocated MAX_LEN buffer size"
+ "No error",
+ "ERROR: Unknown",
+ "ERROR: TDO mismatch",
+ "ERROR: TDO mismatch and exceeded max retries",
+ "ERROR: Unsupported XSVF command",
+ "ERROR: Illegal state specification",
+ "ERROR: Data overflows allocated MAX_LEN buffer size"
};
char* xsvf_pzTapState[] =
{
- "RESET", /* 0x00 */
- "RUNTEST/IDLE", /* 0x01 */
- "DRSELECT", /* 0x02 */
- "DRCAPTURE", /* 0x03 */
- "DRSHIFT", /* 0x04 */
- "DREXIT1", /* 0x05 */
- "DRPAUSE", /* 0x06 */
- "DREXIT2", /* 0x07 */
- "DRUPDATE", /* 0x08 */
- "IRSELECT", /* 0x09 */
- "IRCAPTURE", /* 0x0A */
- "IRSHIFT", /* 0x0B */
- "IREXIT1", /* 0x0C */
- "IRPAUSE", /* 0x0D */
- "IREXIT2", /* 0x0E */
- "IRUPDATE" /* 0x0F */
+ "RESET", /* 0x00 */
+ "RUNTEST/IDLE", /* 0x01 */
+ "DRSELECT", /* 0x02 */
+ "DRCAPTURE", /* 0x03 */
+ "DRSHIFT", /* 0x04 */
+ "DREXIT1", /* 0x05 */
+ "DRPAUSE", /* 0x06 */
+ "DREXIT2", /* 0x07 */
+ "DRUPDATE", /* 0x08 */
+ "IRSELECT", /* 0x09 */
+ "IRCAPTURE", /* 0x0A */
+ "IRSHIFT", /* 0x0B */
+ "IREXIT1", /* 0x0C */
+ "IRPAUSE", /* 0x0D */
+ "IREXIT2", /* 0x0E */
+ "IRUPDATE" /* 0x0F */
};
#endif /* DEBUG_MODE */
-//#ifdef DEBUG_MODE
-// FILE* in; /* Legacy DEBUG_MODE file pointer */
+/*#ifdef DEBUG_MODE */
+/* FILE* in; /XXX* Legacy DEBUG_MODE file pointer */
int xsvf_iDebugLevel;
-//#endif /* DEBUG_MODE */
+/*#endif /XXX* DEBUG_MODE */
/*============================================================================
* Utility Functions
* Returns: int - 0 = success; otherwise error.
*****************************************************************************/
int xsvfGotoTapState( unsigned char* pucTapState,
- unsigned char ucTargetState )
+ unsigned char ucTargetState )
{
int i;
int iErrorCode;
* Returns: void.
*****************************************************************************/
void xsvfShiftOnly( long lNumBits,
- lenVal* plvTdi,
- lenVal* plvTdoCaptured,
- int iExitShift )
+ lenVal* plvTdi,
+ lenVal* plvTdoCaptured,
+ int iExitShift )
{
unsigned char* pucTdi;
unsigned char* pucTdo;
* is NOT all zeros and sMatch==1.
*****************************************************************************/
int xsvfShift( unsigned char* pucTapState,
- unsigned char ucStartState,
- long lNumBits,
- lenVal* plvTdi,
- lenVal* plvTdoCaptured,
- lenVal* plvTdoExpected,
- lenVal* plvTdoMask,
- unsigned char ucEndState,
- long lRunTestTime,
- unsigned char ucMaxRepeat )
+ unsigned char ucStartState,
+ long lNumBits,
+ lenVal* plvTdi,
+ lenVal* plvTdoCaptured,
+ lenVal* plvTdoExpected,
+ lenVal* plvTdoMask,
+ unsigned char ucEndState,
+ long lRunTestTime,
+ unsigned char ucMaxRepeat )
{
int iErrorCode;
int iMismatch;
* Returns: int - 0 = success; otherwise TDO mismatch.
*****************************************************************************/
int xsvfBasicXSDRTDO( unsigned char* pucTapState,
- long lShiftLengthBits,
- short sShiftLengthBytes,
- lenVal* plvTdi,
- lenVal* plvTdoCaptured,
- lenVal* plvTdoExpected,
- lenVal* plvTdoMask,
- unsigned char ucEndState,
- long lRunTestTime,
- unsigned char ucMaxRepeat )
+ long lShiftLengthBits,
+ short sShiftLengthBytes,
+ lenVal* plvTdi,
+ lenVal* plvTdoCaptured,
+ lenVal* plvTdoExpected,
+ lenVal* plvTdoMask,
+ unsigned char ucEndState,
+ long lRunTestTime,
+ unsigned char ucMaxRepeat )
{
readVal( plvTdi, sShiftLengthBytes );
if ( plvTdoExpected )
*****************************************************************************/
#ifdef XSVF_SUPPORT_COMPRESSION
void xsvfDoSDRMasking( lenVal* plvTdi,
- lenVal* plvNextData,
- lenVal* plvAddressMask,
- lenVal* plvDataMask )
+ lenVal* plvNextData,
+ lenVal* plvAddressMask,
+ lenVal* plvDataMask )
{
int i;
unsigned char ucTdi;
-/*\r
- * (C) Copyright 2003\r
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com\r
- *\r
- * See file CREDITS for list of people who contributed to this\r
- * project.\r
- *\r
- * This program is free software; you can redistribute it and/or\r
- * modify it under the terms of the GNU General Public License as\r
- * published by the Free Software Foundation; either version 2 of\r
- * the License, or (at your option) any later version.\r
- *\r
- * This program is distributed in the hope that it will be useful,\r
- * but WITHOUT ANY WARRANTY; without even the implied warranty of\r
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
- * GNU General Public License for more details.\r
- *\r
- * You should have received a copy of the GNU General Public License\r
- * along with this program; if not, write to the Free Software\r
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,\r
- * MA 02111-1307 USA\r
- */\r
-\r
-/*****************************************************************************\r
- * File: micro.h\r
- * Description: This header file contains the function prototype to the\r
- * primary interface function for the XSVF player.\r
- * Usage: FIRST - PORTS.C\r
- * Customize the ports.c function implementations to establish\r
- * the correct protocol for communicating with your JTAG ports\r
- * (setPort() and readTDOBit()) and tune the waitTime() delay\r
- * function. Also, establish access to the XSVF data source\r
- * in the readByte() function.\r
- * FINALLY - Call xsvfExecute().\r
- *****************************************************************************/\r
-#ifndef XSVF_MICRO_H\r
-#define XSVF_MICRO_H\r
-\r
-/* Legacy error codes for xsvfExecute from original XSVF player v2.0 */\r
-#define XSVF_LEGACY_SUCCESS 1\r
-#define XSVF_LEGACY_ERROR 0\r
-\r
-/* 4.04 [NEW] Error codes for xsvfExecute. */\r
-/* Must #define XSVF_SUPPORT_ERRORCODES in micro.c to get these codes */\r
-#define XSVF_ERROR_NONE 0\r
-#define XSVF_ERROR_UNKNOWN 1\r
-#define XSVF_ERROR_TDOMISMATCH 2\r
-#define XSVF_ERROR_MAXRETRIES 3 /* TDO mismatch after max retries */\r
-#define XSVF_ERROR_ILLEGALCMD 4\r
-#define XSVF_ERROR_ILLEGALSTATE 5\r
-#define XSVF_ERROR_DATAOVERFLOW 6 /* Data > lenVal MAX_LEN buffer size*/\r
-/* Insert new errors here */\r
-#define XSVF_ERROR_LAST 7\r
-\r
-/*****************************************************************************\r
- * Function: xsvfExecute\r
- * Description: Process, interpret, and apply the XSVF commands.\r
- * See port.c:readByte for source of XSVF data.\r
- * Parameters: none.\r
- * Returns: int - For error codes see above.\r
- *****************************************************************************/\r
-int xsvfExecute(void);\r
-\r
-#endif /* XSVF_MICRO_H */\r
+/*
+ * (C) Copyright 2003
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*****************************************************************************
+ * File: micro.h
+ * Description: This header file contains the function prototype to the
+ * primary interface function for the XSVF player.
+ * Usage: FIRST - PORTS.C
+ * Customize the ports.c function implementations to establish
+ * the correct protocol for communicating with your JTAG ports
+ * (setPort() and readTDOBit()) and tune the waitTime() delay
+ * function. Also, establish access to the XSVF data source
+ * in the readByte() function.
+ * FINALLY - Call xsvfExecute().
+ *****************************************************************************/
+#ifndef XSVF_MICRO_H
+#define XSVF_MICRO_H
+
+/* Legacy error codes for xsvfExecute from original XSVF player v2.0 */
+#define XSVF_LEGACY_SUCCESS 1
+#define XSVF_LEGACY_ERROR 0
+
+/* 4.04 [NEW] Error codes for xsvfExecute. */
+/* Must #define XSVF_SUPPORT_ERRORCODES in micro.c to get these codes */
+#define XSVF_ERROR_NONE 0
+#define XSVF_ERROR_UNKNOWN 1
+#define XSVF_ERROR_TDOMISMATCH 2
+#define XSVF_ERROR_MAXRETRIES 3 /* TDO mismatch after max retries */
+#define XSVF_ERROR_ILLEGALCMD 4
+#define XSVF_ERROR_ILLEGALSTATE 5
+#define XSVF_ERROR_DATAOVERFLOW 6 /* Data > lenVal MAX_LEN buffer size*/
+/* Insert new errors here */
+#define XSVF_ERROR_LAST 7
+
+/*****************************************************************************
+ * Function: xsvfExecute
+ * Description: Process, interpret, and apply the XSVF commands.
+ * See port.c:readByte for source of XSVF data.
+ * Parameters: none.
+ * Returns: int - For error codes see above.
+ *****************************************************************************/
+int xsvfExecute(void);
+
+#endif /* XSVF_MICRO_H */
unsigned char str[64];
int i = getenv_r ("serial#", str, sizeof(str));
unsigned char trans[16] = {0x0,0x8,0x4,0xc,0x2,0xa,0x6,0xe,
- 0x1,0x9,0x5,0xd,0x3,0xb,0x7,0xf};
+ 0x1,0x9,0x5,0xd,0x3,0xb,0x7,0xf};
unsigned char id1, id2;
puts ("Board: ");
for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
info = & flash_info[i];
- if (info->size &&
+ if (info->size &&
info->start[0] <= base && base <= info->start[0] + info->size - 1)
break;
}
addr2 = (FPW *)((ulong)addr | 0x800000);
if (addr2 != addr &&
((addr2[0] & 0xff) == (addr[0] & 0xff)) && ((FPW)addr2[1] == (FPW)addr[1])) {
- /* Seems 2 banks are the same space (8Mb chip is installed,
+ /* Seems 2 banks are the same space (8Mb chip is installed,
* J24 in default position (CS0)). Disable this (first) bank.
*/
info->flash_id = FLASH_UNKNOWN;
void flash_afterinit(ulong size)
{
if (size == 0x800000) { /* adjust mapping */
- *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
+ *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
START_REG(CFG_BOOTCS_START | size);
- *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
+ *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
STOP_REG(CFG_BOOTCS_START | size, size);
}
}
ENTRY(_start)
SECTIONS
{
- . = 0x00000000;
+ . = 0x00000000;
- . = ALIGN(4);
+ . = ALIGN(4);
.text :
{
cpu/ixp/start.o (.text)
*(.text)
}
- . = ALIGN(4);
- .rodata : { *(.rodata) }
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
- . = ALIGN(4);
- .data : { *(.data) }
+ . = ALIGN(4);
+ .data : { *(.data) }
- . = ALIGN(4);
- .got : { *(.got) }
+ . = ALIGN(4);
+ .got : { *(.got) }
armboot_end_data = .;
- . = ALIGN(4);
+ . = ALIGN(4);
bss_start = .;
- .bss : { *(.bss) }
+ .bss : { *(.bss) }
bss_end = .;
armboot_end = .;
printf(", Using Bank Based Interleave\n");
#else
printf(", Using Page Based Interleave\n");
-#endif
+#endif
printf("\tTotal size: ");
- /* this delay only needed for original 16MB DIMM...
+ /* this delay only needed for original 16MB DIMM...
* Not needed for any other memory configuration */
if ((sdram_size * chipselects) == (16 *1024 *1024))
- udelay (250000);
+ udelay (250000);
return (sdram_size * chipselects);
/*return (16 * 1024 * 1024);*/
}
pci_mpc8250_init(&hose);
}
#endif
-
--- /dev/null
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := $(BOARD).o flash.o
+SOBJS := init.o
+#SOBJS :=
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS) $(SOBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- /dev/null
+# Modified by Xianghua Xiao, X.Xiao@motorola.com
+# (C) Copyright 2002,Motorola Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# mpc8540ads board
+# default CCARBAR is at 0xff700000
+# assume U-Boot is less than 0.5MB
+#
+TEXT_BASE = 0xfff80000
+
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8540=1
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
--- /dev/null
+/*
+ * (C) Copyright 2003 Motorola Inc.
+ * Xianghua Xiao,(X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
+ * Add support the Sharp chips on the mpc8260ads.
+ * I started with board/ip860/flash.c and made changes I found in
+ * the MTD project by David Schleef.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if !defined(CFG_NO_FLASH)
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef CFG_ENV_ADDR
+# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef CFG_ENV_SIZE
+# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
+# endif
+# ifndef CFG_ENV_SECT_SIZE
+# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE
+# endif
+#endif
+
+#undef DEBUG
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static int clear_block_lock_bit(vu_long * addr);
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+ unsigned long size;
+ int i;
+
+ /* Init: enable write,
+ * or we cannot even write flash commands
+ */
+ for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+
+ /* set the default sector offset */
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size, size<<20);
+ }
+
+ /* Re-do sizing to get full correct info */
+ size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+ flash_info[0].size = size;
+
+#if !defined(CONFIG_RAM_AS_FLASH)
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+ /* monitor protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE+monitor_flash_len-1,
+ &flash_info[0]);
+#endif
+
+#ifdef CFG_ENV_IS_IN_FLASH
+ /* ENV protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_ENV_ADDR,
+ CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
+ &flash_info[0]);
+#endif
+#endif
+ return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_INTEL: printf ("Intel "); break;
+ case FLASH_MAN_SHARP: printf ("Sharp "); break;
+ default: printf ("Unknown Vendor "); break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n");
+ break;
+ case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n");
+ break;
+ case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n");
+ break;
+ case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n");
+ break;
+ case FLASH_28F640J3A: printf ("28F640J3A (64 Mbit, 64 x 128K)\n");
+ break;
+ default: printf ("Unknown Chip Type\n");
+ break;
+ }
+
+ printf (" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i=0; i<info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf ("\n ");
+ printf (" %08lX%s",
+ info->start[i],
+ info->protect[i] ? " (RO)" : " "
+ );
+ }
+ printf ("\n");
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+ short i;
+ ulong value;
+ ulong base = (ulong)addr;
+ ulong sector_offset;
+
+#ifdef DEBUG
+ printf("Check flash at 0x%08x\n",(uint)addr);
+#endif
+ /* Write "Intelligent Identifier" command: read Manufacturer ID */
+ *addr = 0x90909090;
+ udelay(20);
+ asm("sync");
+
+ value = addr[0] & 0x00FF00FF;
+
+#ifdef DEBUG
+ printf("manufacturer=0x%x\n",(uint)value);
+#endif
+ switch (value) {
+ case MT_MANUFACT: /* SHARP, MT or => Intel */
+ case INTEL_ALT_MANU:
+ info->flash_id = FLASH_MAN_INTEL;
+ break;
+ default:
+ printf("unknown manufacturer: %x\n", (unsigned int)value);
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return (0); /* no or unknown flash */
+ }
+
+ value = addr[1] & 0x00FF00FF; /* device ID */
+
+#ifdef DEBUG
+ printf("deviceID=0x%x\n",(uint)value);
+#endif
+ switch (value) {
+ case (INTEL_ID_28F016S):
+ info->flash_id += FLASH_28F016SV;
+ info->sector_count = 32;
+ info->size = 0x00400000;
+ sector_offset = 0x20000;
+ break; /* => 2x2 MB */
+
+ case (INTEL_ID_28F160S3):
+ info->flash_id += FLASH_28F160S3;
+ info->sector_count = 32;
+ info->size = 0x00400000;
+ sector_offset = 0x20000;
+ break; /* => 2x2 MB */
+
+ case (INTEL_ID_28F320S3):
+ info->flash_id += FLASH_28F320S3;
+ info->sector_count = 64;
+ info->size = 0x00800000;
+ sector_offset = 0x20000;
+ break; /* => 2x4 MB */
+
+ case (INTEL_ID_28F640J3A):
+ info->flash_id += FLASH_28F640J3A;
+ info->sector_count = 64;
+ info->size = 0x01000000;
+ sector_offset = 0x40000;
+ break; /* => 2x8 MB */
+
+ case SHARP_ID_28F016SCL:
+ case SHARP_ID_28F016SCZ:
+ info->flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT;
+ info->sector_count = 32;
+ info->size = 0x00800000;
+ sector_offset = 0x40000;
+ break; /* => 4x2 MB */
+
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return (0); /* => no or unknown flash */
+
+ }
+
+ /* set up sector start address table */
+ for (i = 0; i < info->sector_count; i++) {
+ info->start[i] = base;
+ base += sector_offset;
+ /* don't know how to check sector protection */
+ info->protect[i] = 0;
+ }
+
+ /*
+ * Prevent writes to uninitialized FLASH.
+ */
+ if (info->flash_id != FLASH_UNKNOWN) {
+ addr = (vu_long *)info->start[0];
+ *addr = 0xFFFFFF; /* reset bank to read array mode */
+ asm("sync");
+ }
+
+ return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+ int flag, prot, sect;
+ ulong start, now, last;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL)
+ && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) {
+ printf ("Can't erase unknown flash type %08lx - aborted\n",
+ info->flash_id);
+ return 1;
+ }
+
+ prot = 0;
+ for (sect=s_first; sect<=s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf ("\n");
+ }
+
+#ifdef DEBUG
+ printf("\nFlash Erase:\n");
+#endif
+ /* Make Sure Block Lock Bit is not set. */
+ if(clear_block_lock_bit((vu_long *)(info->start[s_first]))){
+ return 1;
+ }
+
+ /* Start erase on unprotected sectors */
+#if defined(DEBUG)
+ printf("Begin to erase now,s_first=0x%x s_last=0x%x...\n",s_first,s_last);
+#endif
+ for (sect = s_first; sect<=s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ vu_long *addr = (vu_long *)(info->start[sect]);
+ asm("sync");
+
+ last = start = get_timer (0);
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ /* Reset Array */
+ *addr = 0xffffffff;
+ asm("sync");
+ /* Clear Status Register */
+ *addr = 0x50505050;
+ asm("sync");
+ /* Single Block Erase Command */
+ *addr = 0x20202020;
+ asm("sync");
+ /* Confirm */
+ *addr = 0xD0D0D0D0;
+ asm("sync");
+
+ if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) {
+ /* Resume Command, as per errata update */
+ *addr = 0xD0D0D0D0;
+ asm("sync");
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay (1000);
+ while ((*addr & 0x00800080) != 0x00800080) {
+ if(*addr & 0x00200020){
+ printf("Error in Block Erase - Lock Bit may be set!\n");
+ printf("Status Register = 0x%X\n", (uint)*addr);
+ *addr = 0xFFFFFFFF; /* reset bank */
+ asm("sync");
+ return 1;
+ }
+ if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ *addr = 0xFFFFFFFF; /* reset bank */
+ asm("sync");
+ return 1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc ('.');
+ last = now;
+ }
+ }
+
+ /* reset to read mode */
+ *addr = 0xFFFFFFFF;
+ asm("sync");
+ }
+ }
+
+ printf ("flash erase done\n");
+ return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ ulong cp, wp, data;
+ int i, l, rc;
+
+ wp = (addr & ~3); /* get lower word aligned address */
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i=0, cp=wp; i<l; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+ for (; i<4 && cnt>0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+ for (; cnt==0 && i<4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ while (cnt >= 4) {
+ data = 0;
+ for (i=0; i<4; ++i) {
+ data = (data << 8) | *src++;
+ }
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ cnt -= 4;
+ }
+
+ if (cnt == 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i<4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+ vu_long *addr = (vu_long *)dest;
+ ulong start, csr;
+ int flag;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*addr & data) != data) {
+ return (2);
+ }
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ /* Write Command */
+ *addr = 0x10101010;
+ asm("sync");
+
+ /* Write Data */
+ *addr = data;
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer (0);
+ flag = 0;
+
+ while (((csr = *addr) & 0x00800080) != 0x00800080) {
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ flag = 1;
+ break;
+ }
+ }
+ if (csr & 0x40404040) {
+ printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr);
+ flag = 1;
+ }
+
+ /* Clear Status Registers Command */
+ *addr = 0x50505050;
+ asm("sync");
+ /* Reset to read array mode */
+ *addr = 0xFFFFFFFF;
+ asm("sync");
+
+ return (flag);
+}
+
+/*-----------------------------------------------------------------------
+ * Clear Block Lock Bit, returns:
+ * 0 - OK
+ * 1 - Timeout
+ */
+
+static int clear_block_lock_bit(vu_long * addr)
+{
+ ulong start, now;
+
+ /* Reset Array */
+ *addr = 0xffffffff;
+ asm("sync");
+ /* Clear Status Register */
+ *addr = 0x50505050;
+ asm("sync");
+
+ *addr = 0x60606060;
+ asm("sync");
+ *addr = 0xd0d0d0d0;
+ asm("sync");
+
+ start = get_timer (0);
+ while((*addr & 0x00800080) != 0x00800080){
+ if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf ("Timeout on clearing Block Lock Bit\n");
+ *addr = 0xFFFFFFFF; /* reset bank */
+ asm("sync");
+ return 1;
+ }
+ }
+ return 0;
+}
+
+#endif /* !CFG_NO_FLASH */
--- /dev/null
+/*
+* Copyright (C) 2002,2003, Motorola Inc.
+* Xianghua Xiao <X.Xiao@motorola.com>
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc85xx.h>
+
+#define entry_start \
+ mflr r1 ; \
+ bl 0f ;
+
+#define entry_end \
+0: mflr r0 ; \
+ mtlr r1 ; \
+ blr ;
+
+/* TLB1 entries configuration: */
+
+ .section .bootpg, "ax"
+ .globl tlb1_entry
+tlb1_entry:
+ entry_start
+
+ .long 0x0a /* the following data table uses a few of 16 TLB entries */
+
+ .long TLB1_MAS0(1,1,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
+ .long TLB1_MAS2(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+ #if defined(CFG_FLASH_PORT_WIDTH_16)
+ .long TLB1_MAS0(1,2,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
+ .long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(1,3,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
+ .long TLB1_MAS2((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,0,1,0,1,0,1)
+ #else
+ .long TLB1_MAS0(1,2,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16M)
+ .long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(1,3,0)
+ .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+ .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+ #endif
+
+ #if !defined(CONFIG_SPD_EEPROM)
+ .long TLB1_MAS0(1,4,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(1,5,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+ #else
+ .long TLB1_MAS0(1,4,0)
+ .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+ .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(1,5,0)
+ .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+ .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+ #endif
+
+ .long TLB1_MAS0(1,6,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
+ #if defined(CONFIG_RAM_AS_FLASH)
+ .long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+ #else
+ .long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+ #endif
+ .long TLB1_MAS3(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(1,7,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
+ #ifdef CONFIG_L2_INIT_RAM
+ .long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,1,0,0,0,0)
+ #else
+ .long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+ #endif
+ .long TLB1_MAS3(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(1,8,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(1,9,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
+ .long TLB1_MAS2(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+ #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+ .long TLB1_MAS0(1,15,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
+ .long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+ #else
+ .long TLB1_MAS0(1,15,0)
+ .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+ .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+ #endif
+ entry_end
+
+/* LAW(Local Access Window) configuration:
+ * 0000_0000-0800_0000: DDR(128M) -or- larger
+ * f000_0000-f3ff_ffff: PCI(256M)
+ * f400_0000-f7ff_ffff: RapidIO(128M)
+ * f800_0000-ffff_ffff: localbus(128M)
+ * f800_0000-fbff_ffff: LBC SDRAM(64M)
+ * fc00_0000-fdef_ffff: LBC BCSR,RTC,etc(31M)
+ * fdf0_0000-fdff_ffff: CCSRBAR(1M)
+ * fe00_0000-ffff_ffff: Flash(32M)
+ * Note: CCSRBAR and L2-as-SRAM don't need configure Local Access
+ * Window.
+ * Note: If flash is 8M at default position(last 8M),no LAW needed.
+ */
+
+#if !defined(CONFIG_SPD_EEPROM)
+#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M))
+#else
+#define LAWBAR0 0
+#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+#endif
+
+#define LAWBAR1 ((CFG_PCI_MEM_BASE>>12) & 0xfffff)
+#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+#if !defined(CONFIG_RAM_AS_FLASH)
+#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M))
+#else
+#define LAWBAR2 0
+#define LAWAR2 ((LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+#endif
+
+ .section .bootpg, "ax"
+ .globl law_entry
+law_entry:
+ entry_start
+ .long 0x03
+ .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2
+ entry_end
--- /dev/null
+/*
+ * (C) Copyright 2002,2003, Motorola Inc.
+ * Xianghua Xiao, (X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+extern long int spd_sdram (void);
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <spd.h>
+
+long int fixed_sdram (void);
+
+/* MPC8540ADS Board Status & Control Registers */
+#if 0
+typedef struct bscr_ {
+ unsigned long bcsr0;
+ unsigned long bcsr1;
+ unsigned long bcsr2;
+ unsigned long bcsr3;
+ unsigned long bcsr4;
+ unsigned long bcsr5;
+ unsigned long bcsr6;
+ unsigned long bcsr7;
+} bcsr_t;
+#endif
+
+int board_pre_init (void)
+{
+#if defined(CONFIG_PCI)
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile ccsr_pcix_t *pci = &immr->im_pcix;
+
+ pci->peer &= 0xffffffdf; /* disable master abort */
+#endif
+ return 0;
+}
+
+int checkboard (void)
+{
+ sys_info_t sysinfo;
+
+ get_sys_info (&sysinfo);
+
+ printf ("Board: Motorola MPC8540ADS Board\n");
+ printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
+ printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
+ printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
+ if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \
+ || (CFG_LBC_LCRR & 0x0f) == 8) {
+ printf ("\tLBC: %lu MHz\n", sysinfo.freqSystemBus / 1000000 /(CFG_LBC_LCRR & 0x0f));
+ } else {
+ printf("\tLBC: unknown\n");
+ }
+ printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
+ return (0);
+}
+
+long int initdram (int board_type)
+{
+ long dram_size = 0;
+ extern long spd_sdram (void);
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+#if !defined(CONFIG_RAM_AS_FLASH)
+ volatile ccsr_lbc_t *lbc= &immap->im_lbc;
+ sys_info_t sysinfo;
+ uint temp_lbcdll = 0;
+#endif
+#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
+ volatile ccsr_gur_t *gur= &immap->im_gur;
+#endif
+#if defined(CONFIG_DDR_DLL)
+ uint temp_ddrdll = 0;
+
+ /* Work around to stabilize DDR DLL */
+ temp_ddrdll = gur->ddrdllcr;
+ gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
+ asm("sync;isync;msync");
+#endif
+
+#if defined(CONFIG_SPD_EEPROM)
+ dram_size = spd_sdram ();
+#else
+ dram_size = fixed_sdram ();
+#endif
+
+#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */
+ get_sys_info(&sysinfo);
+ /* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */
+ if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) {
+ lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000;
+ } else {
+#if defined(CONFIG_MPC85xx_REV1) /* need change CLKDIV before enable DLL */
+ lbc->lcrr = 0x10000004; /* default CLKDIV is 8, change it to 4 temporarily */
+#endif
+ lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff;
+ udelay(200);
+ temp_lbcdll = gur->lbcdllcr;
+ gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
+ asm("sync;isync;msync");
+ }
+ lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */
+ lbc->br2 = CFG_BR2_PRELIM;
+ lbc->lbcr = CFG_LBC_LBCR;
+ lbc->lsdmr = CFG_LBC_LSDMR_1;
+ asm("sync");
+ (unsigned int) * (ulong *)0 = 0x000000ff;
+ lbc->lsdmr = CFG_LBC_LSDMR_2;
+ asm("sync");
+ (unsigned int) * (ulong *)0 = 0x000000ff;
+ lbc->lsdmr = CFG_LBC_LSDMR_3;
+ asm("sync");
+ (unsigned int) * (ulong *)0 = 0x000000ff;
+ lbc->lsdmr = CFG_LBC_LSDMR_4;
+ asm("sync");
+ (unsigned int) * (ulong *)0 = 0x000000ff;
+ lbc->lsdmr = CFG_LBC_LSDMR_5;
+ asm("sync");
+ lbc->lsrt = CFG_LBC_LSRT;
+ asm("sync");
+ lbc->mrtpr = CFG_LBC_MRTPR;
+ asm("sync");
+#endif
+
+#if defined(CONFIG_DDR_ECC)
+ {
+ /* Initialize all of memory for ECC, then
+ * enable errors */
+ uint *p = 0;
+ uint i = 0;
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+ dma_init();
+ for (*p = 0; p < (uint *)(8 * 1024); p++) {
+ if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
+ *p = (unsigned int)0xdeadbeef;
+ if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
+ }
+
+ /* 8K */
+ dma_xfer((uint *)0x2000,0x2000,(uint *)0);
+ /* 16K */
+ dma_xfer((uint *)0x4000,0x4000,(uint *)0);
+ /* 32K */
+ dma_xfer((uint *)0x8000,0x8000,(uint *)0);
+ /* 64K */
+ dma_xfer((uint *)0x10000,0x10000,(uint *)0);
+ /* 128k */
+ dma_xfer((uint *)0x20000,0x20000,(uint *)0);
+ /* 256k */
+ dma_xfer((uint *)0x40000,0x40000,(uint *)0);
+ /* 512k */
+ dma_xfer((uint *)0x80000,0x80000,(uint *)0);
+ /* 1M */
+ dma_xfer((uint *)0x100000,0x100000,(uint *)0);
+ /* 2M */
+ dma_xfer((uint *)0x200000,0x200000,(uint *)0);
+ /* 4M */
+ dma_xfer((uint *)0x400000,0x400000,(uint *)0);
+
+ for (i = 1; i < dram_size / 0x800000; i++) {
+ dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0);
+ }
+
+ /* Enable errors for ECC */
+ ddr->err_disable = 0x00000000;
+ asm("sync;isync;msync");
+ }
+#endif
+
+ return dram_size;
+}
+
+
+#if defined(CFG_DRAM_TEST)
+int testdram (void)
+{
+ uint *pstart = (uint *) CFG_MEMTEST_START;
+ uint *pend = (uint *) CFG_MEMTEST_END;
+ uint *p;
+
+ printf("SDRAM test phase 1:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0xaaaaaaaa;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0xaaaaaaaa) {
+ printf ("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("SDRAM test phase 2:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0x55555555;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0x55555555) {
+ printf ("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("SDRAM test passed.\n");
+ return 0;
+}
+#endif
+
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ * fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+long int fixed_sdram (void)
+{
+ #ifndef CFG_RAMBOOT
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+
+ ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
+ ddr->cs0_config = CFG_DDR_CS0_CONFIG;
+ ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
+ ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
+ ddr->sdram_mode = CFG_DDR_MODE;
+ ddr->sdram_interval = CFG_DDR_INTERVAL;
+ #if defined (CONFIG_DDR_ECC)
+ ddr->err_disable = 0x0000000D;
+ ddr->err_sbe = 0x00ff0000;
+ #endif
+ asm("sync;isync;msync");
+ udelay(500);
+ #if defined (CONFIG_DDR_ECC)
+ /* Enable ECC checking */
+ ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
+ #else
+ ddr->sdram_cfg = CFG_DDR_CONTROL;
+ #endif
+ asm("sync; isync; msync");
+ udelay(500);
+ #endif
+ return (CFG_SDRAM_SIZE * 1024 * 1024);
+}
+#endif /* !defined(CONFIG_SPD_EEPROM) */
--- /dev/null
+/*
+ * (C) Copyright 2002,2003, Motorola,Inc.
+ * Xianghua Xiao, X.Xiao@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFFFF000 :
+ {
+ cpu/mpc85xx/start.o (.bootpg)
+ board/mpc8540ads/init.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc85xx/start.o (.text)
+ board/mpc8540ads/init.o (.text)
+ cpu/mpc85xx/traps.o (.text)
+ cpu/mpc85xx/interrupts.o (.text)
+ cpu/mpc85xx/cpu_init.o (.text)
+ cpu/mpc85xx/cpu.o (.text)
+ cpu/mpc85xx/tsec.o (.text)
+ cpu/mpc85xx/speed.o (.text)
+ cpu/mpc85xx/pci.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
--- /dev/null
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := $(BOARD).o flash.o
+SOBJS := init.o
+#SOBJS :=
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS) $(SOBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
--- /dev/null
+# Modified by Xianghua Xiao, X.Xiao@motorola.com
+# (C) Copyright 2002,2003 Motorola Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# mpc8560ads board
+# default CCARBAR is at 0xff700000
+# assume U-Boot is less than 0.5MB
+#
+TEXT_BASE = 0xfff80000
+
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8560=1
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
--- /dev/null
+/*
+ * (C) Copyright 2003 Motorola Inc.
+ * Xianghua Xiao,(X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
+ * Add support the Sharp chips on the mpc8260ads.
+ * I started with board/ip860/flash.c and made changes I found in
+ * the MTD project by David Schleef.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if !defined(CFG_NO_FLASH)
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef CFG_ENV_ADDR
+# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef CFG_ENV_SIZE
+# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
+# endif
+# ifndef CFG_ENV_SECT_SIZE
+# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE
+# endif
+#endif
+
+#undef DEBUG
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static int clear_block_lock_bit(vu_long * addr);
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+ unsigned long size;
+ int i;
+
+ /* Init: enable write,
+ * or we cannot even write flash commands
+ */
+ for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+
+ /* set the default sector offset */
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size, size<<20);
+ }
+
+ /* Re-do sizing to get full correct info */
+ size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+ flash_info[0].size = size;
+
+#if !defined(CONFIG_RAM_AS_FLASH)
+#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+ /* monitor protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE+monitor_flash_len-1,
+ &flash_info[0]);
+#endif
+
+#ifdef CFG_ENV_IS_IN_FLASH
+ /* ENV protection ON by default */
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_ENV_ADDR,
+ CFG_ENV_ADDR+CFG_ENV_SECT_SIZE-1,
+ &flash_info[0]);
+#endif
+#endif
+ return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_INTEL: printf ("Intel "); break;
+ case FLASH_MAN_SHARP: printf ("Sharp "); break;
+ default: printf ("Unknown Vendor "); break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n");
+ break;
+ case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n");
+ break;
+ case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n");
+ break;
+ case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n");
+ break;
+ case FLASH_28F640J3A: printf ("28F640J3A (64 Mbit, 64 x 128K)\n");
+ break;
+ default: printf ("Unknown Chip Type\n");
+ break;
+ }
+
+ printf (" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i=0; i<info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf ("\n ");
+ printf (" %08lX%s",
+ info->start[i],
+ info->protect[i] ? " (RO)" : " "
+ );
+ }
+ printf ("\n");
+}
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+ short i;
+ ulong value;
+ ulong base = (ulong)addr;
+ ulong sector_offset;
+
+#ifdef DEBUG
+ printf("Check flash at 0x%08x\n",(uint)addr);
+#endif
+ /* Write "Intelligent Identifier" command: read Manufacturer ID */
+ *addr = 0x90909090;
+ udelay(20);
+ asm("sync");
+
+ value = addr[0] & 0x00FF00FF;
+
+#ifdef DEBUG
+ printf("manufacturer=0x%x\n",(uint)value);
+#endif
+ switch (value) {
+ case MT_MANUFACT: /* SHARP, MT or => Intel */
+ case INTEL_ALT_MANU:
+ info->flash_id = FLASH_MAN_INTEL;
+ break;
+ default:
+ printf("unknown manufacturer: %x\n", (unsigned int)value);
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return (0); /* no or unknown flash */
+ }
+
+ value = addr[1] & 0x00FF00FF; /* device ID */
+
+#ifdef DEBUG
+ printf("deviceID=0x%x\n",(uint)value);
+#endif
+ switch (value) {
+ case (INTEL_ID_28F016S):
+ info->flash_id += FLASH_28F016SV;
+ info->sector_count = 32;
+ info->size = 0x00400000;
+ sector_offset = 0x20000;
+ break; /* => 2x2 MB */
+
+ case (INTEL_ID_28F160S3):
+ info->flash_id += FLASH_28F160S3;
+ info->sector_count = 32;
+ info->size = 0x00400000;
+ sector_offset = 0x20000;
+ break; /* => 2x2 MB */
+
+ case (INTEL_ID_28F320S3):
+ info->flash_id += FLASH_28F320S3;
+ info->sector_count = 64;
+ info->size = 0x00800000;
+ sector_offset = 0x20000;
+ break; /* => 2x4 MB */
+
+ case (INTEL_ID_28F640J3A):
+ info->flash_id += FLASH_28F640J3A;
+ info->sector_count = 64;
+ info->size = 0x01000000;
+ sector_offset = 0x40000;
+ break; /* => 8 MB */
+
+ case SHARP_ID_28F016SCL:
+ case SHARP_ID_28F016SCZ:
+ info->flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT;
+ info->sector_count = 32;
+ info->size = 0x00800000;
+ sector_offset = 0x40000;
+ break; /* => 4x2 MB */
+
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return (0); /* => no or unknown flash */
+
+ }
+
+ /* set up sector start address table */
+ for (i = 0; i < info->sector_count; i++) {
+ info->start[i] = base;
+ base += sector_offset;
+ /* don't know how to check sector protection */
+ info->protect[i] = 0;
+ }
+
+ /*
+ * Prevent writes to uninitialized FLASH.
+ */
+ if (info->flash_id != FLASH_UNKNOWN) {
+ addr = (vu_long *)info->start[0];
+ *addr = 0xFFFFFF; /* reset bank to read array mode */
+ asm("sync");
+ }
+
+ return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+ int flag, prot, sect;
+ ulong start, now, last;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL)
+ && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) {
+ printf ("Can't erase unknown flash type %08lx - aborted\n",
+ info->flash_id);
+ return 1;
+ }
+
+ prot = 0;
+ for (sect=s_first; sect<=s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf ("\n");
+ }
+
+#ifdef DEBUG
+ printf("\nFlash Erase:\n");
+#endif
+ /* Make Sure Block Lock Bit is not set. */
+ if(clear_block_lock_bit((vu_long *)(info->start[s_first]))){
+ return 1;
+ }
+
+ /* Start erase on unprotected sectors */
+#if defined(DEBUG)
+ printf("Begin to erase now,s_first=0x%x s_last=0x%x...\n",s_first,s_last);
+#endif
+ for (sect = s_first; sect<=s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ vu_long *addr = (vu_long *)(info->start[sect]);
+ asm("sync");
+
+ last = start = get_timer (0);
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ /* Reset Array */
+ *addr = 0xffffffff;
+ asm("sync");
+ /* Clear Status Register */
+ *addr = 0x50505050;
+ asm("sync");
+ /* Single Block Erase Command */
+ *addr = 0x20202020;
+ asm("sync");
+ /* Confirm */
+ *addr = 0xD0D0D0D0;
+ asm("sync");
+
+ if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) {
+ /* Resume Command, as per errata update */
+ *addr = 0xD0D0D0D0;
+ asm("sync");
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay (1000);
+ while ((*addr & 0x00800080) != 0x00800080) {
+ if(*addr & 0x00200020){
+ printf("Error in Block Erase - Lock Bit may be set!\n");
+ printf("Status Register = 0x%X\n", (uint)*addr);
+ *addr = 0xFFFFFFFF; /* reset bank */
+ asm("sync");
+ return 1;
+ }
+ if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ *addr = 0xFFFFFFFF; /* reset bank */
+ asm("sync");
+ return 1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc ('.');
+ last = now;
+ }
+ }
+
+ /* reset to read mode */
+ *addr = 0xFFFFFFFF;
+ asm("sync");
+ }
+ }
+
+ printf ("flash erase done\n");
+ return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ ulong cp, wp, data;
+ int i, l, rc;
+
+ wp = (addr & ~3); /* get lower word aligned address */
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i=0, cp=wp; i<l; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+ for (; i<4 && cnt>0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+ for (; cnt==0 && i<4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ while (cnt >= 4) {
+ data = 0;
+ for (i=0; i<4; ++i) {
+ data = (data << 8) | *src++;
+ }
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ cnt -= 4;
+ }
+
+ if (cnt == 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i<4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+ vu_long *addr = (vu_long *)dest;
+ ulong start, csr;
+ int flag;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*addr & data) != data) {
+ return (2);
+ }
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ /* Write Command */
+ *addr = 0x10101010;
+ asm("sync");
+
+ /* Write Data */
+ *addr = data;
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer (0);
+ flag = 0;
+
+ while (((csr = *addr) & 0x00800080) != 0x00800080) {
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ flag = 1;
+ break;
+ }
+ }
+ if (csr & 0x40404040) {
+ printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr);
+ flag = 1;
+ }
+
+ /* Clear Status Registers Command */
+ *addr = 0x50505050;
+ asm("sync");
+ /* Reset to read array mode */
+ *addr = 0xFFFFFFFF;
+ asm("sync");
+
+ return (flag);
+}
+
+/*-----------------------------------------------------------------------
+ * Clear Block Lock Bit, returns:
+ * 0 - OK
+ * 1 - Timeout
+ */
+
+static int clear_block_lock_bit(vu_long * addr)
+{
+ ulong start, now;
+
+ /* Reset Array */
+ *addr = 0xffffffff;
+ asm("sync");
+ /* Clear Status Register */
+ *addr = 0x50505050;
+ asm("sync");
+
+ *addr = 0x60606060;
+ asm("sync");
+ *addr = 0xd0d0d0d0;
+ asm("sync");
+
+ start = get_timer (0);
+ while((*addr & 0x00800080) != 0x00800080){
+ if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf ("Timeout on clearing Block Lock Bit\n");
+ *addr = 0xFFFFFFFF; /* reset bank */
+ asm("sync");
+ return 1;
+ }
+ }
+ return 0;
+}
+
+#endif /* !CFG_NO_FLASH */
--- /dev/null
+/*
+* Copyright (C) 2002,2003, Motorola Inc.
+* Xianghua Xiao <X.Xiao@motorola.com>
+*
+* See file CREDITS for list of people who contributed to this
+* project.
+*
+* This program is free software; you can redistribute it and/or
+* modify it under the terms of the GNU General Public License as
+* published by the Free Software Foundation; either version 2 of
+* the License, or (at your option) any later version.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+* MA 02111-1307 USA
+*/
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+#include <asm/cache.h>
+#include <asm/mmu.h>
+#include <config.h>
+#include <mpc85xx.h>
+
+#define entry_start \
+ mflr r1 ; \
+ bl 0f ;
+
+#define entry_end \
+0: mflr r0 ; \
+ mtlr r1 ; \
+ blr ;
+
+/* TLB1 entries configuration: */
+
+ .section .bootpg, "ax"
+ .globl tlb1_entry
+tlb1_entry:
+ entry_start
+
+ .long 0x0a /* the following data table uses a few of 16 TLB entries */
+
+ .long TLB1_MAS0(1,1,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
+ .long TLB1_MAS2(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+ #if defined(CFG_FLASH_PORT_WIDTH_16)
+ .long TLB1_MAS0(1,2,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
+ .long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(1,3,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
+ .long TLB1_MAS2((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,0,1,0,1,0,1)
+ #else
+ .long TLB1_MAS0(1,2,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16M)
+ .long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(1,3,0)
+ .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+ .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+ #endif
+
+ #if !defined(CONFIG_SPD_EEPROM)
+ .long TLB1_MAS0(1,4,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(1,5,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+ #else
+ .long TLB1_MAS0(1,4,0)
+ .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+ .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(1,5,0)
+ .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+ .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+ #endif
+
+ .long TLB1_MAS0(1,6,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
+ #if defined(CONFIG_RAM_AS_FLASH)
+ .long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+ #else
+ .long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+ #endif
+ .long TLB1_MAS3(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(1,7,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
+ #ifdef CONFIG_L2_INIT_RAM
+ .long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,1,0,0,0,0)
+ #else
+ .long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,0,0,0)
+ #endif
+ .long TLB1_MAS3(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(1,8,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(((CFG_PCI_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+ .long TLB1_MAS0(1,9,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
+ .long TLB1_MAS2(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+
+ #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+ .long TLB1_MAS0(1,15,0)
+ .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
+ .long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
+ #else
+ .long TLB1_MAS0(1,15,0)
+ .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
+ .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
+ #endif
+ entry_end
+
+/* LAW(Local Access Window) configuration:
+ * 0000_0000-0800_0000: DDR(128M) -or- larger
+ * f000_0000-f3ff_ffff: PCI(256M)
+ * f400_0000-f7ff_ffff: RapidIO(128M)
+ * f800_0000-ffff_ffff: localbus(128M)
+ * f800_0000-fbff_ffff: LBC SDRAM(64M)
+ * fc00_0000-fdef_ffff: LBC BCSR,RTC,etc(31M)
+ * fdf0_0000-fdff_ffff: CCSRBAR(1M)
+ * fe00_0000-ffff_ffff: Flash(32M)
+ * Note: CCSRBAR and L2-as-SRAM don't need configure Local Access
+ * Window.
+ * Note: If flash is 8M at default position(last 8M),no LAW needed.
+ */
+
+#if !defined(CONFIG_SPD_EEPROM)
+#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M))
+#else
+#define LAWBAR0 0
+#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+#endif
+
+#define LAWBAR1 ((CFG_PCI_MEM_BASE>>12) & 0xfffff)
+#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_256M))
+
+#if !defined(CONFIG_RAM_AS_FLASH)
+#define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
+#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M))
+#else
+#define LAWBAR2 0
+#define LAWAR2 ((LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
+#endif
+
+ .section .bootpg, "ax"
+ .globl law_entry
+law_entry:
+ entry_start
+ .long 0x03
+ .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2
+ entry_end
--- /dev/null
+/*
+ * (C) Copyright 2003,Motorola Inc.
+ * Xianghua Xiao, (X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+extern long int spd_sdram (void);
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <ioports.h>
+#include <spd.h>
+#include <miiphy.h>
+
+long int fixed_sdram (void);
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+ /* Port A configuration */
+ { /* conf ppar psor pdir podr pdat */
+ /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
+ /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
+ /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
+ /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
+ /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
+ /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
+ /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
+ /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
+ /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
+ /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
+ /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
+ /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
+ /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
+ /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
+ /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
+ /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
+ /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
+ /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
+ /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
+ /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
+ /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
+ /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
+ /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
+ /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
+ /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
+ /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
+ /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
+ /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
+ /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
+ /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
+ /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
+ /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
+ },
+
+ /* Port B configuration */
+ { /* conf ppar psor pdir podr pdat */
+ /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
+ /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
+ /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
+ /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
+ /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
+ /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
+ /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
+ /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
+ /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
+ /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
+ /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
+ /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
+ /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
+ /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
+ /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
+ /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
+ /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
+ /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
+ /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
+ /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
+ /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
+ },
+
+ /* Port C */
+ { /* conf ppar psor pdir podr pdat */
+ /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
+ /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
+ /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
+ /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
+ /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
+ /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
+ /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
+ /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
+ /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
+ /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
+ /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
+ /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
+ /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
+ /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
+ /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
+ /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
+ /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */
+ /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
+ /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
+ /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
+ /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
+ /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
+ /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
+ /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
+ /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
+ /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
+ /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
+ /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
+ /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
+ /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
+ /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
+ /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
+ },
+
+ /* Port D */
+ { /* conf ppar psor pdir podr pdat */
+ /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
+ /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
+ /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
+ /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
+ /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
+ /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
+ /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
+ /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
+ /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
+ /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
+ /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
+ /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
+ /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
+ /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
+ /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
+ /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
+ /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
+ /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
+ /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
+ /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
+ /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
+ /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
+ /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
+ /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
+ /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
+ /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
+ /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
+ /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
+ /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
+ }
+};
+
+/* MPC8560ADS Board Status & Control Registers */
+typedef struct bscr_ {
+ volatile unsigned char bcsr0;
+ volatile unsigned char bcsr1;
+ volatile unsigned char bcsr2;
+ volatile unsigned char bcsr3;
+ volatile unsigned char bcsr4;
+ volatile unsigned char bcsr5;
+} bcsr_t;
+
+int board_pre_init (void)
+{
+#if defined(CONFIG_PCI)
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile ccsr_pcix_t *pci = &immr->im_pcix;
+
+ pci->peer &= 0xfffffffdf; /* disable master abort */
+#endif
+ return 0;
+}
+
+void reset_phy (void)
+{
+#if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */
+ volatile bcsr_t *bcsr = (bcsr_t *) CFG_BCSR;
+#endif
+ /* reset Giga bit Ethernet port if needed here */
+
+ /* reset the CPM FEC port */
+#if (CONFIG_ETHER_INDEX == 2)
+ bcsr->bcsr2 &= ~FETH2_RST;
+ udelay(2);
+ bcsr->bcsr2 |= FETH2_RST;
+ udelay(1000);
+#elif (CONFIG_ETHER_INDEX == 3)
+ bcsr->bcsr3 &= ~FETH3_RST;
+ udelay(2);
+ bcsr->bcsr3 |= FETH3_RST;
+ udelay(1000);
+#endif
+#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
+ miiphy_reset(0x0); /* reset PHY */
+ miiphy_write(0, PHY_MIPSCR, 0xf028); /* change PHY address to 0x02 */
+ miiphy_write(0x02, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
+#endif /* CONFIG_MII */
+}
+
+int checkboard (void)
+{
+ sys_info_t sysinfo;
+
+ get_sys_info (&sysinfo);
+
+ printf ("Board: Motorola MPC8560ADS Board\n");
+ printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
+ printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
+ printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
+ if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \
+ || (CFG_LBC_LCRR & 0x0f) == 8) {
+ printf ("\tLBC: %lu MHz\n", sysinfo.freqSystemBus / 1000000 /(CFG_LBC_LCRR & 0x0f));
+ } else {
+ printf("\tLBC: unknown\n");
+ }
+ printf("\tCPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
+ printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
+
+ return (0);
+}
+
+
+long int initdram (int board_type)
+{
+ long dram_size = 0;
+ extern long spd_sdram (void);
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+#if !defined(CONFIG_RAM_AS_FLASH)
+ volatile ccsr_lbc_t *lbc= &immap->im_lbc;
+ sys_info_t sysinfo;
+ uint temp_lbcdll = 0;
+#endif
+#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
+ volatile ccsr_gur_t *gur= &immap->im_gur;
+#endif
+#if defined(CONFIG_DDR_DLL)
+ uint temp_ddrdll = 0;
+
+ /* Work around to stabilize DDR DLL */
+ temp_ddrdll = gur->ddrdllcr;
+ gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
+ asm("sync;isync;msync");
+#endif
+
+#if defined(CONFIG_SPD_EEPROM)
+ dram_size = spd_sdram ();
+#else
+ dram_size = fixed_sdram ();
+#endif
+
+#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus SDRAM is not emulating flash */
+ get_sys_info(&sysinfo);
+ /* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */
+ if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) {
+ lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000;
+ } else {
+#if defined(CONFIG_MPC85xx_REV1) /* need change CLKDIV before enable DLL */
+ lbc->lcrr = 0x10000004; /* default CLKDIV is 8, change it to 4 temporarily */
+#endif
+ lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff;
+ udelay(200);
+ temp_lbcdll = gur->lbcdllcr;
+ gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
+ asm("sync;isync;msync");
+ }
+ lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */
+ lbc->br2 = CFG_BR2_PRELIM;
+ lbc->lbcr = CFG_LBC_LBCR;
+ lbc->lsdmr = CFG_LBC_LSDMR_1;
+ asm("sync");
+ (unsigned int) * (ulong *)0 = 0x000000ff;
+ lbc->lsdmr = CFG_LBC_LSDMR_2;
+ asm("sync");
+ (unsigned int) * (ulong *)0 = 0x000000ff;
+ lbc->lsdmr = CFG_LBC_LSDMR_3;
+ asm("sync");
+ (unsigned int) * (ulong *)0 = 0x000000ff;
+ lbc->lsdmr = CFG_LBC_LSDMR_4;
+ asm("sync");
+ (unsigned int) * (ulong *)0 = 0x000000ff;
+ lbc->lsdmr = CFG_LBC_LSDMR_5;
+ asm("sync");
+ lbc->lsrt = CFG_LBC_LSRT;
+ asm("sync");
+ lbc->mrtpr = CFG_LBC_MRTPR;
+ asm("sync");
+#endif
+
+#if defined(CONFIG_DDR_ECC)
+ {
+ /* Initialize all of memory for ECC, then
+ * enable errors */
+ uint *p = 0;
+ uint i = 0;
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+ dma_init();
+ for (*p = 0; p < (uint *)(8 * 1024); p++) {
+ if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
+ *p = (unsigned int)0xdeadbeef;
+ if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
+ }
+
+ /* 8K */
+ dma_xfer((uint *)0x2000,0x2000,(uint *)0);
+ /* 16K */
+ dma_xfer((uint *)0x4000,0x4000,(uint *)0);
+ /* 32K */
+ dma_xfer((uint *)0x8000,0x8000,(uint *)0);
+ /* 64K */
+ dma_xfer((uint *)0x10000,0x10000,(uint *)0);
+ /* 128k */
+ dma_xfer((uint *)0x20000,0x20000,(uint *)0);
+ /* 256k */
+ dma_xfer((uint *)0x40000,0x40000,(uint *)0);
+ /* 512k */
+ dma_xfer((uint *)0x80000,0x80000,(uint *)0);
+ /* 1M */
+ dma_xfer((uint *)0x100000,0x100000,(uint *)0);
+ /* 2M */
+ dma_xfer((uint *)0x200000,0x200000,(uint *)0);
+ /* 4M */
+ dma_xfer((uint *)0x400000,0x400000,(uint *)0);
+
+ for (i = 1; i < dram_size / 0x800000; i++) {
+ dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0);
+ }
+
+ /* Enable errors for ECC */
+ ddr->err_disable = 0x00000000;
+ asm("sync;isync;msync");
+ }
+#endif
+
+ return dram_size;
+}
+
+
+#if defined(CFG_DRAM_TEST)
+int testdram (void)
+{
+ uint *pstart = (uint *) CFG_MEMTEST_START;
+ uint *pend = (uint *) CFG_MEMTEST_END;
+ uint *p;
+
+ printf("SDRAM test phase 1:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0xaaaaaaaa;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0xaaaaaaaa) {
+ printf ("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("SDRAM test phase 2:\n");
+ for (p = pstart; p < pend; p++)
+ *p = 0x55555555;
+
+ for (p = pstart; p < pend; p++) {
+ if (*p != 0x55555555) {
+ printf ("SDRAM test fails at: %08x\n", (uint) p);
+ return 1;
+ }
+ }
+
+ printf("SDRAM test passed.\n");
+ return 0;
+}
+#endif
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*************************************************************************
+ * fixed sdram init -- doesn't use serial presence detect.
+ ************************************************************************/
+long int fixed_sdram (void)
+{
+ #ifndef CFG_RAMBOOT
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+
+ ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
+ ddr->cs0_config = CFG_DDR_CS0_CONFIG;
+ ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
+ ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
+ ddr->sdram_mode = CFG_DDR_MODE;
+ ddr->sdram_interval = CFG_DDR_INTERVAL;
+ #if defined (CONFIG_DDR_ECC)
+ ddr->err_disable = 0x0000000D;
+ ddr->err_sbe = 0x00ff0000;
+ #endif
+ asm("sync;isync;msync");
+ udelay(500);
+ #if defined (CONFIG_DDR_ECC)
+ /* Enable ECC checking */
+ ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
+ #else
+ ddr->sdram_cfg = CFG_DDR_CONTROL;
+ #endif
+ asm("sync; isync; msync");
+ udelay(500);
+ #endif
+ return ( CFG_SDRAM_SIZE * 1024 * 1024);
+}
+#endif /* !defined(CONFIG_SPD_EEPROM) */
--- /dev/null
+/*
+ * (C) Copyright 2002,2003,Motorola,Inc.
+ * Xianghua Xiao, X.Xiao@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ .bootpg 0xFFFFF000 :
+ {
+ cpu/mpc85xx/start.o (.bootpg)
+ board/mpc8560ads/init.o (.bootpg)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ cpu/mpc85xx/start.o (.text)
+ board/mpc8560ads/init.o (.text)
+ cpu/mpc85xx/commproc.o (.text)
+ cpu/mpc85xx/traps.o (.text)
+ cpu/mpc85xx/interrupts.o (.text)
+ cpu/mpc85xx/serial_scc.o (.text)
+ cpu/mpc85xx/ether_fcc.o (.text)
+ cpu/mpc85xx/cpu_init.o (.text)
+ cpu/mpc85xx/cpu.o (.text)
+ cpu/mpc85xx/tsec.o (.text)
+ cpu/mpc85xx/speed.o (.text)
+ cpu/mpc85xx/i2c.o (.text)
+ cpu/mpc85xx/spd_sdram.o (.text)
+ common/dlmalloc.o (.text)
+ lib_generic/crc32.o (.text)
+ lib_ppc/extable.o (.text)
+ lib_generic/zlib.o (.text)
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
* The first thing we do is to map the Flash CS to the Flash area and
* the MPS CS to the MPS area. Since the flash size is unknown at this
* point, we use the max flash size and the lowest flash address as base.
- *
+ *
* After flash detection we adjust the size of the CS area accordingly.
* The board_init_r will fill in wrong values in the board init structure,
* but this will be fixed in the misc_init_r routine:
* bd->bi_flashstart=0-flash_info[0].size
* bd->bi_flashsize=flash_info[0].size-CFG_MONITOR_LEN
* bd->bi_flashoffset=0
- *
+ *
*/
int get_boot_mode(void)
{
}
-
unsigned long flash_init (void)
{
unsigned long size_b0, size_b1,flashcr, size_reg;
case 32: i=5; break; /* = 32MB */
case 64: i=6; break; /* = 64MB */
case 128: i=7; break; /*= 128MB */
- default:
+ default:
printf("\n #### ERROR, wrong size %ld MByte reset board #####\n",size_reg);
while(1);
}
/*-----------------------------------------------------------------------
-
+
*/
/*
"vcma9 - VCMA9 specific commands\n",
"flash mem [SrcAddr]\n - updates U-Boot with image in memory\n"
);
-
ldrb r3, [r2, #SDRAM_REG-PLD_BASE]
mov r4, #SDRAMDATA1_END-SDRAMDATA
/* calculate start and end point */
- mla r0, r3, r4, r0
+ mla r0, r3, r4, r0
add r2, r0, r4
0:
ldr r3, [r0], #4
str r3, [r1], #4
cmp r2, r0
bne 0b
-
+
/* everything is fine now */
mov pc, lr
.word 0x32 + BURST_EN
.word 0x30
.word 0x30
-
+
/* 2Mx8x4 (not implemented yet) */
.word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
.word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
.word 0x32 + BURST_EN
.word 0x30
.word 0x30
-
+
/* 4Mx8x2 (not implemented yet) */
.word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
.word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
static u8 Get_PLD_ID(void)
{
VCMA9_PLD * const pld = VCMA9_GetBase_PLD();
-
+
return(pld->ID);
}
static u8 Get_PLD_BOARD(void)
{
VCMA9_PLD * const pld = VCMA9_GetBase_PLD();
-
+
return(pld->BOARD);
}
static u8 Get_PLD_SDRAM(void)
{
VCMA9_PLD * const pld = VCMA9_GetBase_PLD();
-
+
return(pld->SDRAM);
}
case 2: return 8 * (1024*1024);
case 3: return 8 * (1024*1024);
default: return 0;
- }
+ }
}
static const char * Get_SDRAM_ChipGeom(void)
{
* Print VCMA9 Info
************************************************************************/
void print_vcma9_info(void)
-{
+{
unsigned char s[50];
int i;
-
+
if ((i = getenv_r("serial#", s, 32)) < 0) {
puts ("### No HW ID - assuming VCMA9");
printf("i %d", i*24);
#define mb() __asm__ __volatile__ ("" : : : "memory")
-
/* Flash Organization Structure */
typedef struct OrgDef {
unsigned int sector_number;
}
-
-
/* unprotects a sector for write and erase
* on some intel parts, this unprotects the entire chip, but it
* wont hurt to call this additional times per sector...
}
-
-
start = get_timer (0);
last = start;
while (((status =
*addr) & (FPW) 0x00800080) !=
(FPW) 0x00800080) {
- if (get_timer_masked () >
+ if (get_timer_masked () >
CFG_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
/* suspend erase */
bne watch2Wait
-
-
/* Set memory timings corresponding to the new clock speed */
/* Check execution location to determine current execution location
REG_ARM_IDLECT3: /* 16 bits */
.word 0xfffece24
REG_ARM_IDLECT2: /* 16 bits */
- .word 0xfffece08
+ .word 0xfffece08
REG_ARM_IDLECT1: /* 16 bits */
.word 0xfffece04
.word 0xfffeb048
/* watchdog write pending */
REG_WWPSDOG:
- .word 0xfffeb034
+ .word 0xfffeb034
WSPRDOG_VAL1:
.word 0x0000aaaa
/* 96 MHz Samsung Mobile DDR */
SDRAM_CONFIG_VAL:
- .word 0x001200f4
+ .word 0x001200f4
DLL_LRD_CONTROL_VAL:
.word 0x00800002
.data : { *(.data) }
. = ALIGN(4);
.got : { *(.got) }
-
+
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
-
+
armboot_end_data = .;
. = ALIGN(4);
.bss : { *(.bss) }
setenv("Daq128xSampling", "1");
}
- /*
- * Display the ADC/DAC clocking information
+ /*
+ * Display the ADC/DAC clocking information
*/
if (!quiet) {
- Daq_Display_Clocks();
+ Daq_Display_Clocks();
}
/*
* 3) Write the I2C address to register 6
* 4) Enable address matching by setting the MSB in register 7
*/
-
+
if (!quiet) {
- printf("Initializing the ADC...\n");
+ printf("Initializing the ADC...\n");
}
udelay(ADC_INITIAL_DELAY); /* 10uSec per uF of VREF cap */
I2C_TRISTATE;
if (!quiet) {
- printf("\n");
+ printf("\n");
}
#ifdef CONFIG_ETHER_LOOPBACK_TEST
if(status > 0) {
last_boot_progress = status;
} else {
- /*
+ /*
* If a specific failure code is given, flash this code
* else just use the last success code we've seen
*/
if(status < -1)
last_boot_progress = -status;
-
- /*
+
+ /*
* Flash this code 5 times
*/
for(j=0; j<5; j++) {
status_led_set(STATUS_LED_RED, STATUS_LED_ON);
flash_code(last_boot_progress, 5, 3);
- /*
- * Delay 5 seconds between repetitions,
- * with the fault LED blinking
+ /*
+ * Delay 5 seconds between repetitions,
+ * with the fault LED blinking
*/
for(i=0; i<5; i++) {
- status_led_set(STATUS_LED_RED, STATUS_LED_OFF);
- udelay(500000);
- status_led_set(STATUS_LED_RED, STATUS_LED_ON);
- udelay(500000);
+ status_led_set(STATUS_LED_RED, STATUS_LED_OFF);
+ udelay(500000);
+ status_led_set(STATUS_LED_RED, STATUS_LED_ON);
+ udelay(500000);
}
}
{
pci_mpc824x_init(&hose);
}
-
memctl->memc_or5 = CFG_OR5_ISP1362;
memctl->memc_br5 = CFG_BR5_ISP1362;
#endif /* CONFIG_ISP1362_USB */
-
-
+
+
return (size_b0 + size_b1);
}
#define BWSCON 0x14000000
/* Bank0 */
-#define B0_Tacs 0x0 /* 0 clk */
-#define B0_Tcos 0x0 /* 0 clk */
+#define B0_Tacs 0x3 /* 4 clk */
+#define B0_Tcos 0x3 /* 4 clk */
#define B0_Tacc 0x7 /* 14 clk */
#define B0_Tcoh 0x0 /* 0 clk */
#define B0_Tah 0x0 /* 0 clk */
}
-
int do_touch (char **argv)
{
int x, y;
}
-
int do_rs485 (char **argv)
{
int timeout;
int i;
/* Configure I/O ports. */
- gpio->PDCON = (gpio->PDCON & 0xF3FFFF) | 0x040000;
+ gpio->PDCON = (gpio->PDCON & 0xF3FFFF) | 0x040000;
gpio->PGCON = (gpio->PGCON & 0x0F3FFF) | 0x008000;
gpio->PGCON = (gpio->PGCON & 0x0CFFFF) | 0x020000;
gpio->PGCON = (gpio->PGCON & 0x03FFFF) | 0x080000;
spi->ch[0].SPPRE = 0x1F; /* Baud-rate ca. 514kHz */
spi->ch[0].SPPIN = 0x01; /* SPI-MOSI holds Level after last bit */
spi->ch[0].SPCON = 0x1A; /* Polling, Prescaler, Master, CPOL=0,
- CPHA=1 */
+ CPHA=1 */
/* Dummy byte ensures clock to be low. */
for (i = 0; i < 10; i++) {
SET_CS_TOUCH();
command = reg;
- spi->ch[0].SPTDAT = (command & 0xFF00) >> 8;
+ spi->ch[0].SPTDAT = (command & 0xFF00) >> 8;
spi_wait_transmit_done();
spi->ch[0].SPTDAT = (command & 0x00FF);
spi_wait_transmit_done();
SET_CS_TOUCH();
command = 0x8000 | reg;
- spi->ch[0].SPTDAT = (command & 0xFF00) >> 8;
+ spi->ch[0].SPTDAT = (command & 0xFF00) >> 8;
spi_wait_transmit_done();
spi->ch[0].SPTDAT = (command & 0x00FF);
spi_wait_transmit_done();
- spi->ch[0].SPTDAT = 0xFF;
+ spi->ch[0].SPTDAT = 0xFF;
spi_wait_transmit_done();
data = spi->ch[0].SPRDAT;
spi->ch[0].SPTDAT = 0xFF;
void tsc2000_set_mux (unsigned int channel)
{
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
CLR_MUX1_ENABLE; CLR_MUX2_ENABLE;
CLR_MUX3_ENABLE; CLR_MUX4_ENABLE;
void tsc2000_set_range (unsigned int range)
{
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
switch (range) {
case 1:
udelay(3 * TSC2000_DELAY_BASE);
tsc2000_write(TSC2000_REG_ADC, 0x2036);
- adc_wait_conversion_done ();
- res = tsc2000_read(TSC2000_REG_AUX1);
+ adc_wait_conversion_done ();
+ res = tsc2000_read(TSC2000_REG_AUX1);
return res;
}
s32 tsc2000_contact_temp (void)
{
long adc_pt1000, offset;
- long u_pt1000;
+ long u_pt1000;
long contact_temp;
- tsc2000_reg_init ();
+ tsc2000_reg_init ();
tsc2000_set_range (3);
- adc_pt1000 = tsc2000_read_channel (14);
- debug ("read channel 14 (pt1000 adc value): %ld\n", adc_pt1000);
-
- offset = tsc2000_read_channel (15);
- debug ("read channel 15 (offset): %ld\n", offset);
-
- /*
- * Formula for calculating voltage drop on PT1000 resistor: u_pt1000 =
- * x_range3 * (adc_raw - offset) / 10. Formula to calculate x_range3:
- * x_range3 = (2500 * (1000000 + err_vref + err_amp3)) / (4095*6). The
- * error correction Values err_vref and err_amp3 are assumed as 0 in
- * u-boot, because this could cause only a very small error (< 1%).
- */
- u_pt1000 = (101750 * (adc_pt1000 - offset)) / 10;
- debug ("u_pt1000: %ld\n", u_pt1000);
-
- if (tsc2000_interpolate(u_pt1000, Pt1000_temp_table,
- &contact_temp) == -1) {
- printf ("%s: error interpolating PT1000 vlaue\n",
- __FUNCTION__);
- return (-1000);
- }
- debug ("contact_temp: %ld\n", contact_temp);
+ adc_pt1000 = tsc2000_read_channel (14);
+ debug ("read channel 14 (pt1000 adc value): %ld\n", adc_pt1000);
+
+ offset = tsc2000_read_channel (15);
+ debug ("read channel 15 (offset): %ld\n", offset);
+
+ /*
+ * Formula for calculating voltage drop on PT1000 resistor: u_pt1000 =
+ * x_range3 * (adc_raw - offset) / 10. Formula to calculate x_range3:
+ * x_range3 = (2500 * (1000000 + err_vref + err_amp3)) / (4095*6). The
+ * error correction Values err_vref and err_amp3 are assumed as 0 in
+ * u-boot, because this could cause only a very small error (< 1%).
+ */
+ u_pt1000 = (101750 * (adc_pt1000 - offset)) / 10;
+ debug ("u_pt1000: %ld\n", u_pt1000);
+
+ if (tsc2000_interpolate(u_pt1000, Pt1000_temp_table,
+ &contact_temp) == -1) {
+ printf ("%s: error interpolating PT1000 vlaue\n",
+ __FUNCTION__);
+ return (-1000);
+ }
+ debug ("contact_temp: %ld\n", contact_temp);
return contact_temp;
}
void tsc2000_reg_init (void)
{
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
tsc2000_write(TSC2000_REG_ADC, 0x2036);
tsc2000_write(TSC2000_REG_REF, 0x0011);
void adc_wait_conversion_done(void)
{
- while (!(tsc2000_read(TSC2000_REG_ADC) & (1 << 14)));
+ while (!(tsc2000_read(TSC2000_REG_ADC) & (1 << 14)));
}
#define TSC2000_NO_SENSOR -0x10000
#define ERROR_BATTERY 220 /* must be adjusted, if R68 is changed on
- * TRAB */
+ * TRAB */
void tsc2000_write(unsigned short, unsigned short);
unsigned short tsc2000_read (unsigned short);
print_num ("flashoffset", bd->bi_flashoffset );
print_num ("sramstart", bd->bi_sramstart );
print_num ("sramsize", bd->bi_sramsize );
-#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260)
+#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) || defined(CONFIG_E500)
print_num ("immr_base", bd->bi_immr_base );
#endif
print_num ("bootflags", bd->bi_bootflags );
print_str ("pci_busfreq", strmhz(buf, bd->bi_pci_busfreq));
#endif
#else /* ! CONFIG_405GP, CONFIG_405CR, CONFIG_405EP */
-#if defined(CONFIG_8260)
+#if defined(CONFIG_8260) || defined(CONFIG_MPC8560)
print_str ("vco", strmhz(buf, bd->bi_vco));
print_str ("sccfreq", strmhz(buf, bd->bi_sccfreq));
print_str ("brgfreq", strmhz(buf, bd->bi_brgfreq));
#endif
print_str ("intfreq", strmhz(buf, bd->bi_intfreq));
-#if defined(CONFIG_8260)
+#if defined(CONFIG_8260) || defined(CONFIG_MPC8560)
print_str ("cpmfreq", strmhz(buf, bd->bi_cpmfreq));
#endif
print_str ("busfreq", strmhz(buf, bd->bi_busfreq));
for (i=0; i<6; ++i) {
printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]);
}
-#if (defined CONFIG_PN62) || (defined CONFIG_PPCHAMELEONEVB)
+#if (defined CONFIG_PN62) || (defined CONFIG_PPCHAMELEONEVB) \
+ || (defined CONFIG_MPC8540ADS) || (defined CONFIG_MPC8560ADS)
printf ("\neth1addr =");
for (i=0; i<6; ++i) {
printf ("%c%02X", i ? ':' : ' ', bd->bi_enet1addr[i]);
}
#endif /* CONFIG_PN62 */
+#if defined(CONFIG_MPC8540ADS) || defined(CONFIG_MPC8560ADS)
+ printf ("\neth2addr =");
+ for (i=0; i<6; ++i) {
+ printf ("%c%02X", i ? ':' : ' ', bd->bi_enet2addr[i]);
+ }
+#endif
#ifdef CONFIG_HERMES
print_str ("ethspeed", strmhz(buf, bd->bi_ethspeed));
#endif
/* convert all clock information to MHz */
kbd->bi_intfreq /= 1000000L;
kbd->bi_busfreq /= 1000000L;
-#if defined(CONFIG_8260)
+#if defined(CONFIG_8260) || defined(CONFIG_MPC8560)
kbd->bi_cpmfreq /= 1000000L;
kbd->bi_brgfreq /= 1000000L;
kbd->bi_sccfreq /= 1000000L;
SHOW_BOOT_PROGRESS (15);
-#ifdef CFG_INIT_RAM_LOCK
+#if defined(CFG_INIT_RAM_LOCK) && !defined(CONFIG_E500)
unlock_ram_in_cache();
#endif
/*
}
#endif /* CONFIG_LYNXKDI */
-
#include <fat.h>
-
-
block_dev_desc_t *get_dev (char* ifname, int dev)
{
#if (CONFIG_COMMANDS & CFG_CMD_IDE)
}
-
-
U_BOOT_CMD(
fatload, 6, 0, do_fat_fsload,
"fatload - load binary file from a dos filesystem\n",
#ifdef CONFIG_SPLASH_SCREEN
/* suppress all output if splash screen is enabled and we have
- a bmp to display */
+ a bmp to display */
if (getenv("splashimage") != NULL)
outputdev = search_device (DEV_FLAGS_OUTPUT, "nulldev");
#endif
#endif
#endif /* CONFIG_LYNXKDI */
-
dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
str,
- sohci_get_current_frame_number (dev),
- usb_pipedevice (pipe),
- usb_pipeendpoint (pipe),
- usb_pipeout (pipe)? 'O': 'I',
- usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
- (usb_pipecontrol (pipe)? "CTRL": "BULK"),
- purb->actual_length,
- transfer_len, dev->status);
+ sohci_get_current_frame_number (dev),
+ usb_pipedevice (pipe),
+ usb_pipeendpoint (pipe),
+ usb_pipeout (pipe)? 'O': 'I',
+ usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
+ (usb_pipecontrol (pipe)? "CTRL": "BULK"),
+ purb->actual_length,
+ transfer_len, dev->status);
#ifdef OHCI_VERBOSE_DEBUG
if (!small) {
int i, len;
if (ed->state == ED_NEW) {
ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */
- /* dummy td; end of td list for ed */
+ /* dummy td; end of td list for ed */
td = td_alloc (usb_dev);
ed->hwTailP = m32_swap (td);
ed->hwHeadP = ed->hwTailP;
void *data;
int cnt = 0;
__u32 info = 0;
- unsigned int toggle = 0;
+ unsigned int toggle = 0;
/* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */
- if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
- toggle = TD_T_TOGGLE;
+ if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
+ toggle = TD_T_TOGGLE;
} else {
- toggle = TD_T_DATA0;
+ toggle = TD_T_DATA0;
usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);
}
urb->td_cnt = 0;
static void dl_transfer_length(td_t * td)
{
__u32 tdINFO, tdBE, tdCBP;
- urb_priv_t *lurb_priv = &urb_priv;
+ urb_priv_t *lurb_priv = &urb_priv;
tdINFO = m32_swap (td->hwINFO);
- tdBE = m32_swap (td->hwBE);
- tdCBP = m32_swap (td->hwCBP);
+ tdBE = m32_swap (td->hwBE);
+ tdCBP = m32_swap (td->hwCBP);
if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL &&
__u32 td_list_hc;
td_t *td_rev = NULL;
td_t *td_list = NULL;
- urb_priv_t *lurb_priv = NULL;
+ urb_priv_t *lurb_priv = NULL;
td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0;
ohci->hcca->done_head = 0;
/* td done list */
static int dl_done_list (ohci_t *ohci, td_t *td_list)
{
- td_t *td_list_next = NULL;
+ td_t *td_list_next = NULL;
ed_t *ed;
int cc = 0;
int stat = 0;
/* urb_t *urb; */
urb_priv_t *lurb_priv;
- __u32 tdINFO, edHeadP, edTailP;
+ __u32 tdINFO, edHeadP, edTailP;
- while (td_list) {
- td_list_next = td_list->next_dl_td;
+ while (td_list) {
+ td_list_next = td_list->next_dl_td;
- lurb_priv = &urb_priv;
- tdINFO = m32_swap (td_list->hwINFO);
+ lurb_priv = &urb_priv;
+ tdINFO = m32_swap (td_list->hwINFO);
- ed = td_list->ed;
+ ed = td_list->ed;
- dl_transfer_length(td_list);
+ dl_transfer_length(td_list);
- /* error code of transfer */
- cc = TD_CC_GET (tdINFO);
+ /* error code of transfer */
+ cc = TD_CC_GET (tdINFO);
if (cc != 0) {
dbg("ConditionCode %#x", cc);
stat = cc_to_error[cc];
}
- if (ed->state != ED_NEW) {
- edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0;
- edTailP = m32_swap (ed->hwTailP);
+ if (ed->state != ED_NEW) {
+ edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0;
+ edTailP = m32_swap (ed->hwTailP);
/* unlink eds if they are not busy */
- if ((edHeadP == edTailP) && (ed->state == ED_OPER))
- ep_unlink (ohci, ed);
- }
+ if ((edHeadP == edTailP) && (ed->state == ED_OPER))
+ ep_unlink (ohci, ed);
+ }
- td_list = td_list_next;
- }
+ td_list = td_list_next;
+ }
return stat;
}
0x00, /* __u16 idVendor; */
0x00,
0x00, /* __u16 idProduct; */
- 0x00,
+ 0x00,
0x00, /* __u16 bcdDevice; */
- 0x00,
+ 0x00,
0x00, /* __u8 iManufacturer; */
0x01, /* __u8 iProduct; */
0x00, /* __u8 iSerialNumber; */
0x01, /* __u8 bConfigurationValue; */
0x00, /* __u8 iConfiguration; */
0x40, /* __u8 bmAttributes;
- Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
+ Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
0x00, /* __u8 MaxPower; */
/* interface */
0x07, /* __u8 ep_bLength; */
0x05, /* __u8 ep_bDescriptorType; Endpoint */
0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
- 0x03, /* __u8 ep_bmAttributes; Interrupt */
- 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
- 0x00,
+ 0x03, /* __u8 ep_bmAttributes; Interrupt */
+ 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
+ 0x00,
0xff /* __u8 ep_bInterval; 255 ms */
};
int stat = 0;
__u32 datab[4];
__u8 *data_buf = (__u8 *)datab;
- __u16 bmRType_bReq;
+ __u16 bmRType_bReq;
__u16 wValue;
__u16 wIndex;
__u16 wLength;
len = min_t(int, len, leni);
if (data != data_buf)
memcpy (data, data_buf, len);
- dev->act_len = len;
+ dev->act_len = len;
dev->status = stat;
#ifdef DEBUG
wait_ms(10);
/* ohci_dump_status(&gohci); */
-
+
/* allow more time for a BULK device to react - some are slow */
#define BULK_TO 5000 /* timeout in milliseconds */
if (usb_pipetype (pipe) == PIPE_BULK)
}
dev->status = stat;
- dev->act_len = transfer_len;
+ dev->act_len = transfer_len;
#ifdef DEBUG
pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));
ohci->slot_name,
readl (&ohci->regs->control));
- /* Reset USB (needed by some controllers) */
+ /* Reset USB (needed by some controllers) */
writel (0, &ohci->regs->control);
/* HC Reset requires max 10 us delay */
static int hc_start (ohci_t * ohci)
{
- __u32 mask;
- unsigned int fminterval;
+ __u32 mask;
+ unsigned int fminterval;
ohci->disabled = 1;
writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */
- fminterval = 0x2edf;
+ fminterval = 0x2edf;
writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);
fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
writel (fminterval, &ohci->regs->fminterval);
writel (0x628, &ohci->regs->lsthresh);
- /* start controller operations */
- ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
+ /* start controller operations */
+ ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
ohci->disabled = 0;
- writel (ohci->hc_control, &ohci->regs->control);
+ writel (ohci->hc_control, &ohci->regs->control);
/* disable all interrupts */
mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
{
ohci_t *ohci = &gohci;
struct ohci_regs *regs = ohci->regs;
- int ints;
+ int ints;
int stat = -1;
if ((ohci->hcca->done_head != 0) && !(m32_swap (ohci->hcca->done_head) & 0x01)) {
S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
- /*
- * Set the 48 MHz UPLL clocking. Values are taken from
- * "PLL value selection guide", 6-23, s3c2400_UM.pdf.
- */
- clk_power->UPLLCON = ((40 << 12) + (1 << 4) + 2);
- gpio->MISCCR |= 0x8; /* 1 = use pads related USB for USB host */
+ /*
+ * Set the 48 MHz UPLL clocking. Values are taken from
+ * "PLL value selection guide", 6-23, s3c2400_UM.pdf.
+ */
+ clk_power->UPLLCON = ((40 << 12) + (1 << 4) + 2);
+ gpio->MISCCR |= 0x8; /* 1 = use pads related USB for USB host */
- /*
- * Enable USB host clock.
- */
- clk_power->CLKCON |= (1 << 4);
+ /*
+ * Enable USB host clock.
+ */
+ clk_power->CLKCON |= (1 << 4);
memset (&gohci, 0, sizeof (ohci_t));
memset (&urb_priv, 0, sizeof (urb_priv_t));
}
ptd = gtd;
gohci.hcca = phcca;
- memset (phcca, 0, sizeof (struct ohci_hcca));
+ memset (phcca, 0, sizeof (struct ohci_hcca));
gohci.disabled = 1;
gohci.sleeping = 0;
if (hc_reset (&gohci) < 0) {
hc_release_ohci (&gohci);
- /* Initialization failed */
- clk_power->CLKCON &= ~(1 << 4);
+ /* Initialization failed */
+ clk_power->CLKCON &= ~(1 << 4);
return -1;
}
if (hc_start (&gohci) < 0) {
err ("can't start usb-%s", gohci.slot_name);
hc_release_ohci (&gohci);
- /* Initialization failed */
- clk_power->CLKCON &= ~(1 << 4);
+ /* Initialization failed */
+ clk_power->CLKCON &= ~(1 << 4);
return -1;
}
#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */
-
/* Virtual Root HUB */
struct virt_root_hub {
int devnum; /* Address of Root Hub endpoint */
#endif
-
void bad_mode (void)
{
panic ("Resetting CPU ...\n");
*/
-
#include <config.h>
#include <version.h>
msr cpsr,r0
- /*
+ /*
* turn off the watchdog, unlock/diable sequence
*/
mov r1, #0xF5
strh r1, [r0]
-
-
-
/*
* mask all IRQs by setting all bits in the INTMR - default
*/
.globl reset_cpu
reset_cpu:
ldr r1, rstctl1 /* get clkm1 reset ctl */
- mov r3, #0x0
+ mov r3, #0x0
strh r3, [r1] /* clear it */
mov r3, #0x8
strh r3, [r1] /* force dsp+arm reset */
#endif
-
void bad_mode (void)
{
panic ("Resetting CPU ...\n");
#include <version.h>
#include <asm/arch/ixp425.h>
-#define MMU_Control_M 0x001 // Enable MMU
-#define MMU_Control_A 0x002 // Enable address alignment faults
-#define MMU_Control_C 0x004 // Enable cache
-#define MMU_Control_W 0x008 // Enable write-buffer
-#define MMU_Control_P 0x010 // Compatability: 32 bit code
-#define MMU_Control_D 0x020 // Compatability: 32 bit data
-#define MMU_Control_L 0x040 // Compatability:
-#define MMU_Control_B 0x080 // Enable Big-Endian
-#define MMU_Control_S 0x100 // Enable system protection
-#define MMU_Control_R 0x200 // Enable ROM protection
-#define MMU_Control_I 0x1000 // Enable Instruction cache
-#define MMU_Control_X 0x2000 // Set interrupt vectors at 0xFFFF0000
+#define MMU_Control_M 0x001 /* Enable MMU */
+#define MMU_Control_A 0x002 /* Enable address alignment faults */
+#define MMU_Control_C 0x004 /* Enable cache */
+#define MMU_Control_W 0x008 /* Enable write-buffer */
+#define MMU_Control_P 0x010 /* Compatability: 32 bit code */
+#define MMU_Control_D 0x020 /* Compatability: 32 bit data */
+#define MMU_Control_L 0x040 /* Compatability: */
+#define MMU_Control_B 0x080 /* Enable Big-Endian */
+#define MMU_Control_S 0x100 /* Enable system protection */
+#define MMU_Control_R 0x200 /* Enable ROM protection */
+#define MMU_Control_I 0x1000 /* Enable Instruction cache */
+#define MMU_Control_X 0x2000 /* Set interrupt vectors at 0xFFFF0000 */
#define MMU_Control_Init (MMU_Control_P|MMU_Control_D|MMU_Control_L)
/*
* Macro definitions
*/
- // Delay a bit
- .macro DELAY_FOR cycles, reg0
- ldr \reg0, =\cycles
- subs \reg0, \reg0, #1
- subne pc, pc, #0xc
- .endm
-
- // wait for coprocessor write complete
- .macro CPWAIT reg
- mrc p15,0,\reg,c2,c0,0
- mov \reg,\reg
- sub pc,pc,#4
- .endm
+ /* Delay a bit */
+ .macro DELAY_FOR cycles, reg0
+ ldr \reg0, =\cycles
+ subs \reg0, \reg0, #1
+ subne pc, pc, #0xc
+ .endm
+
+ /* wait for coprocessor write complete */
+ .macro CPWAIT reg
+ mrc p15,0,\reg,c2,c0,0
+ mov \reg,\reg
+ sub pc,pc,#4
+ .endm
.globl _start
_start: b reset
/* disable mmu, set big-endian */
mov r0, #0xf8
mcr p15, 0, r0, c1, c0, 0
- CPWAIT r0
+ CPWAIT r0
/* invalidate I & D caches & BTB */
mcr p15, 0, r0, c7, c7, 0
CPWAIT r0
/* invalidate I & Data TLB */
- mcr p15, 0, r0, c8, c7, 0
- CPWAIT r0
+ mcr p15, 0, r0, c8, c7, 0
+ CPWAIT r0
/* drain write and fill buffers */
mcr p15, 0, r0, c7, c10, 4
ldr r2, =IXP425_EXP_CS0
str r1, [r2]
- /* make sure flash is visible at 0 */
+ /* make sure flash is visible at 0 */
ldr r2, =IXP425_EXP_CFG0
ldr r1, [r2]
orr r1, r1, #0x80000000
mov r1, #3
ldr r4, =IXP425_SDR_IR
str r1, [r4]
- DELAY_FOR 0x4000, r0
+ DELAY_FOR 0x4000, r0
/* set SDRAM internal refresh val */
ldr r1, =CFG_SDRAM_REFRESH_CNT
DELAY_FOR 0x4000, r0
/* copy */
- mov r0, #0
- mov r4, r0
- add r2, r0, #0x40000
+ mov r0, #0
+ mov r4, r0
+ add r2, r0, #0x40000
mov r1, #0x10000000
- mov r5, r1
+ mov r5, r1
30:
- ldr r3, [r0], #4
- str r3, [r1], #4
- cmp r0, r2
- bne 30b
+ ldr r3, [r0], #4
+ str r3, [r1], #4
+ cmp r0, r2
+ bne 30b
/* invalidate I & D caches & BTB */
mcr p15, 0, r0, c7, c7, 0
CPWAIT r0
/* invalidate I & Data TLB */
- mcr p15, 0, r0, c8, c7, 0
- CPWAIT r0
+ mcr p15, 0, r0, c8, c7, 0
+ CPWAIT r0
/* drain write and fill buffers */
mcr p15, 0, r0, c7, c10, 4
CPWAIT r0
- /* move flash to 0x50000000 */
+ /* move flash to 0x50000000 */
ldr r2, =IXP425_EXP_CFG0
ldr r1, [r2]
bic r1, r1, #0x80000000
nop
/* invalidate I & Data TLB */
- mcr p15, 0, r0, c8, c7, 0
- CPWAIT r0
+ mcr p15, 0, r0, c8, c7, 0
+ CPWAIT r0
- /* enable I cache */
- mrc p15, 0, r0, c1, c0, 0
- orr r0, r0, #MMU_Control_I
- mcr p15, 0, r0, c1, c0, 0
- CPWAIT r0
+ /* enable I cache */
+ mrc p15, 0, r0, c1, c0, 0
+ orr r0, r0, #MMU_Control_I
+ mcr p15, 0, r0, c1, c0, 0
+ CPWAIT r0
mrs r0,cpsr /* set the cpu to SVC32 mode */
bic r0,r0,#0x1f /* (superviser mode, M=10011) */
_start_armboot: .word start_armboot
-
-
/****************************************************************************/
/* */
/* Interrupt handling */
/*
* Try to set the mac address now. The fec mac address is
- * a garbage after reset. When not using fec for booting
+ * a garbage after reset. When not using fec for booting
* the Linux fec driver will try to work with this garbage.
*/
tmp = getenv("ethaddr");
mpc_reg_out(®s->mcr, I2C_TX, I2C_TX);
mpc_reg_out(®s->mdr, chip, 0);
- if (wait_for_pin(&status)) {
- return -2;
- }
+ if (wait_for_pin(&status)) {
+ return -2;
+ }
- if (status & I2C_RXAK) {
- return -3;
- }
+ if (status & I2C_RXAK) {
+ return -3;
+ }
return 0;
}
ipb = gd->ipb_clk;
for (i = 7; i >= 0; i--) {
for (j = 7; j >= 0; j--) {
- scl = 2 * (scltap[j].scl2tap +
+ scl = 2 * (scltap[j].scl2tap +
(SCL_Tap[i] - 1) * scltap[j].tap2tap + 2);
if (ipb <= speed*scl) {
if ((speed*scl - ipb) < bestmatch) {
xaddr[2] = (addr >> 8) & 0xFF;
xaddr[3] = addr & 0xFF;
- if (wait_for_bb()) {
+ if (wait_for_bb()) {
printf("i2c_write: bus is busy\n");
goto Done;
}
- mpc_reg_out(®s->mcr, I2C_STA, I2C_STA);
- if (do_address(chip, 0)) {
+ mpc_reg_out(®s->mcr, I2C_STA, I2C_STA);
+ if (do_address(chip, 0)) {
printf("i2c_write: failed to address chip\n");
goto Done;
}
/* GPIO Multiplexing - enable PCI */
*(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~(1 << 15);
-
+
/* Set host bridge as pci master and enable memory decoding */
*(vu_long *)MPC5XXX_PCI_CMD |=
PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
-
+
/* Set maximum latency timer */
*(vu_long *)MPC5XXX_PCI_CFG |= (0xf800);
/* Set cache line size */
*(vu_long *)MPC5XXX_PCI_CFG = (*(vu_long *)MPC5XXX_PCI_CFG & ~0xff) |
(CFG_CACHELINE_SIZE / 4);
-
+
/* Map MBAR to PCI space */
*(vu_long *)MPC5XXX_PCI_BAR0 = CFG_MBAR;
*(vu_long *)MPC5XXX_PCI_TBATR1 = CFG_MBAR | 1;
-
+
/* Map RAM to PCI space */
*(vu_long *)MPC5XXX_PCI_BAR1 = CONFIG_PCI_MEMORY_BUS | (1 << 3);
*(vu_long *)MPC5XXX_PCI_TBATR1 = CONFIG_PCI_MEMORY_PHYS | 1;
/* Enable piplining */
*(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~(1 << 31);
#endif
-
+
/* Disable interrupts from PCI controller */
*(vu_long *)MPC5XXX_PCI_GSCR &= ~(7 << 12);
*(vu_long *)MPC5XXX_PCI_ICR &= ~(7 << 24);
-
+
/* Disable initiator windows */
*(vu_long *)MPC5XXX_PCI_IWCR = 0;
-
+
/* Map PCI memory to physical space */
*(vu_long *)MPC5XXX_PCI_IW0BTAR = CONFIG_PCI_MEM_PHYS |
(((CONFIG_PCI_MEM_SIZE - 1) >> 8) & 0x00ff0000) |
pci_hose_write_config_byte_via_dword,
pci_hose_write_config_word_via_dword,
mpc5200_write_config_dword);
-
+
udelay(1000);
#ifdef CONFIG_PCI_SCAN_SHOW
/* 28.9 - (3): connect FCC's tx and rx clocks */
immr->im_cpmux.cmx_uar = 0;
immr->im_cpmux.cmx_fcr = (immr->im_cpmux.cmx_fcr & ~info->cmxfcr_mask) |
- info->cmxfcr_value;
+ info->cmxfcr_value;
/* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, Mode Ethernet */
immr->im_fcc[info->ether_index].fcc_gfmr =
memset(dev, 0, sizeof *dev);
sprintf(dev->name, "FCC%d ETHERNET",
- ether_fcc_info[i].ether_index + 1);
+ ether_fcc_info[i].ether_index + 1);
dev->priv = ðer_fcc_info[i];
dev->init = fec_init;
dev->halt = fec_halt;
#if defined(CONFIG_HYMOD)
/*
* Attention: this is board-specific
- * 0, FCC1
- * 1, FCC2
- * 2, FCC3
- */
+ * 0, FCC1
+ * 1, FCC2
+ * 2, FCC3
+ */
# define FCC_START_LOOP 0
# define FCC_END_LOOP 2
#elif defined(CONFIG_SBC8260) || defined(CONFIG_SACSng)
/*
* Attention: this is board-specific
- * 1, FCC2
- */
+ * 1, FCC2
+ */
# define FCC_START_LOOP 1
# define FCC_END_LOOP 1
--- /dev/null
+#
+# (C) Copyright 2002,2003 Motorola Inc.
+# Xianghua Xiao,X.Xiao@motorola.com
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(CPU).a
+
+START = start.o resetvec.o
+COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o tsec.o \
+ pci.o serial_scc.o commproc.o ether_fcc.o i2c.o spd_sdram.o
+OBJS = $(COBJS)
+
+all: .depend $(START) $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) crv $@ $(OBJS)
+
+#########################################################################
+
+.depend: Makefile $(START:.o=.S) $(AOBJS:.o=.S) $(COBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(START:.o=.S) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+/*
+ * Adapted for Motorola MPC8560 chips
+ * Xianghua Xiao <x.xiao@motorola.com>
+ *
+ * This file is based on "arch/ppc/8260_io/commproc.c" - here is it's
+ * copyright notice:
+ *
+ * General Purpose functions for the global management of the
+ * 8220 Communication Processor Module.
+ * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
+ * Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com)
+ * 2.3.99 Updates
+ * Copyright (c) 2003 Motorola,Inc.
+ *
+ * In addition to the individual control of the communication
+ * channels, there are a few functions that globally affect the
+ * communication processor.
+ *
+ * Buffer descriptors must be allocated from the dual ported memory
+ * space. The allocator for that is here. When the communication
+ * process is reset, we reclaim the memory available. There is
+ * currently no deallocator for this memory.
+ */
+#include <common.h>
+#include <asm/cpm_85xx.h>
+
+#if defined(CONFIG_MPC8560)
+/*
+ * because we have stack and init data in dual port ram
+ * we must reduce the size
+ */
+#undef CPM_DATAONLY_SIZE
+#define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE)
+
+void
+m8560_cpm_reset(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile ulong count;
+
+ gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
+
+ /* Reclaim the DP memory for our use.
+ */
+ gd->dp_alloc_base = CPM_DATAONLY_BASE;
+ gd->dp_alloc_top = gd->dp_alloc_base + CPM_DATAONLY_SIZE;
+
+ /*
+ * Reset CPM
+ */
+ immr->im_cpm.im_cpm_cp.cpcr = CPM_CR_RST;
+ count = 0;
+ do { /* Spin until command processed */
+ __asm__ __volatile__ ("eieio");
+ } while ((immr->im_cpm.im_cpm_cp.cpcr & CPM_CR_FLG) && ++count < 1000000);
+}
+
+/* Allocate some memory from the dual ported ram.
+ * To help protocols with object alignment restrictions, we do that
+ * if they ask.
+ */
+uint
+m8560_cpm_dpalloc(uint size, uint align)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ uint retloc;
+ uint align_mask, off;
+ uint savebase;
+
+ align_mask = align - 1;
+ savebase = gd->dp_alloc_base;
+
+ if ((off = (gd->dp_alloc_base & align_mask)) != 0)
+ gd->dp_alloc_base += (align - off);
+
+ if ((off = size & align_mask) != 0)
+ size += align - off;
+
+ if ((gd->dp_alloc_base + size) >= gd->dp_alloc_top) {
+ gd->dp_alloc_base = savebase;
+ panic("m8560_cpm_dpalloc: ran out of dual port ram!");
+ }
+
+ retloc = gd->dp_alloc_base;
+ gd->dp_alloc_base += size;
+
+ memset((void *)&(immr->im_cpm.im_dprambase[retloc]), 0, size);
+
+ return(retloc);
+}
+
+/* We also own one page of host buffer space for the allocation of
+ * UART "fifos" and the like.
+ */
+uint
+m8560_cpm_hostalloc(uint size, uint align)
+{
+ /* the host might not even have RAM yet - just use dual port RAM */
+ return (m8560_cpm_dpalloc(size, align));
+}
+
+/* Set a baud rate generator. This needs lots of work. There are
+ * eight BRGs, which can be connected to the CPM channels or output
+ * as clocks. The BRGs are in two different block of internal
+ * memory mapped space.
+ * The baud rate clock is the system clock divided by something.
+ * It was set up long ago during the initial boot phase and is
+ * is given to us.
+ * Baud rate clocks are zero-based in the driver code (as that maps
+ * to port numbers). Documentation uses 1-based numbering.
+ */
+#define BRG_INT_CLK gd->brg_clk
+#define BRG_UART_CLK ((BRG_INT_CLK + 15) / 16)
+
+/* This function is used by UARTS, or anything else that uses a 16x
+ * oversampled clock.
+ */
+void
+m8560_cpm_setbrg(uint brg, uint rate)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile uint *bp;
+
+ /* This is good enough to get SMCs running.....
+ */
+ if (brg < 4) {
+ bp = (uint *)&(immr->im_cpm.im_cpm_brg1.brgc1);
+ }
+ else {
+ bp = (uint *)&(immr->im_cpm.im_cpm_brg2.brgc5);
+ brg -= 4;
+ }
+ bp += brg;
+ *bp = (((((BRG_UART_CLK+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN;
+}
+
+/* This function is used to set high speed synchronous baud rate
+ * clocks.
+ */
+void
+m8560_cpm_fastbrg(uint brg, uint rate, int div16)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile uint *bp;
+
+ /* This is good enough to get SMCs running.....
+ */
+ if (brg < 4) {
+ bp = (uint *)&(immr->im_cpm.im_cpm_brg1.brgc1);
+ }
+ else {
+ bp = (uint *)&(immr->im_cpm.im_cpm_brg2.brgc5);
+ brg -= 4;
+ }
+ bp += brg;
+ *bp = (((((BRG_INT_CLK+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN;
+ if (div16)
+ *bp |= CPM_BRG_DIV16;
+}
+
+/* This function is used to set baud rate generators using an external
+ * clock source and 16x oversampling.
+ */
+
+void
+m8560_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel)
+{
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile uint *bp;
+
+ if (brg < 4) {
+ bp = (uint *)&(immr->im_cpm.im_cpm_brg1.brgc1);
+ }
+ else {
+ bp = (uint *)&(immr->im_cpm.im_cpm_brg2.brgc5);
+ brg -= 4;
+ }
+ bp += brg;
+ *bp = ((((((extclk/16)+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN;
+ if (pinsel == 0)
+ *bp |= CPM_BRG_EXTC_CLK3_9;
+ else
+ *bp |= CPM_BRG_EXTC_CLK5_15;
+}
+
+#ifdef CONFIG_POST
+
+void post_word_store (ulong a)
+{
+ volatile ulong *save_addr =
+ (volatile ulong *)(CFG_IMMR + CPM_POST_WORD_ADDR);
+
+ *save_addr = a;
+}
+
+ulong post_word_load (void)
+{
+ volatile ulong *save_addr =
+ (volatile ulong *)(CFG_IMMR + CPM_POST_WORD_ADDR);
+
+ return *save_addr;
+}
+
+#endif /* CONFIG_POST */
+
+#endif /* CONFIG_MPC8560 */
--- /dev/null
+#
+# (C) Copyright 2002,2003 Motorola Inc.
+# Xianghua Xiao, X.Xiao@motorola.com
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_RELFLAGS += -mrelocatable -ffixed-r14 -meabi
+
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx -DCONFIG_E500 -ffixed-r2 -ffixed-r29 -Wa,-me500 -msoft-float
--- /dev/null
+/*
+ * (C) Copyright 2002, 2003 Motorola Inc.
+ * Xianghua Xiao (X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <command.h>
+#include <asm/cache.h>
+
+/* ------------------------------------------------------------------------- */
+
+int checkcpu (void)
+{
+ uint pir = get_pir();
+ uint pvr = get_pvr();
+
+ printf("Motorola PowerPC ProcessorID=%08x Rev. ",pir);
+ switch(pvr) {
+ default:
+ printf("PVR=%08x", pvr);
+ break;
+ }
+
+ printf("\n");
+
+ return 0;
+}
+
+
+/* ------------------------------------------------------------------------- */
+
+int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+{
+ /*
+ * Initiate hard reset in debug control register DBCR0
+ * Make sure MSR[DE] = 1
+ */
+ __asm__ __volatile__("lis 3, 0x7000" ::: "r3");
+ mtspr(DBCR0,3);
+ return 1;
+}
+
+
+/*
+ * Get timebase clock frequency
+ */
+unsigned long get_tbclk (void)
+{
+
+ sys_info_t sys_info;
+
+ get_sys_info(&sys_info);
+ return ((sys_info.freqSystemBus + 3L) / 4L);
+}
+
+
+#if defined(CONFIG_WATCHDOG)
+void
+watchdog_reset(void)
+{
+ int re_enable = disable_interrupts();
+ reset_85xx_watchdog();
+ if (re_enable) enable_interrupts();
+}
+
+void
+reset_85xx_watchdog(void)
+{
+ /*
+ * Clear TSR(WIS) bit by writing 1
+ */
+ unsigned long val;
+ val = mfspr(tsr);
+ val |= 0x40000000;
+ mtspr(tsr, val);
+}
+#endif /* CONFIG_WATCHDOG */
+
+#if defined(CONFIG_DDR_ECC)
+__inline__ void dcbz(const void* addr)
+{
+ __asm__ __volatile__ ("dcbz 0,%0" :: "r" (addr));
+}
+
+__inline__ void dcbf(const void* addr)
+{
+ __asm__ __volatile__ ("dcbf 0,%0" :: "r" (addr));
+}
+
+void dma_init(void) {
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile ccsr_dma_t *dma = &immap->im_dma;
+
+ dma->satr0 = 0x02c40000;
+ dma->datr0 = 0x02c40000;
+ asm("sync; isync; msync");
+ return;
+}
+
+uint dma_check(void) {
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile ccsr_dma_t *dma = &immap->im_dma;
+ volatile uint status = dma->sr0;
+
+ /* While the channel is busy, spin */
+ while((status & 4) == 4) {
+ status = dma->sr0;
+ }
+
+ if (status != 0) {
+ printf ("DMA Error: status = %x\n", status);
+ }
+ return status;
+}
+
+int dma_xfer(void *dest, uint count, void *src) {
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile ccsr_dma_t *dma = &immap->im_dma;
+
+ dma->dar0 = (uint) dest;
+ dma->sar0 = (uint) src;
+ dma->bcr0 = count;
+ dma->mr0 = 0xf000004;
+ asm("sync;isync;msync");
+ dma->mr0 = 0xf000005;
+ asm("sync;isync;msync");
+ return dma_check();
+}
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2003 Motorola Inc.
+ * Modified by Xianghua Xiao, X.Xiao@motorola.com
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <asm/processor.h>
+#include <ioports.h>
+#include <asm/io.h>
+
+#ifdef CONFIG_MPC8560
+static void config_8560_ioports (volatile immap_t * immr)
+{
+ int portnum;
+
+ for (portnum = 0; portnum < 4; portnum++) {
+ uint pmsk = 0,
+ ppar = 0,
+ psor = 0,
+ pdir = 0,
+ podr = 0,
+ pdat = 0;
+ iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
+ iop_conf_t *eiopc = iopc + 32;
+ uint msk = 1;
+
+ /*
+ * NOTE:
+ * index 0 refers to pin 31,
+ * index 31 refers to pin 0
+ */
+ while (iopc < eiopc) {
+ if (iopc->conf) {
+ pmsk |= msk;
+ if (iopc->ppar)
+ ppar |= msk;
+ if (iopc->psor)
+ psor |= msk;
+ if (iopc->pdir)
+ pdir |= msk;
+ if (iopc->podr)
+ podr |= msk;
+ if (iopc->pdat)
+ pdat |= msk;
+ }
+
+ msk <<= 1;
+ iopc++;
+ }
+
+ if (pmsk != 0) {
+ volatile ioport_t *iop = ioport_addr (immr, portnum);
+ uint tpmsk = ~pmsk;
+
+ /*
+ * the (somewhat confused) paragraph at the
+ * bottom of page 35-5 warns that there might
+ * be "unknown behaviour" when programming
+ * PSORx and PDIRx, if PPARx = 1, so I
+ * decided this meant I had to disable the
+ * dedicated function first, and enable it
+ * last.
+ */
+ iop->ppar &= tpmsk;
+ iop->psor = (iop->psor & tpmsk) | psor;
+ iop->podr = (iop->podr & tpmsk) | podr;
+ iop->pdat = (iop->pdat & tpmsk) | pdat;
+ iop->pdir = (iop->pdir & tpmsk) | pdir;
+ iop->ppar |= ppar;
+ }
+ }
+}
+#endif
+
+/*
+ * Breathe some life into the CPU...
+ *
+ * Set up the memory map
+ * initialize a bunch of registers
+ */
+
+void cpu_init_f (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile ccsr_lbc_t *memctl = &immap->im_lbc;
+ extern void m8560_cpm_reset (void);
+
+ /* Pointer is writable since we allocated a register for it */
+ gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
+
+ /* Clear initial global data */
+ memset ((void *) gd, 0, sizeof (gd_t));
+
+
+#ifdef CONFIG_MPC8560
+ config_8560_ioports(immap);
+#endif
+
+ /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
+ * addresses - these have to be modified later when FLASH size
+ * has been determined
+ */
+#if defined(CFG_OR0_REMAP)
+ memctl->or0 = CFG_OR0_REMAP;
+#endif
+#if defined(CFG_OR1_REMAP)
+ memctl->or1 = CFG_OR1_REMAP;
+#endif
+
+ /* now restrict to preliminary range */
+#if defined(CFG_BR0_PRELIM) && defined(CFG_OR0_PRELIM)
+ memctl->br0 = CFG_BR0_PRELIM;
+ memctl->or0 = CFG_OR0_PRELIM;
+#endif
+
+#if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM)
+ memctl->or1 = CFG_OR1_PRELIM;
+ memctl->br1 = CFG_BR1_PRELIM;
+#endif
+
+#if !defined(CONFIG_MPC85xx)
+#if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM)
+ memctl->or2 = CFG_OR2_PRELIM;
+ memctl->br2 = CFG_BR2_PRELIM;
+#endif
+#endif
+
+#if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM)
+ memctl->or3 = CFG_OR3_PRELIM;
+ memctl->br3 = CFG_BR3_PRELIM;
+#endif
+
+#if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM)
+ memctl->or4 = CFG_OR4_PRELIM;
+ memctl->br4 = CFG_BR4_PRELIM;
+#endif
+
+#if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM)
+ memctl->or5 = CFG_OR5_PRELIM;
+ memctl->br5 = CFG_BR5_PRELIM;
+#endif
+
+#if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM)
+ memctl->or6 = CFG_OR6_PRELIM;
+ memctl->br6 = CFG_BR6_PRELIM;
+#endif
+
+#if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM)
+ memctl->or7 = CFG_OR7_PRELIM;
+ memctl->br7 = CFG_BR7_PRELIM;
+#endif
+
+#if defined(CONFIG_MPC8560)
+ m8560_cpm_reset();
+#endif
+}
+
+/*
+ * We initialize L2 as cache here.
+ */
+int cpu_init_r (void)
+{
+#if defined(CONFIG_L2_CACHE)
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile ccsr_l2cache_t *l2cache = &immap->im_l2cache;
+ volatile uint temp;
+
+ asm("msync;isync");
+ l2cache->l2ctl = 0x68000000; /* invalidate */
+ temp = l2cache->l2ctl;
+ asm("msync;isync");
+ l2cache->l2ctl = 0xa8000000; /* enable 256KB L2 cache */
+ temp = l2cache->l2ctl;
+ asm("msync;isync");
+
+ printf("L2 cache enabled: 256KB\n");
+#else
+ printf("L2 cache disabled.\n");
+#endif
+
+ return 0;
+}
--- /dev/null
+/*
+ * MPC8560 FCC Fast Ethernet
+ * Copyright (c) 2003 Motorola,Inc.
+ * Xianghua Xiao, (X.Xiao@motorola.com)
+ *
+ * Copyright (c) 2000 MontaVista Software, Inc. Dan Malek (dmalek@jlc.net)
+ *
+ * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * MPC8560 FCC Fast Ethernet
+ * Basic ET HW initialization and packet RX/TX routines
+ *
+ * This code will not perform the IO port configuration. This should be
+ * done in the iop_conf_t structure specific for the board.
+ *
+ * TODO:
+ * add a PHY driver to do the negotiation
+ * reflect negotiation results in FPSMR
+ * look for ways to configure the board specific stuff elsewhere, eg.
+ * config_xxx.h or the board directory
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/cpm_85xx.h>
+#include <command.h>
+#include <config.h>
+#include <net.h>
+
+#if defined(CONFIG_MPC8560)
+
+#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_COMMANDS & CFG_CMD_NET) && \
+ defined(CONFIG_NET_MULTI)
+
+static struct ether_fcc_info_s
+{
+ int ether_index;
+ int proff_enet;
+ ulong cpm_cr_enet_sblock;
+ ulong cpm_cr_enet_page;
+ ulong cmxfcr_mask;
+ ulong cmxfcr_value;
+}
+ ether_fcc_info[] =
+{
+#ifdef CONFIG_ETHER_ON_FCC1
+{
+ 0,
+ PROFF_FCC1,
+ CPM_CR_FCC1_SBLOCK,
+ CPM_CR_FCC1_PAGE,
+ CFG_CMXFCR_MASK1,
+ CFG_CMXFCR_VALUE1
+},
+#endif
+
+#ifdef CONFIG_ETHER_ON_FCC2
+{
+ 1,
+ PROFF_FCC2,
+ CPM_CR_FCC2_SBLOCK,
+ CPM_CR_FCC2_PAGE,
+ CFG_CMXFCR_MASK2,
+ CFG_CMXFCR_VALUE2
+},
+#endif
+
+#ifdef CONFIG_ETHER_ON_FCC3
+{
+ 2,
+ PROFF_FCC3,
+ CPM_CR_FCC3_SBLOCK,
+ CPM_CR_FCC3_PAGE,
+ CFG_CMXFCR_MASK3,
+ CFG_CMXFCR_VALUE3
+},
+#endif
+};
+
+/*---------------------------------------------------------------------*/
+
+/* Maximum input DMA size. Must be a should(?) be a multiple of 4. */
+#define PKT_MAXDMA_SIZE 1520
+
+/* The FCC stores dest/src/type, data, and checksum for receive packets. */
+#define PKT_MAXBUF_SIZE 1518
+#define PKT_MINBUF_SIZE 64
+
+/* Maximum input buffer size. Must be a multiple of 32. */
+#define PKT_MAXBLR_SIZE 1536
+
+#define TOUT_LOOP 1000000
+
+#define TX_BUF_CNT 2
+
+static uint rxIdx; /* index of the current RX buffer */
+static uint txIdx; /* index of the current TX buffer */
+
+/*
+ * FCC Ethernet Tx and Rx buffer descriptors.
+ * Provide for Double Buffering
+ * Note: PKTBUFSRX is defined in net.h
+ */
+
+typedef volatile struct rtxbd {
+ cbd_t rxbd[PKTBUFSRX];
+ cbd_t txbd[TX_BUF_CNT];
+} RTXBD;
+
+/* Good news: the FCC supports external BDs! */
+#ifdef __GNUC__
+static RTXBD rtx __attribute__ ((aligned(8)));
+#else
+#error "rtx must be 64-bit aligned"
+#endif
+
+#define ET_DEBUG
+
+static int fec_send(struct eth_device* dev, volatile void *packet, int length)
+{
+ int i = 0;
+ int result = 0;
+
+ if (length <= 0) {
+ printf("fec: bad packet size: %d\n", length);
+ goto out;
+ }
+
+ for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
+ if (i >= TOUT_LOOP) {
+ printf("fec: tx buffer not ready\n");
+ goto out;
+ }
+ }
+
+ rtx.txbd[txIdx].cbd_bufaddr = (uint)packet;
+ rtx.txbd[txIdx].cbd_datlen = length;
+ rtx.txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST | \
+ BD_ENET_TX_TC );
+
+ for(i=0; rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
+ if (i >= TOUT_LOOP) {
+ printf("fec: tx error\n");
+ goto out;
+ }
+ }
+
+#ifdef ET_DEBUG
+ printf("cycles: 0x%x txIdx=0x%04x status: 0x%04x\n", i, txIdx,rtx.txbd[txIdx].cbd_sc);
+ printf("packets at 0x%08x, length_in_bytes=0x%x\n",(uint)packet,length);
+ for(i=0;i<(length/16 + 1);i++) {
+ printf("%08x %08x %08x %08x\n",*((uint *)rtx.txbd[txIdx].cbd_bufaddr+i*4),\
+ *((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 1),*((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 2), \
+ *((uint *)rtx.txbd[txIdx].cbd_bufaddr + i*4 + 3));
+ }
+#endif
+
+ /* return only status bits */
+ result = rtx.txbd[txIdx].cbd_sc & BD_ENET_TX_STATS;
+ txIdx = (txIdx + 1) % TX_BUF_CNT;
+
+out:
+ return result;
+}
+
+static int fec_recv(struct eth_device* dev)
+{
+ int length;
+
+ for (;;)
+ {
+ if (rtx.rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
+ length = -1;
+ break; /* nothing received - leave for() loop */
+ }
+ length = rtx.rxbd[rxIdx].cbd_datlen;
+
+ if (rtx.rxbd[rxIdx].cbd_sc & 0x003f) {
+ printf("fec: rx error %04x\n", rtx.rxbd[rxIdx].cbd_sc);
+ }
+ else {
+ /* Pass the packet up to the protocol layers. */
+ NetReceive(NetRxPackets[rxIdx], length - 4);
+ }
+
+
+ /* Give the buffer back to the FCC. */
+ rtx.rxbd[rxIdx].cbd_datlen = 0;
+
+ /* wrap around buffer index when necessary */
+ if ((rxIdx + 1) >= PKTBUFSRX) {
+ rtx.rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
+ rxIdx = 0;
+ }
+ else {
+ rtx.rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
+ rxIdx++;
+ }
+ }
+ return length;
+}
+
+
+static int fec_init(struct eth_device* dev, bd_t *bis)
+{
+ struct ether_fcc_info_s * info = dev->priv;
+ int i;
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile ccsr_cpm_cp_t *cp = &(immr->im_cpm.im_cpm_cp);
+ fcc_enet_t *pram_ptr;
+ unsigned long mem_addr;
+
+#if 0
+ mii_discover_phy();
+#endif
+
+ /* 28.9 - (1-2): ioports have been set up already */
+
+ /* 28.9 - (3): connect FCC's tx and rx clocks */
+ immr->im_cpm.im_cpm_mux.cmxuar = 0; /* ATM */
+ immr->im_cpm.im_cpm_mux.cmxfcr = (immr->im_cpm.im_cpm_mux.cmxfcr & ~info->cmxfcr_mask) |
+ info->cmxfcr_value;
+
+ /* 28.9 - (4): GFMR: disable tx/rx, CCITT CRC, set Mode Ethernet */
+ if(info->ether_index == 0) {
+ immr->im_cpm.im_cpm_fcc1.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
+ } else if (info->ether_index == 1) {
+ immr->im_cpm.im_cpm_fcc2.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
+ } else if (info->ether_index == 2) {
+ immr->im_cpm.im_cpm_fcc3.gfmr = FCC_GFMR_MODE_ENET | FCC_GFMR_TCRC_32;
+ }
+
+ /* 28.9 - (5): FPSMR: enable full duplex, select CCITT CRC for Ethernet,MII */
+ if(info->ether_index == 0) {
+ immr->im_cpm.im_cpm_fcc1.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
+ } else if (info->ether_index == 1){
+ immr->im_cpm.im_cpm_fcc2.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
+ } else if (info->ether_index == 2){
+ immr->im_cpm.im_cpm_fcc3.fpsmr = CFG_FCC_PSMR | FCC_PSMR_ENCRC;
+ }
+
+ /* 28.9 - (6): FDSR: Ethernet Syn */
+ if(info->ether_index == 0) {
+ immr->im_cpm.im_cpm_fcc1.fdsr = 0xD555;
+ } else if (info->ether_index == 1) {
+ immr->im_cpm.im_cpm_fcc2.fdsr = 0xD555;
+ } else if (info->ether_index == 2) {
+ immr->im_cpm.im_cpm_fcc3.fdsr = 0xD555;
+ }
+
+ /* reset indeces to current rx/tx bd (see eth_send()/eth_rx()) */
+ rxIdx = 0;
+ txIdx = 0;
+
+ /* Setup Receiver Buffer Descriptors */
+ for (i = 0; i < PKTBUFSRX; i++)
+ {
+ rtx.rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
+ rtx.rxbd[i].cbd_datlen = 0;
+ rtx.rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i];
+ }
+ rtx.rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
+
+ /* Setup Ethernet Transmitter Buffer Descriptors */
+ for (i = 0; i < TX_BUF_CNT; i++)
+ {
+ rtx.txbd[i].cbd_sc = 0;
+ rtx.txbd[i].cbd_datlen = 0;
+ rtx.txbd[i].cbd_bufaddr = 0;
+ }
+ rtx.txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
+
+ /* 28.9 - (7): initialize parameter ram */
+ pram_ptr = (fcc_enet_t *)&(immr->im_cpm.im_dprambase[info->proff_enet]);
+
+ /* clear whole structure to make sure all reserved fields are zero */
+ memset((void*)pram_ptr, 0, sizeof(fcc_enet_t));
+
+ /*
+ * common Parameter RAM area
+ *
+ * Allocate space in the reserved FCC area of DPRAM for the
+ * internal buffers. No one uses this space (yet), so we
+ * can do this. Later, we will add resource management for
+ * this area. CPM_FCC_SPECIAL_BASE: 0xb000.
+ */
+ mem_addr = CPM_FCC_SPECIAL_BASE + ((info->ether_index) * 64);
+ pram_ptr->fen_genfcc.fcc_riptr = mem_addr;
+ pram_ptr->fen_genfcc.fcc_tiptr = mem_addr+32;
+ /*
+ * Set maximum bytes per receive buffer.
+ * It must be a multiple of 32.
+ */
+ pram_ptr->fen_genfcc.fcc_mrblr = PKT_MAXBLR_SIZE; /* 1536 */
+ /* localbus SDRAM should be preferred */
+ pram_ptr->fen_genfcc.fcc_rstate = (CPMFCR_GBL | CPMFCR_EB |
+ CFG_CPMFCR_RAMTYPE) << 24;
+ pram_ptr->fen_genfcc.fcc_rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
+ pram_ptr->fen_genfcc.fcc_rbdstat = 0;
+ pram_ptr->fen_genfcc.fcc_rbdlen = 0;
+ pram_ptr->fen_genfcc.fcc_rdptr = 0;
+ /* localbus SDRAM should be preferred */
+ pram_ptr->fen_genfcc.fcc_tstate = (CPMFCR_GBL | CPMFCR_EB |
+ CFG_CPMFCR_RAMTYPE) << 24;
+ pram_ptr->fen_genfcc.fcc_tbase = (unsigned int)(&rtx.txbd[txIdx]);
+ pram_ptr->fen_genfcc.fcc_tbdstat = 0;
+ pram_ptr->fen_genfcc.fcc_tbdlen = 0;
+ pram_ptr->fen_genfcc.fcc_tdptr = 0;
+
+ /* protocol-specific area */
+ pram_ptr->fen_statbuf = 0x0;
+ pram_ptr->fen_cmask = 0xdebb20e3; /* CRC mask */
+ pram_ptr->fen_cpres = 0xffffffff; /* CRC preset */
+ pram_ptr->fen_crcec = 0;
+ pram_ptr->fen_alec = 0;
+ pram_ptr->fen_disfc = 0;
+ pram_ptr->fen_retlim = 15; /* Retry limit threshold */
+ pram_ptr->fen_retcnt = 0;
+ pram_ptr->fen_pper = 0;
+ pram_ptr->fen_boffcnt = 0;
+ pram_ptr->fen_gaddrh = 0;
+ pram_ptr->fen_gaddrl = 0;
+ pram_ptr->fen_mflr = PKT_MAXBUF_SIZE; /* maximum frame length register */
+ /*
+ * Set Ethernet station address.
+ *
+ * This is supplied in the board information structure, so we
+ * copy that into the controller.
+ * So far we have only been given one Ethernet address. We make
+ * it unique by setting a few bits in the upper byte of the
+ * non-static part of the address.
+ */
+#define ea eth_get_dev()->enetaddr
+ pram_ptr->fen_paddrh = (ea[5] << 8) + ea[4];
+ pram_ptr->fen_paddrm = (ea[3] << 8) + ea[2];
+ pram_ptr->fen_paddrl = (ea[1] << 8) + ea[0];
+#undef ea
+ pram_ptr->fen_ibdcount = 0;
+ pram_ptr->fen_ibdstart = 0;
+ pram_ptr->fen_ibdend = 0;
+ pram_ptr->fen_txlen = 0;
+ pram_ptr->fen_iaddrh = 0; /* disable hash */
+ pram_ptr->fen_iaddrl = 0;
+ pram_ptr->fen_minflr = PKT_MINBUF_SIZE; /* minimum frame length register: 64 */
+ /* pad pointer. use tiptr since we don't need a specific padding char */
+ pram_ptr->fen_padptr = pram_ptr->fen_genfcc.fcc_tiptr;
+ pram_ptr->fen_maxd1 = PKT_MAXDMA_SIZE; /* maximum DMA1 length:1520 */
+ pram_ptr->fen_maxd2 = PKT_MAXDMA_SIZE; /* maximum DMA2 length:1520 */
+
+#if defined(ET_DEBUG)
+ printf("parm_ptr(0xff788500) = %p\n",pram_ptr);
+ printf("pram_ptr->fen_genfcc.fcc_rbase %08x\n",
+ pram_ptr->fen_genfcc.fcc_rbase);
+ printf("pram_ptr->fen_genfcc.fcc_tbase %08x\n",
+ pram_ptr->fen_genfcc.fcc_tbase);
+#endif
+
+ /* 28.9 - (8)(9): clear out events in FCCE */
+ /* 28.9 - (9): FCCM: mask all events */
+ if(info->ether_index == 0) {
+ immr->im_cpm.im_cpm_fcc1.fcce = ~0x0;
+ immr->im_cpm.im_cpm_fcc1.fccm = 0;
+ } else if (info->ether_index == 1) {
+ immr->im_cpm.im_cpm_fcc2.fcce = ~0x0;
+ immr->im_cpm.im_cpm_fcc2.fccm = 0;
+ } else if (info->ether_index == 2) {
+ immr->im_cpm.im_cpm_fcc3.fcce = ~0x0;
+ immr->im_cpm.im_cpm_fcc3.fccm = 0;
+ }
+
+ /* 28.9 - (10-12): we don't use ethernet interrupts */
+
+ /* 28.9 - (13)
+ *
+ * Let's re-initialize the channel now. We have to do it later
+ * than the manual describes because we have just now finished
+ * the BD initialization.
+ */
+ cp->cpcr = mk_cr_cmd(info->cpm_cr_enet_page,
+ info->cpm_cr_enet_sblock,
+ 0x0c,
+ CPM_CR_INIT_TRX) | CPM_CR_FLG;
+ do {
+ __asm__ __volatile__ ("eieio");
+ } while (cp->cpcr & CPM_CR_FLG);
+
+ /* 28.9 - (14): enable tx/rx in gfmr */
+ if(info->ether_index == 0) {
+ immr->im_cpm.im_cpm_fcc1.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
+ } else if (info->ether_index == 1) {
+ immr->im_cpm.im_cpm_fcc2.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
+ } else if (info->ether_index == 2) {
+ immr->im_cpm.im_cpm_fcc3.gfmr |= FCC_GFMR_ENT | FCC_GFMR_ENR;
+ }
+
+ return 0;
+}
+
+static void fec_halt(struct eth_device* dev)
+{
+ struct ether_fcc_info_s * info = dev->priv;
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+
+ /* write GFMR: disable tx/rx */
+ if(info->ether_index == 0) {
+ immr->im_cpm.im_cpm_fcc1.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
+ } else if(info->ether_index == 1) {
+ immr->im_cpm.im_cpm_fcc2.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
+ } else if(info->ether_index == 2) {
+ immr->im_cpm.im_cpm_fcc3.gfmr &= ~(FCC_GFMR_ENT | FCC_GFMR_ENR);
+ }
+}
+
+int fec_initialize(bd_t *bis)
+{
+ struct eth_device* dev;
+ int i;
+
+ for (i = 0; i < sizeof(ether_fcc_info) / sizeof(ether_fcc_info[0]); i++)
+ {
+ dev = (struct eth_device*) malloc(sizeof *dev);
+ memset(dev, 0, sizeof *dev);
+
+ sprintf(dev->name, "FCC%d ETHERNET",
+ ether_fcc_info[i].ether_index + 1);
+ dev->priv = ðer_fcc_info[i];
+ dev->init = fec_init;
+ dev->halt = fec_halt;
+ dev->send = fec_send;
+ dev->recv = fec_recv;
+
+ eth_register(dev);
+ }
+
+ return 1;
+}
+
+#endif /* CONFIG_ETHER_ON_FCC && CFG_CMD_NET && CONFIG_NET_MULTI */
+
+#endif /* CONFIG_MPC8560 */
--- /dev/null
+/*
+ * (C) Copyright 2003,Motorola Inc.
+ * Xianghua Xiao <x.xiao@motorola.com>
+ * Adapted for Motorola 85xx chip.
+ *
+ * (C) Copyright 2003
+ * Gleb Natapov <gnatapov@mrv.com>
+ * Some bits are taken from linux driver writen by adrian@humboldt.co.uk
+ *
+ * Hardware I2C driver for MPC107 PCI bridge.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+
+#define DEBUG
+
+#if defined(DEBUG)
+#define DEB(x) x
+#else
+#define DEB(x)
+#endif
+
+#ifdef CONFIG_HARD_I2C
+#include <i2c.h>
+
+#define TIMEOUT (CFG_HZ/4)
+
+#define I2C_Addr ((unsigned *)(CFG_CCSRBAR + 0x3000))
+
+#define I2CADR &I2C_Addr[0]
+#define I2CFDR &I2C_Addr[1]
+#define I2CCCR &I2C_Addr[2]
+#define I2CCSR &I2C_Addr[3]
+#define I2CCDR &I2C_Addr[4]
+#define I2CDFSRR &I2C_Addr[5]
+
+#define I2C_READ 1
+#define I2C_WRITE 0
+
+/* taken from linux include/asm-ppc/io.h */
+inline unsigned in_le32(volatile unsigned *addr)
+{
+ unsigned ret;
+
+ __asm__ __volatile__("lwbrx %0,0,%1;\n"
+ "twi 0,%0,0;\n"
+ "isync" : "=r" (ret) :
+ "r" (addr), "m" (*addr));
+ return ret;
+}
+
+inline void out_le32(volatile unsigned *addr, int val)
+{
+ __asm__ __volatile__("stwbrx %1,0,%2; eieio" : "=m" (*addr) :
+ "r" (val), "r" (addr));
+}
+
+#define writel(val, addr) out_le32(addr, val)
+#define readl(addr) in_le32(addr)
+
+void
+i2c_init(int speed, int slaveadd)
+{
+ /* stop I2C controller */
+ writel (0x0, I2CCCR);
+ /* set clock */
+ writel (0x3f, I2CFDR);
+ /* set default filter */
+ writel (0x10,I2CDFSRR);
+ /* write slave address */
+ writel (slaveadd, I2CADR);
+ /* clear status register */
+ writel (0x0, I2CCSR);
+ /* start I2C controller */
+ writel (MPC85xx_I2CCR_MEN, I2CCCR);
+}
+
+static __inline__ int
+i2c_wait4bus (void)
+{
+ ulong timeval = get_timer (0);
+
+ while (readl (I2CCSR) & MPC85xx_I2CSR_MBB)
+ if (get_timer (timeval) > TIMEOUT)
+ return -1;
+
+ return 0;
+}
+
+static __inline__ int
+i2c_wait (int write)
+{
+ u32 csr;
+ ulong timeval = get_timer (0);
+
+ do
+ {
+ csr = readl (I2CCSR);
+
+ if (!(csr & MPC85xx_I2CSR_MIF))
+ continue;
+
+ writel (0x0, I2CCSR);
+
+ if (csr & MPC85xx_I2CSR_MAL)
+ {
+ DEB(printf ("i2c_wait: MAL\n"));
+ return -1;
+ }
+
+ if (!(csr & MPC85xx_I2CSR_MCF))
+ {
+ DEB(printf ("i2c_wait: unfinished\n"));
+ return -1;
+ }
+
+ if (write == I2C_WRITE && (csr & MPC85xx_I2CSR_RXAK))
+ {
+ DEB(printf ("i2c_wait: No RXACK\n"));
+ return -1;
+ }
+
+ return 0;
+ } while (get_timer (timeval) < TIMEOUT);
+
+ DEB(printf ("i2c_wait: timed out\n"));
+ return -1;
+}
+
+static __inline__ int
+i2c_write_addr (u8 dev, u8 dir, int rsta)
+{
+ writel (MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA | MPC85xx_I2CCR_MTX |
+ (rsta?MPC85xx_I2CCR_RSTA:0), I2CCCR);
+
+ writel ((dev << 1) | dir, I2CCDR);
+
+ if (i2c_wait (I2C_WRITE) < 0)
+ return 0;
+
+ return 1;
+}
+
+static __inline__ int
+__i2c_write (u8 *data, int length)
+{
+ int i;
+
+ writel (MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA | MPC85xx_I2CCR_MTX, I2CCCR);
+
+ for (i=0; i < length; i++)
+ {
+ writel (data[i], I2CCDR);
+
+ if (i2c_wait (I2C_WRITE) < 0)
+ break;
+ }
+
+ return i;
+}
+
+static __inline__ int
+__i2c_read (u8 *data, int length)
+{
+ int i;
+
+ writel (MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA |
+ ((length == 1) ? MPC85xx_I2CCR_TXAK : 0), I2CCCR);
+
+ /* dummy read */
+ readl (I2CCDR);
+
+ for (i=0; i < length; i++)
+ {
+ if (i2c_wait (I2C_READ) < 0)
+ break;
+
+ /* Generate ack on last next to last byte */
+ if (i == length - 2)
+ writel (MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA |
+ MPC85xx_I2CCR_TXAK, I2CCCR);
+
+ /* Generate stop on last byte */
+ if (i == length - 1)
+ writel (MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_TXAK, I2CCCR);
+
+ data[i] = readl (I2CCDR);
+ }
+
+ return i;
+}
+
+int
+i2c_read (u8 dev, uint addr, int alen, u8 *data, int length)
+{
+ int i = 0;
+ u8 *a = (u8*)&addr;
+
+ if (i2c_wait4bus () < 0)
+ goto exit;
+
+ if (i2c_write_addr (dev, I2C_WRITE, 0) == 0)
+ goto exit;
+
+ if (__i2c_write (&a[4 - alen], alen) != alen)
+ goto exit;
+
+ if (i2c_write_addr (dev, I2C_READ, 1) == 0)
+ goto exit;
+
+ i = __i2c_read (data, length);
+
+ exit:
+ writel (MPC85xx_I2CCR_MEN, I2CCCR);
+
+ return !(i == length);
+}
+
+int
+i2c_write (u8 dev, uint addr, int alen, u8 *data, int length)
+{
+ int i = 0;
+ u8 *a = (u8*)&addr;
+
+ if (i2c_wait4bus () < 0)
+ goto exit;
+
+ if (i2c_write_addr (dev, I2C_WRITE, 0) == 0)
+ goto exit;
+
+ if (__i2c_write (&a[4 - alen], alen) != alen)
+ goto exit;
+
+ i = __i2c_write (data, length);
+
+ exit:
+ writel (MPC85xx_I2CCR_MEN, I2CCCR);
+
+ return !(i == length);
+}
+
+int i2c_probe (uchar chip)
+{
+ int tmp;
+
+ /*
+ * Try to read the first location of the chip. The underlying
+ * driver doesn't appear to support sending just the chip address
+ * and looking for an <ACK> back.
+ */
+ udelay(10000);
+ return i2c_read (chip, 0, 1, (char *)&tmp, 1);
+}
+
+uchar i2c_reg_read (uchar i2c_addr, uchar reg)
+{
+ char buf[1];
+
+ i2c_read (i2c_addr, reg, 1, buf, 1);
+
+ return (buf[0]);
+}
+
+void i2c_reg_write (uchar i2c_addr, uchar reg, uchar val)
+{
+ i2c_write (i2c_addr, reg, 1, &val, 1);
+}
+
+#endif /* CONFIG_HARD_I2C */
--- /dev/null
+/*
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2002 (440 port)
+ * Scott McNutt, Artesyn Communication Producs, smcnutt@artsyncp.com
+ *
+ * (C) Copyright 2003 Motorola Inc. (MPC85xx port)
+ * Xianghua Xiao (X.Xiao@motorola.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <ppc_asm.tmpl>
+
+unsigned decrementer_count; /* count value for 1e6/HZ microseconds */
+
+static __inline__ unsigned long get_msr(void)
+{
+ unsigned long msr;
+
+ asm volatile("mfmsr %0" : "=r" (msr) :);
+ return msr;
+}
+
+static __inline__ void set_msr(unsigned long msr)
+{
+ asm volatile("mtmsr %0" : : "r" (msr));
+ asm volatile("isync");
+}
+
+void enable_interrupts (void)
+{
+ set_msr (get_msr() | MSR_EE);
+}
+
+/* returns flag if MSR_EE was set before */
+int disable_interrupts (void)
+{
+ ulong msr = get_msr();
+ set_msr (msr & ~MSR_EE);
+ return ((msr & MSR_EE) != 0);
+}
+
+/* interrupt is not supported yet */
+int interrupt_init (void)
+{
+ return (0);
+}
+
+/*
+ * Install and free a interrupt handler. Not implemented yet.
+ */
+
+void
+irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
+{
+ return;
+}
+
+void
+irq_free_handler(int vec)
+{
+ return;
+}
+
+/****************************************************************************/
+
+
+volatile ulong timestamp = 0;
+
+/*
+ * timer_interrupt - gets called when the decrementer overflows,
+ * with interrupts disabled.
+ * Trivial implementation - no need to be really accurate.
+ */
+void timer_interrupt(struct pt_regs *regs)
+{
+ printf ("*** Timer Interrupt *** ");
+ timestamp++;
+
+#if defined(CONFIG_WATCHDOG)
+ if ((timestamp % 1000) == 0)
+ reset_85xx_watchdog();
+#endif /* CONFIG_WATCHDOG */
+}
+
+void reset_timer (void)
+{
+ timestamp = 0;
+}
+
+ulong get_timer (ulong base)
+{
+ return (timestamp - base);
+}
+
+void set_timer (ulong t)
+{
+ timestamp = t;
+}
+
+#if (CONFIG_COMMANDS & CFG_CMD_IRQ)
+
+/*******************************************************************************
+ *
+ * irqinfo - print information about PCI devices,not implemented.
+ *
+ */
+int
+do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ printf ("\nInterrupt-unsupported:\n");
+
+ return 0;
+}
+
+#endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */
--- /dev/null
+/*
+ * Copyright (C) 2003 Motorola Inc.
+ * Xianghua Xiao (x.xiao@motorola.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * PCI Configuration space access support for MPC85xx PCI Bridge
+ */
+#include <common.h>
+#include <asm/cpm_85xx.h>
+#include <pci.h>
+
+#if defined(CONFIG_PCI)
+/*
+ * Initialize PCI Devices, report devices found.
+ */
+#ifndef CONFIG_PCI_PNP
+static struct pci_config_table pci_mpc85xxads_config_table[] = {
+ { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_IDSEL_NUMBER, PCI_ANY_ID,
+ pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
+ PCI_ENET0_MEMADDR,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
+ { }
+};
+#endif
+
+struct pci_controller local_hose = {
+#ifndef CONFIG_PCI_PNP
+ config_table: pci_mpc85xxads_config_table,
+#endif
+};
+
+void pci_init_board(void)
+{
+ struct pci_controller* hose = (struct pci_controller *)&local_hose;
+ volatile immap_t *immap = (immap_t *)CFG_CCSRBAR;
+ volatile ccsr_pcix_t *pcix = &immap->im_pcix;
+
+ u16 reg16;
+
+ hose->first_busno = 0;
+ hose->last_busno = 0xff;
+
+ pci_set_region(hose->regions + 0,
+ CFG_PCI_MEM_BASE,
+ CFG_PCI_MEM_PHYS,
+ (CFG_PCI_MEM_SIZE/2),
+ PCI_REGION_MEM);
+
+ pci_set_region(hose->regions + 1,
+ (CFG_PCI_MEM_BASE+0x08000000),
+ (CFG_PCI_MEM_PHYS+0x08000000),
+ 0x1000000, /* 16M */
+ PCI_REGION_IO);
+
+ hose->region_count = 2;
+
+ pci_setup_indirect(hose,
+ (CFG_IMMR+0x8000),
+ (CFG_IMMR+0x8004));
+
+ pci_register_hose(hose);
+
+ hose->last_busno = pci_hose_scan(hose);
+
+ pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16);
+ reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);
+
+ /* Clear non-reserved bits in status register */
+ pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
+ pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
+
+ pcix->potar1 = (CFG_PCI_MEM_BASE >> 12) & 0x000fffff;
+ pcix->potear1 = 0x00000000;
+ pcix->powbar1 = (CFG_PCI_MEM_BASE >> 12) & 0x000fffff;
+ pcix->powbear1 = 0x00000000;
+ pcix->powar1 = 0x8004401a; /* 128M MEM space */
+ pcix->potar2 = ((CFG_PCI_MEM_BASE + 0x08000000) >> 12) & 0x000fffff;
+ pcix->potear2 = 0x00000000;
+ pcix->powbar2 = ((CFG_PCI_MEM_BASE + 0x08000000) >> 12) && 0x000fffff;
+ pcix->powbear2 = 0x00000000;
+ pcix->powar2 = 0x80088017; /* 16M IO space */
+ pcix->pitar1 = 0x00000000;
+ pcix->piwbar1 = 0x00000000;
+ pcix->piwar1 = 0xa0F5501f;
+
+}
+#endif /* CONFIG_PCI */
--- /dev/null
+ .section .resetvec,"ax"
+ b _start_e500
--- /dev/null
+/*
+ * (C) Copyright 2003 Motorola Inc.
+ * Xianghua Xiao (X.Xiao@motorola.com)
+ * Modified based on 8260 for 8560.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00.
+ */
+
+/*
+ * Minimal serial functions needed to use one of the SCC ports
+ * as serial console interface.
+ */
+
+#include <common.h>
+#include <asm/cpm_85xx.h>
+
+#if defined(CONFIG_MPC8560)
+#if defined(CONFIG_CONS_ON_SCC)
+
+#if CONFIG_CONS_INDEX == 1 /* Console on SCC1 */
+
+#define SCC_INDEX 0
+#define PROFF_SCC PROFF_SCC1
+#define CMXSCR_MASK (CMXSCR_GR1|CMXSCR_SC1|\
+ CMXSCR_RS1CS_MSK|CMXSCR_TS1CS_MSK)
+#define CMXSCR_VALUE (CMXSCR_RS1CS_BRG1|CMXSCR_TS1CS_BRG1)
+#define CPM_CR_SCC_PAGE CPM_CR_SCC1_PAGE
+#define CPM_CR_SCC_SBLOCK CPM_CR_SCC1_SBLOCK
+
+#elif CONFIG_CONS_INDEX == 2 /* Console on SCC2 */
+
+#define SCC_INDEX 1
+#define PROFF_SCC PROFF_SCC2
+#define CMXSCR_MASK (CMXSCR_GR2|CMXSCR_SC2|\
+ CMXSCR_RS2CS_MSK|CMXSCR_TS2CS_MSK)
+#define CMXSCR_VALUE (CMXSCR_RS2CS_BRG2|CMXSCR_TS2CS_BRG2)
+#define CPM_CR_SCC_PAGE CPM_CR_SCC2_PAGE
+#define CPM_CR_SCC_SBLOCK CPM_CR_SCC2_SBLOCK
+
+#elif CONFIG_CONS_INDEX == 3 /* Console on SCC3 */
+
+#define SCC_INDEX 2
+#define PROFF_SCC PROFF_SCC3
+#define CMXSCR_MASK (CMXSCR_GR3|CMXSCR_SC3|\
+ CMXSCR_RS3CS_MSK|CMXSCR_TS3CS_MSK)
+#define CMXSCR_VALUE (CMXSCR_RS3CS_BRG3|CMXSCR_TS3CS_BRG3)
+#define CPM_CR_SCC_PAGE CPM_CR_SCC3_PAGE
+#define CPM_CR_SCC_SBLOCK CPM_CR_SCC3_SBLOCK
+
+#elif CONFIG_CONS_INDEX == 4 /* Console on SCC4 */
+
+#define SCC_INDEX 3
+#define PROFF_SCC PROFF_SCC4
+#define CMXSCR_MASK (CMXSCR_GR4|CMXSCR_SC4|\
+ CMXSCR_RS4CS_MSK|CMXSCR_TS4CS_MSK)
+#define CMXSCR_VALUE (CMXSCR_RS4CS_BRG4|CMXSCR_TS4CS_BRG4)
+#define CPM_CR_SCC_PAGE CPM_CR_SCC4_PAGE
+#define CPM_CR_SCC_SBLOCK CPM_CR_SCC4_SBLOCK
+
+#else
+
+#error "console not correctly defined"
+
+#endif
+
+int serial_init (void)
+{
+ volatile immap_t *im = (immap_t *)CFG_IMMR;
+ volatile ccsr_cpm_scc_t *sp;
+ volatile scc_uart_t *up;
+ volatile cbd_t *tbdf, *rbdf;
+ volatile ccsr_cpm_cp_t *cp = &(im->im_cpm.im_cpm_cp);
+ uint dpaddr;
+
+ /* initialize pointers to SCC */
+
+ sp = (ccsr_cpm_scc_t *) &(im->im_cpm.im_cpm_scc[SCC_INDEX]);
+ up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]);
+
+ /* Disable transmitter/receiver.
+ */
+ sp->gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
+
+ /* put the SCC channel into NMSI (non multiplexd serial interface)
+ * mode and wire the selected SCC Tx and Rx clocks to BRGx (15-15).
+ */
+ im->im_cpm.im_cpm_mux.cmxscr = \
+ (im->im_cpm.im_cpm_mux.cmxscr&~CMXSCR_MASK)|CMXSCR_VALUE;
+
+ /* Set up the baud rate generator.
+ */
+ serial_setbrg ();
+
+ /* Allocate space for two buffer descriptors in the DP ram.
+ * damm: allocating space after the two buffers for rx/tx data
+ */
+
+ dpaddr = m8560_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16);
+
+ /* Set the physical address of the host memory buffers in
+ * the buffer descriptors.
+ */
+ rbdf = (cbd_t *)&(im->im_cpm.im_dprambase[dpaddr]);
+ rbdf->cbd_bufaddr = (uint) (rbdf+2);
+ rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP;
+ tbdf = rbdf + 1;
+ tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
+ tbdf->cbd_sc = BD_SC_WRAP;
+
+ /* Set up the uart parameters in the parameter ram.
+ */
+ up->scc_genscc.scc_rbase = dpaddr;
+ up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t);
+ up->scc_genscc.scc_rfcr = CPMFCR_EB;
+ up->scc_genscc.scc_tfcr = CPMFCR_EB;
+ up->scc_genscc.scc_mrblr = 1;
+ up->scc_maxidl = 0;
+ up->scc_brkcr = 1;
+ up->scc_parec = 0;
+ up->scc_frmec = 0;
+ up->scc_nosec = 0;
+ up->scc_brkec = 0;
+ up->scc_uaddr1 = 0;
+ up->scc_uaddr2 = 0;
+ up->scc_toseq = 0;
+ up->scc_char1 = up->scc_char2 = up->scc_char3 = up->scc_char4 = 0x8000;
+ up->scc_char5 = up->scc_char6 = up->scc_char7 = up->scc_char8 = 0x8000;
+ up->scc_rccm = 0xc0ff;
+
+ /* Mask all interrupts and remove anything pending.
+ */
+ sp->sccm = 0;
+ sp->scce = 0xffff;
+
+ /* Set 8 bit FIFO, 16 bit oversampling and UART mode.
+ */
+ sp->gsmrh = SCC_GSMRH_RFW; /* 8 bit FIFO */
+ sp->gsmrl = \
+ SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16 | SCC_GSMRL_MODE_UART;
+
+ /* Set CTS no flow control, 1 stop bit, 8 bit character length,
+ * normal async UART mode, no parity
+ */
+ sp->psmr = SCU_PSMR_CL;
+
+ /* execute the "Init Rx and Tx params" CP command.
+ */
+
+ while (cp->cpcr & CPM_CR_FLG) /* wait if cp is busy */
+ ;
+
+ cp->cpcr = mk_cr_cmd(CPM_CR_SCC_PAGE, CPM_CR_SCC_SBLOCK,
+ 0, CPM_CR_INIT_TRX) | CPM_CR_FLG;
+
+ while (cp->cpcr & CPM_CR_FLG) /* wait if cp is busy */
+ ;
+
+ /* Enable transmitter/receiver.
+ */
+ sp->gsmrl |= SCC_GSMRL_ENR | SCC_GSMRL_ENT;
+
+ return (0);
+}
+
+void
+serial_setbrg (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_CONS_USE_EXTC)
+ m8560_cpm_extcbrg(SCC_INDEX, gd->baudrate,
+ CONFIG_CONS_EXTC_RATE, CONFIG_CONS_EXTC_PINSEL);
+#else
+ m8560_cpm_setbrg(SCC_INDEX, gd->baudrate);
+#endif
+}
+
+void
+serial_putc(const char c)
+{
+ volatile scc_uart_t *up;
+ volatile cbd_t *tbdf;
+ volatile immap_t *im;
+
+ if (c == '\n')
+ serial_putc ('\r');
+
+ im = (immap_t *)CFG_IMMR;
+ up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]);
+ tbdf = (cbd_t *)&(im->im_cpm.im_dprambase[up->scc_genscc.scc_tbase]);
+
+ /* Wait for last character to go.
+ */
+ while (tbdf->cbd_sc & BD_SC_READY)
+ ;
+
+ /* Load the character into the transmit buffer.
+ */
+ *(volatile char *)tbdf->cbd_bufaddr = c;
+ tbdf->cbd_datlen = 1;
+ tbdf->cbd_sc |= BD_SC_READY;
+}
+
+void
+serial_puts (const char *s)
+{
+ while (*s) {
+ serial_putc (*s++);
+ }
+}
+
+int
+serial_getc(void)
+{
+ volatile cbd_t *rbdf;
+ volatile scc_uart_t *up;
+ volatile immap_t *im;
+ unsigned char c;
+
+ im = (immap_t *)CFG_IMMR;
+ up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]);
+ rbdf = (cbd_t *)&(im->im_cpm.im_dprambase[up->scc_genscc.scc_rbase]);
+
+ /* Wait for character to show up.
+ */
+ while (rbdf->cbd_sc & BD_SC_EMPTY)
+ ;
+
+ /* Grab the char and clear the buffer again.
+ */
+ c = *(volatile unsigned char *)rbdf->cbd_bufaddr;
+ rbdf->cbd_sc |= BD_SC_EMPTY;
+
+ return (c);
+}
+
+int
+serial_tstc()
+{
+ volatile cbd_t *rbdf;
+ volatile scc_uart_t *up;
+ volatile immap_t *im;
+
+ im = (immap_t *)CFG_IMMR;
+ up = (scc_uart_t *)&(im->im_cpm.im_dprambase[PROFF_SCC]);
+ rbdf = (cbd_t *)&(im->im_cpm.im_dprambase[up->scc_genscc.scc_rbase]);
+
+ return ((rbdf->cbd_sc & BD_SC_EMPTY) == 0);
+}
+
+#endif /* CONFIG_CONS_ON_SCC */
+
+#endif /* CONFIG_MPC8560 */
--- /dev/null
+/*
+ * (C) Copyright 2003 Motorola Inc.
+ * Xianghua Xiao (X.Xiao@motorola.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <i2c.h>
+#include <spd.h>
+#include <asm/mmu.h>
+
+#ifdef CONFIG_SPD_EEPROM
+
+#undef DEBUG
+
+#if defined(DEBUG)
+#define DEB(x) x
+#else
+#define DEB(x)
+#endif
+
+#define ns2clk(ns) ((ns) / (2000000000 /get_bus_freq(0) + 1))
+
+long int spd_sdram(void) {
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile ccsr_ddr_t *ddr = &immap->im_ddr;
+ volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
+ spd_eeprom_t spd;
+ unsigned int memsize,tmp,tmp1,tmp2;
+ unsigned char caslat;
+
+ i2c_read (SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
+
+ if ( spd.nrows > 2 ) {
+ printf("DDR:Only two chip selects are supported on ADS.\n");
+ return 0;
+ }
+
+ if ( spd.nrow_addr < 12 || spd.nrow_addr > 14 || spd.ncol_addr < 8 || spd.ncol_addr > 11) {
+ printf("DDR:Row or Col number unsupported.\n");
+ return 0;
+ }
+
+ ddr->cs0_bnds = ((spd.row_dens>>2) - 1);
+ ddr->cs0_config = ( 1<<31 | (spd.nrow_addr-12)<<8 | (spd.ncol_addr-8) );
+ DEB(printf("\n"));
+ DEB(printf("cs0_bnds = 0x%08x\n",ddr->cs0_bnds));
+ DEB(printf("cs0_config = 0x%08x\n",ddr->cs0_config));
+ if ( spd.nrows == 2 ) {
+ ddr->cs1_bnds = ((spd.row_dens<<14) | ((spd.row_dens>>1) - 1));
+ ddr->cs1_config = ( 1<<31 | (spd.nrow_addr-12)<<8 | (spd.ncol_addr-8) );
+ DEB(printf("cs1_bnds = 0x%08x\n",ddr->cs1_bnds));
+ DEB(printf("cs1_config = 0x%08x\n",ddr->cs1_config));
+ }
+
+ memsize = spd.nrows * (4 * spd.row_dens);
+ if( spd.mem_type == 0x07 ) {
+ printf("DDR module detected, total size:%dMB.\n",memsize);
+ } else {
+ printf("No DDR module found!\n");
+ return 0;
+ }
+
+ switch(memsize) {
+ case 16:
+ tmp = 7; /* TLB size */
+ tmp1 = 1; /* TLB entry number */
+ tmp2 = 23; /* Local Access Window size */
+ break;
+ case 32:
+ tmp = 7;
+ tmp1 = 2;
+ tmp2 = 24;
+ break;
+ case 64:
+ tmp = 8;
+ tmp1 = 1;
+ tmp2 = 25;
+ break;
+ case 128:
+ tmp = 8;
+ tmp1 = 2;
+ tmp2 = 26;
+ break;
+ case 256:
+ tmp = 9;
+ tmp1 = 1;
+ tmp2 = 27;
+ break;
+ case 512:
+ tmp = 9;
+ tmp1 = 2;
+ tmp2 = 28;
+ break;
+ case 1024:
+ tmp = 10;
+ tmp1 = 1;
+ tmp2 = 29;
+ break;
+ default:
+ printf("DDR:we only added support 16M,32M,64M,128M,256M,512M and 1G DDR I.\n");
+ return 0;
+ break;
+ }
+
+ /* configure DDR TLB to TLB1 Entry 4,5 */
+ mtspr(MAS0, TLB1_MAS0(1,4,0));
+ mtspr(MAS1, TLB1_MAS1(1,1,0,0,tmp));
+ mtspr(MAS2, TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0));
+ mtspr(MAS3, TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1));
+ asm volatile("isync;msync;tlbwe;isync");
+ DEB(printf("DDR:MAS0=0x%08x\n",TLB1_MAS0(1,4,0)));
+ DEB(printf("DDR:MAS1=0x%08x\n",TLB1_MAS1(1,1,0,0,tmp)));
+ DEB(printf("DDR:MAS2=0x%08x\n",TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) \
+ & 0xfffff),0,0,0,0,0,0,0,0)));
+ DEB(printf("DDR:MAS3=0x%08x\n",TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) \
+ & 0xfffff),0,0,0,0,0,1,0,1,0,1)));
+
+ if(tmp1 == 2) {
+ mtspr(MAS0, TLB1_MAS0(1,5,0));
+ mtspr(MAS1, TLB1_MAS1(1,1,0,0,tmp));
+ mtspr(MAS2, TLB1_MAS2((((CFG_DDR_SDRAM_BASE+(memsize*1024*1024)/2)>>12) \
+ & 0xfffff),0,0,0,0,0,0,0,0));
+ mtspr(MAS3, TLB1_MAS3((((CFG_DDR_SDRAM_BASE+(memsize*1024*1024)/2)>>12) \
+ & 0xfffff),0,0,0,0,0,1,0,1,0,1));
+ asm volatile("isync;msync;tlbwe;isync");
+ DEB(printf("DDR:MAS0=0x%08x\n",TLB1_MAS0(1,5,0)));
+ DEB(printf("DDR:MAS1=0x%08x\n",TLB1_MAS1(1,1,0,0,tmp)));
+ DEB(printf("DDR:MAS2=0x%08x\n",TLB1_MAS2((((CFG_DDR_SDRAM_BASE \
+ +(memsize*1024*1024)/2)>>12) & 0xfffff),0,0,0,0,0,0,0,0)));
+ DEB(printf("DDR:MAS3=0x%08x\n",TLB1_MAS3((((CFG_DDR_SDRAM_BASE \
+ +(memsize*1024*1024)/2)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)));
+ }
+
+#if defined(CONFIG_RAM_AS_FLASH)
+ ecm->lawbar2 = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
+ ecm->lawar2 = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & tmp2));
+ DEB(printf("DDR:LAWBAR2=0x%08x\n",ecm->lawbar2));
+ DEB(printf("DDR:LARAR2=0x%08x\n",ecm->lawar2));
+#else
+ ecm->lawbar1 = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
+ ecm->lawar1 = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & tmp2));
+ DEB(printf("DDR:LAWBAR1=0x%08x\n",ecm->lawbar1));
+ DEB(printf("DDR:LARAR1=0x%08x\n",ecm->lawar1));
+#endif
+
+ tmp = 20000/(((spd.clk_cycle & 0xF0) >> 4) * 10 + (spd.clk_cycle & 0x0f));
+ DEB(printf("DDR:Module maximum data rate is: %dMhz\n",tmp));
+
+ /* find the largest CAS */
+ if(spd.cas_lat & 0x40) {
+ caslat = 7;
+ } else if (spd.cas_lat & 0x20) {
+ caslat = 6;
+ } else if (spd.cas_lat & 0x10) {
+ caslat = 5;
+ } else if (spd.cas_lat & 0x08) {
+ caslat = 4;
+ } else if (spd.cas_lat & 0x04) {
+ caslat = 3;
+ } else if (spd.cas_lat & 0x02) {
+ caslat = 2;
+ } else if (spd.cas_lat & 0x01) {
+ caslat = 1;
+ } else {
+ printf("DDR:no valid CAS Latency information.\n");
+ return 0;
+ }
+
+ tmp1 = get_bus_freq(0)/1000000;
+ if(tmp1<230 && tmp1>=90 && tmp>=230) { /* 90~230 range, treated as DDR 200 */
+ if(spd.clk_cycle3 == 0xa0) caslat -= 2;
+ else if(spd.clk_cycle2 == 0xa0) caslat--;
+ } else if(tmp1<280 && tmp1>=230 && tmp>=280) { /* 230-280 range, treated as DDR 266 */
+ if(spd.clk_cycle3 == 0x75) caslat -= 2;
+ else if(spd.clk_cycle2 == 0x75) caslat--;
+ } else if(tmp1<350 && tmp1>=280 && tmp>=350) { /* 280~350 range, treated as DDR 333 */
+ if(spd.clk_cycle3 == 0x60) caslat -= 2;
+ else if(spd.clk_cycle2 == 0x60) caslat--;
+ } else if(tmp1<90 || tmp1 >=350) { /* DDR rate out-of-range */
+ printf("DDR:platform frequency is not fit for DDR rate\n");
+ return 0;
+ }
+
+ /* note: caslat must also be programmed into ddr->sdram_mode register */
+ /* note: WRREC(Twr) and WRTORD(Twtr) are not in SPD,use conservative value here */
+#if 1
+ ddr->timing_cfg_1 = (((ns2clk(spd.trp/4) & 0x07) << 28 ) | \
+ ((ns2clk(spd.tras) & 0x0f ) << 24 ) | \
+ ((ns2clk(spd.trcd/4) & 0x07) << 20 ) | \
+ ((caslat & 0x07)<< 16 ) | \
+ (((ns2clk(spd.sset[6]) - 8) & 0x0f) << 12 ) | \
+ ( 0x300 ) | \
+ ((ns2clk(spd.trrd/4) & 0x07) << 4) | 1);
+#else
+ ddr->timing_cfg_1 = 0x37344321;
+ caslat = 4;
+#endif
+ DEB(printf("DDR:timing_cfg_1=0x%08x\n",ddr->timing_cfg_1));
+
+ /* note: hand-coded value for timing_cfg_2, see Errata DDR1*/
+#if defined(CONFIG_MPC85xx_REV1)
+ ddr->timing_cfg_2 = 0x00000800;
+#endif
+ DEB(printf("DDR:timing_cfg_2=0x%08x\n",ddr->timing_cfg_2));
+
+ /* only DDR I is supported, DDR I and II have different mode-register-set definition */
+ /* burst length is always 4 */
+ switch(caslat) {
+ case 2:
+ ddr->sdram_mode = 0x52; /* 1.5 */
+ break;
+ case 3:
+ ddr->sdram_mode = 0x22; /* 2.0 */
+ break;
+ case 4:
+ ddr->sdram_mode = 0x62; /* 2.5 */
+ break;
+ case 5:
+ ddr->sdram_mode = 0x32; /* 3.0 */
+ break;
+ default:
+ printf("DDR:only CAS Latency 1.5,2.0,2.5,3.0 is supported.\n");
+ return 0;
+ }
+ DEB(printf("DDR:sdram_mode=0x%08x\n",ddr->sdram_mode));
+
+ switch(spd.refresh) {
+ case 0x00:
+ case 0x80:
+ tmp = ns2clk(15625);
+ break;
+ case 0x01:
+ case 0x81:
+ tmp = ns2clk(3900);
+ break;
+ case 0x02:
+ case 0x82:
+ tmp = ns2clk(7800);
+ break;
+ case 0x03:
+ case 0x83:
+ tmp = ns2clk(31300);
+ break;
+ case 0x04:
+ case 0x84:
+ tmp = ns2clk(62500);
+ break;
+ case 0x05:
+ case 0x85:
+ tmp = ns2clk(125000);
+ break;
+ default:
+ tmp = 0x512;
+ break;
+ }
+
+ /* set BSTOPRE to 0x100 for page mode, if auto-charge is used, set BSTOPRE = 0 */
+ ddr->sdram_interval = ((tmp & 0x3fff) << 16) | 0x100;
+ DEB(printf("DDR:sdram_interval=0x%08x\n",ddr->sdram_interval));
+
+ /* is this an ECC DDR chip? */
+#if defined(CONFIG_DDR_ECC)
+ if(spd.config == 0x02) {
+ ddr->err_disable = 0x0000000d;
+ ddr->err_sbe = 0x00ff0000;
+ }
+ DEB(printf("DDR:err_disable=0x%08x\n",ddr->err_disable));
+ DEB(printf("DDR:err_sbe=0x%08x\n",ddr->err_sbe));
+#endif
+ asm("sync;isync;msync");
+
+ udelay(500);
+
+ /* registered or unbuffered? */
+#if defined(CONFIG_DDR_ECC)
+ ddr->sdram_cfg = (spd.config == 0x02)?0x20000000:0x0;
+#endif
+ ddr->sdram_cfg = 0xc2000000|((spd.mod_attr == 0x20) ? 0x0 : \
+ ((spd.mod_attr == 0x26) ? 0x10000000:0x0));
+ asm("sync;isync;msync");
+
+ udelay(500);
+
+ DEB(printf("DDR:sdram_cfg=0x%08x\n",ddr->sdram_cfg));
+
+ return (memsize*1024*1024);
+}
+
+#endif /* CONFIG_SPD_EEPROM */
--- /dev/null
+/*
+ * (C) Copyright 2003 Motorola Inc.
+ * Xianghua Xiao, (X.Xiao@motorola.com)
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc_asm.tmpl>
+#include <asm/processor.h>
+
+/* --------------------------------------------------------------- */
+
+#define ONE_BILLION 1000000000
+
+void get_sys_info (sys_info_t * sysInfo)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile ccsr_gur_t *gur = &immap->im_gur;
+ uint plat_ratio,e500_ratio;
+
+ plat_ratio = (gur->porpllsr) & 0x0000003e;
+ plat_ratio >>= 1;
+ switch(plat_ratio) {
+ case 0x02:
+ case 0x03:
+ case 0x04:
+ case 0x05:
+ case 0x06:
+ case 0x08:
+ case 0x09:
+ case 0x0a:
+ case 0x0c:
+ case 0x10:
+ sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ;
+ break;
+ default:
+ sysInfo->freqSystemBus = 0;
+ break;
+ }
+
+ e500_ratio = (gur->porpllsr) & 0x003f0000;
+ e500_ratio >>= 16;
+ switch(e500_ratio) {
+ case 0x04:
+ sysInfo->freqProcessor = 2*sysInfo->freqSystemBus;
+ break;
+ case 0x05:
+ sysInfo->freqProcessor = 5*sysInfo->freqSystemBus/2;
+ break;
+ case 0x06:
+ sysInfo->freqProcessor = 3*sysInfo->freqSystemBus;
+ break;
+ case 0x07:
+ sysInfo->freqProcessor = 7*sysInfo->freqSystemBus/2;
+ break;
+ default:
+ sysInfo->freqProcessor = 0;
+ break;
+ }
+}
+
+int get_clocks (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ sys_info_t sys_info;
+#if defined(CONFIG_MPC8560)
+ volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ uint sccr, dfbrg;
+
+ /* set VCO = 4 * BRG */
+ immap->im_cpm.im_cpm_intctl.sccr &= 0xfffffffc;
+ sccr = immap->im_cpm.im_cpm_intctl.sccr;
+ dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
+#endif
+ get_sys_info (&sys_info);
+ gd->cpu_clk = sys_info.freqProcessor;
+ gd->bus_clk = sys_info.freqSystemBus;
+#if defined(CONFIG_MPC8560)
+ gd->vco_out = 2*sys_info.freqSystemBus;
+ gd->cpm_clk = gd->vco_out / 2;
+ gd->scc_clk = gd->vco_out / 4;
+ gd->brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1)));
+#endif
+
+ if(gd->cpu_clk != 0) return (0);
+ else return (1);
+}
+
+
+/********************************************
+ * get_bus_freq
+ * return system bus freq in Hz
+ *********************************************/
+ulong get_bus_freq (ulong dummy)
+{
+ ulong val;
+
+ sys_info_t sys_info;
+
+ get_sys_info (&sys_info);
+ val = sys_info.freqSystemBus;
+
+ return val;
+}
--- /dev/null
+/*
+ * Copyright (C) 2003 Motorola,Inc.
+ * Xianghua Xiao<X.Xiao@motorola.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards
+ *
+ * The processor starts at 0xfffffffc and the code is first executed in the
+ * last 4K page(0xfffff000-0xffffffff) in flash/rom.
+ *
+ */
+
+#include <config.h>
+#include <mpc85xx.h>
+#include <version.h>
+
+#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#include <asm/cache.h>
+#include <asm/mmu.h>
+
+#ifndef CONFIG_IDENT_STRING
+#define CONFIG_IDENT_STRING ""
+#endif
+
+#undef MSR_KERNEL
+#define MSR_KERNEL ( MSR_ME ) /* Machine Check */
+
+/*
+ * Set up GOT: Global Offset Table
+ *
+ * Use r14 to access the GOT
+ */
+ START_GOT
+ GOT_ENTRY(_GOT2_TABLE_)
+ GOT_ENTRY(_FIXUP_TABLE_)
+
+ GOT_ENTRY(_start)
+ GOT_ENTRY(_start_of_vectors)
+ GOT_ENTRY(_end_of_vectors)
+ GOT_ENTRY(transfer_to_handler)
+
+ GOT_ENTRY(__init_end)
+ GOT_ENTRY(_end)
+ GOT_ENTRY(__bss_start)
+ END_GOT
+
+/*
+ * e500 Startup -- after reset only the last 4KB of the effective
+ * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg
+ * section is located at THIS LAST page and basically does three
+ * things: clear some registers, set up exception tables and
+ * add more TLB entries for 'larger spaces'(e.g. the boot rom) to
+ * continue the boot procedure.
+
+ * Once the boot rom is mapped by TLB entries we can proceed
+ * with normal startup.
+ *
+ */
+
+ .section .bootpg,"ax"
+ .globl _start_e500
+
+_start_e500:
+#if defined(CONFIG_MPC85xx_REV1)
+ li r0,0x2000
+ mtspr 977,r0
+#endif
+
+ /* Clear and set up some registers. Note: Some registers need strict
+ * synchronization by sync/mbar/msync/isync when being "mtspr".
+ * BookE: isync before PID,tlbivax,tlbwe
+ * BookE: isync after MSR,PID; msync_isync after tlbivax & tlbwe
+ * E500: msync,isync before L1CSR0
+ * E500: isync after BBEAR,BBTAR,BUCSR,DBCR0,DBCR1,HID0,HID1,L1CSR0
+ * L1CSR1, MAS[0,1,2,3,4,6],MMUCSR0, PID[0,1,2],SPEFCSR
+ */
+
+ /* invalidate d-cache */
+ mfspr r0,L1CSR0
+ ori r0,r0,0x0002
+ msync
+ isync
+ mtspr L1CSR0,r0
+ isync
+
+ /* disable d-cache */
+ li r0,0x0
+ mtspr L1CSR0,r0
+ isync
+
+ /* invalidate i-cache */
+ mfspr r0,L1CSR1
+ ori r0,r0,0x0002
+ mtspr L1CSR1,r0
+ isync
+
+ /* disable i-cache */
+ li r0,0x0
+ mtspr L1CSR1,r0
+ isync
+
+ /* clear registers */
+ sync
+ li r0,0
+ mtspr SRR0,r0
+ mtspr SRR1,r0
+ mtspr CSRR0,r0
+ mtspr CSRR1,r0
+ mtspr MCSRR0,r0
+ mtspr MCSRR1,r0
+
+ mtspr ESR,r0
+ mtspr MCSR,r0
+ mtspr DEAR,r0
+
+ mtspr DBCR0,r0
+ isync
+ mtspr DBCR1,r0
+ isync
+ mtspr DBCR2,r0
+ isync
+ mtspr IAC1,r0
+ mtspr IAC2,r0
+ mtspr DAC1,r0
+ mtspr DAC2,r0
+
+ mfspr r1,DBSR
+ mtspr DBSR,r1 /* Clear all valid bits */
+
+ isync
+ mtspr PID0,r0
+ isync
+ mtspr PID1,r0
+ isync
+ mtspr PID2,r0
+ isync
+
+ mtspr TCR,r0
+
+ mtspr BUCSR,r0 /* disable branch prediction */
+ isync
+
+ mtspr HID0,r0
+ isync
+ mtspr HID1,r0
+ isync
+
+ mtspr MAS4,r0
+ isync
+ mtspr MAS6,r0
+ isync
+
+ /* Setup interrupt vectors */
+ mtspr IVPR, r0
+
+ li r1,0x0100
+ mtspr IVOR0,r1 /* 0: Critical input */
+ li r1,0x0200
+ mtspr IVOR1,r1 /* 1: Machine check */
+ li r1,0x0300
+ mtspr IVOR2,r1 /* 2: Data storage */
+ li r1,0x0400
+ mtspr IVOR3,r1 /* 3: Instruction storage */
+ li r1,0x0500
+ mtspr IVOR4,r1 /* 4: External interrupt */
+ li r1,0x0600
+ mtspr IVOR5,r1 /* 5: Alignment */
+ li r1,0x0700
+ mtspr IVOR6,r1 /* 6: Program check */
+ li r1,0x0800
+ mtspr IVOR7,r1 /* 7: floating point unavailable */
+ li r1,0x0c00
+ mtspr IVOR8,r1 /* 8: System call */
+ /* 9: Auxiliary processor unavailable(unsupported) */
+ li r1,0x1000
+ mtspr IVOR10,r1 /* 10: Decrementer */
+ li r1,0x1400
+ mtspr IVOR13,r1 /* 13: Data TLB error */
+ li r1,0x1300
+ mtspr IVOR14,r1 /* 14: Instruction TLB error */
+ li r1,0x2000
+ mtspr IVOR15,r1 /* 15: Debug */
+
+ /* invalidate MMU L1/L2 */
+ /* Note: before invalidate MMU L1/L2, we read TLB1 Entry 0 and then
+ * write it back immediately to fixup a bug(Errata CPU4) for this initial
+ * TLB1 entry 0,otherwise the TLB1 entry 0 will be invalidated.
+ */
+#if defined(CONFIG_MPC85xx_REV1)
+ lis r2,0x1000
+ mtspr MAS0,r2
+ tlbre
+ tlbwe
+ isync
+ li r2, 0x001e
+ mtspr MMUCSR0, r2
+ isync
+#endif
+
+ /* After reset, CCSRBAR is located at CFG_CCSRBAR_DEFAULT, i.e.
+ * 0xff700000-0xff800000. We need add a TLB1 entry for this 1MB
+ * region before we can access any CCSR registers such as L2
+ * registers, Local Access Registers,etc. We will also re-allocate
+ * CFG_CCSRBAR_DEFAULT to CFG_CCSRBAR immediately after TLB1 setup.
+ *
+ * Please refer to board-specif directory for TLB1 entry configuration.
+ * (e.g. board/<yourboard>/init.S)
+ *
+ */
+ bl tlb1_entry
+ mr r5,r0
+ li r1,0x000f /* max 16 TLB1 entries */
+ mtctr r1
+ lwzu r4,0(r5) /* how many TLB1 entries we actually use */
+
+0: cmpwi r4,0
+ beq 1f
+ lwzu r0,4(r5)
+ lwzu r1,4(r5)
+ lwzu r2,4(r5)
+ lwzu r3,4(r5)
+ mtspr MAS0,r0
+ mtspr MAS1,r1
+ mtspr MAS2,r2
+ mtspr MAS3,r3
+ isync
+ msync
+ tlbwe
+ isync
+ addi r4,r4,-1
+ bdnz 0b
+
+1:
+#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
+ /* Special sequence needed to update CCSRBAR itself */
+ lis r4, CFG_CCSRBAR_DEFAULT@h
+ ori r4, r4, CFG_CCSRBAR_DEFAULT@l
+
+ lis r5, CFG_CCSRBAR@h
+ ori r5, r5, CFG_CCSRBAR@l
+ srwi r6,r5,12
+ stw r6, 0(r4)
+ isync
+
+ lis r5, 0xffff
+ ori r5,r5,0xf000
+ lwz r5, 0(r5)
+ isync
+
+ lis r3, CFG_CCSRBAR@h
+ lwz r5, CFG_CCSRBAR@l(r3)
+ isync
+#endif
+
+ /* invalidate all TLB0 entries */
+ li r3,4
+ li r4,0
+ tlbivax r4,r3
+#if defined(CONFIG_MPC85xx_REV1) /* Errata CPU6 */
+ nop
+#endif
+
+ /* set up local access windows, defined at board/<boardname>/init.S */
+ lis r7,CFG_CCSRBAR@h
+ ori r7,r7,CFG_CCSRBAR@l
+
+ bl law_entry
+ mr r6,r0
+#if defined(CONFIG_RAM_AS_FLASH)
+ li r1,0x0006
+#else
+ li r1,0x0007 /*we have 8 LAWs, but reseve one for boot-over-rio-or-pci */
+#endif
+ mtctr r1
+ lwzu r5,0(r6) /* how many windows we actually use */
+
+#if defined(CONFIG_RAM_AS_FLASH)
+ li r2,0x0c48
+ li r1,0x0c50
+#else
+ li r2,0x0c28 /* the first pair is reserved for boot-over-rio-or-pci */
+ li r1,0x0c30
+#endif
+
+0: cmpwi r5,0
+ beq 1f
+ lwzu r4,4(r6)
+ lwzu r3,4(r6)
+ stwx r4,r7,r2
+ stwx r3,r7,r1
+ addi r5,r5,-1
+ addi r2,r2,0x0020
+ addi r1,r1,0x0020
+ bdnz 0b
+
+ /* Jump out the last 4K page and continue to 'normal' start */
+1: bl 3f
+ b _start
+
+3: li r0,0
+ mtspr SRR1,r0 /* Keep things disabled for now */
+ mflr r1
+ mtspr SRR0,r1
+ rfi
+
+/*
+ * r3 - 1st arg to board_init(): IMMP pointer
+ * r4 - 2nd arg to board_init(): boot flag
+ */
+ .text
+ .long 0x27051956 /* U-BOOT Magic Number */
+ .globl version_string
+version_string:
+ .ascii U_BOOT_VERSION
+ .ascii " (", __DATE__, " - ", __TIME__, ")"
+ .ascii CONFIG_IDENT_STRING, "\0"
+
+ . = EXC_OFF_SYS_RESET
+ .globl _start
+_start:
+ /* Clear and set up some registers. */
+ li r0,0x0000
+ lis r1,0xffff
+ mtspr DEC,r0 /* prevent dec exceptions */
+ mttbl r0 /* prevent fit & wdt exceptions */
+ mttbu r0
+ mtspr TSR,r1 /* clear all timer exception status */
+ mtspr TCR,r0 /* disable all */
+ mtspr ESR,r0 /* clear exception syndrome register */
+ mtspr MCSR,r0 /* machine check syndrome register */
+ mtxer r0 /* clear integer exception register */
+ lis r1,0x0002 /* set CE bit (Critical Exceptions) */
+ ori r1,r1,0x1200 /* set ME/DE bit */
+ mtmsr r1 /* change MSR */
+ isync
+
+ /* Enable Time Base and Select Time Base Clock */
+ li r0,0x4000 /* time base is processor clock */
+ mtspr HID0,r0
+ isync
+
+#if defined(CONFIG_ADDR_STREAMING)
+ li r0,0x2000
+ mtspr HID1,r0
+ isync
+#endif
+
+ /* Enable Branch Prediction */
+#if defined(CONFIG_BTB)
+ li r0,0x201 /* BBFI = 1, BPEN = 1 */
+ mtspr BUCSR,r0
+ isync
+#endif
+
+#if defined(CFG_INIT_DBCR)
+ lis r1,0xffff
+ ori r1,r1,0xffff
+ mtspr dbsr,r1 /* Clear all status bits */
+ lis r0,CFG_INIT_DBCR@h /* DBCR0[IDM] must be set */
+ ori r0,r0,CFG_INIT_DBCR@l
+ mtspr dbcr0,r0
+ isync
+#endif
+
+/* L1 DCache is used for initial RAM */
+ mfspr r2, L1CSR0
+ ori r2, r2, 0x0003
+ oris r2, r2, 0x0001
+ msync
+ isync
+ mtspr L1CSR0, r2 /* enable/invalidate L1 Dcache */
+ isync
+
+ /* Allocate Initial RAM in data cache.
+ */
+ lis r3, CFG_INIT_RAM_ADDR@h
+ ori r3, r3, CFG_INIT_RAM_ADDR@l
+ li r2, 512 /* 512*32=16K */
+ mtctr r2
+ li r0, 0
+1:
+ dcbz r0, r3
+ dcbtls 0,r0, r3
+ addi r3, r3, 32
+ bdnz 1b
+
+#ifndef CFG_RAMBOOT
+ /* Calculate absolute address in FLASH and jump there */
+ /*--------------------------------------------------------------*/
+ lis r3, CFG_MONITOR_BASE@h
+ ori r3, r3, CFG_MONITOR_BASE@l
+ addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
+ mtlr r3
+ blr
+
+in_flash:
+#endif /* CFG_RAMBOOT */
+
+ /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
+ lis r1,CFG_INIT_RAM_ADDR@h
+ ori r1,r1,CFG_INIT_SP_OFFSET@l
+
+ li r0,0
+ stwu r0,-4(r1)
+ stwu r0,-4(r1) /* Terminate call chain */
+
+ stwu r1,-8(r1) /* Save back chain and move SP */
+ lis r0,RESET_VECTOR@h /* Address of reset vector */
+ ori r0,r0, RESET_VECTOR@l
+ stwu r1,-8(r1) /* Save back chain and move SP */
+ stw r0,+12(r1) /* Save return addr (underflow vect) */
+
+ GET_GOT
+ bl cpu_init_f
+ bl icache_enable
+ bl board_init_f
+ sync
+
+
+/* --FIXME-- machine check with MCSRRn and rfmci */
+
+ .globl _start_of_vectors
+_start_of_vectors:
+#if 0
+/* Critical input. */
+ CRIT_EXCEPTION(0x0100, CritcalInput, CritcalInputException)
+#endif
+/* Machine check --FIXME-- Should be MACH_EXCEPTION */
+ CRIT_EXCEPTION(0x0200, MachineCheck, MachineCheckException)
+
+/* Data Storage exception. */
+ STD_EXCEPTION(0x0300, DataStorage, UnknownException)
+
+/* Instruction Storage exception. */
+ STD_EXCEPTION(0x0400, InstStorage, UnknownException)
+
+/* External Interrupt exception. */
+ STD_EXCEPTION(0x0500, ExtInterrupt, UnknownException)
+
+/* Alignment exception. */
+ . = 0x0600
+Alignment:
+ EXCEPTION_PROLOG
+ mfspr r4,DAR
+ stw r4,_DAR(r21)
+ mfspr r5,DSISR
+ stw r5,_DSISR(r21)
+ addi r3,r1,STACK_FRAME_OVERHEAD
+ li r20,MSR_KERNEL
+ rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
+ lwz r6,GOT(transfer_to_handler)
+ mtlr r6
+ blrl
+.L_Alignment:
+ .long AlignmentException - _start + EXC_OFF_SYS_RESET
+ .long int_return - _start + EXC_OFF_SYS_RESET
+
+/* Program check exception */
+ . = 0x0700
+ProgramCheck:
+ EXCEPTION_PROLOG
+ addi r3,r1,STACK_FRAME_OVERHEAD
+ li r20,MSR_KERNEL
+ rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
+ lwz r6,GOT(transfer_to_handler)
+ mtlr r6
+ blrl
+.L_ProgramCheck:
+ .long ProgramCheckException - _start + EXC_OFF_SYS_RESET
+ .long int_return - _start + EXC_OFF_SYS_RESET
+
+ /* No FPU on MPC85xx. This exception is not supposed to happen.
+ */
+ STD_EXCEPTION(0x0800, FPUnavailable, UnknownException)
+ STD_EXCEPTION(0x0900, Decrementer, timer_interrupt)
+ STD_EXCEPTION(0x0a00, Trap_0a, UnknownException)
+ STD_EXCEPTION(0x0b00, Trap_0b, UnknownException)
+
+ . = 0x0c00
+/*
+ * r0 - SYSCALL number
+ * r3-... arguments
+ */
+SystemCall:
+ addis r11,r0,0 /* get functions table addr */
+ ori r11,r11,0 /* Note: this code is patched in trap_init */
+ addis r12,r0,0 /* get number of functions */
+ ori r12,r12,0
+
+ cmplw 0, r0, r12
+ bge 1f
+
+ rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */
+ add r11,r11,r0
+ lwz r11,0(r11)
+
+ li r20,0xd00-4 /* Get stack pointer */
+ lwz r12,0(r20)
+ subi r12,r12,12 /* Adjust stack pointer */
+ li r0,0xc00+_end_back-SystemCall
+ cmplw 0, r0, r12 /* Check stack overflow */
+ bgt 1f
+ stw r12,0(r20)
+
+ mflr r0
+ stw r0,0(r12)
+ mfspr r0,SRR0
+ stw r0,4(r12)
+ mfspr r0,SRR1
+ stw r0,8(r12)
+
+ li r12,0xc00+_back-SystemCall
+ mtlr r12
+ mtspr SRR0,r11
+
+1: SYNC
+ rfi
+_back:
+
+ mfmsr r11 /* Disable interrupts */
+ li r12,0
+ ori r12,r12,MSR_EE
+ andc r11,r11,r12
+ SYNC /* Some chip revs need this... */
+ mtmsr r11
+ SYNC
+
+ li r12,0xd00-4 /* restore regs */
+ lwz r12,0(r12)
+
+ lwz r11,0(r12)
+ mtlr r11
+ lwz r11,4(r12)
+ mtspr SRR0,r11
+ lwz r11,8(r12)
+ mtspr SRR1,r11
+
+ addi r12,r12,12 /* Adjust stack pointer */
+ li r20,0xd00-4
+ stw r12,0(r20)
+
+ SYNC
+ rfi
+_end_back:
+
+ STD_EXCEPTION(0xd00, SingleStep, UnknownException)
+
+ STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
+ STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
+
+ STD_EXCEPTION(0x1000, PIT, PITException)
+
+ STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
+ STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
+ STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
+ STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
+
+ STD_EXCEPTION(0x1500, Reserved5, UnknownException)
+ STD_EXCEPTION(0x1600, Reserved6, UnknownException)
+ STD_EXCEPTION(0x1700, Reserved7, UnknownException)
+ STD_EXCEPTION(0x1800, Reserved8, UnknownException)
+ STD_EXCEPTION(0x1900, Reserved9, UnknownException)
+ STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
+ STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
+
+ STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
+ STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
+ STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
+ STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
+
+ CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
+
+ .globl _end_of_vectors
+_end_of_vectors:
+
+
+ . = 0x2100
+
+/*
+ * This code finishes saving the registers to the exception frame
+ * and jumps to the appropriate handler for the exception.
+ * Register r21 is pointer into trap frame, r1 has new stack pointer.
+ */
+ .globl transfer_to_handler
+transfer_to_handler:
+ stw r22,_NIP(r21)
+ lis r22,MSR_POW@h
+ andc r23,r23,r22
+ stw r23,_MSR(r21)
+ SAVE_GPR(7, r21)
+ SAVE_4GPRS(8, r21)
+ SAVE_8GPRS(12, r21)
+ SAVE_8GPRS(24, r21)
+
+ mflr r23
+ andi. r24,r23,0x3f00 /* get vector offset */
+ stw r24,TRAP(r21)
+ li r22,0
+ stw r22,RESULT(r21)
+ mtspr SPRG2,r22 /* r1 is now kernel sp */
+
+ lwz r24,0(r23) /* virtual address of handler */
+ lwz r23,4(r23) /* where to go when done */
+ mtspr SRR0,r24
+ mtspr SRR1,r20
+ mtlr r23
+ SYNC
+ rfi /* jump to handler, enable MMU */
+
+int_return:
+ mfmsr r28 /* Disable interrupts */
+ li r4,0
+ ori r4,r4,MSR_EE
+ andc r28,r28,r4
+ SYNC /* Some chip revs need this... */
+ mtmsr r28
+ SYNC
+ lwz r2,_CTR(r1)
+ lwz r0,_LINK(r1)
+ mtctr r2
+ mtlr r0
+ lwz r2,_XER(r1)
+ lwz r0,_CCR(r1)
+ mtspr XER,r2
+ mtcrf 0xFF,r0
+ REST_10GPRS(3, r1)
+ REST_10GPRS(13, r1)
+ REST_8GPRS(23, r1)
+ REST_GPR(31, r1)
+ lwz r2,_NIP(r1) /* Restore environment */
+ lwz r0,_MSR(r1)
+ mtspr SRR0,r2
+ mtspr SRR1,r0
+ lwz r0,GPR0(r1)
+ lwz r2,GPR2(r1)
+ lwz r1,GPR1(r1)
+ SYNC
+ rfi
+
+crit_return:
+ mfmsr r28 /* Disable interrupts */
+ li r4,0
+ ori r4,r4,MSR_EE
+ andc r28,r28,r4
+ SYNC /* Some chip revs need this... */
+ mtmsr r28
+ SYNC
+ lwz r2,_CTR(r1)
+ lwz r0,_LINK(r1)
+ mtctr r2
+ mtlr r0
+ lwz r2,_XER(r1)
+ lwz r0,_CCR(r1)
+ mtspr XER,r2
+ mtcrf 0xFF,r0
+ REST_10GPRS(3, r1)
+ REST_10GPRS(13, r1)
+ REST_8GPRS(23, r1)
+ REST_GPR(31, r1)
+ lwz r2,_NIP(r1) /* Restore environment */
+ lwz r0,_MSR(r1)
+ mtspr 990,r2 /* SRR2 */
+ mtspr 991,r0 /* SRR3 */
+ lwz r0,GPR0(r1)
+ lwz r2,GPR2(r1)
+ lwz r1,GPR1(r1)
+ SYNC
+ rfci
+
+/* Cache functions.
+*/
+invalidate_icache:
+ mfspr r0,L1CSR1
+ ori r0,r0,0x0002
+ mtspr L1CSR1,r0
+ isync
+ blr /* entire I cache */
+
+invalidate_dcache:
+ mfspr r0,L1CSR0
+ ori r0,r0,0x0002
+ msync
+ isync
+ mtspr L1CSR0,r0
+ isync
+ blr
+
+ .globl icache_enable
+icache_enable:
+ mflr r8
+ bl invalidate_icache
+ mtlr r8
+ isync
+ mfspr r4,L1CSR1
+ ori r4,r4,0x0001
+ oris r4,r4,0x0001
+ mtspr L1CSR1,r4
+ isync
+ blr
+
+ .globl icache_disable
+icache_disable:
+ mfspr r0,L1CSR1
+ lis r1,0xfffffffe@h
+ ori r1,r1,0xfffffffe@l
+ and r0,r0,r1
+ mtspr L1CSR1,r0
+ isync
+ blr
+
+ .globl icache_status
+icache_status:
+ mfspr r3,L1CSR1
+ srwi r3, r3, 31 /* >>31 => select bit 0 */
+ blr
+
+ .globl dcache_enable
+dcache_enable:
+ mflr r8
+ bl invalidate_dcache
+ mtlr r8
+ isync
+ mfspr r0,L1CSR0
+ ori r0,r0,0x0001
+ oris r0,r0,0x0001
+ msync
+ isync
+ mtspr L1CSR0,r0
+ isync
+ blr
+
+ .globl dcache_disable
+dcache_disable:
+ mfspr r0,L1CSR0
+ lis r1,0xfffffffe@h
+ ori r1,r1,0xfffffffe@l
+ and r0,r0,r1
+ msync
+ isync
+ mtspr L1CSR0,r0
+ isync
+ blr
+
+ .globl dcache_status
+dcache_status:
+ mfspr r3,L1CSR0
+ srwi r3, r3, 31 /* >>31 => select bit 0 */
+ blr
+
+ .globl get_pir
+get_pir:
+ mfspr r3, PIR
+ blr
+
+ .globl get_pvr
+get_pvr:
+ mfspr r3, PVR
+ blr
+
+ .globl wr_tcr
+wr_tcr:
+ mtspr TCR, r3
+ blr
+
+/*------------------------------------------------------------------------------- */
+/* Function: in8 */
+/* Description: Input 8 bits */
+/*------------------------------------------------------------------------------- */
+ .globl in8
+in8:
+ lbz r3,0x0000(r3)
+ blr
+
+/*------------------------------------------------------------------------------- */
+/* Function: out8 */
+/* Description: Output 8 bits */
+/*------------------------------------------------------------------------------- */
+ .globl out8
+out8:
+ stb r4,0x0000(r3)
+ blr
+
+/*------------------------------------------------------------------------------- */
+/* Function: out16 */
+/* Description: Output 16 bits */
+/*------------------------------------------------------------------------------- */
+ .globl out16
+out16:
+ sth r4,0x0000(r3)
+ blr
+
+/*------------------------------------------------------------------------------- */
+/* Function: out16r */
+/* Description: Byte reverse and output 16 bits */
+/*------------------------------------------------------------------------------- */
+ .globl out16r
+out16r:
+ sthbrx r4,r0,r3
+ blr
+
+/*------------------------------------------------------------------------------- */
+/* Function: out32 */
+/* Description: Output 32 bits */
+/*------------------------------------------------------------------------------- */
+ .globl out32
+out32:
+ stw r4,0x0000(r3)
+ blr
+
+/*------------------------------------------------------------------------------- */
+/* Function: out32r */
+/* Description: Byte reverse and output 32 bits */
+/*------------------------------------------------------------------------------- */
+ .globl out32r
+out32r:
+ stwbrx r4,r0,r3
+ blr
+
+/*------------------------------------------------------------------------------- */
+/* Function: in16 */
+/* Description: Input 16 bits */
+/*------------------------------------------------------------------------------- */
+ .globl in16
+in16:
+ lhz r3,0x0000(r3)
+ blr
+
+/*------------------------------------------------------------------------------- */
+/* Function: in16r */
+/* Description: Input 16 bits and byte reverse */
+/*------------------------------------------------------------------------------- */
+ .globl in16r
+in16r:
+ lhbrx r3,r0,r3
+ blr
+
+/*------------------------------------------------------------------------------- */
+/* Function: in32 */
+/* Description: Input 32 bits */
+/*------------------------------------------------------------------------------- */
+ .globl in32
+in32:
+ lwz 3,0x0000(3)
+ blr
+
+/*------------------------------------------------------------------------------- */
+/* Function: in32r */
+/* Description: Input 32 bits and byte reverse */
+/*------------------------------------------------------------------------------- */
+ .globl in32r
+in32r:
+ lwbrx r3,r0,r3
+ blr
+
+/*------------------------------------------------------------------------------- */
+/* Function: ppcDcbf */
+/* Description: Data Cache block flush */
+/* Input: r3 = effective address */
+/* Output: none. */
+/*------------------------------------------------------------------------------- */
+ .globl ppcDcbf
+ppcDcbf:
+ dcbf r0,r3
+ blr
+
+/*------------------------------------------------------------------------------- */
+/* Function: ppcDcbi */
+/* Description: Data Cache block Invalidate */
+/* Input: r3 = effective address */
+/* Output: none. */
+/*------------------------------------------------------------------------------- */
+ .globl ppcDcbi
+ppcDcbi:
+ dcbi r0,r3
+ blr
+
+/*------------------------------------------------------------------------------- */
+/* Function: ppcSync */
+/* Description: Processor Synchronize */
+/* Input: none. */
+/* Output: none. */
+/*------------------------------------------------------------------------------- */
+ .globl ppcSync
+ppcSync:
+ sync
+ blr
+
+/*------------------------------------------------------------------------------*/
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ * r3 = dest
+ * r4 = src
+ * r5 = length in bytes
+ * r6 = cachelinesize
+ */
+ .globl relocate_code
+relocate_code:
+ mr r1, r3 /* Set new stack pointer */
+ mr r9, r4 /* Save copy of Init Data pointer */
+ mr r10, r5 /* Save copy of Destination Address */
+
+ mr r3, r5 /* Destination Address */
+ lis r4, CFG_MONITOR_BASE@h /* Source Address */
+ ori r4, r4, CFG_MONITOR_BASE@l
+ lwz r5,GOT(__init_end)
+ sub r5,r5,r4
+ li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
+
+ /*
+ * Fix GOT pointer:
+ *
+ * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
+ *
+ * Offset:
+ */
+ sub r15, r10, r4
+
+ /* First our own GOT */
+ add r14, r14, r15
+ /* the the one used by the C code */
+ add r30, r30, r15
+
+ /*
+ * Now relocate code
+ */
+
+ cmplw cr1,r3,r4
+ addi r0,r5,3
+ srwi. r0,r0,2
+ beq cr1,4f /* In place copy is not necessary */
+ beq 7f /* Protect against 0 count */
+ mtctr r0
+ bge cr1,2f
+
+ la r8,-4(r4)
+ la r7,-4(r3)
+1: lwzu r0,4(r8)
+ stwu r0,4(r7)
+ bdnz 1b
+ b 4f
+
+2: slwi r0,r0,2
+ add r8,r4,r0
+ add r7,r3,r0
+3: lwzu r0,-4(r8)
+ stwu r0,-4(r7)
+ bdnz 3b
+
+/*
+ * Now flush the cache: note that we must start from a cache aligned
+ * address. Otherwise we might miss one cache line.
+ */
+4: cmpwi r6,0
+ add r5,r3,r5
+ beq 7f /* Always flush prefetch queue in any case */
+ subi r0,r6,1
+ andc r3,r3,r0
+ mr r4,r3
+5: dcbst 0,r4
+ add r4,r4,r6
+ cmplw r4,r5
+ blt 5b
+ sync /* Wait for all dcbst to complete on bus */
+ mr r4,r3
+6: icbi 0,r4
+ add r4,r4,r6
+ cmplw r4,r5
+ blt 6b
+7: sync /* Wait for all icbi to complete on bus */
+ isync
+
+/*
+ * We are done. Do not return, instead branch to second part of board
+ * initialization, now running from RAM.
+ */
+
+ addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
+ mtlr r0
+ blr /* NEVER RETURNS! */
+
+in_ram:
+
+ /*
+ * Relocation Function, r14 point to got2+0x8000
+ *
+ * Adjust got2 pointers, no need to check for 0, this code
+ * already puts a few entries in the table.
+ */
+ li r0,__got2_entries@sectoff@l
+ la r3,GOT(_GOT2_TABLE_)
+ lwz r11,GOT(_GOT2_TABLE_)
+ mtctr r0
+ sub r11,r3,r11
+ addi r3,r3,-4
+1: lwzu r0,4(r3)
+ add r0,r0,r11
+ stw r0,0(r3)
+ bdnz 1b
+
+ /*
+ * Now adjust the fixups and the pointers to the fixups
+ * in case we need to move ourselves again.
+ */
+2: li r0,__fixup_entries@sectoff@l
+ lwz r3,GOT(_FIXUP_TABLE_)
+ cmpwi r0,0
+ mtctr r0
+ addi r3,r3,-4
+ beq 4f
+3: lwzu r4,4(r3)
+ lwzux r0,r4,r11
+ add r0,r0,r11
+ stw r10,0(r3)
+ stw r0,0(r4)
+ bdnz 3b
+4:
+clear_bss:
+ /*
+ * Now clear BSS segment
+ */
+ lwz r3,GOT(__bss_start)
+ lwz r4,GOT(_end)
+
+ cmplw 0, r3, r4
+ beq 6f
+
+ li r0, 0
+5:
+ stw r0, 0(r3)
+ addi r3, r3, 4
+ cmplw 0, r3, r4
+ bne 5b
+6:
+
+ mr r3, r9 /* Init Data pointer */
+ mr r4, r10 /* Destination Address */
+ bl board_init_r
+
+ /*
+ * Copy exception vector code to low memory
+ *
+ * r3: dest_addr
+ * r7: source address, r8: end address, r9: target address
+ */
+ .globl trap_init
+trap_init:
+ lwz r7, GOT(_start)
+ lwz r8, GOT(_end_of_vectors)
+
+ li r9, 0x100 /* reset vector always at 0x100 */
+
+ cmplw 0, r7, r8
+ bgelr /* return if r7>=r8 - just in case */
+
+ mflr r4 /* save link register */
+1:
+ lwz r0, 0(r7)
+ stw r0, 0(r9)
+ addi r7, r7, 4
+ addi r9, r9, 4
+ cmplw 0, r7, r8
+ bne 1b
+
+ /*
+ * relocate `hdlr' and `int_return' entries
+ */
+ li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
+ li r8, Alignment - _start + EXC_OFF_SYS_RESET
+2:
+ bl trap_reloc
+ addi r7, r7, 0x100 /* next exception vector */
+ cmplw 0, r7, r8
+ blt 2b
+
+ li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
+ bl trap_reloc
+
+ li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
+ bl trap_reloc
+
+ li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
+ li r8, SystemCall - _start + EXC_OFF_SYS_RESET
+3:
+ bl trap_reloc
+ addi r7, r7, 0x100 /* next exception vector */
+ cmplw 0, r7, r8
+ blt 3b
+
+ li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
+ li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
+4:
+ bl trap_reloc
+ addi r7, r7, 0x100 /* next exception vector */
+ cmplw 0, r7, r8
+ blt 4b
+
+ mtlr r4 /* restore link register */
+ blr
+
+ /*
+ * Function: relocate entries for one exception vector
+ */
+trap_reloc:
+ lwz r0, 0(r7) /* hdlr ... */
+ add r0, r0, r3 /* ... += dest_addr */
+ stw r0, 0(r7)
+
+ lwz r0, 4(r7) /* int_return ... */
+ add r0, r0, r3 /* ... += dest_addr */
+ stw r0, 4(r7)
+
+ blr
+
+#ifdef CFG_INIT_RAM_LOCK
+.globl unlock_ram_in_cache
+unlock_ram_in_cache:
+ /* invalidate the INIT_RAM section */
+ lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
+ ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
+ li r2,512
+ mtctr r2
+1: icbi r0, r3
+ dcbi r0, r3
+ addi r3, r3, 32
+ bdnz 1b
+ sync /* Wait for all icbi to complete on bus */
+ isync
+ blr
+#endif
--- /dev/null
+/*
+ * linux/arch/ppc/kernel/traps.c
+ *
+ * Copyright (C) 2003 Motorola
+ * Modified by Xianghua Xiao(x.xiao@motorola.com)
+ *
+ * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
+ *
+ * Modified by Cort Dougan (cort@cs.nmt.edu)
+ * and Paul Mackerras (paulus@cs.anu.edu.au)
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * This file handles the architecture-dependent parts of hardware exceptions
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/processor.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+int (*debugger_exception_handler)(struct pt_regs *) = 0;
+#endif
+
+/* Returns 0 if exception not found and fixup otherwise. */
+extern unsigned long search_exception_table(unsigned long);
+
+/* THIS NEEDS CHANGING to use the board info structure.
+ */
+#define END_OF_MEM (CFG_SDRAM_SIZE * 1024 * 1024)
+
+
+static __inline__ void set_tsr(unsigned long val)
+{
+ asm volatile("mtspr 0x150, %0" : : "r" (val));
+}
+
+static __inline__ unsigned long get_esr(void)
+{
+ unsigned long val;
+ asm volatile("mfspr %0, 0x03e" : "=r" (val) :);
+ return val;
+}
+
+#define ESR_MCI 0x80000000
+#define ESR_PIL 0x08000000
+#define ESR_PPR 0x04000000
+#define ESR_PTR 0x02000000
+#define ESR_DST 0x00800000
+#define ESR_DIZ 0x00400000
+#define ESR_U0F 0x00008000
+
+#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG)
+extern void do_bedbug_breakpoint(struct pt_regs *);
+#endif
+
+/*
+ * Trap & Exception support
+ */
+
+void
+print_backtrace(unsigned long *sp)
+{
+ int cnt = 0;
+ unsigned long i;
+
+ printf("Call backtrace: ");
+ while (sp) {
+ if ((uint)sp > END_OF_MEM)
+ break;
+
+ i = sp[1];
+ if (cnt++ % 7 == 0)
+ printf("\n");
+ printf("%08lX ", i);
+ if (cnt > 32) break;
+ sp = (unsigned long *)*sp;
+ }
+ printf("\n");
+}
+
+void show_regs(struct pt_regs * regs)
+{
+ int i;
+
+ printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n",
+ regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar);
+ printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n",
+ regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0,
+ regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0,
+ regs->msr&MSR_IR ? 1 : 0,
+ regs->msr&MSR_DR ? 1 : 0);
+
+ printf("\n");
+ for (i = 0; i < 32; i++) {
+ if ((i % 8) == 0)
+ {
+ printf("GPR%02d: ", i);
+ }
+
+ printf("%08lX ", regs->gpr[i]);
+ if ((i % 8) == 7)
+ {
+ printf("\n");
+ }
+ }
+}
+
+
+void
+_exception(int signr, struct pt_regs *regs)
+{
+ show_regs(regs);
+ print_backtrace((unsigned long *)regs->gpr[1]);
+ panic("Exception in kernel pc %lx signal %d",regs->nip,signr);
+}
+
+void
+CritcalInputException(struct pt_regs *regs)
+{
+ panic("Critical Input Exception");
+}
+
+void
+MachineCheckException(struct pt_regs *regs)
+{
+ unsigned long fixup;
+
+ /* Probing PCI using config cycles cause this exception
+ * when a device is not present. Catch it and return to
+ * the PCI exception handler.
+ */
+ if ((fixup = search_exception_table(regs->nip)) != 0) {
+ regs->nip = fixup;
+ return;
+ }
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+ if (debugger_exception_handler && (*debugger_exception_handler)(regs))
+ return;
+#endif
+
+ printf("Machine check in kernel mode.\n");
+ printf("Caused by (from msr): ");
+ printf("regs %p ",regs);
+ switch( regs->msr & 0x0000F000)
+ {
+ case (1<<12) :
+ printf("Machine check signal - probably due to mm fault\n"
+ "with mmu off\n");
+ break;
+ case (1<<13) :
+ printf("Transfer error ack signal\n");
+ break;
+ case (1<<14) :
+ printf("Data parity signal\n");
+ break;
+ case (1<<15) :
+ printf("Address parity signal\n");
+ break;
+ default:
+ printf("Unknown values in msr\n");
+ }
+ show_regs(regs);
+ print_backtrace((unsigned long *)regs->gpr[1]);
+ panic("machine check");
+}
+
+void
+AlignmentException(struct pt_regs *regs)
+{
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+ if (debugger_exception_handler && (*debugger_exception_handler)(regs))
+ return;
+#endif
+
+ show_regs(regs);
+ print_backtrace((unsigned long *)regs->gpr[1]);
+ panic("Alignment Exception");
+}
+
+void
+ProgramCheckException(struct pt_regs *regs)
+{
+ long esr_val;
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+ if (debugger_exception_handler && (*debugger_exception_handler)(regs))
+ return;
+#endif
+
+ show_regs(regs);
+
+ esr_val = get_esr();
+ if( esr_val & ESR_PIL )
+ printf( "** Illegal Instruction **\n" );
+ else if( esr_val & ESR_PPR )
+ printf( "** Privileged Instruction **\n" );
+ else if( esr_val & ESR_PTR )
+ printf( "** Trap Instruction **\n" );
+
+ print_backtrace((unsigned long *)regs->gpr[1]);
+ panic("Program Check Exception");
+}
+
+void
+PITException(struct pt_regs *regs)
+{
+ /*
+ * Reset PIT interrupt
+ */
+ set_tsr(0x0c000000);
+
+ /*
+ * Call timer_interrupt routine in interrupts.c
+ */
+ timer_interrupt(NULL);
+}
+
+
+void
+UnknownException(struct pt_regs *regs)
+{
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+ if (debugger_exception_handler && (*debugger_exception_handler)(regs))
+ return;
+#endif
+
+ printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
+ regs->nip, regs->msr, regs->trap);
+ _exception(0, regs);
+}
+
+void
+DebugException(struct pt_regs *regs)
+{
+ printf("Debugger trap at @ %lx\n", regs->nip );
+ show_regs(regs);
+#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG)
+ do_bedbug_breakpoint( regs );
+#endif
+}
+
+/* Probe an address by reading. If not present, return -1, otherwise
+ * return 0.
+ */
+int
+addr_probe(uint *addr)
+{
+ return 0;
+}
--- /dev/null
+/*
+ * tsec.c
+ * Motorola Three Speed Ethernet Controller driver
+ *
+ * This software may be used and distributed according to the
+ * terms of the GNU Public License, Version 2, incorporated
+ * herein by reference.
+ *
+ * (C) Copyright 2003, Motorola, Inc.
+ * maintained by Xianghua Xiao (x.xiao@motorola.com)
+ * author Andy Fleming
+ *
+ */
+
+#include <config.h>
+#include <mpc85xx.h>
+#include <common.h>
+#include <malloc.h>
+#include <net.h>
+#include <command.h>
+
+#if defined(CONFIG_TSEC_ENET)
+#include "tsec.h"
+
+#define TX_BUF_CNT 2
+
+#undef TSEC_DEBUG
+#ifdef TSEC_DEBUG
+#define DBGPRINT(x) printf(x)
+#else
+#define DBGPRINT(x)
+#endif
+
+static uint rxIdx; /* index of the current RX buffer */
+static uint txIdx; /* index of the current TX buffer */
+
+typedef volatile struct rtxbd {
+ txbd8_t txbd[TX_BUF_CNT];
+ rxbd8_t rxbd[PKTBUFSRX];
+} RTXBD;
+
+#ifdef __GNUC__
+static RTXBD rtx __attribute__ ((aligned(8)));
+#else
+#error "rtx must be 64-bit aligned"
+#endif
+
+static int tsec_send(struct eth_device* dev, volatile void *packet, int length);
+static int tsec_recv(struct eth_device* dev);
+static int tsec_init(struct eth_device* dev, bd_t * bd);
+static void tsec_halt(struct eth_device* dev);
+static void init_registers(tsec_t *regs);
+static void startup_tsec(tsec_t *regs);
+static void init_phy(tsec_t *regs);
+
+/* Initialize device structure. returns 0 on failure, 1 on
+ * success */
+int tsec_initialize(bd_t *bis)
+{
+ struct eth_device* dev;
+ int i;
+
+ dev = (struct eth_device*) malloc(sizeof *dev);
+
+ if(dev == NULL)
+ return 0;
+
+ memset(dev, 0, sizeof *dev);
+
+ sprintf(dev->name, "MOTOROLA ETHERNET");
+ dev->iobase = 0;
+ dev->priv = 0;
+ dev->init = tsec_init;
+ dev->halt = tsec_halt;
+ dev->send = tsec_send;
+ dev->recv = tsec_recv;
+
+ /* Tell u-boot to get the addr from the env */
+ for(i=0;i<6;i++)
+ dev->enetaddr[i] = 0;
+
+ eth_register(dev);
+
+ return 1;
+}
+
+
+/* Initializes data structures and registers for the controller,
+ * and brings the interface up */
+int tsec_init(struct eth_device* dev, bd_t * bd)
+{
+ tsec_t *regs;
+ uint tempval;
+ char tmpbuf[MAC_ADDR_LEN];
+ int i;
+
+ regs = (tsec_t *)(TSEC_BASE_ADDR);
+
+ /* Make sure the controller is stopped */
+ tsec_halt(dev);
+
+ /* Reset the MAC */
+ regs->maccfg1 |= MACCFG1_SOFT_RESET;
+
+ /* Clear MACCFG1[Soft_Reset] */
+ regs->maccfg1 &= ~(MACCFG1_SOFT_RESET);
+
+ /* Init MACCFG2. Defaults to GMII/MII */
+ regs->maccfg2 = MACCFG2_INIT_SETTINGS;
+
+ /* Init ECNTRL */
+ regs->ecntrl = ECNTRL_INIT_SETTINGS;
+
+ /* Copy the station address into the address registers.
+ * Backwards, because little endian MACS are dumb */
+ for(i=0;i<MAC_ADDR_LEN;i++) {
+ tmpbuf[MAC_ADDR_LEN - 1 - i] = bd->bi_enetaddr[i];
+ }
+ (uint)(regs->macstnaddr1) = *((uint *)(tmpbuf));
+
+ tempval = *((uint *)(tmpbuf +4));
+
+ (uint)(regs->macstnaddr2) = tempval;
+
+ /* Initialize the PHY */
+ init_phy(regs);
+
+ /* reset the indices to zero */
+ rxIdx = 0;
+ txIdx = 0;
+
+ /* Clear out (for the most part) the other registers */
+ init_registers(regs);
+
+ /* Ready the device for tx/rx */
+ startup_tsec(regs);
+
+ return 1;
+
+}
+
+
+/* Reads from the register at offset in the PHY at phyid, */
+/* using the register set defined in regbase. It waits until the */
+/* bits in the miimstat are valid (miimind notvalid bit cleared), */
+/* and then passes those bits on to the variable specified in */
+/* value */
+/* Before it does the read, it needs to clear the command field */
+uint read_phy_reg(tsec_t *regbase, uint phyid, uint offset)
+{
+ uint value;
+
+ /* Put the address of the phy, and the register number into
+ * MIIMADD
+ */
+ regbase->miimadd = (phyid << 8) | offset;
+
+ /* Clear the command register, and wait */
+ regbase->miimcom = 0;
+ asm("msync");
+
+ /* Initiate a read command, and wait */
+ regbase->miimcom = MIIM_READ_COMMAND;
+ asm("msync");
+
+ /* Wait for the the indication that the read is done */
+ while((regbase->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY)));
+
+ /* Grab the value read from the PHY */
+ value = regbase->miimstat;
+
+ return value;
+}
+
+/* Setup the PHY */
+static void init_phy(tsec_t *regs)
+{
+ uint testval;
+ unsigned int timeout = TSEC_TIMEOUT;
+
+ /* Assign a Physical address to the TBI */
+ regs->tbipa=TBIPA_VALUE;
+
+ /* reset the management interface */
+ regs->miimcfg=MIIMCFG_RESET;
+
+ regs->miimcfg=MIIMCFG_INIT_VALUE;
+
+ /* Wait until the bus is free */
+ while(regs->miimind & MIIMIND_BUSY);
+
+#ifdef CONFIG_PHY_CIS8201
+ /* override PHY config settings */
+ write_phy_reg(regs, 0, MIIM_AUX_CONSTAT, MIIM_AUXCONSTAT_INIT);
+
+ /* Set up interface mode */
+ write_phy_reg(regs, 0, MIIM_EXT_CON1, MIIM_EXTCON1_INIT);
+#endif
+
+ /* Set the PHY to gigabit, full duplex, Auto-negotiate */
+ write_phy_reg(regs, 0, MIIM_CONTROL, MIIM_CONTROL_INIT);
+
+ /* Wait until TBI_STATUS indicates AN is done */
+ DBGPRINT("Waiting for Auto-negotiation to complete\n");
+ testval=read_phy_reg(regs, 0, MIIM_TBI_STATUS);
+
+ while((!(testval & MIIM_TBI_STATUS_AN_DONE))&& timeout--) {
+ testval=read_phy_reg(regs, 0, MIIM_TBI_STATUS);
+ }
+
+ if(testval & MIIM_TBI_STATUS_AN_DONE)
+ DBGPRINT("Auto-negotiation done\n");
+ else
+ DBGPRINT("Auto-negotiation timed-out.\n");
+
+#ifdef CONFIG_PHY_CIS8201
+ /* Find out what duplexity (duplicity?) we have */
+ /* Read it twice to make sure */
+ testval=read_phy_reg(regs, 0, MIIM_AUX_CONSTAT);
+
+ if(testval & MIIM_AUXCONSTAT_DUPLEX) {
+ DBGPRINT("Enet starting in full duplex\n");
+ regs->maccfg2 |= MACCFG2_FULL_DUPLEX;
+ } else {
+ DBGPRINT("Enet starting in half duplex\n");
+ regs->maccfg2 &= ~MACCFG2_FULL_DUPLEX;
+ }
+
+ /* Also, we look to see what speed we are at
+ * if Gigabit, MACCFG2 goes in GMII, otherwise,
+ * MII mode.
+ */
+ if((testval & MIIM_AUXCONSTAT_SPEED) != MIIM_AUXCONSTAT_GBIT) {
+ if((testval & MIIM_AUXCONSTAT_SPEED) == MIIM_AUXCONSTAT_100)
+ DBGPRINT("Enet starting in 100BT\n");
+ else
+ DBGPRINT("Enet starting in 10BT\n");
+
+ /* mark the mode in MACCFG2 */
+ regs->maccfg2 = ((regs->maccfg2&~(MACCFG2_IF)) | MACCFG2_MII);
+ } else {
+ DBGPRINT("Enet starting in 1000BT\n");
+ }
+
+#endif
+
+#ifdef CONFIG_PHY_M88E1011
+ /* Read the PHY to see what speed and duplex we are */
+ testval=read_phy_reg(regs, 0, MIIM_PHY_STATUS);
+
+ timeout = TSEC_TIMEOUT;
+ while((!(testval & MIIM_PHYSTAT_SPDDONE)) && timeout--) {
+ testval = read_phy_reg(regs,0,MIIM_PHY_STATUS);
+ }
+
+ if(!(testval & MIIM_PHYSTAT_SPDDONE))
+ DBGPRINT("Enet: Speed not resolved\n");
+
+ testval=read_phy_reg(regs, 0, MIIM_PHY_STATUS);
+ if(testval & MIIM_PHYSTAT_DUPLEX) {
+ DBGPRINT("Enet starting in Full Duplex\n");
+ regs->maccfg2 |= MACCFG2_FULL_DUPLEX;
+ } else {
+ DBGPRINT("Enet starting in Half Duplex\n");
+ regs->maccfg2 &= ~MACCFG2_FULL_DUPLEX;
+ }
+
+ if(!((testval&MIIM_PHYSTAT_SPEED) == MIIM_PHYSTAT_GBIT)) {
+ if((testval & MIIM_PHYSTAT_SPEED) == MIIM_PHYSTAT_100)
+ DBGPRINT("Enet starting in 100BT\n");
+ else
+ DBGPRINT("Enet starting in 10BT\n");
+
+ regs->maccfg2 = ((regs->maccfg2&~(MACCFG2_IF)) | MACCFG2_MII);
+ } else {
+ DBGPRINT("Enet starting in 1000BT\n");
+ }
+#endif
+
+}
+
+
+static void init_registers(tsec_t *regs)
+{
+ /* Clear IEVENT */
+ regs->ievent = IEVENT_INIT_CLEAR;
+
+ regs->imask = IMASK_INIT_CLEAR;
+
+ regs->hash.iaddr0 = 0;
+ regs->hash.iaddr1 = 0;
+ regs->hash.iaddr2 = 0;
+ regs->hash.iaddr3 = 0;
+ regs->hash.iaddr4 = 0;
+ regs->hash.iaddr5 = 0;
+ regs->hash.iaddr6 = 0;
+ regs->hash.iaddr7 = 0;
+
+ regs->hash.gaddr0 = 0;
+ regs->hash.gaddr1 = 0;
+ regs->hash.gaddr2 = 0;
+ regs->hash.gaddr3 = 0;
+ regs->hash.gaddr4 = 0;
+ regs->hash.gaddr5 = 0;
+ regs->hash.gaddr6 = 0;
+ regs->hash.gaddr7 = 0;
+
+ regs->rctrl = 0x00000000;
+
+ /* Init RMON mib registers */
+ memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t));
+
+ regs->rmon.cam1 = 0xffffffff;
+ regs->rmon.cam2 = 0xffffffff;
+
+ regs->mrblr = MRBLR_INIT_SETTINGS;
+
+ regs->minflr = MINFLR_INIT_SETTINGS;
+
+ regs->attr = ATTR_INIT_SETTINGS;
+ regs->attreli = ATTRELI_INIT_SETTINGS;
+
+}
+
+static void startup_tsec(tsec_t *regs)
+{
+ int i;
+
+ /* Point to the buffer descriptors */
+ regs->tbase = (unsigned int)(&rtx.txbd[txIdx]);
+ regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
+
+ /* Initialize the Rx Buffer descriptors */
+ for (i = 0; i < PKTBUFSRX; i++) {
+ rtx.rxbd[i].status = RXBD_EMPTY;
+ rtx.rxbd[i].length = 0;
+ rtx.rxbd[i].bufPtr = (uint)NetRxPackets[i];
+ }
+ rtx.rxbd[PKTBUFSRX -1].status |= RXBD_WRAP;
+
+ /* Initialize the TX Buffer Descriptors */
+ for(i=0; i<TX_BUF_CNT; i++) {
+ rtx.txbd[i].status = 0;
+ rtx.txbd[i].length = 0;
+ rtx.txbd[i].bufPtr = 0;
+ }
+ rtx.txbd[TX_BUF_CNT -1].status |= TXBD_WRAP;
+
+ /* Enable Transmit and Receive */
+ regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
+
+ /* Tell the DMA it is clear to go */
+ regs->dmactrl |= DMACTRL_INIT_SETTINGS;
+ regs->tstat = TSTAT_CLEAR_THALT;
+ regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
+}
+
+/* This returns the status bits of the device. The return value
+ * is never checked, and this is what the 8260 driver did, so we
+ * do the same. Presumably, this would be zero if there were no
+ * errors */
+static int tsec_send(struct eth_device* dev, volatile void *packet, int length)
+{
+ int i;
+ int result = 0;
+ tsec_t * regs = (tsec_t *)(TSEC_BASE_ADDR);
+
+ /* Find an empty buffer descriptor */
+ for(i=0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
+ if (i >= TOUT_LOOP) {
+ DBGPRINT("tsec: tx buffers full\n");
+ return result;
+ }
+ }
+
+ rtx.txbd[txIdx].bufPtr = (uint)packet;
+ rtx.txbd[txIdx].length = length;
+ rtx.txbd[txIdx].status |= (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT);
+
+ /* Tell the DMA to go */
+ regs->tstat = TSTAT_CLEAR_THALT;
+
+ /* Wait for buffer to be transmitted */
+ for(i=0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
+ if (i >= TOUT_LOOP) {
+ DBGPRINT("tsec: tx error\n");
+ return result;
+ }
+ }
+
+ txIdx = (txIdx + 1) % TX_BUF_CNT;
+ result = rtx.txbd[txIdx].status & TXBD_STATS;
+
+ return result;
+}
+
+static int tsec_recv(struct eth_device* dev)
+{
+ int length;
+ tsec_t *regs = (tsec_t *)(TSEC_BASE_ADDR);
+
+ while(!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) {
+
+ length = rtx.rxbd[rxIdx].length;
+
+ /* Send the packet up if there were no errors */
+ if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) {
+ NetReceive(NetRxPackets[rxIdx], length - 4);
+ }
+
+ rtx.rxbd[rxIdx].length = 0;
+
+ /* Set the wrap bit if this is the last element in the list */
+ rtx.rxbd[rxIdx].status = RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
+
+ rxIdx = (rxIdx + 1) % PKTBUFSRX;
+ }
+
+ if(regs->ievent&IEVENT_BSY) {
+ regs->ievent = IEVENT_BSY;
+ regs->rstat = RSTAT_CLEAR_RHALT;
+ }
+
+ return -1;
+
+}
+
+
+static void tsec_halt(struct eth_device* dev)
+{
+ tsec_t *regs = (tsec_t *)(TSEC_BASE_ADDR);
+
+ regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
+ regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS);
+
+ while(!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC)));
+
+ regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN);
+
+}
+#endif /* CONFIG_TSEC_ENET */
--- /dev/null
+/*
+ * tsec.h
+ *
+ * Driver for the Motorola Triple Speed Ethernet Controller
+ *
+ * This software may be used and distributed according to the
+ * terms of the GNU Public License, Version 2, incorporated
+ * herein by reference.
+ *
+ * (C) Copyright 2003, Motorola, Inc.
+ * maintained by Xianghua Xiao (x.xiao@motorola.com)
+ * author Andy Fleming
+ *
+ */
+
+#ifndef __TSEC_H
+#define __TSEC_H
+
+#include <net.h>
+#include <mpc85xx.h>
+
+#define TSEC_BASE_ADDR (CFG_IMMR + 0x24000)
+#define TSEC_MEM_SIZE 0x01000
+
+#define MAC_ADDR_LEN 6
+
+#define TSEC_TIMEOUT 1000000
+#define TOUT_LOOP 1000000
+
+/* MAC register bits */
+#define MACCFG1_SOFT_RESET 0x80000000
+#define MACCFG1_RESET_RX_MC 0x00080000
+#define MACCFG1_RESET_TX_MC 0x00040000
+#define MACCFG1_RESET_RX_FUN 0x00020000
+#define MACCFG1_RESET_TX_FUN 0x00010000
+#define MACCFG1_LOOPBACK 0x00000100
+#define MACCFG1_RX_FLOW 0x00000020
+#define MACCFG1_TX_FLOW 0x00000010
+#define MACCFG1_SYNCD_RX_EN 0x00000008
+#define MACCFG1_RX_EN 0x00000004
+#define MACCFG1_SYNCD_TX_EN 0x00000002
+#define MACCFG1_TX_EN 0x00000001
+
+#define MACCFG2_INIT_SETTINGS 0x00007205
+#define MACCFG2_FULL_DUPLEX 0x00000001
+#define MACCFG2_IF 0x00000300
+#define MACCFG2_MII 0x00000100
+
+#define ECNTRL_INIT_SETTINGS 0x00001000
+#define ECNTRL_TBI_MODE 0x00000020
+
+#define TBIPA_VALUE 0x1f
+#define MIIMCFG_INIT_VALUE 0x00000003
+#define MIIMCFG_RESET 0x80000000
+
+#define MIIMIND_BUSY 0x00000001
+#define MIIMIND_NOTVALID 0x00000004
+
+#define MIIM_TBICON 0x11
+#define MIIM_TBICON_GMII 0x00000010
+#define MIIM_TBICON_AN 0x00000100
+
+#define MIIM_CONTROL 0x00
+#define MIIM_CONTROL_INIT 0x00001140
+#define MIIM_ANEN 0x00001000
+
+#define MIIM_TBI_STATUS 0x1
+#define MIIM_TBI_STATUS_AN_DONE 0x00000020
+
+#define MIIM_TBI_ANEX 0x6
+#define MIIM_TBI_ANEX_NP 0x00000004
+#define MIIM_TBI_ANEX_PRX 0x00000002
+
+#define MIIM_TBI_ANLPBPA 0x5
+#define MIIM_TBI_ANLPBPA_HALF 0x00000040
+#define MIIM_TBI_ANLPBPA_FULL 0x00000020
+
+#ifdef CONFIG_PHY_CIS8201
+#define MIIM_AUX_CONSTAT 0x1c
+#define MIIM_AUXCONSTAT_INIT 0x0004
+#define MIIM_AUXCONSTAT_DUPLEX 0x0020
+#define MIIM_AUXCONSTAT_SPEED 0x0018
+#define MIIM_AUXCONSTAT_GBIT 0x0010
+#define MIIM_AUXCONSTAT_100 0x0008
+
+#define MIIM_EXT_CON1 0x17
+#define MIIM_EXTCON1_INIT 0x0000
+
+#endif
+
+#ifdef CONFIG_PHY_M88E1011
+#define MIIM_ANAR 0x04
+#define MIIM_ANAR_ADVERTISEMENT 0x01e1
+
+#define MIIM_GBIT_CON 0x09
+#define MIIM_GBIT_CON_ADVERT 0x1e00
+
+#define MIIM_PHY_STATUS 0x11
+#define MIIM_PHYSTAT_SPEED 0xc000
+#define MIIM_PHYSTAT_GBIT 0x8000
+#define MIIM_PHYSTAT_100 0x4000
+#define MIIM_PHYSTAT_DUPLEX 0x2000
+#define MIIM_PHYSTAT_SPDDONE 0x0800
+#define MIIM_PHYSTAT_LINK 0x0400
+#endif
+
+#define MIIM_READ_COMMAND 0x00000001
+
+#define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN
+
+#define MINFLR_INIT_SETTINGS 0x00000040
+
+#define DMACTRL_INIT_SETTINGS 0x000000c3
+#define DMACTRL_GRS 0x00000010
+#define DMACTRL_GTS 0x00000008
+
+#define TSTAT_CLEAR_THALT 0x80000000
+#define RSTAT_CLEAR_RHALT 0x00800000
+
+/* Write value to the PHY at phyid to the register at offset, */
+/* using the register space defined in regbase. Note that */
+/* miimcfg needs to have the clock speed setup correctly. This */
+/* macro will wait until the write is done before it finishes */
+#define write_phy_reg(regbase, phyid, offset, value) do { \
+ int timeout=1000000; \
+ regbase->miimadd = (phyid << 8) | offset; \
+ regbase->miimcon = value; \
+ asm("msync"); \
+ while((regbase->miimind & MIIMIND_BUSY) && timeout--); \
+} while(0)
+
+
+#define IEVENT_INIT_CLEAR 0xffffffff
+#define IEVENT_BABR 0x80000000
+#define IEVENT_RXC 0x40000000
+#define IEVENT_BSY 0x20000000
+#define IEVENT_EBERR 0x10000000
+#define IEVENT_MSRO 0x04000000
+#define IEVENT_GTSC 0x02000000
+#define IEVENT_BABT 0x01000000
+#define IEVENT_TXC 0x00800000
+#define IEVENT_TXE 0x00400000
+#define IEVENT_TXB 0x00200000
+#define IEVENT_TXF 0x00100000
+#define IEVENT_IE 0x00080000
+#define IEVENT_LC 0x00040000
+#define IEVENT_CRL 0x00020000
+#define IEVENT_XFUN 0x00010000
+#define IEVENT_RXB0 0x00008000
+#define IEVENT_GRSC 0x00000100
+#define IEVENT_RXF0 0x00000080
+
+#define IMASK_INIT_CLEAR 0x00000000
+#define IMASK_TXEEN 0x00400000
+#define IMASK_TXBEN 0x00200000
+#define IMASK_TXFEN 0x00100000
+#define IMASK_RXFEN0 0x00000080
+
+
+/* Default Attribute fields */
+#define ATTR_INIT_SETTINGS 0x000000c0
+#define ATTRELI_INIT_SETTINGS 0x00000000
+
+
+/* TxBD status field bits */
+#define TXBD_READY 0x8000
+#define TXBD_PADCRC 0x4000
+#define TXBD_WRAP 0x2000
+#define TXBD_INTERRUPT 0x1000
+#define TXBD_LAST 0x0800
+#define TXBD_CRC 0x0400
+#define TXBD_DEF 0x0200
+#define TXBD_HUGEFRAME 0x0080
+#define TXBD_LATECOLLISION 0x0080
+#define TXBD_RETRYLIMIT 0x0040
+#define TXBD_RETRYCOUNTMASK 0x003c
+#define TXBD_UNDERRUN 0x0002
+#define TXBD_STATS 0x03ff
+
+/* RxBD status field bits */
+#define RXBD_EMPTY 0x8000
+#define RXBD_RO1 0x4000
+#define RXBD_WRAP 0x2000
+#define RXBD_INTERRUPT 0x1000
+#define RXBD_LAST 0x0800
+#define RXBD_FIRST 0x0400
+#define RXBD_MISS 0x0100
+#define RXBD_BROADCAST 0x0080
+#define RXBD_MULTICAST 0x0040
+#define RXBD_LARGE 0x0020
+#define RXBD_NONOCTET 0x0010
+#define RXBD_SHORT 0x0008
+#define RXBD_CRCERR 0x0004
+#define RXBD_OVERRUN 0x0002
+#define RXBD_TRUNCATED 0x0001
+#define RXBD_STATS 0x003f
+
+typedef struct txbd8
+{
+ ushort status; /* Status Fields */
+ ushort length; /* Buffer length */
+ uint bufPtr; /* Buffer Pointer */
+} txbd8_t;
+
+typedef struct rxbd8
+{
+ ushort status; /* Status Fields */
+ ushort length; /* Buffer Length */
+ uint bufPtr; /* Buffer Pointer */
+} rxbd8_t;
+
+typedef struct rmon_mib
+{
+ /* Transmit and Receive Counters */
+ uint tr64; /* Transmit and Receive 64-byte Frame Counter */
+ uint tr127; /* Transmit and Receive 65-127 byte Frame Counter */
+ uint tr255; /* Transmit and Receive 128-255 byte Frame Counter */
+ uint tr511; /* Transmit and Receive 256-511 byte Frame Counter */
+ uint tr1k; /* Transmit and Receive 512-1023 byte Frame Counter */
+ uint trmax; /* Transmit and Receive 1024-1518 byte Frame Counter */
+ uint trmgv; /* Transmit and Receive 1519-1522 byte Good VLAN Frame */
+ /* Receive Counters */
+ uint rbyt; /* Receive Byte Counter */
+ uint rpkt; /* Receive Packet Counter */
+ uint rfcs; /* Receive FCS Error Counter */
+ uint rmca; /* Receive Multicast Packet (Counter) */
+ uint rbca; /* Receive Broadcast Packet */
+ uint rxcf; /* Receive Control Frame Packet */
+ uint rxpf; /* Receive Pause Frame Packet */
+ uint rxuo; /* Receive Unknown OP Code */
+ uint raln; /* Receive Alignment Error */
+ uint rflr; /* Receive Frame Length Error */
+ uint rcde; /* Receive Code Error */
+ uint rcse; /* Receive Carrier Sense Error */
+ uint rund; /* Receive Undersize Packet */
+ uint rovr; /* Receive Oversize Packet */
+ uint rfrg; /* Receive Fragments */
+ uint rjbr; /* Receive Jabber */
+ uint rdrp; /* Receive Drop */
+ /* Transmit Counters */
+ uint tbyt; /* Transmit Byte Counter */
+ uint tpkt; /* Transmit Packet */
+ uint tmca; /* Transmit Multicast Packet */
+ uint tbca; /* Transmit Broadcast Packet */
+ uint txpf; /* Transmit Pause Control Frame */
+ uint tdfr; /* Transmit Deferral Packet */
+ uint tedf; /* Transmit Excessive Deferral Packet */
+ uint tscl; /* Transmit Single Collision Packet */
+ /* (0x2_n700) */
+ uint tmcl; /* Transmit Multiple Collision Packet */
+ uint tlcl; /* Transmit Late Collision Packet */
+ uint txcl; /* Transmit Excessive Collision Packet */
+ uint tncl; /* Transmit Total Collision */
+
+ uint res2;
+
+ uint tdrp; /* Transmit Drop Frame */
+ uint tjbr; /* Transmit Jabber Frame */
+ uint tfcs; /* Transmit FCS Error */
+ uint txcf; /* Transmit Control Frame */
+ uint tovr; /* Transmit Oversize Frame */
+ uint tund; /* Transmit Undersize Frame */
+ uint tfrg; /* Transmit Fragments Frame */
+ /* General Registers */
+ uint car1; /* Carry Register One */
+ uint car2; /* Carry Register Two */
+ uint cam1; /* Carry Register One Mask */
+ uint cam2; /* Carry Register Two Mask */
+} rmon_mib_t;
+
+typedef struct tsec_hash_regs
+{
+ uint iaddr0; /* Individual Address Register 0 */
+ uint iaddr1; /* Individual Address Register 1 */
+ uint iaddr2; /* Individual Address Register 2 */
+ uint iaddr3; /* Individual Address Register 3 */
+ uint iaddr4; /* Individual Address Register 4 */
+ uint iaddr5; /* Individual Address Register 5 */
+ uint iaddr6; /* Individual Address Register 6 */
+ uint iaddr7; /* Individual Address Register 7 */
+ uint res1[24];
+ uint gaddr0; /* Group Address Register 0 */
+ uint gaddr1; /* Group Address Register 1 */
+ uint gaddr2; /* Group Address Register 2 */
+ uint gaddr3; /* Group Address Register 3 */
+ uint gaddr4; /* Group Address Register 4 */
+ uint gaddr5; /* Group Address Register 5 */
+ uint gaddr6; /* Group Address Register 6 */
+ uint gaddr7; /* Group Address Register 7 */
+ uint res2[24];
+} tsec_hash_t;
+
+typedef struct tsec
+{
+ /* General Control and Status Registers (0x2_n000) */
+ uint res000[4];
+
+ uint ievent; /* Interrupt Event */
+ uint imask; /* Interrupt Mask */
+ uint edis; /* Error Disabled */
+ uint res01c;
+ uint ecntrl; /* Ethernet Control */
+ uint minflr; /* Minimum Frame Length */
+ uint ptv; /* Pause Time Value */
+ uint dmactrl; /* DMA Control */
+ uint tbipa; /* TBI PHY Address */
+
+ uint res034[3];
+ uint res040[48];
+
+ /* Transmit Control and Status Registers (0x2_n100) */
+ uint tctrl; /* Transmit Control */
+ uint tstat; /* Transmit Status */
+ uint res108;
+ uint tbdlen; /* Tx BD Data Length */
+ uint res110[5];
+ uint ctbptr; /* Current TxBD Pointer */
+ uint res128[23];
+ uint tbptr; /* TxBD Pointer */
+ uint res188[30];
+ /* (0x2_n200) */
+ uint res200;
+ uint tbase; /* TxBD Base Address */
+ uint res208[42];
+ uint ostbd; /* Out of Sequence TxBD */
+ uint ostbdp; /* Out of Sequence Tx Data Buffer Pointer */
+ uint res2b8[18];
+
+ /* Receive Control and Status Registers (0x2_n300) */
+ uint rctrl; /* Receive Control */
+ uint rstat; /* Receive Status */
+ uint res308;
+ uint rbdlen; /* RxBD Data Length */
+ uint res310[4];
+ uint res320;
+ uint crbptr; /* Current Receive Buffer Pointer */
+ uint res328[6];
+ uint mrblr; /* Maximum Receive Buffer Length */
+ uint res344[16];
+ uint rbptr; /* RxBD Pointer */
+ uint res388[30];
+ /* (0x2_n400) */
+ uint res400;
+ uint rbase; /* RxBD Base Address */
+ uint res408[62];
+
+ /* MAC Registers (0x2_n500) */
+ uint maccfg1; /* MAC Configuration #1 */
+ uint maccfg2; /* MAC Configuration #2 */
+ uint ipgifg; /* Inter Packet Gap/Inter Frame Gap */
+ uint hafdup; /* Half-duplex */
+ uint maxfrm; /* Maximum Frame */
+ uint res514;
+ uint res518;
+
+ uint res51c;
+
+ uint miimcfg; /* MII Management: Configuration */
+ uint miimcom; /* MII Management: Command */
+ uint miimadd; /* MII Management: Address */
+ uint miimcon; /* MII Management: Control */
+ uint miimstat; /* MII Management: Status */
+ uint miimind; /* MII Management: Indicators */
+
+ uint res538;
+
+ uint ifstat; /* Interface Status */
+ uint macstnaddr1; /* Station Address, part 1 */
+ uint macstnaddr2; /* Station Address, part 2 */
+ uint res548[46];
+
+ /* (0x2_n600) */
+ uint res600[32];
+
+ /* RMON MIB Registers (0x2_n680-0x2_n73c) */
+ rmon_mib_t rmon;
+ uint res740[48];
+
+ /* Hash Function Registers (0x2_n800) */
+ tsec_hash_t hash;
+
+ uint res900[128];
+
+ /* Pattern Registers (0x2_nb00) */
+ uint resb00[62];
+ uint attr; /* Default Attribute Register */
+ uint attreli; /* Default Attribute Extract Length and Index */
+
+ /* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */
+ uint resc00[256];
+} tsec_t;
+
+#endif /* __TSEC_H */
switch (k) {
#ifdef CONFIG_MPC866_et_al
- /* MPC866P/MPC866T/MPC859T/MPC859DSL/MPC852T */
+ /* MPC866P/MPC866T/MPC859T/MPC859DSL/MPC852T */
case 0x08000003: pre = 'M'; suf = ""; m = 1; break;
#else
case 0x00020001: pre = 'p'; suf = ""; break;
putc ('\n');
#ifdef DEBUG
- if(clock != measure_gclk()) {
- printf ("clock %ldHz != %dHz\n", clock, measure_gclk());
- }
+ if(clock != measure_gclk()) {
+ printf ("clock %ldHz != %dHz\n", clock, measure_gclk());
+ }
#endif
return 0;
}
#define PLPRCR_val(a) (((CFG_PLPRCR) & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT)
#ifdef CONFIG_MPC866_et_al
- /* MFN
- MFI + -------
- MFD + 1
- factor = -----------------
- (PDF + 1) * 2^S
- */
+ /* MFN
+ MFI + -------
+ MFD + 1
+ factor = -----------------
+ (PDF + 1) * 2^S
+ */
factor = (PLPRCR_val(MFI) + PLPRCR_val(MFN)/(PLPRCR_val(MFD)+1))/
-
(PLPRCR_val(PDF)+1) / (1<<PLPRCR_val(S));
+ (PLPRCR_val(PDF)+1) / (1<<PLPRCR_val(S));
#else
factor = PLPRCR_val(MF)+1;
#endif
ulong msr_val;
#ifdef CONFIG_MPC866_et_al
- /* dont use OSCM, only use EXTCLK/512 */
- immr->im_clkrst.car_sccr |= SCCR_RTSEL | SCCR_RTDIV;
+ /* dont use OSCM, only use EXTCLK/512 */
+ immr->im_clkrst.car_sccr |= SCCR_RTSEL | SCCR_RTDIV;
#else
- immr->im_clkrst.car_sccr &= ~(SCCR_RTSEL | SCCR_RTDIV);
+ immr->im_clkrst.car_sccr &= ~(SCCR_RTSEL | SCCR_RTDIV);
#endif
/* Reset + Stop Timer 2, no cascading
immr->im_sit.sit_piscr &= ~PISCR_PTE;
#ifdef CONFIG_MPC866_et_al
- /* not using OSCM, using XIN, so scale appropriately */
+ /* not using OSCM, using XIN, so scale appropriately */
return (((timer2_val + 2) / 4) * (CFG_8XX_XIN/512))/8192 * 100000L;
#else
return ((timer2_val + 2) / 4) * 100000L; /* convert to Hz */
MMC_CLKRT = 0; /* 20 MHz */
resp = mmc_cmd(7, MMC_DEFAULT_RCA, 0, MMC_CMDAT_R1);
- fat_register_device(&mmc_dev,1); /* partitions start counting with 1 */
+ fat_register_device(&mmc_dev,1); /* partitions start counting with 1 */
return rc;
}
go 0xb0000000
-
Ethernet autonegotiation needs some time to complete. Instead of
delaying the boot process in all cases, we just start the
autonegotiation process when U-Boot comes up and that is all. Most
--- /dev/null
+Motorola MPC8540ADS and MPC8560ADS board
+
+Xianghua Xiao(X.Xiao@motorola.com)
+Created 10/15/03
+-----------------------------------------
+
+1. SWITCH SETTINGS & JUMPERS
+1.1 First, make sure the board default setting is consistent with the document
+ shipped with your board. Then apply the following changes:
+ SW3[1-6]="all OFF" (boot from 32bit flash, no boot sequence is used)
+ SW10[2-6]="all OFF" (turn on CPM SCC for serial port,works for 8540/8560)
+ SW11[2]='OFF for dracom, ON for draco' (single switch to toggle draco.dracom mode)
+ SW4[7-8]="OFF OFF" (enable serial ports,I'm using the top serial connector)
+ SW22[1-4]="OFF OFF ON OFF"
+ SW5[1-10[="ON ON OFF OFF OFF OFF OFF OFF OFF OFF"
+ J1 = "Enable Prog" (Make sure your flash is programmable for development)
+ Ethernet PHY connectors(J47,J56) should be removed if you want to use the ethernet.
+1.2 If you want to test PCI functionality with a 33Mhz PCI card, you will have to change
+ the system clock from the default 66Mhz to 33Mhz by setting SW15[1]="OFF" and
+ SW17[8]="OFF". After that you may also need double your platform clock(SW6) because
+ the system clock is now only half of its original value.
+1.3 SW6 is a very important switch, it decides your platform clock and CPU clock based on
+ the on-board system clock(default 66MHz). Check the document along with your board
+ for details.
+
+2. MEMORY MAP TO WORK WITH LINUX KERNEL
+2.1. For the initial bringup, we adopted a consistent memory scheme between u-boot and
+ linux kernel, you can customize it based on your system requirements:
+ DDR: 0x00000000-0x1fffffff (max 512MB)
+ PCI: 0xe0000000-0xefffffff (256MB)
+ RIO: 0xf0000000-0xf7ffffff (128MB)
+ Local SDRAM: 0xf8000000-0xfbffffff (64MB)
+ Local CSx: 0xfc000000-0xfdefffff (31MB) BCSR,RTC,ATM config,etc.
+ CCSRBAR: 0xfdf00000-0xfdffffff (1MB)
+ Flash: 0xfe000000-0xffffffff (max 32MB)
+2.2 We are submitting Linux kernel patches for MPC8540 and MPC8560. Hope you will be
+ able to download them from linuxppc-2.4 public source by the time you are reading
+ this. Please make sure the kernel's ppcboot.h is consistent with U-Boot's u-boot.h,
+ then you can use two default configuration files in the kernel source as a test:
+ arch/ppc/configs/mpc8540ads_defconfig
+ arch/ppc/configs/mpc8560ads_defconfig
+
+3. DEFINITIONS AND COMPILATION
+3.1 Explanation on NEW definitions in include/configs/MPC8540ADS.h and include/
+ configs/MPC8560ADS.h
+ CONFIG_BOOKE BOOKE(e.g. Motorola MPC85xx, IBM 440, etc)
+ CONFIG_E500 BOOKE e500 family(Motorola)
+ CONFIG_MPC85xx MPC8540,MPC8560 and their derivatives
+ CONFIG_MPC85xx_REV1 MPC85xx Rev 1 Chip, in general you will use a Rev2
+ chip from Nov.2003. If you still see this definition
+ while you have a Rev2(and newer) chip,undef this.
+ CONFIG_MPC8540 MPC8540 specific
+ CONFIG_MPC8560 MPC8560 specific
+ CONFIG_MPC8540ADS MPC8540ADS board specific
+ CONFIG_MPC8560ADS MPC8560ADS board specific
+ CONFIG_TSEC_ENET Use on-chip 10/100/1000 ethernet for networking
+ CONFIG_SPD_EEPROM Use SPD EEPROM for DDR auto configuration, you can also
+ manual config the DDR after undef this definition.
+ CONFIG_DDR_ECC only for ECC DDR module
+ CONFIG_DDR_DLL possible DLL fix needed for Rev1 chip for more stability.
+ you can disable this if you're having a newer chip.
+ CONFIG_RAM_AS_FLASH after define this, you can load U-Boot into localbus
+ SDRAM and treat localbus SDRAM as a flash. We use this
+ memory based U-Boot before flash is working while Metrowerks
+ and Windriver are still working on their flash/JTAG tools.
+ if you can program the flash directly, undef this.
+ Other than the above definitions, the rest in the config files are straightforward.
+
+
+3.2 Compilation
+ export CROSS_COMPILE=your-cross-compile-prefix(assuming you're using BASH shell)
+ cd u-boot
+ make distclean
+ make MPC8560ADS_config (or make MPC8540ADS_config)
+ make
+
+4. Note on the 10/100/1000 Ethernet controller:
+4.1 Sometimes after U-Boot is up, the 'tftp' won't work well with TSEC ethernet. If that
+ happens, you can try the following steps to make network work:
+ MPC8560ADS>tftp 1000000 pImage
+ (if it hangs, use Ctrl-C to quit)
+ MPC8560ADS>nm fdf24524
+ >0
+ >1
+ >. (to quit this memory operation)
+ MPC8560ADS>tftp 1000000 pImage
+
+5. Screen dump:
+5.1 MPC8540ADS board
+U-Boot 1.0.0-pre (Oct 15 2003 - 13:40:33)
+
+Motorola PowerPC ProcessorID=00000000 Rev. PVR=80200010
+Board: Motorola MPC8540ADS Board
+ CPU: 792 MHz
+ CCB: 264 MHz
+ DDR: 132 MHz
+ LBC: 66 MHz
+L1 D-cache 32KB, L1 I-cache 32KB enabled.
+I2C: ready
+DRAM: DDR module detected, total size:128MB.
+128 MB
+FLASH: 16 MB
+L2 cache enabled: 256KB
+*** Warning - bad CRC, using default environment
+
+In: serial
+Out: serial
+Err: serial
+Net: MOTOROLA ETHERNE
+Hit any key to stop autoboot: 0
+MPC8540ADS=> fli
+
+Bank # 1: Intel 28F640J3A (64 Mbit, 64 x 128K)
+ Size: 16 MB in 64 Sectors
+ Sector Start Addresses:
+ FF000000 FF040000 FF080000 FF0C0000 FF100000
+ FF140000 FF180000 FF1C0000 FF200000 FF240000
+ FF280000 FF2C0000 FF300000 FF340000 FF380000
+ FF3C0000 FF400000 FF440000 FF480000 FF4C0000
+ FF500000 FF540000 FF580000 FF5C0000 FF600000
+ FF640000 FF680000 FF6C0000 FF700000 FF740000
+ FF780000 FF7C0000 FF800000 FF840000 FF880000
+ FF8C0000 FF900000 FF940000 FF980000 FF9C0000
+ FFA00000 FFA40000 FFA80000 FFAC0000 FFB00000
+ FFB40000 FFB80000 FFBC0000 FFC00000 FFC40000
+ FFC80000 FFCC0000 FFD00000 FFD40000 FFD80000
+ FFDC0000 FFE00000 FFE40000 FFE80000 FFEC0000
+ FFF00000 FFF40000 FFF80000 (RO) FFFC0000 (RO)
+MPC8540ADS=> imi ff000000
+
+## Checking Image at ff000000 ...
+ Image Name: Linux-2.4.21-rc5
+ Image Type: PowerPC Linux Kernel Image (gzip compressed)
+ Data Size: 800594 Bytes = 781.8 kB
+ Load Address: 00000000
+ Entry Point: 00000000
+ Verifying Checksum ... OK
+MPC8540ADS=> bdinfo
+memstart = 0x00000000
+memsize = 0x08000000
+flashstart = 0xFF000000
+flashsize = 0x01000000
+flashoffset = 0x00000000
+sramstart = 0x00000000
+sramsize = 0x00000000
+immr_base = 0xFDF00000
+bootflags = 0x40003F80
+intfreq = 792 MHz
+busfreq = 264 MHz
+ethaddr = 00:01:AF:07:9B:8A
+eth1addr = 00:01:AF:07:9B:8B
+eth2addr = 00:01:AF:07:9B:8C
+IP addr = 10.82.0.105
+baudrate = 115200 bps
+MPC8540ADS=> printenv
+bootargs=root=/dev/nfs rw nfsroot=163.12.64.52:/localhome/r6aads/linuxppc/target ip=10.82.0.105:163.12.64.52:10.82.1.254:255.255.254.0:mpc8540ads-003:eth0:off console=ttyS0,115200
+bootcmd=bootm 0xff300000 0xff700000
+bootdelay=3
+baudrate=115200
+loads_echo=1
+ethaddr=00:01:af:07:9b:8a
+eth1addr=00:01:af:07:9b:8b
+eth2addr=00:01:af:07:9b:8c
+ipaddr=10.82.0.105
+serverip=163.12.64.52
+rootpath=/home/r6aads/mpclinux/eldk-2.0.2/ppc_82xx
+gatewayip=10.82.1.254
+netmask=255.255.254.0
+hostname=MPC8560ADS_PILOT_003
+bootfile=pImage
+stdin=serial
+stdout=serial
+stderr=serial
+
+Environment size: 560/8188 bytes
+MPC8540ADS=> bootm ff000000
+## Booting image at ff000000 ...
+ Image Name: Linux-2.4.21-rc5
+ Image Type: PowerPC Linux Kernel Image (gzip compressed)
+ Data Size: 800594 Bytes = 781.8 kB
+ Load Address: 00000000
+ Entry Point: 00000000
+ Verifying Checksum ... OK
+ Uncompressing Kernel Image ... OK
+mpc85xx_init(): exit
+id mach(): done
+MMU:enter
+Memory CAM mapping: CAM0=64Mb, CAM1=64Mb, CAM2=0Mb residual: 0Mb
+MMU:hw init
+MMU:mapin
+MMU:mapin_ram done
+MMU:setio
+MMU:exit
+Linux version 2.4.21-rc5 (@etest) (gcc version 2.95.3 20010315 (release)) #1 Wed Oct 15 09:05:42 CDT 2003
+setup_arch: enter
+setup_arch: bootmem
+mpc85xx_setup_arch
+Host Bridge Vendor ID = 1057
+Host Bridge Device ID = 3
+Host Bridge header = 0
+arch: exit
+On node 0 totalpages: 32768
+zone(0): 32768 pages.
+zone(1): 0 pages.
+zone(2): 0 pages.
+Kernel command line: root=/dev/nfs rw nfsroot=163.12.64.52:/localhome/r6aads/linuxppc/target ip=10.82.0.105:163.12.64.52:10.82.1.254:255.255.254.0:mpc8540ads-003:eth0:off console=ttyS0,115200
+openpic: enter
+OpenPIC Version 1.2 (1 CPUs and 44 IRQ sources) at fdf40000
+openpic: timer
+openpic: external
+openpic: spurious
+openpic: exit
+time_init: decrementer frequency = 33.000000 MHz
+Calibrating delay loop... 226.09 BogoMIPS
+Memory: 127488k available (1344k kernel code, 448k data, 248k init, 0k highmem)
+Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
+Inode cache hash table entries: 8192 (order: 4, 65536 bytes)
+Mount cache hash table entries: 512 (order: 0, 4096 bytes)
+Buffer-cache hash table entries: 8192 (order: 3, 32768 bytes)
+Page-cache hash table entries: 32768 (order: 5, 131072 bytes)
+POSIX conformance testing by UNIFIX
+PCI: Probing PCI hardware
+
+Linux NET4.0 for Linux 2.4
+Based upon Swansea University Computer Society NET3.039
+Initializing RT netlink socket
+Starting kswapd
+Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
+pty: 256 Unix98 ptys configured
+Serial driver version 5.05c (2001-07-08) with MANY_PORTS SHARE_IRQ SERIAL_PCI enabled
+ttyS00 at 0xfdf04500 (irq = 90) is a 16550A
+ttyS01 at 0xfdf04600 (irq = 0) is a 16550A
+eth0: Three Speed Ethernet Controller Version 0.2, 00:01:af:07:9b:8a:
+eth1: Three Speed Ethernet Controller Version 0.2, 00:01:af:07:9b:8b:
+RAMDISK driver initialized: 16 RAM disks of 32768K size 1024 blocksize
+loop: loaded (max 8 devices)
+Intel(R) PRO/1000 Network Driver - version 5.0.43-k1
+Copyright (c) 1999-2003 Intel Corporation.
+PPP generic driver version 2.4.2
+PPP Deflate Compression module registered
+NET4: Linux TCP/IP 1.0 for NET4.0
+IP Protocols: ICMP, UDP, TCP, IGMP
+IP: routing cache hash table of 1024 buckets, 8Kbytes
+TCP: Hash tables configured (established 8192 bind 8192)
+IP-Config: Complete:
+ device=eth0, addr=10.82.0.105, mask=255.255.254.0, gw=10.82.1.254,
+ host=mpc8540ads-003, domain=, nis-domain=(none),
+ bootserver=163.12.64.52, rootserver=163.12.64.52, rootpath=
+NET4: Unix domain sockets 1.0/SMP for Linux NET4.0.
+Looking up port of RPC 100003/2 on 163.12.64.52
+Looking up port of RPC 100005/1 on 163.12.64.52
+VFS: Mounted root (nfs filesystem).
+Freeing unused kernel memory: 248k init
+INIT: version 2.78 booting
+Activating swap...
+Checking all file systems...
+Parallelizing fsck version 1.22 (22-Jun-2001)
+Mounting local filesystems...
+nothing was mounted
+Cleaning: /etc/network/ifstate.
+Setting up IP spoofing protection: rp_filter.
+Disable TCP/IP Explicit Congestion Notification: done.
+Configuring network interfaces: done.
+Starting portmap daemon: portmap.
+Cleaning: /tmp /var/lock /var/run.
+INIT: Entering runlevel: 2
+Starting system log daemon: syslogd klogd.
+Starting internet superserver: inetd.
+
+mpc8540ads-003 login: root
+Last login: Thu Jan 1 00:00:07 1970 on console
+Linux mpc8540ads-003 2.4.21-rc5 #1 Wed Oct 15 09:05:42 CDT 2003 ppc unknown
+
+root@mpc8540ads-003:~# ls
+21142.o aa e100.o hello.o mii.o timer.o
+root@mpc8540ads-003:~# /sbin/ifconfig
+eth0 Link encap:Ethernet HWaddr 00:01:AF:07:9B:8A
+ inet addr:10.82.0.105 Bcast:10.82.1.255 Mask:255.255.254.0
+ UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1
+ RX packets:4576 errors:0 dropped:0 overruns:0 frame:0
+ TX packets:2587 errors:0 dropped:0 overruns:0 carrier:0
+ collisions:0 txqueuelen:100
+ RX bytes:4457023 (4.2 Mb) TX bytes:437770 (427.5 Kb)
+ Base address:0x4000
+
+lo Link encap:Local Loopback
+ inet addr:127.0.0.1 Mask:255.0.0.0
+ UP LOOPBACK RUNNING MTU:16436 Metric:1
+ RX packets:4 errors:0 dropped:0 overruns:0 frame:0
+ TX packets:4 errors:0 dropped:0 overruns:0 carrier:0
+ collisions:0 txqueuelen:0
+ RX bytes:296 (296.0 b) TX bytes:296 (296.0 b)
+
+root@mpc8540ads-003:~# ping 163.12.64.52
+PING 163.12.64.52 (163.12.64.52): 56 data bytes
+64 bytes from 163.12.64.52: icmp_seq=0 ttl=63 time=0.2 ms
+64 bytes from 163.12.64.52: icmp_seq=1 ttl=63 time=0.1 ms
+64 bytes from 163.12.64.52: icmp_seq=2 ttl=63 time=0.1 ms
+
+--- 163.12.64.52 ping statistics ---
+3 packets transmitted, 3 packets received, 0% packet loss
+round-trip min/avg/max = 0.1/0.1/0.2 ms
+root@mpc8540ads-003:~#
+
+5.2 MPC8560ADS board
+U-Boot 1.0.0-pre (Oct 15 2003 - 13:42:04)
+
+Motorola PowerPC ProcessorID=00000000 Rev. PVR=80200010
+Board: Motorola MPC8560ADS Board
+ CPU: 792 MHz
+ CCB: 264 MHz
+ DDR: 132 MHz
+ LBC: 66 MHz
+ CPM: 264 Mhz
+L1 D-cache 32KB, L1 I-cache 32KB enabled.
+I2C: ready
+DRAM: DDR module detected, total size:128MB.
+128 MB
+FLASH: 16 MB
+L2 cache enabled: 256KB
+*** Warning - bad CRC, using default environment
+
+In: serial
+Out: serial
+Err: serial
+Net: MOTOROLA ETHERNE
+Hit any key to stop autoboot: 3
+MPC8560ADS=> bdinfo
+memstart = 0x00000000
+memsize = 0x08000000
+flashstart = 0xFF000000
+flashsize = 0x01000000
+flashoffset = 0x00000000
+sramstart = 0x00000000
+sramsize = 0x00000000
+immr_base = 0xFDF00000
+bootflags = 0x00000000
+vco = 528 MHz
+sccfreq = 132 MHz
+brgfreq = 132 MHz
+intfreq = 792 MHz
+cpmfreq = 264 MHz
+busfreq = 264 MHz
+ethaddr = 00:01:AF:07:9B:8A
+eth1addr = 00:01:AF:07:9B:8B
+eth2addr = 00:01:AF:07:9B:8C
+IP addr = 10.82.0.105
+baudrate = 115200 bps
+MPC8560ADS=> printenv
+bootargs=root=/dev/nfs rw nfsroot=163.12.64.52:/localhome/r6aads/linuxppc/target ip=10.82.0.105:163.12.64.52:10.82.1.254:255.255.254.0:mpc8560ads-003:eth0:off console=ttyS0,115200
+bootcmd=bootm 0xff400000 0xff700000
+bootdelay=3
+baudrate=115200
+loads_echo=1
+ethaddr=00:01:af:07:9b:8a
+eth1addr=00:01:af:07:9b:8b
+eth2addr=00:01:af:07:9b:8c
+ipaddr=10.82.0.105
+serverip=163.12.64.52
+rootpath=/home/r6aads/mpclinux/eldk-2.0.2/ppc_82xx
+gatewayip=10.82.1.254
+netmask=255.255.254.0
+hostname=MPC8560ADS_PILOT_003
+bootfile=pImage
+stdin=serial
+stdout=serial
+stderr=serial
+
+Environment size: 560/8188 bytes
+MPC8560ADS=> fli
+
+Bank # 1: Intel 28F640J3A (64 Mbit, 64 x 128K)
+ Size: 16 MB in 64 Sectors
+ Sector Start Addresses:
+ FF000000 FF040000 FF080000 FF0C0000 FF100000
+ FF140000 FF180000 FF1C0000 FF200000 FF240000
+ FF280000 FF2C0000 FF300000 FF340000 FF380000
+ FF3C0000 FF400000 FF440000 FF480000 FF4C0000
+ FF500000 FF540000 FF580000 FF5C0000 FF600000
+ FF640000 FF680000 FF6C0000 FF700000 FF740000
+ FF780000 FF7C0000 FF800000 FF840000 FF880000
+ FF8C0000 FF900000 FF940000 FF980000 FF9C0000
+ FFA00000 FFA40000 FFA80000 FFAC0000 FFB00000
+ FFB40000 FFB80000 FFBC0000 FFC00000 FFC40000
+ FFC80000 FFCC0000 FFD00000 FFD40000 FFD80000
+ FFDC0000 FFE00000 FFE40000 FFE80000 FFEC0000
+ FFF00000 FFF40000 FFF80000 (RO) FFFC0000 (RO)
+MPC8560ADS=> imi ff100000
+
+## Checking Image at ff100000 ...
+ Image Name: Linux-2.4.21-rc5
+ Image Type: PowerPC Linux Kernel Image (gzip compressed)
+ Data Size: 755361 Bytes = 737.7 kB
+ Load Address: 00000000
+ Entry Point: 00000000
+ Verifying Checksum ... OK
+MPC8560ADS=> tftp 1000000 pImage.dracom.public
+TFTP from server 163.12.64.52; our IP address is 10.82.0.105; sending through gateway 10.82.1.254
+Filename 'pImage.dracom.public'.
+Load address: 0x1000000
+Loading: *#################################################################
+ #################################################################
+ ##################
+done
+Bytes transferred = 755425 (b86e1 hex)
+MPC8560ADS=> bootm ff100000
+## Booting image at ff100000 ...
+ Image Name: Linux-2.4.21-rc5
+ Image Type: PowerPC Linux Kernel Image (gzip compressed)
+ Data Size: 755361 Bytes = 737.7 kB
+ Load Address: 00000000
+ Entry Point: 00000000
+ Verifying Checksum ... OK
+ Uncompressing Kernel Image ... OK
+mpc85xx_init(): exit
+id mach(): done
+MMU:enter
+Memory CAM mapping: CAM0=64Mb, CAM1=64Mb, CAM2=0Mb residual: 0Mb
+MMU:hw init
+MMU:mapin
+MMU:mapin_ram done
+MMU:setio
+MMU:exit
+Linux version 2.4.21-rc5 (@etest) (gcc version 2.95.3 20010315 (release)) #2 Wed Oct 15 09:13:46 CDT 2003
+setup_arch: enter
+setup_arch: bootmem
+mpc85xx_setup_arch
+Host Bridge Vendor ID = 1057
+Host Bridge Device ID = 3
+Host Bridge header = 0
+arch: exit
+On node 0 totalpages: 32768
+zone(0): 32768 pages.
+zone(1): 0 pages.
+zone(2): 0 pages.
+Kernel command line: root=/dev/nfs rw nfsroot=163.12.64.52:/localhome/r6aads/linuxppc/target ip=10.82.0.105:163.12.64.52:10.82.1.254:255.255.254.0:mpc8560ads-003:eth0:off console=ttyS0,115200
+openpic: enter
+OpenPIC Version 1.2 (1 CPUs and 44 IRQ sources) at fdf40000
+openpic: timer
+openpic: external
+openpic: spurious
+openpic: exit
+time_init: decrementer frequency = 33.000000 MHz
+Calibrating delay loop... 226.09 BogoMIPS
+Memory: 127624k available (1276k kernel code, 384k data, 236k init, 0k highmem)
+Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
+Inode cache hash table entries: 8192 (order: 4, 65536 bytes)
+Mount cache hash table entries: 512 (order: 0, 4096 bytes)
+Buffer-cache hash table entries: 8192 (order: 3, 32768 bytes)
+Page-cache hash table entries: 32768 (order: 5, 131072 bytes)
+POSIX conformance testing by UNIFIX
+PCI: Probing PCI hardware
+
+Linux NET4.0 for Linux 2.4
+Based upon Swansea University Computer Society NET3.039
+Initializing RT netlink socket
+Starting kswapd
+Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
+CPM UART driver version 0.01
+ttyS0 on SCC1 at 0x8000, BRG1
+UART interrupt installed(40)
+pty: 256 Unix98 ptys configured
+eth0: Three Speed Ethernet Controller Version 0.2, 00:01:af:07:9b:8a:
+eth1: Three Speed Ethernet Controller Version 0.2, 00:01:af:07:9b:8b:
+RAMDISK driver initialized: 16 RAM disks of 32768K size 1024 blocksize
+loop: loaded (max 8 devices)
+Intel(R) PRO/1000 Network Driver - version 5.0.43-k1
+Copyright (c) 1999-2003 Intel Corporation.
+PPP generic driver version 2.4.2
+PPP Deflate Compression module registered
+NET4: Linux TCP/IP 1.0 for NET4.0
+IP Protocols: ICMP, UDP, TCP, IGMP
+IP: routing cache hash table of 1024 buckets, 8Kbytes
+TCP: Hash tables configured (established 8192 bind 8192)
+IP-Config: Complete:
+ device=eth0, addr=10.82.0.105, mask=255.255.254.0, gw=10.82.1.254,
+ host=mpc8560ads-003, domain=, nis-domain=(none),
+ bootserver=163.12.64.52, rootserver=163.12.64.52, rootpath=
+NET4: Unix domain sockets 1.0/SMP for Linux NET4.0.
+Looking up port of RPC 100003/2 on 163.12.64.52
+Looking up port of RPC 100005/1 on 163.12.64.52
+VFS: Mounted root (nfs filesystem).
+Freeing unused kernel memory: 236k init
+INIT: version 2.78 booting
+Activating swap...
+Checking all file systems...
+Parallelizing fsck version 1.22 (22-Jun-2001)
+Mounting local filesystems...
+nothing was mounted
+Cleaning: /etc/network/ifstate.
+Setting up IP spoofing protection: FAILED
+Configuring network interfaces: done.
+Starting portmap daemon: portmap.
+Cleaning: /tmp /var/lock /var/run.
+INIT: Entering runlevel: 2
+Starting system log daemon: syslogd klogd.
+Starting internet superserver: inetd.
+
+mpc8560ads-003 login: root
+Last login: Thu Jan 1 00:00:05 1970 on console
+Linux mpc8560ads-003 2.4.21-rc5 #2 Wed Oct 15 09:13:46 CDT 2003 ppc unknown
+
+root@mpc8560ads-003:~# ls
+21142.o aa e100.o hello.o mii.o timer.o
+root@mpc8560ads-003:~# cd /
+root@mpc8560ads-003:/# ls
+bin boot dev etc home lib mnt opt proc root sbin tmp usr var
+root@mpc8560ads-003:/# /sbin/ifconfig
+eth0 Link encap:Ethernet HWaddr 00:01:AF:07:9B:8A
+ inet addr:10.82.0.105 Bcast:10.82.1.255 Mask:255.255.254.0
+ UP BROADCAST RUNNING MULTICAST MTU:1500 Metric:1
+ RX packets:4608 errors:0 dropped:0 overruns:0 frame:0
+ TX packets:2610 errors:0 dropped:0 overruns:0 carrier:0
+ collisions:0 txqueuelen:100
+ RX bytes:4465943 (4.2 Mb) TX bytes:440944 (430.6 Kb)
+ Base address:0x4000
+
+lo Link encap:Local Loopback
+ inet addr:127.0.0.1 Mask:255.0.0.0
+ UP LOOPBACK RUNNING MTU:16436 Metric:1
+ RX packets:4 errors:0 dropped:0 overruns:0 frame:0
+ TX packets:4 errors:0 dropped:0 overruns:0 carrier:0
+ collisions:0 txqueuelen:0
+ RX bytes:296 (296.0 b) TX bytes:296 (296.0 b)
+
+root@mpc8560ads-003:/# ping 163.12.64.52
+PING 163.12.64.52 (163.12.64.52): 56 data bytes
+64 bytes from 163.12.64.52: icmp_seq=0 ttl=63 time=0.1 ms
+64 bytes from 163.12.64.52: icmp_seq=1 ttl=63 time=0.1 ms
+64 bytes from 163.12.64.52: icmp_seq=2 ttl=63 time=0.1 ms
+
+--- 163.12.64.52 ping statistics ---
+3 packets transmitted, 3 packets received, 0% packet loss
+round-trip min/avg/max = 0.1/0.1/0.1 ms
+root@mpc8560ads-003:/#
structure definitions from the Nios SDK.
-
2. CONFIGURATION OPTIONS/SETTINGS
----------------------------------
MSTEP and MUL instructions (e.g. CFG_NIOS_MULT_HW and CFG_NIOS_MULT_MSTEP).
-
Regards,
--Scott
extern void dc21x4x_select_media(struct eth_device* dev);
#endif
+#if defined(CONFIG_E500)
+#define phys_to_bus(a) (a)
+#else
#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
+#endif
static int INL(struct eth_device* dev, u_long addr)
{
static int eepro100_recv (struct eth_device *dev);
static void eepro100_halt (struct eth_device *dev);
+#if defined(CONFIG_E500)
+#define bus_to_phys(a) (a)
+#define phys_to_bus(a) (a)
+#else
#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
+#endif
static inline int INW (struct eth_device *dev, u_long addr)
{
cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
return 0; \
}
+#elif defined(CONFIG_E500)
+#define INDIRECT_PCI_OP(rw, size, type, op, mask) \
+static int \
+indirect_##rw##_config_##size(struct pci_controller *hose, \
+ pci_dev_t dev, int offset, type val) \
+{ \
+ *(hose->cfg_addr) = dev | (offset & 0xfc) | 0x80000000; \
+ sync(); \
+ cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
+ return 0; \
+}
#else
#define INDIRECT_PCI_OP(rw, size, type, op, mask) \
static int \
LIB := libsk98lin.a
OBJS := skge.o skaddr.o skgehwt.o skgeinit.o skgepnmi.o skgesirq.o \
- ski2c.o sklm80.o skqueue.o skrlmt.o sktimer.o skvpd.o \
- skxmac2.o skcsum.o #skproc.o
+ ski2c.o sklm80.o skqueue.o skrlmt.o sktimer.o skvpd.o \
+ skxmac2.o skcsum.o #skproc.o
OBJS += uboot_skb.o uboot_drv.o
sinclude .depend
#########################################################################
-
-
/******************************************************************************
*
- * Name: lm80.h
+ * Name: lm80.h
* Project: GEnesis, PCI Gigabit Ethernet Adapter
* Version: $Revision: 1.4 $
* Date: $Date: 2002/04/25 11:04:10 $
* $Log: lm80.h,v $
* Revision 1.4 2002/04/25 11:04:10 rschmidt
* Editorial changes
- *
+ *
* Revision 1.3 1999/11/22 13:41:19 cgoos
* Changed license header to GPL.
- *
+ *
* Revision 1.2 1999/03/12 13:26:51 malthoff
* remove __STDC__.
- *
+ *
* Revision 1.1 1998/06/19 09:28:31 malthoff
* created.
- *
+ *
*
******************************************************************************/
* $Log: skaddr.h,v $
* Revision 1.26 2002/11/15 07:24:42 tschilli
* SK_ADDR_EQUAL macro fixed.
- *
+ *
* Revision 1.25 2002/06/10 13:55:18 tschilli
* Changes for handling YUKON.
* All changes are internally and not visible to the programmer
* using this module.
- *
+ *
* Revision 1.24 2001/01/22 13:41:34 rassmann
* Supporting two nets on dual-port adapters.
- *
+ *
* Revision 1.23 2000/08/10 11:27:50 rassmann
* Editorial changes.
* Preserving 32-bit alignment in structs for the adapter context.
- *
+ *
* Revision 1.22 2000/08/07 11:10:40 rassmann
* Editorial changes.
- *
+ *
* Revision 1.21 2000/05/04 09:39:59 rassmann
* Editorial changes.
* Corrected multicast address hashing.
- *
+ *
* Revision 1.20 1999/11/22 13:46:14 cgoos
* Changed license header to GPL.
* Allowing overwrite for SK_ADDR_EQUAL.
- *
+ *
* Revision 1.19 1999/05/28 10:56:07 rassmann
* Editorial changes.
- *
+ *
* Revision 1.18 1999/04/06 17:22:04 rassmann
* Added private "ActivePort".
- *
+ *
* Revision 1.17 1999/01/14 16:18:19 rassmann
* Corrected multicast initialization.
- *
+ *
* Revision 1.16 1999/01/04 10:30:36 rassmann
* SkAddrOverride only possible after SK_INIT_IO phase.
- *
+ *
* Revision 1.15 1998/12/29 13:13:11 rassmann
* An address override is now preserved in the SK_INIT_IO phase.
* All functions return an int now.
* Extended parameter checking.
- *
+ *
* Revision 1.14 1998/11/24 12:39:45 rassmann
* Reserved multicast entry for BPDU address.
* 13 multicast entries left for protocol.
- *
+ *
* Revision 1.13 1998/11/13 17:24:32 rassmann
* Changed return value of SkAddrOverride to int.
- *
+ *
* Revision 1.12 1998/11/13 16:56:19 rassmann
* Added macro SK_ADDR_COMPARE.
* Changed return type of SkAddrOverride to SK_BOOL.
- *
+ *
* Revision 1.11 1998/10/28 18:16:35 rassmann
* Avoiding I/Os before SK_INIT_RUN level.
* Aligning InexactFilter.
- *
+ *
* Revision 1.10 1998/10/22 11:39:10 rassmann
* Corrected signed/unsigned mismatches.
- *
+ *
* Revision 1.9 1998/10/15 15:15:49 rassmann
* Changed Flags Parameters from SK_U8 to int.
* Checked with lint.
- *
+ *
* Revision 1.8 1998/09/24 19:15:12 rassmann
* Code cleanup.
- *
+ *
* Revision 1.7 1998/09/18 20:22:13 rassmann
* Added HW access.
- *
+ *
* Revision 1.6 1998/09/04 19:40:20 rassmann
* Interface enhancements.
- *
+ *
* Revision 1.5 1998/09/04 12:40:57 rassmann
* Interface cleanup.
- *
+ *
* Revision 1.4 1998/09/04 12:14:13 rassmann
* Interface cleanup.
- *
+ *
* Revision 1.3 1998/09/02 16:56:40 rassmann
* Updated interface.
- *
+ *
* Revision 1.2 1998/08/27 14:26:09 rassmann
* Updated interface.
- *
+ *
* Revision 1.1 1998/08/21 08:31:08 rassmann
* First public version.
*
SK_AC *pAC,
SK_IOC IoC,
SK_U32 PortNumber,
- int NewPromMode);
+ int NewPromMode);
extern int SkAddrSwap(
SK_AC *pAC,
* $Log: skcsum.h,v $
* Revision 1.9 2001/02/06 11:21:39 rassmann
* Editorial changes.
- *
+ *
* Revision 1.8 2001/02/06 11:15:36 rassmann
* Supporting two nets on dual-port adapters.
- *
+ *
* Revision 1.7 2000/06/29 13:17:05 rassmann
* Corrected reception of a packet with UDP checksum == 0 (which means there
* is no UDP checksum).
- *
+ *
* Revision 1.6 2000/02/28 12:33:44 cgoos
* Changed C++ style comments to C style.
- *
+ *
* Revision 1.5 2000/02/21 12:10:05 cgoos
* Fixed license comment.
- *
+ *
* Revision 1.4 2000/02/21 11:08:37 cgoos
* Merged changes back into common source.
- *
+ *
* Revision 1.1 1999/07/26 14:47:49 mkarl
* changed from common source to windows specific source
* added return SKCS_STATUS_IP_CSUM_ERROR_UDP and
* SKCS_STATUS_IP_CSUM_ERROR_TCP to pass the NidsTester
* changes for Tx csum offload
- *
+ *
* Revision 1.2 1998/09/04 12:16:34 mhaveman
* Checked in for Stephan to allow compilation.
* -Added definition SK_CSUM_EVENT_CLEAR_PROTO_STATS to clear statistic
* -Added prototype for SkCsEvent()
- *
+ *
* Revision 1.1 1998/09/01 15:36:53 swolf
* initial revision
*
* SKCS_STATUS_UDP_CSUM_ERROR - UDP checksum error (IP checksum ok).
* SKCS_STATUS_TCP_CSUM_OK - IP and TCP checksum ok.
* SKCS_STATUS_UDP_CSUM_OK - IP and UDP checksum ok.
- * SKCS_STATUS_IP_CSUM_OK_NO_UDP - IP checksum OK and no UDP checksum.
+ * SKCS_STATUS_IP_CSUM_OK_NO_UDP - IP checksum OK and no UDP checksum.
*/
#ifndef SKCS_OVERWRITE_STATUS /* User overwrite? */
#define SKCS_STATUS int /* Define status type. */
* Revision 1.12 2002/07/15 15:37:13 rschmidt
* Power Management support
* Editorial changes
- *
+ *
* Revision 1.11 2002/04/25 11:04:39 rschmidt
* Editorial changes
- *
+ *
* Revision 1.10 1999/11/22 13:47:40 cgoos
* Changed license header to GPL.
- *
+ *
* Revision 1.9 1999/09/14 14:02:43 rwahl
* Added SK_DBGMOD_PECP.
- *
+ *
* Revision 1.8 1998/11/25 08:31:54 gklug
* fix: no C++ comments allowed in common sources
- *
+ *
* Revision 1.7 1998/11/24 16:47:24 swolf
* Driver may now define its own SK_DBG_MSG() (eg. in "h/skdrv1st.h").
- *
+ *
* Revision 1.6 1998/10/28 10:23:55 rassmann
* ADDED SK_DBGMOD_ADDR.
- *
+ *
* Revision 1.5 1998/10/22 09:43:55 gklug
* add: CSUM module
- *
+ *
* Revision 1.4 1998/10/01 07:54:44 gklug
* add: PNMI debug module
- *
+ *
* Revision 1.3 1998/09/18 08:32:34 afischer
* Macros changed according ssr-spec.:
* SK_DBG_MODCHK -> SK_DBG_CHKMOD
* SK_DBG_CATCHK -> SK_DBG_CHKCAT
- *
+ *
* Revision 1.2 1998/07/03 14:38:25 malthoff
* Add category SK_DBGCAT_FATAL.
- *
+ *
* Revision 1.1 1998/06/19 13:39:01 malthoff
* created.
- *
+ *
*
******************************************************************************/
* $Log: skdrv1st.h,v $
* Revision 1.11 2003/02/25 14:16:40 mlindner
* Fix: Copyright statement
- *
+ *
* Revision 1.10 2002/10/02 12:46:02 mlindner
* Add: Support for Yukon
- *
+ *
* Revision 1.9.2.2 2001/12/07 12:06:42 mlindner
* Fix: malloc -> slab changes
- *
+ *
* Revision 1.9.2.1 2001/03/12 16:50:59 mlindner
* chg: kernel 2.4 adaption
- *
+ *
* Revision 1.9 2001/01/22 14:16:04 mlindner
* added ProcFs functionality
* Dual Net functionality integrated
* Rlmt networks added
- *
+ *
* Revision 1.8 2000/02/21 12:19:18 cgoos
* Added default for SK_DEBUG_CHKMOD/_CHKCAT
- *
+ *
* Revision 1.7 1999/11/22 13:50:00 cgoos
* Changed license header to GPL.
* Added overwrite for several functions.
* Removed linux 2.0.x definitions.
* Removed PCI vendor ID definition (now in kernel).
- *
+ *
* Revision 1.6 1999/07/27 08:03:33 cgoos
* Changed SK_IN/OUT macros to readX/writeX instead of memory
* accesses (necessary for ALPHA).
- *
+ *
* Revision 1.5 1999/07/23 12:10:21 cgoos
* Removed SK_RLMT_SLOW_LOOKAHEAD define.
- *
+ *
* Revision 1.4 1999/07/14 12:31:13 cgoos
* Added SK_RLMT_SLOW_LOOKAHEAD define.
- *
+ *
* Revision 1.3 1999/04/07 10:12:54 cgoos
* Added check for KERNEL and OPTIMIZATION defines.
- *
+ *
* Revision 1.2 1999/03/01 08:51:47 cgoos
* Fixed pcibios_read/write definitions.
- *
+ *
* Revision 1.1 1999/02/16 07:40:49 cgoos
* First version.
- *
- *
+ *
+ *
*
******************************************************************************/
#define SK_MEM_MAPPED_IO
-// #define SK_RLMT_SLOW_LOOKAHEAD
+/* #define SK_RLMT_SLOW_LOOKAHEAD */
#define SK_MAX_MACS 2
#define SK_MAX_NETS 2
#define SK_STRCMP(pStr1,pStr2) strcmp((char*)(pStr1),(char*)(pStr2))
/* macros to access the adapter */
-#define SK_OUT8(b,a,v) writeb((v), ((b)+(a)))
-#define SK_OUT16(b,a,v) writew((v), ((b)+(a)))
-#define SK_OUT32(b,a,v) writel((v), ((b)+(a)))
+#define SK_OUT8(b,a,v) writeb((v), ((b)+(a)))
+#define SK_OUT16(b,a,v) writew((v), ((b)+(a)))
+#define SK_OUT32(b,a,v) writel((v), ((b)+(a)))
#define SK_IN8(b,a,pv) (*(pv) = readb((b)+(a)))
#define SK_IN16(b,a,pv) (*(pv) = readw((b)+(a)))
#define SK_IN32(b,a,pv) (*(pv) = readl((b)+(a)))
extern void SkErrorLog(SK_AC*, int, int, char*);
#endif
-
* $Log: skdrv2nd.h,v $
* Revision 1.15 2003/02/25 14:16:40 mlindner
* Fix: Copyright statement
- *
+ *
* Revision 1.14 2003/02/25 13:26:26 mlindner
* Add: Support for various vendors
- *
+ *
* Revision 1.13 2002/10/02 12:46:02 mlindner
* Add: Support for Yukon
- *
+ *
* Revision 1.12.2.2 2001/09/05 12:14:50 mlindner
* add: New hardware revision int
- *
+ *
* Revision 1.12.2.1 2001/03/12 16:50:59 mlindner
* chg: kernel 2.4 adaption
- *
+ *
* Revision 1.12 2001/03/01 12:52:15 mlindner
* Fixed ring size
*
*
* Revision 1.7 1999/09/28 12:38:21 cgoos
* Added CheckQueue to SK_AC.
- *
+ *
* Revision 1.6 1999/07/27 08:04:05 cgoos
* Added checksumming variables to SK_AC.
- *
+ *
* Revision 1.5 1999/03/29 12:33:26 cgoos
* Rreversed to fine lock granularity.
- *
+ *
* Revision 1.4 1999/03/15 12:14:02 cgoos
* Added DriverLock to SK_AC.
* Removed other locks.
- *
+ *
* Revision 1.3 1999/03/01 08:52:27 cgoos
* Changed pAC->PciDev declaration.
- *
+ *
* Revision 1.2 1999/02/18 10:57:14 cgoos
* Removed SkDrvTimeStamp prototype.
* Fixed SkGeOsGetTime prototype.
- *
+ *
* Revision 1.1 1999/02/16 07:41:01 cgoos
* First version.
- *
- *
+ *
+ *
*
******************************************************************************/
result = SK_FALSE; /* default */ \
/* 3Com (0x10b7) */ \
if (pdev->vendor == 0x10b7) { \
- /* Gigabit Ethernet Adapter (0x1700) */ \
- if ((pdev->device == 0x1700)) { \
- result = SK_TRUE; \
- } \
+ /* Gigabit Ethernet Adapter (0x1700) */ \
+ if ((pdev->device == 0x1700)) { \
+ result = SK_TRUE; \
+ } \
/* SysKonnect (0x1148) */ \
} else if (pdev->vendor == 0x1148) { \
- /* SK-98xx Gigabit Ethernet Server Adapter (0x4300) */ \
- /* SK-98xx V2 Gigabit Ethernet Adapter (0x4320) */ \
- if ((pdev->device == 0x4300) || \
- (pdev->device == 0x4320)) { \
- result = SK_TRUE; \
- } \
+ /* SK-98xx Gigabit Ethernet Server Adapter (0x4300) */ \
+ /* SK-98xx V2 Gigabit Ethernet Adapter (0x4320) */ \
+ if ((pdev->device == 0x4300) || \
+ (pdev->device == 0x4320)) { \
+ result = SK_TRUE; \
+ } \
/* D-Link (0x1186) */ \
} else if (pdev->vendor == 0x1186) { \
- /* Gigabit Ethernet Adapter (0x4c00) */ \
- if ((pdev->device == 0x4c00)) { \
- result = SK_TRUE; \
- } \
+ /* Gigabit Ethernet Adapter (0x4c00) */ \
+ if ((pdev->device == 0x4c00)) { \
+ result = SK_TRUE; \
+ } \
/* CNet (0x1371) */ \
} else if (pdev->vendor == 0x1371) { \
- /* GigaCard Network Adapter (0x434e) */ \
- if ((pdev->device == 0x434e)) { \
- result = SK_TRUE; \
- } \
+ /* GigaCard Network Adapter (0x434e) */ \
+ if ((pdev->device == 0x434e)) { \
+ result = SK_TRUE; \
+ } \
/* Linksys (0x1737) */ \
} else if (pdev->vendor == 0x1737) { \
- /* Gigabit Network Adapter (0x1032) */ \
- /* Gigabit Network Adapter (0x1064) */ \
- if ((pdev->device == 0x1032) || \
- (pdev->device == 0x1064)) { \
- result = SK_TRUE; \
- } \
+ /* Gigabit Network Adapter (0x1032) */ \
+ /* Gigabit Network Adapter (0x1064) */ \
+ if ((pdev->device == 0x1032) || \
+ (pdev->device == 0x1064)) { \
+ result = SK_TRUE; \
+ } \
} else { \
- result = SK_FALSE; \
+ result = SK_FALSE; \
} \
}
};
-
/*
* ioctl definitions
*/
#define TX_CTRL_LEN_MASK UINT32_C(0x0000FFFF)
-
/* The offsets of registers in the TX and RX queue control io area ***********/
#define RX_Q_BUF_CTRL_CNT 0x00
int Mtu;
int Up;
SK_AC *pAC;
-};
+};
typedef struct s_TxPort TX_PORT;
SK_PNMI_STRUCT_DATA PnmiStruct; /* structure to get all Pnmi-Data */
int RlmtMode; /* link check mode to set */
int RlmtNets; /* Number of nets */
-
+
SK_IOC IoBase; /* register set of adapter */
int BoardLevel; /* level of active hw init (0-2) */
char DeviceStr[80]; /* adapter string from vpd */
struct SK_NET_DEVICE *Next; /* link all devices (for clearing) */
int RxBufSize; /* length of receive buffers */
#if 0
- struct net_device_stats stats; /* linux 'netstat -i' statistics */
+ struct net_device_stats stats; /* linux 'netstat -i' statistics */
#endif
int Index; /* internal board index number */
};
-
#endif /* __INC_SKDRV2ND_H */
-
* $Log: skerror.h,v $
* Revision 1.5 2002/04/25 11:05:10 rschmidt
* Editorial changes
- *
+ *
* Revision 1.4 1999/11/22 13:51:59 cgoos
* Changed license header to GPL.
- *
+ *
* Revision 1.3 1999/09/14 14:04:42 rwahl
* Added error base SK_ERRBASE_PECP.
* Changed error base for driver.
- *
+ *
* Revision 1.2 1998/08/11 11:15:41 gklug
* chg: comments
- *
+ *
* Revision 1.1 1998/08/11 11:09:38 gklug
* add: error bases
* add: error Classes
* first version
- *
- *
+ *
+ *
*
******************************************************************************/
* Revision 1.6 2002/07/15 15:38:01 rschmidt
* Power Management support
* Editorial changes
- *
+ *
* Revision 1.5 2002/04/25 11:05:47 rschmidt
* Editorial changes
- *
+ *
* Revision 1.4 1999/11/22 13:52:46 cgoos
* Changed license header to GPL.
- *
+ *
* Revision 1.3 1998/12/01 13:31:39 cgoos
* SWITCH INTERN Event added.
- *
+ *
* Revision 1.2 1998/11/25 08:28:38 gklug
* rmv: PORT SWITCH Event
- *
+ *
* Revision 1.1 1998/09/29 06:14:07 gklug
* add: driver events (initial version)
- *
+ *
*
******************************************************************************/
WOL_CTL_DIS_LINK_CHG_UNIT | \
WOL_CTL_DIS_PATTERN_UNIT | \
WOL_CTL_DIS_MAGIC_PKT_UNIT)
-
+
/* WOL_MATCH_CTL 8 bit WOL Match Control Reg */
#define WOL_CTL_PATT_ENA(x) (BIT_0 << (x))
SK_U32 RxAdrHi; /* Physical Rx Buffer Address upper dword */
SK_U32 RxStat; /* Receive Frame Status Word */
SK_U32 RxTiSt; /* Receive Time Stamp (from XMAC on GENESIS) */
-#ifndef SK_USE_REV_DESC
+#ifndef SK_USE_REV_DESC
SK_U16 RxTcpSum1; /* TCP Checksum 1 */
SK_U16 RxTcpSum2; /* TCP Checksum 2 */
SK_U16 RxTcpSp1; /* TCP Checksum Calculation Start Position 1 */
*
* Use this macro to access the Receive and Transmit Queue Registers.
*
- * para:
+ * para:
* Queue Queue to access.
* Values: Q_R1, Q_R2, Q_XS1, Q_XA1, Q_XS2, and Q_XA2
* Offs Queue register offset.
*
* Use this macro to access the RAM Buffer Registers.
*
- * para:
+ * para:
* Queue Queue to access.
* Values: Q_R1, Q_R2, Q_XS1, Q_XA1, Q_XS2, and Q_XA2
* Offs Queue register offset.
*
* Use this macro to access a MAC Related Registers inside the ASIC.
*
- * para:
+ * para:
* Mac MAC to access.
* Values: MAC_1, MAC_2
* Offs MAC register offset.
#define PHY_ADDR_BCOM (1<<8)
#define PHY_ADDR_LONE (3<<8)
#define PHY_ADDR_NAT (0<<8)
-
+
/* GPHY address (bits 15..11 of SMI control reg) */
#define PHY_ADDR_MARV 0
* PHY_READ() read a 16 bit value from the PHY
* PHY_WRITE() write a 16 bit value to the PHY
*
- * para:
+ * para:
* IoC I/O context needed for SK I/O macros
* pPort Pointer to port struct for PhyAddr
* Mac XMAC to access values: MAC_1 or MAC_2
* $Log: skgehwt.h,v $
* Revision 1.5 1999/11/22 13:54:24 cgoos
* Changed license header to GPL.
- *
+ *
* Revision 1.4 1998/08/19 09:50:58 gklug
* fix: remove struct keyword from c-code (see CCC) add typedefs
- *
+ *
* Revision 1.3 1998/08/14 07:09:29 gklug
* fix: chg pAc -> pAC
- *
+ *
* Revision 1.2 1998/08/07 12:54:21 gklug
* fix: first compiled version
- *
+ *
* Revision 1.1 1998/08/07 09:32:58 gklug
* first version
- *
- *
- *
- *
+ *
+ *
+ *
+ *
*
******************************************************************************/
* Revision 1.23 2002/12/19 14:34:27 rschmidt
* Added cast in macros SK_I2C_SET_BIT() and SK_I2C_CLR_BIT()
* Editorial changes (TWSI)
- *
+ *
* Revision 1.22 2002/10/14 16:45:56 rschmidt
* Editorial changes (TWSI)
- *
+ *
* Revision 1.21 2002/08/13 08:42:24 rschmidt
* Changed define for SK_MIN_SENSORS back to 5
* Merged defines for PHY PLL 3V3 voltage (A and B)
* Editorial changes
- *
+ *
* Revision 1.20 2002/08/06 09:43:56 jschmalz
* Extensions and changes for Yukon
- *
+ *
* Revision 1.19 2002/08/02 12:00:08 rschmidt
* Added defines for YUKON sensors
* Editorial changes
- *
+ *
* Revision 1.18 2001/08/16 12:44:33 afischer
* LM80 sensor init values corrected
- *
+ *
* Revision 1.17 1999/11/22 13:55:25 cgoos
* Changed license header to GPL.
- *
+ *
* Revision 1.16 1999/11/12 08:24:10 malthoff
* Change voltage warning and error limits
* (warning +-5%, error +-10%).
- *
+ *
* Revision 1.15 1999/09/14 14:14:43 malthoff
* The 1000BT Dual Link adapter has got only one Fan.
* The second Fan has been removed.
- *
+ *
* Revision 1.14 1999/05/27 13:40:50 malthoff
* Fan Divisor = 1. Assuming fan with 6500 rpm.
- *
+ *
* Revision 1.13 1999/05/20 14:56:55 malthoff
* Bug Fix: Missing brace in SK_LM80_FAN_FAKTOR.
- *
+ *
* Revision 1.12 1999/05/20 09:22:00 cgoos
* Changes for 1000Base-T (Fan sensors).
- *
+ *
* Revision 1.11 1998/10/14 05:57:22 cgoos
* Fixed compilation warnings.
- *
+ *
* Revision 1.10 1998/09/04 08:37:00 malthoff
* bugfix: correct the SK_I2C_GET_CTL() macro.
- *
+ *
* Revision 1.9 1998/08/25 06:10:03 gklug
* add: thresholds for all sensors
*
* Revision 1.8 1998/08/20 11:37:42 gklug
* chg: change Ioc to IoC
- *
+ *
* Revision 1.7 1998/08/20 08:53:11 gklug
* fix: compiler errors
* add: Threshold values
- *
+ *
* Revision 1.6 1998/08/17 11:37:09 malthoff
* Bugfix in SK_I2C_CTL macro. The parameter 'dev'
* has to be shifted 9 bits.
- *
+ *
* Revision 1.5 1998/08/17 06:52:21 malthoff
* Remove unrequired macros.
* Add macros for accessing TWSI SW register.
- *
+ *
* Revision 1.4 1998/08/13 08:30:18 gklug
* add: conversion factors for read values
* add: new state SEN_VALEXT to read extension value of temperature sensor
* Revision 1.75 2003/02/05 13:36:39 rschmidt
* Added define SK_FACT_78 for YUKON's Host Clock of 78.12 MHz
* Editorial changes
- *
+ *
* Revision 1.74 2003/01/28 09:39:16 rschmidt
* Added entry GIYukonLite in s_GeInit structure
* Editorial changes
- *
+ *
* Revision 1.73 2002/11/15 12:47:25 rschmidt
* Replaced error message SKERR_HWI_E024 for Cable Diagnostic with
* Rx queue error in SkGeStopPort().
- *
+ *
* Revision 1.72 2002/11/12 17:08:35 rschmidt
* Added entries for Cable Diagnostic to Port structure
* Added entries GIPciSlot64 and GIPciClock66 in s_GeInit structure
* Added error message for Cable Diagnostic
* Added prototypes for SkGmCableDiagStatus()
* Editorial changes
- *
+ *
* Revision 1.71 2002/10/21 11:26:10 mkarl
* Changed interface of SkGeInitAssignRamToQueues().
- *
+ *
* Revision 1.70 2002/10/14 08:21:32 rschmidt
* Changed type of GICopperType, GIVauxAvail to SK_BOOL
* Added entry PRxOverCnt to Port structure
* Added entry GIYukon32Bit in s_GeInit structure
* Editorial changes
- *
+ *
* Revision 1.69 2002/10/09 16:57:15 mkarl
* Added some constants and macros for SkGeInitAssignRamToQueues().
- *
+ *
* Revision 1.68 2002/09/12 08:58:51 rwahl
* Retrieve counters needed for XMAC errata workarounds directly because
* PNMI returns corrected counter values (e.g. #10620).
- *
+ *
* Revision 1.67 2002/08/16 14:40:30 rschmidt
* Added entries GIGenesis and GICopperType in s_GeInit structure
* Added prototypes for SkMacHashing()
* Editorial changes
- *
+ *
* Revision 1.66 2002/08/12 13:27:21 rschmidt
* Added defines for Link speed capabilities
* Added entry PLinkSpeedCap to Port structure
* Added entry GIVauxAvail in s_GeInit structure
* Added prototypes for SkMacPromiscMode()
* Editorial changes
- *
+ *
* Revision 1.65 2002/08/08 15:46:18 rschmidt
* Added define SK_PHY_ACC_TO for PHY access timeout
* Added define SK_XM_RX_HI_WM for XMAC Rx High Watermark
* Added define SK_MIN_TXQ_SIZE for Min RAM Buffer Tx Queue Size
* Added entry PhyId1 to Port structure
- *
+ *
* Revision 1.64 2002/07/23 16:02:56 rschmidt
* Added entry GIWolOffs in s_GeInit struct (HW-Bug in YUKON 1st rev.)
* Added prototypes for: SkGePhyRead(), SkGePhyWrite()
- *
+ *
* Revision 1.63 2002/07/18 08:17:38 rwahl
* Corrected definitions for SK_LSPEED_xxx & SK_LSPEED_STAT_xxx.
- *
+ *
* Revision 1.62 2002/07/17 18:21:55 rwahl
* Added SK_LSPEED_INDETERMINATED define.
- *
+ *
* Revision 1.61 2002/07/17 17:16:03 rwahl
* - MacType now member of GIni struct.
* - Struct alignment to 32bit.
* - Editorial change.
- *
+ *
* Revision 1.60 2002/07/15 18:23:39 rwahl
* Added GeMacFunc to GE Init structure.
* Added prototypes for SkXmUpdateStats(), SkGmUpdateStats(),
* SkGmResetCounter(), SkXmOverflowStatus(), SkGmOverflowStatus().
* Added defines for current link speed state.
* Added ERRMSG defintions for MacUpdateStat() & MacStatistics().
- *
+ *
* Revision 1.59 2002/07/15 15:40:22 rschmidt
* Added entry PLinkSpeedUsed to Port structure
* Editorial changes
- *
+ *
* Revision 1.58 2002/06/10 09:36:30 rschmidt
* Editorial changes.
- *
+ *
* Revision 1.57 2002/06/05 08:18:00 rschmidt
* Corrected alignment in Port Structure
* Added new prototypes for GMAC
* Editorial changes
- *
+ *
* Revision 1.56 2002/04/25 11:38:12 rschmidt
* Added defines for Link speed values
* Added defines for Loopback parameters for MAC and PHY
* SkXmPhyRead(), SkXmPhyRead(), SkGmPhyWrite(), SkGmPhyWrite();
* Removed prototypes for static functions in SkXmac2.c
* Editorial changes
- *
+ *
* Revision 1.55 2002/02/26 15:24:53 rwahl
* Fix: no link with manual configuration (#10673). The previous fix for
* #10639 was removed. So for RLMT mode = CLS the RLMT may switch to
* misconfigured port. It should not occur for the other RLMT modes.
- *
+ *
* Revision 1.54 2002/01/18 16:52:52 rwahl
* Editorial corrections.
- *
+ *
* Revision 1.53 2001/11/20 09:19:58 rwahl
* Reworked bugfix #10639 (no dependency to RLMT mode).
- *
+ *
* Revision 1.52 2001/10/26 07:52:23 afischer
* Port switching bug in `check local link` mode
- *
+ *
* Revision 1.51 2001/02/09 12:26:38 cgoos
* Inserted #ifdef DIAG for half duplex workaround timer.
- *
+ *
* Revision 1.50 2001/02/07 07:56:40 rassmann
* Corrected copyright.
- *
+ *
* Revision 1.49 2001/01/31 15:32:18 gklug
* fix: problem with autosensing an SR8800 switch
* add: counter for autoneg timeouts
- *
+ *
* Revision 1.48 2000/11/09 11:30:10 rassmann
* WA: Waiting after releasing reset until BCom chip is accessible.
- *
+ *
* Revision 1.47 2000/10/18 12:22:40 cgoos
* Added workaround for half duplex hangup.
- *
+ *
* Revision 1.46 2000/08/10 11:28:00 rassmann
* Editorial changes.
* Preserving 32-bit alignment in structs for the adapter context.
- *
+ *
* Revision 1.45 1999/11/22 13:56:19 cgoos
* Changed license header to GPL.
- *
+ *
* Revision 1.44 1999/10/26 07:34:15 malthoff
* The define SK_LNK_ON has been lost in v1.41.
- *
+ *
* Revision 1.43 1999/10/06 09:30:16 cgoos
* Changed SK_XM_THR_JUMBO.
- *
+ *
* Revision 1.42 1999/09/16 12:58:26 cgoos
* Changed SK_LED_STANDY macro to be independent of HW link sync.
- *
+ *
* Revision 1.41 1999/07/30 06:56:14 malthoff
* Correct comment for SK_MS_STAT_UNSET.
- *
+ *
* Revision 1.40 1999/05/27 13:38:46 cgoos
* Added SK_BMU_TX_WM.
* Made SK_BMU_TX_WM and SK_BMU_RX_WM user-definable.
* Changed XMAC Tx treshold to max. values.
- *
+ *
* Revision 1.39 1999/05/20 14:35:26 malthoff
* Remove prototypes for SkGeLinkLED().
- *
+ *
* Revision 1.38 1999/05/19 11:59:12 cgoos
* Added SK_MS_CAP_INDETERMINATED define.
- *
+ *
* Revision 1.37 1999/05/19 07:32:33 cgoos
* Changes for 1000Base-T.
* LED-defines for HWAC_LINK_LED macro.
- *
+ *
* Revision 1.36 1999/04/08 14:00:24 gklug
* add:Port struct field PLinkResCt
- *
+ *
* Revision 1.35 1999/03/25 07:43:07 malthoff
* Add error string for SKERR_HWI_E018MSG.
- *
+ *
* Revision 1.34 1999/03/12 16:25:57 malthoff
* Remove PPollRxD and PPollTxD.
* Add SKERR_HWI_E017MSG. and SK_DPOLL_MAX.
- *
+ *
* Revision 1.33 1999/03/12 13:34:41 malthoff
* Add Autonegotiation error codes.
* Change defines for parameter Mode in SkXmSetRxCmd().
* Replace __STDC__ by SK_KR_PROTO.
- *
+ *
* Revision 1.32 1999/01/25 14:40:20 mhaveman
* Added new return states for the virtual management port if multiple
* ports are active but differently configured.
- *
+ *
* Revision 1.31 1998/12/11 15:17:02 gklug
* add: Link partnet autoneg states : Unknown Manual and Auto-negotiation
- *
+ *
* Revision 1.30 1998/12/07 12:17:04 gklug
* add: Link Partner auto-negotiation flag
- *
+ *
* Revision 1.29 1998/12/01 10:54:42 gklug
* add: variables for XMAC Errata
- *
+ *
* Revision 1.28 1998/12/01 10:14:15 gklug
* add: PIsave saves the Interrupt status word
- *
+ *
* Revision 1.27 1998/11/26 15:24:52 mhaveman
* Added link status states SK_LMODE_STAT_AUTOHALF and
* SK_LMODE_STAT_AUTOFULL which are used by PNMI.
- *
+ *
* Revision 1.26 1998/11/26 14:53:01 gklug
* add:autoNeg Timeout variable
- *
+ *
* Revision 1.25 1998/11/26 08:58:50 gklug
* add: Link Mode configuration (AUTO Sense mode)
- *
+ *
* Revision 1.24 1998/11/24 13:30:27 gklug
* add: PCheckPar to port struct
- *
+ *
* Revision 1.23 1998/11/18 13:23:26 malthoff
* Add SK_PKT_TO_MAX.
- *
+ *
* Revision 1.22 1998/11/18 13:19:54 gklug
* add: PPrevShorts and PLinkBroken to port struct for WA XMAC Errata #C1
*
* Revision 1.21 1998/10/26 08:02:57 malthoff
* Add GIRamOffs.
- *
+ *
* Revision 1.20 1998/10/19 07:28:37 malthoff
* Add prototype for SkGeInitRamIface().
- *
+ *
* Revision 1.19 1998/10/14 14:47:48 malthoff
* SK_TIMER should not be defined for Diagnostics.
* Add SKERR_HWI_E015MSG and SKERR_HWI_E016MSG.
- *
+ *
* Revision 1.18 1998/10/14 14:00:03 gklug
* add: timer to port struct for workaround of Errata #2
- *
+ *
* Revision 1.17 1998/10/14 11:23:09 malthoff
* Add prototype for SkXmAutoNegDone().
* Fix SkXmSetRxCmd() prototype statement.
*
* Revision 1.16 1998/10/14 05:42:29 gklug
* add: HWLinkUp flag to Port struct
- *
+ *
* Revision 1.15 1998/10/09 08:26:33 malthoff
* Rename SK_RB_ULPP_B to SK_RB_LLPP_B.
- *
+ *
* Revision 1.14 1998/10/09 07:11:13 malthoff
* bug fix: SK_FACT_53 is 85 not 117.
* Rework time out init values.
* Add GIPortUsage and corresponding defines.
* Add some error log messages.
- *
+ *
* Revision 1.13 1998/10/06 14:13:14 malthoff
* Add prototype for SkGeLoadLnkSyncCnt().
*
/* modifying Link LED behaviour (used with SkGeLinkLED()) */
#define SK_LNK_OFF LED_OFF
-#define SK_LNK_ON (LED_ON | LED_BLK_OFF | LED_SYNC_OFF)
+#define SK_LNK_ON (LED_ON | LED_BLK_OFF | LED_SYNC_OFF)
#define SK_LNK_BLINK (LED_ON | LED_BLK_ON | LED_SYNC_ON)
#define SK_LNK_PERM (LED_ON | LED_BLK_OFF | LED_SYNC_ON)
#define SK_LNK_TST (LED_ON | LED_BLK_ON | LED_SYNC_OFF)
#define SK_LENERR_OK_ON (1<<4) /* Don't chk fr for in range len error */
#define SK_LENERR_OK_OFF (1<<5) /* Check frames for in range len error */
#define SK_BIG_PK_OK_ON (1<<6) /* Don't set Rx Error bit for big frames */
-#define SK_BIG_PK_OK_OFF (1<<7) /* Set Rx Error bit for big frames */
+#define SK_BIG_PK_OK_OFF (1<<7) /* Set Rx Error bit for big frames */
#define SK_SELF_RX_ON (1<<8) /* Enable Rx of own packets */
#define SK_SELF_RX_OFF (1<<9) /* Disable Rx of own packets */
* $Log: skgepnm2.h,v $
* Revision 1.34 2002/12/16 09:05:18 tschilli
* Code for VCT handling added.
- *
+ *
* Revision 1.33 2002/09/10 09:00:03 rwahl
* Adapted boolean definitions according sktypes.
- *
+ *
* Revision 1.32 2002/08/09 09:47:01 rwahl
* Added write-only flag to oid access defines.
* Editorial changes.
- *
+ *
* Revision 1.31 2002/07/17 19:23:18 rwahl
* - Replaced MAC counter definitions by enumeration.
* - Added definition SK_PNMI_MAC_TYPES.
* - Added chipset defnition for Yukon.
- *
+ *
* Revision 1.30 2001/02/06 10:03:41 mkunz
* - Pnmi V4 dual net support added. Interface functions and macros extended
* - Vpd bug fixed
* - OID_SKGE_MTU added
- *
+ *
* Revision 1.29 2001/01/22 13:41:37 rassmann
* Supporting two nets on dual-port adapters.
- *
+ *
* Revision 1.28 2000/08/03 15:12:48 rwahl
* - Additional comment for MAC statistic data structure.
- *
+ *
* Revision 1.27 2000/08/01 16:10:18 rwahl
* - Added mac statistic data structure for StatRxLongFrame counter.
- *
+ *
* Revision 1.26 2000/03/31 13:51:34 rwahl
* Added SK_UPTR cast to offset calculation for PNMI struct fields;
* missing cast caused compiler warnings by Win64 compiler.
- *
+ *
* Revision 1.25 1999/11/22 13:57:41 cgoos
* Changed license header to GPL.
* Allowing overwrite for SK_PNMI_STORE/_READ defines.
- *
+ *
* Revision 1.24 1999/04/13 15:11:11 mhaveman
* Changed copyright.
- *
+ *
* Revision 1.23 1999/01/28 15:07:12 mhaveman
* Changed default threshold for port switches per hour from 10
* to 240 which means 4 switches per minute. This fits better
* the granularity of 32 for the port switch estimate
* counter.
- *
+ *
* Revision 1.22 1999/01/05 12:52:30 mhaveman
* Removed macro SK_PNMI_MICRO_SEC.
- *
+ *
* Revision 1.21 1999/01/05 12:50:34 mhaveman
* Enlarged macro definition SK_PNMI_HUNDREDS_SEC() so that no 64-bit
* arithmetic is necessary if SK_TICKS_PER_SEC is 100.
- *
+ *
* Revision 1.20 1998/12/09 14:02:53 mhaveman
* Defined macro SK_PNMI_DEF_RLMT_CHG_THRES for default port switch
* threshold.
- *
+ *
* Revision 1.19 1998/12/03 11:28:41 mhaveman
* Removed SK_PNMI_CHECKPTR macro.
- *
+ *
* Revision 1.18 1998/12/03 11:21:00 mhaveman
* -Added pointer check macro SK_PNMI_CHECKPTR
* -Added macros SK_PNMI_VPD_ARR_SIZE and SK_PNMI_VPD_STR_SIZE for
* VPD key evaluation.
- *
+ *
* Revision 1.17 1998/11/20 13:20:33 mhaveman
* Fixed bug in SK_PNMI_SET_STAT macro. ErrorStatus was not correctly set.
- *
+ *
* Revision 1.16 1998/11/20 08:08:49 mhaveman
* Macro SK_PNMI_CHECKFLAGS has got a if clause.
- *
+ *
* Revision 1.15 1998/11/03 13:53:40 mhaveman
* Fixed alignment problem in macor SK_PNMI_SET_STAT macro.
- *
+ *
* Revision 1.14 1998/10/30 15:50:13 mhaveman
* Added macro SK_PNMI_MICRO_SEC()
- *
+ *
* Revision 1.13 1998/10/30 12:32:20 mhaveman
* Added forgotten cast in SK_PNMI_READ_U32 macro.
*
* -Changed SK_PNMI_TRAP_SENSOR_LEN because SensorDescr has now
* variable string length.
* -Defined SK_PNMI_CHECKFLAGS macro
- *
+ *
* Revision 1.11 1998/10/29 08:53:34 mhaveman
* Removed SK_PNMI_RLM_XXX table indexed because these counters need
* not been saved over XMAC resets.
- *
+ *
* Revision 1.10 1998/10/28 08:48:20 mhaveman
* -Added macros for storage according to alignment
* -Changed type of Instance to SK_U32 because of VPD
* -Removed trap structures. Not needed because of alignment problem
* -Changed type of Action form SK_U8 to int
- *
+ *
* Revision 1.9 1998/10/21 13:34:45 mhaveman
* Shit, mismatched calculation of SK_PNMI_HUNDREDS_SEC. Corrected.
- *
+ *
* Revision 1.8 1998/10/21 13:24:58 mhaveman
* Changed calculation of hundreds of seconds.
- *
+ *
* Revision 1.7 1998/10/20 07:31:41 mhaveman
* Made type changes to unsigned int where possible.
- *
+ *
* Revision 1.6 1998/09/04 17:04:05 mhaveman
* Added Sync counters to offset storage to provided settled values on
* port switch.
- *
+ *
* Revision 1.5 1998/09/04 12:45:35 mhaveman
* Removed dummies for SK_DRIVER_ macros. They should be added by driver
* writer in skdrv2nd.h.
- *
+ *
* Revision 1.4 1998/09/04 11:59:50 mhaveman
* Everything compiles now. Driver Macros for counting still missing.
- *
+ *
* Revision 1.3 1998/08/24 12:01:35 mhaveman
* Intermediate state.
- *
+ *
* Revision 1.2 1998/08/17 07:51:40 mhaveman
* Intermediate state.
- *
+ *
* Revision 1.1 1998/08/11 09:08:40 mhaveman
* Intermediate state.
- *
+ *
****************************************************************************/
#ifndef _SKGEPNM2_H_
SK_PNMI_HTX_SYNC,
SK_PNMI_HTX_SYNC_OCTET,
SK_PNMI_HTX_RESERVED,
-
+
SK_PNMI_HRX,
SK_PNMI_HRX_OCTET,
SK_PNMI_HRX_OCTETHIGH = SK_PNMI_HRX_OCTET,
SK_PNMI_HRX_1023,
SK_PNMI_HRX_MAX,
SK_PNMI_HRX_LONGFRAMES,
-
+
SK_PNMI_HRX_RESERVED,
-
+
SK_PNMI_MAX_IDX /* NOTE: Ensure SK_PNMI_CNT_NO is set to this value */
};
* $Log: skgepnmi.h,v $
* Revision 1.59 2002/12/16 14:03:50 tschilli
* New defines for VCT added.
- *
+ *
* Revision 1.58 2002/12/16 09:04:59 tschilli
* Code for VCT handling added.
- *
+ *
* Revision 1.57 2002/09/26 12:41:05 tschilli
* SK_PNMI_PORT BufPort entry in struct SK_PNMI added.
- *
+ *
* Revision 1.56 2002/08/16 11:10:41 rwahl
* - Replaced c++ comment.
- *
+ *
* Revision 1.55 2002/08/09 15:40:21 rwahl
* Editorial change (renamed ConfSpeedCap).
- *
+ *
* Revision 1.54 2002/08/09 11:06:07 rwahl
* Added OID_SKGE_SPEED_CAP.
- *
+ *
* Revision 1.53 2002/08/09 09:45:28 rwahl
* Added support for NDIS OID_PNP_xxx.
* Editorial changes.
- *
+ *
* Revision 1.52 2002/08/06 17:54:07 rwahl
* - Added speed cap to PNMI config struct.
- *
+ *
* Revision 1.51 2002/07/17 19:19:26 rwahl
* - Added OID_SKGE_SPEED_MODE and OID_SKGE_SPEED_STATUS.
* - Added SK_PNMI_CNT_RX_PMACC_ERR() & SK_PNMI_CNT_RX_LONGFRAMES().
* - Added speed mode & status to PNMI config struct.
* - Editorial changes.
- *
+ *
* Revision 1.50 2002/05/22 08:59:37 rwahl
* Added string definitions for error msgs.
- *
+ *
* Revision 1.49 2001/11/20 09:23:50 rwahl
* - pnmi struct: reordered and aligned to 32bit.
- *
+ *
* Revision 1.48 2001/02/23 14:34:24 mkunz
* Changed macro PHYS2INST. Added pAC to Interface
- *
+ *
* Revision 1.47 2001/02/07 08:28:23 mkunz
* - Added Oids: OID_SKGE_DIAG_ACTION
* OID_SKGE_DIAG_RESULT
* OID_SKGE_CURRENT_PACKET_FILTER
* OID_SKGE_INTERMEDIATE_SUPPORT
* - Changed value of OID_SKGE_MTU
- *
+ *
* Revision 1.46 2001/02/06 10:01:41 mkunz
* - Pnmi V4 dual net support added. Interface functions and macros extended
* - Vpd bug fixed
* - OID_SKGE_MTU added
- *
+ *
* Revision 1.45 2001/01/22 13:41:37 rassmann
* Supporting two nets on dual-port adapters.
- *
+ *
* Revision 1.44 2000/09/07 07:35:27 rwahl
* - removed NDIS counter specific data type.
* - fixed spelling for OID_SKGE_RLMT_PORT_PREFERRED.
- *
+ *
* Revision 1.43 2000/08/04 11:41:08 rwahl
* - Fixed compiler warning (port is always >= 0) for macros
* SK_PNMI_CNT_RX_LONGFRAMES & SK_PNMI_CNT_SYNC_OCTETS
- *
+ *
* Revision 1.42 2000/08/03 15:14:07 rwahl
* - Corrected error in driver macros addressing a physical port.
- *
+ *
* Revision 1.41 2000/08/01 16:22:29 rwahl
* - Changed MDB version to 3.1.
* - Added definitions for StatRxLongFrames counter.
* - Added macro to be used by driver to count long frames received.
* - Added directive to control width (default = 32bit) of NDIS statistic
* counters (SK_NDIS_64BIT_CTR).
- *
+ *
* Revision 1.40 2000/03/31 13:51:34 rwahl
* Added SK_UPTR cast to offset calculation for PNMI struct fields;
* missing cast caused compiler warnings by Win64 compiler.
*
* Revision 1.39 1999/12/06 10:09:47 rwahl
* Added new error log message.
- *
+ *
* Revision 1.38 1999/11/22 13:57:55 cgoos
* Changed license header to GPL.
*
* Revision 1.37 1999/09/14 14:25:32 rwahl
* Set MDB version for 1000Base-T (sensors, Master/Slave) changes.
- *
+ *
* Revision 1.36 1999/05/20 09:24:56 cgoos
* Changes for 1000Base-T (sensors, Master/Slave).
- *
+ *
* Revision 1.35 1999/04/13 15:10:51 mhaveman
* Replaced RLMT macros SK_RLMT_CHECK_xxx again by those of PNMI to
* grant unified interface. But PNMI macros will store the same
* value as RLMT macros.
- *
+ *
* Revision 1.34 1999/04/13 15:03:49 mhaveman
* -Changed copyright
* -Removed SK_PNMI_RLMT_MODE_CHK_xxx macros. Those of RLMT should be
* used.
- *
+ *
* Revision 1.33 1999/03/23 10:41:02 mhaveman
* Changed comments.
- *
+ *
* Revision 1.32 1999/01/25 15:01:33 mhaveman
* Added support for multiple simultaniously active ports.
- *
+ *
* Revision 1.31 1999/01/19 10:06:26 mhaveman
* Added new error log message.
- *
+ *
* Revision 1.30 1999/01/05 10:34:49 mhaveman
* Fixed little error in RlmtChangeEstimate calculation.
- *
+ *
* Revision 1.29 1999/01/05 09:59:41 mhaveman
* Redesigned port switch average calculation to avoid 64bit
* arithmetic.
- *
+ *
* Revision 1.28 1998/12/08 10:05:48 mhaveman
* Defined macro SK_PNMI_MIN_STRUCT_SIZE.
- *
+ *
* Revision 1.27 1998/12/03 14:39:35 mhaveman
* Fixed problem that LSTAT was enumerated wrong.
- *
+ *
* Revision 1.26 1998/12/03 11:19:51 mhaveman
* Changed contents of errlog message SK_PNMI_ERR016MSG
- *
+ *
* Revision 1.25 1998/12/01 10:40:04 mhaveman
* Changed size of SensorNumber, ChecksumNumber and RlmtPortNumber in
* SK_PNMI_STRUCT_DATA to be conform with OID definition.
- *
+ *
* Revision 1.24 1998/11/20 08:09:27 mhaveman
* Added macros to convert between logical, physical port indexes and
* instances.
- *
+ *
* Revision 1.23 1998/11/10 13:41:13 mhaveman
* Needed to change interface, because NT driver needs a return value
* of needed buffer space on TOO_SHORT errors. Therefore all
* SkPnmiGet/Preset/Set functions now have a pointer to the length
* parameter, where the needed space on error is returned.
- *
+ *
* Revision 1.22 1998/11/03 12:05:51 mhaveman
* Added pAC parameter to counter macors.
*
* Revision 1.21 1998/11/02 10:47:36 mhaveman
* Added syslog messages for internal errors.
- *
+ *
* Revision 1.20 1998/10/30 15:49:36 mhaveman
* -Removed unused SK_PNMI_UTILIZATION_BASE and EstOldCnt.
* -Redefined SK_PNMI_CHG_EST_BASE to hundreds of seconds.
- *
+ *
* Revision 1.19 1998/10/29 15:38:44 mhaveman
* Changed string lengths of PNMI_STRUCT_DATA structure because
* string OIDs are now encoded with leading length ocetet.
- *
+ *
* Revision 1.18 1998/10/29 08:52:27 mhaveman
* -Added byte to strings in PNMI_STRUCT_DATA structure.
* -Shortened SK_PNMI_RLMT structure to SK_MAX_MACS elements.
- *
+ *
* Revision 1.17 1998/10/28 08:49:50 mhaveman
* -Changed type of Instance back to SK_U32 because of VPD
* -Changed type from SK_U8 to char of PciBusSpeed, PciBusWidth, PMD,
* and Connector.
- *
+ *
* Revision 1.16 1998/10/22 10:42:31 mhaveman
* -Removed (SK_U32) casts for OIDs
* -excluded NDIS OIDs when they are already defined with ifndef _NDIS_
- *
+ *
* Revision 1.15 1998/10/20 13:56:28 mhaveman
* Headerfile includes now directly other header files to comile correctly.
- *
+ *
* Revision 1.14 1998/10/20 07:31:09 mhaveman
* Made type changes to unsigned int where possible.
- *
+ *
* Revision 1.13 1998/10/19 10:53:13 mhaveman
* -Casted OID definitions to SK_U32
* -Renamed RlmtMAC... to RlmtPort...
* -Changed wrong type of VpdEntriesList from SK_U32 to char *
- *
+ *
* Revision 1.12 1998/10/13 07:42:27 mhaveman
* -Added OIDs OID_SKGE_TRAP_NUMBER and OID_SKGE_ALL_DATA
* -Removed old cvs history entries
* -Renamed MacNumber to PortNumber
- *
+ *
* Revision 1.11 1998/10/07 10:55:24 mhaveman
* -Added OID_MDB_VERSION. Therefore was a renumbering of the VPD OIDs
* necessary.
* -Added OID_GEN_ Ids to support the windows driver.
- *
+ *
* Revision 1.10 1998/09/30 13:41:10 mhaveman
* Renamed some OIDs to reduce usage of 'MAC' which is replaced by 'PORT'.
- *
+ *
* Revision 1.9 1998/09/04 17:06:17 mhaveman
* -Added SyncCounter as macro.
* -Renamed OID_SKGE_.._NO_DESCR_CTS to OID_SKGE_.._NO_BUF_CTS.
* -Added macros for driver description and version strings.
- *
+ *
* Revision 1.8 1998/09/04 14:36:52 mhaveman
* Added OIDs and Structure to access value of macro counters which are
* counted by the driver.
- *
+ *
* Revision 1.7 1998/09/04 11:59:36 mhaveman
* Everything compiles now. Driver Macros for counting still missing.
- *
+ *
****************************************************************************/
#ifndef _SKGEPNMI_H_
/* #define OID_802_3_MULTICAST_LIST 0x01010103 */
/* #define OID_802_3_MAXIMUM_LIST_SIZE 0x01010104 */
/* #define OID_802_3_MAC_OPTIONS 0x01010105 */
-
+
#define OID_802_3_RCV_ERROR_ALIGNMENT 0x01020101
#define OID_802_3_XMIT_ONE_COLLISION 0x01020102
#define OID_802_3_XMIT_MORE_COLLISIONS 0x01020103
#define OID_SKGE_VPD_VALUE 0xFF010106
#define OID_SKGE_VPD_ACCESS 0xFF010107
#define OID_SKGE_VPD_ACTION 0xFF010108
-
+
#define OID_SKGE_PORT_NUMBER 0xFF010110
#define OID_SKGE_DEVICE_TYPE 0xFF010111
#define OID_SKGE_DRIVER_DESCR 0xFF010112
#define OID_SKGE_SPEED_MODE 0xFF010171
#define OID_SKGE_SPEED_STATUS 0xFF010172
-#define OID_SKGE_SENSOR_NUMBER 0xFF020100
+#define OID_SKGE_SENSOR_NUMBER 0xFF020100
#define OID_SKGE_SENSOR_INDEX 0xFF020101
#define OID_SKGE_SENSOR_DESCR 0xFF020102
#define OID_SKGE_SENSOR_TYPE 0xFF020103
* Revision 1.26 2002/10/14 09:52:36 rschmidt
* Added SKERR_SIRQ_E023 and SKERR_SIRQ_E023 for GPHY (Yukon)
* Editorial changes
- *
+ *
* Revision 1.25 2002/07/15 18:15:52 rwahl
* Editorial changes.
- *
+ *
* Revision 1.24 2002/07/15 15:39:21 rschmidt
* Corrected define for SKERR_SIRQ_E022
* Editorial changes
- *
+ *
* Revision 1.23 2002/04/25 11:09:45 rschmidt
* Removed declarations for SkXmInitPhy(), SkXmRxTxEnable()
* Editorial changes
- *
+ *
* Revision 1.22 2000/11/09 11:30:10 rassmann
* WA: Waiting after releasing reset until BCom chip is accessible.
- *
+ *
* Revision 1.21 2000/10/18 12:22:40 cgoos
* Added workaround for half duplex hangup.
- *
+ *
* Revision 1.20 1999/12/06 10:00:44 cgoos
* Added SET event for role.
- *
+ *
* Revision 1.19 1999/11/22 13:58:26 cgoos
* Changed license header to GPL.
- *
+ *
* Revision 1.18 1999/05/19 07:32:59 cgoos
* Changes for 1000Base-T.
- *
+ *
* Revision 1.17 1999/03/12 13:29:31 malthoff
* Move Autonegotiation Error Codes to skgeinit.h.
- *
+ *
* Revision 1.16 1999/03/08 10:11:28 gklug
* add: AutoNegDone return codes
- *
+ *
* Revision 1.15 1998/11/18 13:20:53 gklug
* add: different timeouts for active and non-active links
- *
+ *
* Revision 1.14 1998/11/04 07:18:14 cgoos
* Added prototype for SkXmRxTxEnable.
- *
+ *
* Revision 1.13 1998/10/21 05:52:23 gklug
* add: parameter DoLoop to InitPhy function
- *
+ *
* Revision 1.12 1998/10/19 06:45:03 cgoos
* Added prototype for SkXmInitPhy.
- *
+ *
* Revision 1.11 1998/10/15 14:34:10 gklug
* add: WA_TIME is 500 msec
- *
+ *
* Revision 1.10 1998/10/14 14:49:41 malthoff
* Remove err log defines E021 and E022. They are
* defined in skgeinit.h now.
*
* Revision 1.9 1998/10/14 14:00:39 gklug
* add: error logs for init phys
- *
+ *
* Revision 1.8 1998/10/14 05:44:05 gklug
* add: E020
- *
+ *
* Revision 1.7 1998/10/02 06:24:58 gklug
* add: error messages
- *
+ *
* Revision 1.6 1998/10/01 07:54:45 gklug
* add: PNMI debug module
- *
+ *
* Revision 1.5 1998/09/28 13:36:31 malthoff
* Move the bit definitions for Autonegotiation
* and Flow Control to skgeinit.h.
- *
+ *
* Revision 1.4 1998/09/15 12:29:34 gklug
* add: error logs
- *
+ *
* Revision 1.3 1998/09/03 13:54:02 gklug
* add: function prototypes
- *
+ *
* Revision 1.2 1998/09/03 10:24:36 gklug
* add: Events send by PNMI
* add: parameter definition for Flow Control etc.
- *
+ *
* Revision 1.1 1998/08/27 11:50:27 gklug
* initial revision
- *
+ *
*
******************************************************************************/
* $Log: ski2c.h,v $
* Revision 1.34 2003/01/28 09:11:21 rschmidt
* Editorial changes
- *
+ *
* Revision 1.33 2002/10/14 16:40:50 rschmidt
* Editorial changes (TWSI)
- *
+ *
* Revision 1.32 2002/08/13 08:55:07 rschmidt
* Editorial changes
- *
+ *
* Revision 1.31 2002/08/06 09:44:22 jschmalz
* Extensions and changes for Yukon
- *
+ *
* Revision 1.30 2001/04/05 11:38:09 rassmann
* Set SenState to idle in SkI2cWaitIrq().
* Changed error message in SkI2cWaitIrq().
- *
+ *
* Revision 1.29 2000/08/03 14:28:17 rassmann
* - Added function to wait for I2C being ready before resetting the board.
* - Replaced one duplicate "out of range" message with correct one.
- *
+ *
* Revision 1.28 1999/11/22 13:55:46 cgoos
* Changed license header to GPL.
- *
+ *
* Revision 1.27 1999/05/20 09:23:10 cgoos
* Changes for 1000Base-T (Fan sensors).
- *
+ *
* Revision 1.26 1998/12/01 13:45:47 gklug
* add: InitLevel to I2c struct
- *
+ *
* Revision 1.25 1998/11/03 06:55:16 gklug
* add: Dummy Reads to I2c struct
- *
+ *
* Revision 1.24 1998/10/02 14:28:59 cgoos
* Added prototype for SkI2cIsr.
- *
+ *
* Revision 1.23 1998/09/08 12:20:11 gklug
* add: prototypes for init and read functions
- *
+ *
* Revision 1.22 1998/09/08 07:37:56 gklug
* add: log error if PCI_IO voltage sensor could not be initialized
- *
+ *
* Revision 1.21 1998/09/04 08:38:05 malthoff
* Change the values for I2C_READ and I2C_WRITE
- *
+ *
* Revision 1.20 1998/08/25 07:52:22 gklug
* chg: Timestamps (last) added for logging
*
* Revision 1.19 1998/08/25 06:09:00 gklug
* rmv: warning and error levels of the individual sensors.
* add: timing definitions for sending traps and logging errors
- *
+ *
* Revision 1.18 1998/08/20 11:41:15 gklug
* chg: omit STRCPY macro by using char * as Sensor Description
- *
+ *
* Revision 1.17 1998/08/20 11:37:43 gklug
* chg: change Ioc to IoC
- *
+ *
* Revision 1.16 1998/08/20 11:30:38 gklug
* fix: SenRead declaration
- *
+ *
* Revision 1.15 1998/08/20 11:27:53 gklug
* fix: Compile bugs with new awrning constants
- *
+ *
* Revision 1.14 1998/08/20 08:53:12 gklug
* fix: compiler errors
* add: Threshold values
- *
+ *
* Revision 1.13 1998/08/19 12:21:16 gklug
* fix: remove struct from C files (see CCC)
* add: typedefs for all structs
- *
+ *
* Revision 1.12 1998/08/19 10:57:41 gklug
* add: Warning levels
- *
+ *
* Revision 1.11 1998/08/18 08:37:02 malthoff
* Prototypes not required for SK_DIAG.
- *
+ *
* Revision 1.10 1998/08/17 13:54:00 gklug
* fix: declaration of event function
- *
+ *
* Revision 1.9 1998/08/17 06:48:39 malthoff
* Remove some unrequired macros.
* Fix the compiler errors.
- *
+ *
* Revision 1.8 1998/08/14 06:47:19 gklug
* fix: Values are intergers
*
#endif
#endif /* n_SKI2C_H */
-
* $Log: skqueue.h,v $
* Revision 1.14 2002/03/15 10:52:13 mkunz
* Added event classes for link aggregation
- *
+ *
* Revision 1.13 1999/11/22 13:59:05 cgoos
* Changed license header to GPL.
- *
+ *
* Revision 1.12 1998/09/08 08:48:01 gklug
* add: init level handling
- *
+ *
* Revision 1.11 1998/09/03 14:15:11 gklug
* add: CSUM and HWAC Eventclass and function.
* fix: pParaPtr according to CCC
- *
+ *
* Revision 1.10 1998/08/20 12:43:03 gklug
* add: typedef SK_QUEUE
- *
+ *
* Revision 1.9 1998/08/19 09:50:59 gklug
* fix: remove struct keyword from c-code (see CCC) add typedefs
- *
+ *
* Revision 1.8 1998/08/18 07:00:01 gklug
* fix: SK_PTR not defined use void * instead.
- *
+ *
* Revision 1.7 1998/08/17 13:43:19 gklug
* chg: Parameter will be union of 64bit para, 2 times SK_U32 or SK_PTR
- *
+ *
* Revision 1.6 1998/08/14 07:09:30 gklug
* fix: chg pAc -> pAC
- *
+ *
* Revision 1.5 1998/08/11 14:26:44 gklug
* chg: Event Dispatcher returns now int.
- *
+ *
* Revision 1.4 1998/08/11 12:15:21 gklug
* add: Error numbers of skqueue module
- *
+ *
* Revision 1.3 1998/08/07 12:54:23 gklug
* fix: first compiled version
- *
+ *
* Revision 1.2 1998/08/07 09:34:00 gklug
* adapt structure defs to CCC
* add: prototypes for functions
- *
+ *
* Revision 1.1 1998/07/30 14:52:12 gklug
* Initial version.
* Defines Event Classes, Event structs and queue management variables.
- *
- *
+ *
+ *
*
******************************************************************************/
#define SKERR_Q_E002 (SKERR_Q_E001+1)
#define SKERR_Q_E002MSG "Undefined event class"
#endif /* _SKQUEUE_H_ */
-
* $Log: skrlmt.h,v $
* Revision 1.35 2003/01/31 14:12:41 mkunz
* single port adapter runs now with two identical MAC addresses
- *
+ *
* Revision 1.34 2002/09/23 15:13:41 rwahl
* Editorial changes.
- *
+ *
* Revision 1.33 2001/07/03 12:16:48 mkunz
* New Flag ChgBcPrio (Change priority of last broadcast received)
- *
+ *
* Revision 1.32 2001/02/14 14:06:31 rassmann
* Editorial changes.
- *
+ *
* Revision 1.31 2001/02/05 14:25:26 rassmann
* Prepared RLMT for transparent operation.
- *
+ *
* Revision 1.30 2001/01/22 13:41:39 rassmann
* Supporting two nets on dual-port adapters.
- *
+ *
* Revision 1.29 2000/11/17 08:58:00 rassmann
* Moved CheckSwitch from SK_RLMT_PACKET_RECEIVED to SK_RLMT_TIM event.
- *
+ *
* Revision 1.28 2000/11/09 12:24:34 rassmann
* Editorial changes.
- *
+ *
* Revision 1.27 1999/11/22 13:59:56 cgoos
* Changed license header to GPL.
- *
+ *
* Revision 1.26 1999/10/04 14:01:19 rassmann
* Corrected reaction to reception of BPDU frames (#10441).
- *
+ *
* Revision 1.25 1999/07/20 12:53:39 rassmann
* Fixed documentation errors for lookahead macros.
- *
+ *
* Revision 1.24 1999/05/28 11:15:56 rassmann
* Changed behaviour to reflect Design Spec v1.2.
* Controlling Link LED(s).
* Introduced RLMT Packet Version field in RLMT Packet.
* Newstyle lookahead macros (checking meta-information before looking at
* the packet).
- *
+ *
* Revision 1.23 1999/01/28 12:50:42 rassmann
* Not using broadcast time stamps in CheckLinkState mode.
- *
+ *
* Revision 1.22 1999/01/27 14:13:04 rassmann
* Monitoring broadcast traffic.
* Switching more reliably and not too early if switch is
* configured for spanning tree.
- *
+ *
* Revision 1.21 1998/12/08 13:11:25 rassmann
* Stopping SegTimer at RlmtStop.
- *
+ *
* Revision 1.20 1998/11/24 12:37:33 rassmann
* Implemented segmentation check.
- *
+ *
* Revision 1.19 1998/11/17 13:43:06 rassmann
* Handling (logical) tx failure.
* Sending packet on logical address after PORT_SWITCH.
- *
+ *
* Revision 1.18 1998/11/13 16:56:56 rassmann
* Added macro version of SkRlmtLookaheadPacket.
- *
+ *
* Revision 1.17 1998/11/06 18:06:05 rassmann
* Corrected timing when RLMT checks fail.
* Clearing tx counter earlier in periodical checks.
- *
+ *
* Revision 1.16 1998/11/03 13:53:50 rassmann
* RLMT should switch now (at least in mode 3).
- *
+ *
* Revision 1.15 1998/10/22 11:39:52 rassmann
* Corrected signed/unsigned mismatches.
* Corrected receive list handling and address recognition.
- *
+ *
* Revision 1.14 1998/10/15 15:16:36 rassmann
* Finished Spanning Tree checking.
* Checked with lint.
- *
+ *
* Revision 1.13 1998/09/24 19:16:08 rassmann
* Code cleanup.
* Introduced Timer for PORT_DOWN due to no RX.
- *
+ *
* Revision 1.12 1998/09/16 11:09:52 rassmann
* Syntax corrections.
- *
+ *
* Revision 1.11 1998/09/15 11:28:50 rassmann
* Syntax corrections.
- *
+ *
* Revision 1.10 1998/09/14 17:07:38 rassmann
* Added code for port checking via LAN.
* Changed Mbuf definition.
- *
+ *
* Revision 1.9 1998/09/07 11:14:15 rassmann
* Syntax corrections.
- *
+ *
* Revision 1.8 1998/09/07 09:06:08 rassmann
* Syntax corrections.
- *
+ *
* Revision 1.7 1998/09/04 19:41:34 rassmann
* Syntax corrections.
* Started entering code for checking local links.
- *
+ *
* Revision 1.6 1998/09/04 12:14:28 rassmann
* Interface cleanup.
- *
+ *
* Revision 1.5 1998/09/02 16:55:29 rassmann
* Updated to reflect new DRV/HWAC/RLMT interface.
- *
+ *
* Revision 1.4 1998/09/02 07:26:02 afischer
* typedef for SK_RLMT_PORT
*
* Revision 1.3 1998/08/27 14:29:03 rassmann
* Code cleanup.
- *
+ *
* Revision 1.2 1998/08/27 14:26:25 rassmann
* Updated interface.
- *
+ *
* Revision 1.1 1998/08/21 08:29:10 rassmann
* First public version.
- *
+ *
******************************************************************************/
/******************************************************************************
*(pNumBytes) = 0; \
} \
else {\
- if ((_pAC->Rlmt.Port[_PortNum].Net->RlmtMode & SK_RLMT_TRANSPARENT) != 0) { \
- *(pNumBytes) = 0; \
- } \
- else if (IsBc) { \
- if (_pAC->Rlmt.Port[_PortNum].Net->RlmtMode != SK_RLMT_MODE_CLS) { \
- *(pNumBytes) = 6; \
- *(pOffset) = 6; \
- } \
- else { \
- *(pNumBytes) = 0; \
- } \
- } \
- else { \
- if ((PktLen) > SK_RLMT_MAX_TX_BUF_SIZE) { \
- /* _pAC->Rlmt.Port[_PortNum].DataPacketsPerTimeSlot++; */ \
- *(pNumBytes) = 0; \
- } \
- else { \
- *(pNumBytes) = 6; \
- *(pOffset) = 0; \
- } \
- } \
+ if ((_pAC->Rlmt.Port[_PortNum].Net->RlmtMode & SK_RLMT_TRANSPARENT) != 0) { \
+ *(pNumBytes) = 0; \
+ } \
+ else if (IsBc) { \
+ if (_pAC->Rlmt.Port[_PortNum].Net->RlmtMode != SK_RLMT_MODE_CLS) { \
+ *(pNumBytes) = 6; \
+ *(pOffset) = 6; \
+ } \
+ else { \
+ *(pNumBytes) = 0; \
+ } \
+ } \
+ else { \
+ if ((PktLen) > SK_RLMT_MAX_TX_BUF_SIZE) { \
+ /* _pAC->Rlmt.Port[_PortNum].DataPacketsPerTimeSlot++; */ \
+ *(pNumBytes) = 0; \
+ } \
+ else { \
+ *(pNumBytes) = 6; \
+ *(pOffset) = 0; \
+ } \
+ } \
} \
}
/* ----- Private part ----- */
SK_BOOL CheckSwitch;
- SK_BOOL RlmtOff; /* set to zero if the Mac addresses
- are equal or the second one
- is zero */
+ SK_BOOL RlmtOff; /* set to zero if the Mac addresses
+ are equal or the second one
+ is zero */
SK_U16 Align01;
} SK_RLMT;
* $Log: sktimer.h,v $
* Revision 1.9 1999/11/22 14:00:29 cgoos
* Changed license header to GPL.
- *
+ *
* Revision 1.8 1998/09/08 08:48:02 gklug
* add: init level handling
- *
+ *
* Revision 1.7 1998/08/20 12:31:29 gklug
* fix: SK_TIMCTRL needs to be defined
- *
+ *
* Revision 1.6 1998/08/19 09:51:00 gklug
* fix: remove struct keyword from c-code (see CCC) add typedefs
- *
+ *
* Revision 1.5 1998/08/17 13:43:21 gklug
* chg: Parameter will be union of 64bit para, 2 times SK_U32 or SK_PTR
- *
+ *
* Revision 1.4 1998/08/14 07:09:31 gklug
* fix: chg pAc -> pAC
- *
+ *
* Revision 1.3 1998/08/07 12:54:24 gklug
* fix: first compiled version
- *
+ *
* Revision 1.2 1998/08/07 09:35:29 gklug
* add: Timer control struct for Adapters context
* add: function prototypes
- *
+ *
* Revision 1.1 1998/08/05 11:27:01 gklug
* First version: adapted from SMT
- *
+ *
*
******************************************************************************/
* The information in this file is provided "AS IS" without warranty.
*
******************************************************************************/
-
+
/*****************************************************************************
*
* History:
* $Log: sktypes.h,v $
* Revision 1.3 2003/02/25 14:16:40 mlindner
* Fix: Copyright statement
- *
+ *
* Revision 1.2 1999/11/22 14:01:58 cgoos
* Changed license header to GPL.
* Now using Linux' fixed size types instead of standard types.
- *
+ *
* Revision 1.1 1999/02/16 07:41:40 cgoos
* First version.
- *
- *
+ *
+ *
*
*****************************************************************************/
*
* In this file, all data types that are needed by the common modules
* are mapped to Linux data types.
- *
+ *
*
* Include File Hierarchy:
*
* $Log: skversion.h,v $
* Revision 1.4 2003/02/25 14:16:40 mlindner
* Fix: Copyright statement
- *
+ *
* Revision 1.3 2003/02/25 13:30:18 mlindner
* Add: Support for various vendors
- *
+ *
* Revision 1.1.2.1 2001/09/05 13:38:30 mlindner
* Removed FILE description
- *
+ *
* Revision 1.1 2001/03/06 09:25:00 mlindner
* first version
- *
- *
+ *
+ *
*
******************************************************************************/
-
-
+
+
static const char SysKonnectFileId[] = "@(#) (C) SysKonnect GmbH.";
static const char SysKonnectBuildNumber[] =
- "@(#)SK-BUILD: 6.05 PL: 01";
+ "@(#)SK-BUILD: 6.05 PL: 01";
#define BOOT_STRING "sk98lin: Network Device Driver v6.05\n" \
"(C)Copyright 1999-2003 Marvell(R)."
#define VER_STRING "6.05"
-
-
* Revision 1.15 2003/01/13 10:39:38 rschmidt
* Replaced define for PCI device Id for YUKON with GENESIS
* Editorial changes
- *
+ *
* Revision 1.14 2002/11/14 15:18:10 gheinig
* Added const specifier to key and buf parameters for VpdPara,VpdRead
* and VpdWrite. This is necessary for the Diag 7 GUI API
- *
+ *
* Revision 1.13 2002/10/14 15:58:18 rschmidt
* Added entry in rom_size struct s_vpd
* Editorial changes
- *
+ *
* Revision 1.12 2002/09/09 14:43:51 mkarl
* added PCI Id of Yukon for reading VPD in diag before the adapter has
* been initialized
* editorial changes
- *
+ *
* Revision 1.11 2002/07/26 13:19:16 mkarl
* added support for Yukon
* added vpd_size to VPD struct
- *
+ *
* Revision 1.10 2000/08/10 11:29:07 rassmann
* Editorial changes.
* Preserving 32-bit alignment in structs for the adapter context.
* Removed unused function VpdWriteDword() (#if 0).
* Made VpdReadKeyword() available for SKDIAG only.
- *
+ *
* Revision 1.9 1999/11/22 14:02:27 cgoos
* Changed license header to GPL.
- *
+ *
* Revision 1.8 1999/03/11 14:26:40 malthoff
* Replace __STDC__ with SK_KR_PROTO.
- *
+ *
* Revision 1.7 1998/10/28 07:27:17 gklug
* rmv: SWAP macros
* add: VPD_IN/OUT8 macros
* chg: interface definition
- *
+ *
* Revision 1.6 1998/10/22 10:03:44 gklug
* fix: use SK_OUT16 instead of SK_OUTW
- *
+ *
* Revision 1.5 1998/10/14 07:05:31 cgoos
* Changed constants in SK_SWAP_32 to UL.
- *
+ *
* Revision 1.4 1998/08/19 08:14:09 gklug
* fix: remove struct keyword as much as possible from the C-code (see CCC)
- *
+ *
* Revision 1.3 1998/08/18 08:18:56 malthoff
* Modify VPD in and out macros for SK_DIAG
- *
+ *
* Revision 1.2 1998/07/03 14:49:08 malthoff
* Add VPD_INxx() and VPD_OUTxx() macros for the Diagnostics tool.
- *
+ *
* Revision 1.1 1998/06/19 14:08:03 malthoff
* Created.
- *
+ *
*
******************************************************************************/
* Added defines for copper MDI/MDIX configuration
* Added defines for LED Control Register
* Editorial changes
- *
+ *
* Revision 1.45 2002/12/10 14:35:13 rschmidt
* Corrected defines for Extended PHY Specific Control
* Added defines for Ext. PHY Specific Ctrl 2 Reg. (Fiber specific)
- *
+ *
* Revision 1.44 2002/12/09 14:58:41 rschmidt
* Added defines for Ext. PHY Specific Ctrl Reg. (downshift feature)
* Added 'GMR_FS_UN_SIZE'-Bit to Rx GMAC FIFO Flush Mask
- *
+ *
* Revision 1.43 2002/12/05 10:14:45 rschmidt
* Added define for GMAC's Half Duplex Burst Mode
* Added define for Rx GMAC FIFO Flush Mask (default)
- *
+ *
* Revision 1.42 2002/11/12 16:48:19 rschmidt
* Added defines for Cable Diagnostic Register (GPHY)
* Editorial changes
- *
+ *
* Revision 1.41 2002/10/21 11:20:22 rschmidt
* Added bit GMR_FS_GOOD_FC to GMR_FS_ANY_ERR
* Editorial changes
- *
+ *
* Revision 1.40 2002/10/14 14:54:14 rschmidt
* Added defines for GPHY Specific Status and GPHY Interrupt Status
* Added bits PHY_M_IS_AN_ERROR and PHY_M_IS_FIFO_ERROR to PHY_M_DEF_MSK
* Editorial changes
- *
+ *
* Revision 1.39 2002/10/10 15:53:44 mkarl
* added some bit definitions for link speed status and LED's
- *
+ *
* Revision 1.38 2002/08/21 16:23:46 rschmidt
* Added defines for PHY Specific Ctrl Reg
* Editorial changes
- *
+ *
* Revision 1.37 2002/08/16 14:50:33 rschmidt
* Added defines for Auto-Neg. Advertisement YUKON Fiber (88E1011S only)
* Changed define PHY_M_DEF_MSK for GPHY IRQ Mask
* Editorial changes
- *
+ *
* Revision 1.36 2002/08/12 13:21:10 rschmidt
* Added defines for different Broadcom PHY Ids
- *
+ *
* Revision 1.35 2002/08/08 15:58:01 rschmidt
* Added defines for Manual LED Override register (YUKON)
* Editorial changes
- *
+ *
* Revision 1.34 2002/07/31 17:23:36 rwahl
* Added define GMR_FS_ANY_ERR (analogous to XMR_FS_ANY_ERR).
- *
+ *
* Revision 1.33 2002/07/23 16:03:37 rschmidt
* Added defines for GPHY registers
* Editorial changes
- *
+ *
* Revision 1.32 2002/07/15 18:14:37 rwahl
* Added GMAC MIB counters definitions.
* Editorial changes.
- *
+ *
* Revision 1.31 2002/07/15 15:42:50 rschmidt
* Removed defines from PHY specific reg. which are
* common to all PHYs
* Added defines for GMAC MIB Counters
* Editorial changes
- *
+ *
* Revision 1.30 2002/06/05 08:22:12 rschmidt
* Changed defines for GMAC Rx Control Register and Rx Status
* Editorial changes
- *
+ *
* Revision 1.29 2002/04/25 11:43:56 rschmidt
* Added define PHY_B_AS_PAUSE_MSK for BCom Pause Res.
* Added new registers and defines for YUKON (GMAC, GPHY)
* Added Receive Frame Status Encoding for YUKON
* Editorial changes
- *
+ *
* Revision 1.28 2000/11/09 12:32:49 rassmann
* Renamed variables.
- *
+ *
* Revision 1.27 2000/05/17 11:00:46 malthoff
* Add bit for enable/disable power management in BCOM chip.
- *
+ *
* Revision 1.26 1999/11/22 14:03:00 cgoos
* Changed license header to GPL.
- *
+ *
* Revision 1.25 1999/08/12 19:19:38 malthoff
* Add PHY_B_AC_TX_TST bit according to BCOM A1 errata sheet.
- *
+ *
* Revision 1.24 1999/07/30 11:27:21 cgoos
* Fixed a missing end-of-comment.
- *
+ *
* Revision 1.23 1999/07/30 07:03:31 malthoff
* Cut some long comments.
* Correct the XMAC PHY ID definitions.
- *
+ *
* Revision 1.22 1999/05/19 07:33:18 cgoos
* Changes for 1000Base-T.
- *
+ *
* Revision 1.21 1999/03/25 07:46:11 malthoff
* Add XM_HW_CFG, XM_TS_READ, and XM_TS_LOAD registers.
- *
+ *
* Revision 1.20 1999/03/12 13:36:09 malthoff
* Remove __STDC__.
*
/* PHY_AN_LP_NP (see XMAC) Bit 3: Link Partner can Next Page */
/* PHY_AN_LOC_NP (see XMAC) Bit 2: Local PHY can Next Page */
/* PHY_AN_RX_PG (see XMAC) Bit 1: Page Received */
-#define PHY_B_AN_LP_CAP (1<<0) /* Bit 0: Link Partner Auto-Neg. Cap. */
+#define PHY_B_AN_LP_CAP (1<<0) /* Bit 0: Link Partner Auto-Neg. Cap. */
/***** PHY_LONE_AUNE_EXP 16 bit r/o Auto-Negotiation Expansion Reg *****/
#define PHY_L_AN_BP (1<<5) /* Bit 5: Base Page Indication */
/* PHY_AN_LP_NP (see XMAC) Bit 3: Link Partner can Next Page */
/* PHY_AN_LOC_NP (see XMAC) Bit 2: Local PHY can Next Page */
/* PHY_AN_RX_PG (see XMAC) Bit 1: Page Received */
-#define PHY_B_AN_LP_CAP (1<<0) /* Bit 0: Link Partner Auto-Neg. Cap. */
+#define PHY_B_AN_LP_CAP (1<<0) /* Bit 0: Link Partner Auto-Neg. Cap. */
/***** PHY_XMAC_NEPG 16 bit r/w Next Page Register *****/
#define PHY_M_PC_POL_R_DIS (1<<1) /* Bit 1: Polarity Reversal Disabled */
#define PHY_M_PC_DIS_JABBER (1<<0) /* Bit 0: Disable Jabber */
-#define PHY_M_PC_MDI_XMODE(x) SHIFT5(x)
+#define PHY_M_PC_MDI_XMODE(x) SHIFT5(x)
#define PHY_M_PC_MAN_MDI 0 /* 00 = Manual MDI configuration */
#define PHY_M_PC_MAN_MDIX 1 /* 01 = Manual MDIX configuration */
#define PHY_M_PC_ENA_AUTO 3 /* 11 = Enable Automatic Crossover */
#define GM_GPSR_FC_RX_DIS (1<<2) /* Bit 2: Rx Flow Control Mode Disabled */
#define GM_GPSR_PROM_EN (1<<1) /* Bit 1: Promiscuous Mode Enabled */
/* Bit 0: reserved */
-
+
/* GM_GP_CTRL 16 bit r/w General Purpose Control Register */
/* Bit 15: reserved */
#define GM_GPCR_PROM_ENA (1<<14) /* Bit 14: Enable Promiscuous Mode */
#define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
#define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |\
GM_GPCR_AU_SPD_DIS)
-
+
/* GM_TX_CTRL 16 bit r/w Transmit Control Register */
#define GM_TXCR_FORCE_JAM (1<<15) /* Bit 15: Force Jam / Flow-Control */
#define GM_TXCR_CRC_DIS (1<<14) /* Bit 14: Disable insertion of CRC */
#define GM_TXCR_PAD_DIS (1<<13) /* Bit 13: Disable padding of packets */
#define GM_TXCR_COL_THR (4<<10) /* Bit 12..10: Collision Threshold */
-
+
/* GM_RX_CTRL 16 bit r/w Receive Control Register */
#define GM_RXCR_UCF_ENA (1<<15) /* Bit 15: Enable Unicast filtering */
#define GM_RXCR_MCF_ENA (1<<14) /* Bit 14: Enable Multicast filtering */
#define GM_RXCR_CRC_DIS (1<<13) /* Bit 13: Remove 4-byte CRC */
#define GM_RXCR_PASS_FC (1<<12) /* Bit 12: Pass FC packets to FIFO */
-
+
/* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */
#define GM_TXPA_JAMLEN_MSK (0x03<<14) /* Bit 15..14: Jam Length */
#define GM_TXPA_JAMIPG_MSK (0x1f<<9) /* Bit 13..9: Jam IPG */
#define GM_SMOD_JUMBO_ENA (1<<8) /* Bit 8: Enable Jumbo (Max. Frame Length) */
/* Bit 7..5: reserved */
#define GM_SMOD_IPG_MSK 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */
-
+
#define DATA_BLIND_VAL(x) SHIFT11(x)
#define DATA_BLIND_FAST_ETH 0x1c
#define DATA_BLIND_GIGABIT 4
#define GM_SMI_CT_RD_VAL (1<<4) /* Bit 4: Read Valid (Read completed) */
#define GM_SMI_CT_BUSY (1<<3) /* Bit 3: Busy (Operation in progress) */
/* Bit 2..0: reserved */
-
+
/* GM_PHY_ADDR 16 bit r/w GPHY Address Register */
/* Bit 15..6: reserved */
#define GM_PAR_MIB_CLR (1<<5) /* Bit 5: Set MIB Clear Counter Mode */
#define GM_PAR_MIB_TST (1<<4) /* Bit 4: MIB Load Counter (Test Mode) */
/* Bit 3..0: reserved */
-
+
/* Receive Frame Status Encoding */
#define GMR_FS_LEN (0xffffUL<<16) /* Bit 31..16: Rx Frame Length */
/* Bit 15..14: reserved */
* Revision 1.48 2003/02/12 17:09:37 tschilli
* Fix in SkAddrOverride() to set both (physical and logical) MAC addresses
* in case that both addresses are identical.
- *
+ *
* Revision 1.47 2002/09/17 06:31:10 tschilli
* Handling of SK_PROM_MODE_ALL_MC flag in SkAddrGmacMcUpdate()
* and SkAddrGmacPromiscuousChange() fixed.
* Editorial changes.
- *
+ *
* Revision 1.46 2002/08/22 07:55:41 tschilli
* New function SkGmacMcHash() for GMAC multicast hashing algorithm added.
* Editorial changes.
- *
+ *
* Revision 1.45 2002/08/15 12:29:35 tschilli
* SkAddrGmacMcUpdate() and SkAddrGmacPromiscuousChange() changed.
- *
+ *
* Revision 1.44 2002/08/14 12:18:03 rschmidt
* Replaced direct handling of MAC Hashing (XMAC and GMAC)
* with routine SkMacHashing().
* Replaced wrong 3rd para 'i' with 'PortNumber' in SkMacPromiscMode().
- *
+ *
* Revision 1.43 2002/08/13 09:37:43 rschmidt
* Corrected some SK_DBG_MSG outputs.
* Replaced wrong 2nd para pAC with IoC in SkMacPromiscMode().
* Editorial changes.
- *
+ *
* Revision 1.42 2002/08/12 11:24:36 rschmidt
* Remove setting of logical MAC address GM_SRC_ADDR_2 in SkAddrInit().
* Replaced direct handling of MAC Promiscuous Mode (XMAC and GMAC)
* with routine SkMacPromiscMode().
* Editorial changes.
- *
+ *
* Revision 1.41 2002/06/10 13:52:18 tschilli
* Changes for handling YUKON.
* All changes are internally and not visible to the programmer
* using this module.
- *
+ *
* Revision 1.40 2001/02/14 14:04:59 rassmann
* Editorial changes.
- *
+ *
* Revision 1.39 2001/01/30 10:30:04 rassmann
* Editorial changes.
- *
+ *
* Revision 1.38 2001/01/25 16:26:52 rassmann
* Ensured that logical address overrides are done on net's active port.
- *
+ *
* Revision 1.37 2001/01/22 13:41:34 rassmann
* Supporting two nets on dual-port adapters.
- *
+ *
* Revision 1.36 2000/08/07 11:10:39 rassmann
* Editorial changes.
- *
+ *
* Revision 1.35 2000/05/04 09:38:41 rassmann
* Editorial changes.
* Corrected multicast address hashing.
- *
+ *
* Revision 1.34 1999/11/22 13:23:44 cgoos
* Changed license header to GPL.
- *
+ *
* Revision 1.33 1999/05/28 10:56:06 rassmann
* Editorial changes.
- *
+ *
* Revision 1.32 1999/03/31 10:59:20 rassmann
* Returning Success instead of DupAddr if address shall be overridden
* with same value.
- *
+ *
* Revision 1.31 1999/01/14 16:18:17 rassmann
* Corrected multicast initialization.
- *
+ *
* Revision 1.30 1999/01/04 10:30:35 rassmann
* SkAddrOverride only possible after SK_INIT_IO phase.
- *
+ *
* Revision 1.29 1998/12/29 13:13:10 rassmann
* An address override is now preserved in the SK_INIT_IO phase.
* All functions return an int now.
* Extended parameter checking.
- *
+ *
* Revision 1.28 1998/12/01 11:45:53 rassmann
* Code cleanup.
- *
+ *
* Revision 1.27 1998/12/01 09:22:49 rassmann
* SkAddrMcAdd and SkAddrMcUpdate returned SK_MC_FILTERING_INEXACT
* too often.
- *
+ *
* Revision 1.26 1998/11/24 12:39:44 rassmann
* Reserved multicast entry for BPDU address.
* 13 multicast entries left for protocol.
- *
+ *
* Revision 1.25 1998/11/17 16:54:23 rassmann
* Using exact match for up to 14 multicast addresses.
* Still receiving all multicasts if more addresses are added.
- *
+ *
* Revision 1.24 1998/11/13 17:24:31 rassmann
* Changed return value of SkAddrOverride to int.
- *
+ *
* Revision 1.23 1998/11/13 16:56:18 rassmann
* Added macro SK_ADDR_COMPARE.
* Changed return type of SkAddrOverride to SK_BOOL.
- *
+ *
* Revision 1.22 1998/11/04 17:06:17 rassmann
* Corrected McUpdate and PromiscuousChange functions.
- *
+ *
* Revision 1.21 1998/10/29 14:34:04 rassmann
* Clearing SK_ADDR struct at startup.
- *
+ *
* Revision 1.20 1998/10/28 18:16:34 rassmann
* Avoiding I/Os before SK_INIT_RUN level.
* Aligning InexactFilter.
- *
+ *
* Revision 1.19 1998/10/28 11:29:28 rassmann
* Programming physical address in SkAddrMcUpdate.
* Corrected programming of exact match entries.
- *
+ *
* Revision 1.18 1998/10/28 10:34:48 rassmann
* Corrected reading of physical addresses.
- *
+ *
* Revision 1.17 1998/10/28 10:26:13 rassmann
* Getting ports' current MAC addresses from EPROM now.
* Added debug output.
- *
+ *
* Revision 1.16 1998/10/27 16:20:12 rassmann
* Reading MAC address byte by byte.
- *
+ *
* Revision 1.15 1998/10/22 11:39:09 rassmann
* Corrected signed/unsigned mismatches.
- *
+ *
* Revision 1.14 1998/10/19 17:12:35 rassmann
* Syntax corrections.
- *
+ *
* Revision 1.13 1998/10/19 17:02:19 rassmann
* Now reading permanent MAC addresses from CRF.
- *
+ *
* Revision 1.12 1998/10/15 15:15:48 rassmann
* Changed Flags Parameters from SK_U8 to int.
* Checked with lint.
- *
+ *
* Revision 1.11 1998/09/24 19:15:12 rassmann
* Code cleanup.
- *
+ *
* Revision 1.10 1998/09/18 20:18:54 rassmann
* Added HW access.
* Implemented swapping.
- *
+ *
* Revision 1.9 1998/09/16 11:32:00 rassmann
* Including skdrv1st.h again. :(
- *
+ *
* Revision 1.8 1998/09/16 11:09:34 rassmann
* Syntax corrections.
- *
+ *
* Revision 1.7 1998/09/14 17:06:34 rassmann
* Minor changes.
- *
+ *
* Revision 1.6 1998/09/07 08:45:41 rassmann
* Syntax corrections.
- *
+ *
* Revision 1.5 1998/09/04 19:40:19 rassmann
* Interface enhancements.
- *
+ *
* Revision 1.4 1998/09/04 12:14:12 rassmann
* Interface cleanup.
- *
+ *
* Revision 1.3 1998/09/02 16:56:40 rassmann
* Updated interface.
- *
+ *
* Revision 1.2 1998/08/27 14:26:09 rassmann
* Updated interface.
- *
+ *
* Revision 1.1 1998/08/21 08:30:22 rassmann
* First public version.
*
for (i = 0; i < SK_MAX_MACS; i++) {
pAPort = &pAC->Addr.Port[i];
pAPort->PromMode = SK_PROM_MODE_NONE;
-
+
pAPort->FirstExactMatchRlmt = SK_ADDR_FIRST_MATCH_RLMT;
pAPort->FirstExactMatchDrv = SK_ADDR_FIRST_MATCH_DRV;
pAPort->NextExactMatchRlmt = SK_ADDR_FIRST_MATCH_RLMT;
}
}
#endif /* DEBUG */
-
+
/* Read permanent logical MAC address from Control Register File. */
for (j = 0; j < SK_MAC_ADDR_LEN; j++) {
InAddr = (SK_U8 *) &pAC->Addr.Net[0].PermanentMacAddress.a[j];
pAC->Addr.Net[i].PermanentMacAddress.a[3],
pAC->Addr.Net[i].PermanentMacAddress.a[4],
pAC->Addr.Net[i].PermanentMacAddress.a[5]))
-
+
SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_INIT,
("Logical MAC Address (Net%d): %02X %02X %02X %02X %02X %02X\n",
i,
/* Set port's current physical MAC address. */
OutAddr = (SK_U16 *) &pAPort->CurrentMacAddress.a[0];
-
+
if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) {
XM_OUTADDR(IoC, i, XM_SA, OutAddr);
}
pAPort->PermanentMacAddress.a[3],
pAPort->PermanentMacAddress.a[4],
pAPort->PermanentMacAddress.a[5]))
-
+
SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_INIT,
("SkAddrInit: Physical MAC Address: %02X %02X %02X %02X %02X %02X\n",
pAPort->CurrentMacAddress.a[0],
}
return (SK_ADDR_SUCCESS);
-
+
} /* SkAddrInit */
int Flags) /* permanent/non-perm, sw-only */
{
int ReturnCode;
-
+
if (PortNumber >= (SK_U32) pAC->GIni.GIMacsFound) {
return (SK_ADDR_ILLEGAL_PORT);
}
-
+
if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) {
ReturnCode = SkAddrXmacMcClear(pAC, IoC, PortNumber, Flags);
}
}
return (SK_ADDR_SUCCESS);
-
+
} /* SkAddrXmacMcClear */
for (i = 0; i < 8; i++) {
pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] = 0;
}
-
+
if (Flags & SK_ADDR_PERMANENT) { /* permanent => RLMT */
-
+
/* Copy DRV bits to InexactFilter. */
for (i = 0; i < 8; i++) {
pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] |=
pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[i];
-
+
/* Clear InexactRlmtFilter. */
pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[i] = 0;
- }
+ }
}
else { /* not permanent => DRV */
-
+
/* Copy RLMT bits to InexactFilter. */
for (i = 0; i < 8; i++) {
pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] |=
pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[i];
-
+
/* Clear InexactDrvFilter. */
pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[i] = 0;
}
}
-
+
#ifdef DEBUG
SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
("GMAC InexactFilter (cleared): %02X %02X %02X %02X %02X %02X %02X %02X\n",
pAC->Addr.Port[PortNumber].InexactFilter.Bytes[6],
pAC->Addr.Port[PortNumber].InexactFilter.Bytes[7]))
#endif /* DEBUG */
-
+
if (!(Flags & SK_MC_SW_ONLY)) {
(void) SkAddrGmacMcUpdate(pAC, IoC, PortNumber);
}
-
+
return (SK_ADDR_SUCCESS);
} /* SkAddrGmacMcClear */
for (Byte = 0; Byte < 6; Byte++) {
/* Get next byte. */
Data = (SK_U32) pMc[Byte];
-
+
/* Change bit order in byte. */
TmpData = Data;
for (Bit = 0; Bit < 8; Bit++) {
}
TmpData >>= 1;
}
-
+
Crc ^= (Data << 24);
for (Bit = 0; Bit < 8; Bit++) {
if (Crc & 0x80000000) {
}
}
}
-
+
return (Crc & ((1 << HASH_BITS) - 1));
} /* SkGmacMcHash */
int Flags) /* permanent/non-permanent */
{
int ReturnCode;
-
+
if (PortNumber >= (SK_U32) pAC->GIni.GIMacsFound) {
return (SK_ADDR_ILLEGAL_PORT);
}
-
+
if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) {
ReturnCode = SkAddrXmacMcAdd(pAC, IoC, PortNumber, pMc, Flags);
}
return (SK_MC_RLMT_OVERFLOW);
}
#endif /* DEBUG */
-
+
if (pAC->Addr.Port[PortNumber].NextExactMatchRlmt >
SK_ADDR_LAST_MATCH_RLMT) {
return (SK_MC_RLMT_OVERFLOW);
return (SK_MC_RLMT_OVERFLOW);
}
#endif /* DEBUG */
-
+
if (pAC->Addr.Port[PortNumber].NextExactMatchDrv <= SK_ADDR_LAST_MATCH_DRV) {
/* Set exact match entry. */
#ifndef SK_ADDR_CHEAT
SK_U32 HashBit;
#endif /* !defined(SK_ADDR_CHEAT) */
-
+
if (!(pMc->a[0] & SK_MC_BIT)) {
/* Hashing only possible with multicast addresses. */
return (SK_MC_ILLEGAL_ADDRESS);
}
-
+
#ifndef SK_ADDR_CHEAT
-
+
/* Compute hash value of address. */
HashBit = SkGmacMcHash(&pMc->a[0]);
-
+
if (Flags & SK_ADDR_PERMANENT) { /* permanent => RLMT */
-
+
/* Add bit to InexactRlmtFilter. */
pAC->Addr.Port[PortNumber].InexactRlmtFilter.Bytes[HashBit / 8] |=
1 << (HashBit % 8);
-
+
/* Copy bit to InexactFilter. */
for (i = 0; i < 8; i++) {
pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] |=
#endif /* DEBUG */
}
else { /* not permanent => DRV */
-
+
/* Add bit to InexactDrvFilter. */
pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[HashBit / 8] |=
1 << (HashBit % 8);
-
+
/* Copy bit to InexactFilter. */
for (i = 0; i < 8; i++) {
pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] |=
pAC->Addr.Port[PortNumber].InexactDrvFilter.Bytes[7]))
#endif /* DEBUG */
}
-
+
#else /* SK_ADDR_CHEAT */
-
+
/* Set all bits in InexactFilter. */
for (i = 0; i < 8; i++) {
pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i] = 0xFF;
}
#endif /* SK_ADDR_CHEAT */
-
+
return (SK_MC_FILTERING_INEXACT);
-
+
} /* SkAddrGmacMcAdd */
SK_U32 PortNumber) /* Port Number */
{
int ReturnCode;
-
+
if (PortNumber >= (SK_U32) pAC->GIni.GIMacsFound) {
return (SK_ADDR_ILLEGAL_PORT);
}
-
+
if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) {
ReturnCode = SkAddrXmacMcUpdate(pAC, IoC, PortNumber);
}
else {
ReturnCode = SkAddrGmacMcUpdate(pAC, IoC, PortNumber);
}
-
+
return (ReturnCode);
} /* SkAddrMcUpdate */
SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
("SkAddrXmacMcUpdate on Port %u.\n", PortNumber))
-
+
pAPort = &pAC->Addr.Port[PortNumber];
#ifdef DEBUG
/* Clear other permanent exact match addresses on XMAC */
if (pAPort->NextExactMatchRlmt <= SK_ADDR_LAST_MATCH_RLMT) {
-
+
SkXmClrExactAddr(pAC, IoC, PortNumber, pAPort->NextExactMatchRlmt,
SK_ADDR_LAST_MATCH_RLMT);
}
/* Clear other non-permanent exact match addresses on XMAC */
if (pAPort->NextExactMatchDrv <= SK_ADDR_LAST_MATCH_DRV) {
-
+
SkXmClrExactAddr(pAC, IoC, PortNumber, pAPort->NextExactMatchDrv,
SK_ADDR_LAST_MATCH_DRV);
}
}
if (pAPort->PromMode & SK_PROM_MODE_ALL_MC) {
-
+
/* Set all bits in 64-bit hash register. */
XM_OUTHASH(IoC, PortNumber, XM_HSM, &OnesHash);
-
+
/* Enable Hashing */
SkMacHashing(pAC, IoC, PortNumber, SK_TRUE);
}
else if (Inexact != 0) {
-
+
/* Set 64-bit hash register to InexactFilter. */
XM_OUTHASH(IoC, PortNumber, XM_HSM, &pAPort->InexactFilter.Bytes[0]);
-
+
/* Enable Hashing */
SkMacHashing(pAC, IoC, PortNumber, SK_TRUE);
}
/* Set port's current physical MAC address. */
OutAddr = (SK_U16 *) &pAPort->CurrentMacAddress.a[0];
-
+
XM_OUTADDR(IoC, PortNumber, XM_SA, OutAddr);
#ifdef xDEBUG
/* Get exact match address i from port PortNumber. */
InAddr = (SK_U16 *) &InAddr8[0];
-
+
XM_INADDR(IoC, PortNumber, XM_EXM(i), InAddr);
-
+
SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
("SkAddrXmacMcUpdate: MC address %d on Port %u: ",
"%02x %02x %02x %02x %02x %02x -- %02x %02x %02x %02x %02x %02x\n",
pAPort->Exact[i].a[4],
pAPort->Exact[i].a[5]))
}
-#endif /* DEBUG */
+#endif /* DEBUG */
/* Determine return value. */
if (Inexact == 0 && pAPort->PromMode == 0) {
else {
return (SK_MC_FILTERING_INEXACT);
}
-
+
} /* SkAddrXmacMcUpdate */
SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
("SkAddrGmacMcUpdate on Port %u.\n", PortNumber))
-
+
pAPort = &pAC->Addr.Port[PortNumber];
#ifdef DEBUG
SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
("Next0 on Port %d: %d\n", PortNumber, Next0[PortNumber]))
#endif /* DEBUG */
-
+
for (Inexact = 0, i = 0; i < 8; i++) {
Inexact |= pAPort->InexactFilter.Bytes[i];
}
-
+
/* Set 64-bit hash register to InexactFilter. */
GM_OUTHASH(IoC, PortNumber, GM_MC_ADDR_H1,
&pAPort->InexactFilter.Bytes[0]);
-
- if (pAPort->PromMode & SK_PROM_MODE_ALL_MC) {
-
+
+ if (pAPort->PromMode & SK_PROM_MODE_ALL_MC) {
+
/* Set all bits in 64-bit hash register. */
GM_OUTHASH(IoC, PortNumber, GM_MC_ADDR_H1, &OnesHash);
-
+
/* Enable Hashing */
SkMacHashing(pAC, IoC, PortNumber, SK_TRUE);
}
- else {
+ else {
/* Enable Hashing. */
SkMacHashing(pAC, IoC, PortNumber, SK_TRUE);
}
-
+
if (pAPort->PromMode != SK_PROM_MODE_NONE) {
(void) SkAddrGmacPromiscuousChange(pAC, IoC, PortNumber, pAPort->PromMode);
}
-
+
/* Set port's current physical MAC address. */
OutAddr = (SK_U16 *) &pAPort->CurrentMacAddress.a[0];
GM_OUTADDR(IoC, PortNumber, GM_SRC_ADDR_1L, OutAddr);
-
+
/* Set port's current logical MAC address. */
OutAddr = (SK_U16 *) &pAPort->Exact[0].a[0];
GM_OUTADDR(IoC, PortNumber, GM_SRC_ADDR_2L, OutAddr);
-
+
#ifdef DEBUG
SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
("SkAddrGmacMcUpdate: Permanent Physical MAC Address: %02X %02X %02X %02X %02X %02X\n",
pAPort->Exact[0].a[3],
pAPort->Exact[0].a[4],
pAPort->Exact[0].a[5]))
-
+
SK_DBG_MSG(pAC, SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
("SkAddrGmacMcUpdate: Physical MAC Address: %02X %02X %02X %02X %02X %02X\n",
pAPort->CurrentMacAddress.a[0],
pAPort->CurrentMacAddress.a[4],
pAPort->CurrentMacAddress.a[5]))
#endif /* DEBUG */
-
+
/* Determine return value. */
if (Inexact == 0 && pAPort->PromMode == 0) {
return (SK_MC_FILTERING_EXACT);
else {
return (SK_MC_FILTERING_INEXACT);
}
-
+
} /* SkAddrGmacMcUpdate */
/* Change port's physical MAC address. */
OutAddr = (SK_U16 *) pNewAddr;
-
+
if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) {
XM_OUTADDR(IoC, PortNumber, XM_SA, OutAddr);
}
pAC->Addr.Net[NetNumber].CurrentMacAddress.a)) {
return (SK_ADDR_SUCCESS);
}
-
+
for (i = 0; i < (SK_U32) pAC->GIni.GIMacsFound; i++) {
if (!pAC->Addr.Port[i].CurrentMacAddressSet) {
return (SK_ADDR_TOO_EARLY);
return (SK_ADDR_DUPLICATE_ADDRESS);
}
}
-
+
/*
* In case that the physical and the logical MAC addresses are equal
* we must also change the physical MAC address here.
*/
if (SK_ADDR_EQUAL(pAC->Addr.Port[PortNumber].CurrentMacAddress.a,
pAC->Addr.Port[PortNumber].Exact[0].a)) {
-
+
pAC->Addr.Port[PortNumber].PreviousMacAddress =
pAC->Addr.Port[PortNumber].CurrentMacAddress;
pAC->Addr.Port[PortNumber].CurrentMacAddress = *pNewAddr;
-
+
/* Report address change to RLMT. */
Para.Para32[0] = PortNumber;
Para.Para32[0] = -1;
SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_PORT_ADDR, Para);
}
-
+
/* Set PortNumber to number of net's active port. */
PortNumber = pAC->Rlmt.Net[NetNumber].
Port[pAC->Addr.Net[NetNumber].ActivePort]->PortNumber;
pAC->Addr.Net[NetNumber].PermanentMacAddress.a[3],
pAC->Addr.Net[NetNumber].PermanentMacAddress.a[4],
pAC->Addr.Net[NetNumber].PermanentMacAddress.a[5]))
-
+
SK_DBG_MSG(pAC,SK_DBGMOD_ADDR, SK_DBGCAT_CTRL,
("SkAddrOverride: New logical MAC Address: %02X %02X %02X %02X %02X %02X\n",
pAC->Addr.Net[NetNumber].CurrentMacAddress.a[0],
pAC->Addr.Net[NetNumber].CurrentMacAddress.a[5]))
#endif /* DEBUG */
- /* Write address to first exact match entry of active port. */
+ /* Write address to first exact match entry of active port. */
(void) SkAddrMcUpdate(pAC, IoC, PortNumber);
}
return (SK_ADDR_SUCCESS);
-
+
} /* SkAddrOverride */
int NewPromMode) /* new promiscuous mode */
{
int ReturnCode;
-
+
if (PortNumber >= (SK_U32) pAC->GIni.GIMacsFound) {
return (SK_ADDR_ILLEGAL_PORT);
}
-
+
if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) {
ReturnCode = SkAddrXmacPromiscuousChange(pAC, IoC, PortNumber, NewPromMode);
}
/* Promiscuous mode! */
CurPromMode |= SK_PROM_MODE_LLC;
}
-
+
for (Inexact = 0xFF, i = 0; i < 8; i++) {
Inexact &= pAC->Addr.Port[PortNumber].InexactFilter.Bytes[i];
}
else {
/* Get InexactModeBit (bit XM_MD_ENA_HASH in mode register) */
XM_IN16(IoC, PortNumber, XM_MODE, &LoMode);
-
+
InexactModeBit = (LoMode & XM_MD_ENA_HASH) != 0;
/* Read 64-bit hash register from XMAC */
if ((NewPromMode & SK_PROM_MODE_ALL_MC) &&
!(CurPromMode & SK_PROM_MODE_ALL_MC)) { /* All MC. */
-
+
/* Set all bits in 64-bit hash register. */
XM_OUTHASH(IoC, PortNumber, XM_HSM, &OnesHash);
/* Clear Promiscuous Mode */
SkMacPromiscMode(pAC, IoC, PortNumber, SK_FALSE);
}
-
+
return (SK_ADDR_SUCCESS);
-
+
} /* SkAddrXmacPromiscuousChange */
if (NewPromMode == CurPromMode) {
return (SK_ADDR_SUCCESS);
}
-
+
if ((NewPromMode & SK_PROM_MODE_ALL_MC) &&
!(CurPromMode & SK_PROM_MODE_ALL_MC)) { /* All MC */
-
+
/* Set all bits in 64-bit hash register. */
GM_OUTHASH(IoC, PortNumber, GM_MC_ADDR_H1, &OnesHash);
-
+
/* Enable Hashing */
SkMacHashing(pAC, IoC, PortNumber, SK_TRUE);
}
-
+
if ((CurPromMode & SK_PROM_MODE_ALL_MC) &&
!(NewPromMode & SK_PROM_MODE_ALL_MC)) { /* Norm. MC */
if ((NewPromMode & SK_PROM_MODE_LLC) &&
!(CurPromMode & SK_PROM_MODE_LLC)) { /* Prom. LLC */
-
+
/* Set the MAC to Promiscuous Mode. */
SkMacPromiscMode(pAC, IoC, PortNumber, SK_TRUE);
}
else if ((CurPromMode & SK_PROM_MODE_LLC) &&
!(NewPromMode & SK_PROM_MODE_LLC)) { /* Norm. LLC */
-
+
/* Clear Promiscuous Mode. */
SkMacPromiscMode(pAC, IoC, PortNumber, SK_FALSE);
}
return (SK_ADDR_SUCCESS);
-
+
} /* SkAddrGmacPromiscuousChange */
pAC->Addr.Port[ToPortNumber].InexactFilter.Bytes[i];
pAC->Addr.Port[ToPortNumber].InexactFilter.Bytes[i] = Byte;
}
-
+
i = pAC->Addr.Port[FromPortNumber].PromMode;
pAC->Addr.Port[FromPortNumber].PromMode = pAC->Addr.Port[ToPortNumber].PromMode;
pAC->Addr.Port[ToPortNumber].PromMode = i;
-
+
if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) {
DWord = pAC->Addr.Port[FromPortNumber].FirstExactMatchRlmt;
pAC->Addr.Port[FromPortNumber].FirstExactMatchRlmt =
pAC->Addr.Port[ToPortNumber].FirstExactMatchRlmt;
pAC->Addr.Port[ToPortNumber].FirstExactMatchRlmt = DWord;
-
+
DWord = pAC->Addr.Port[FromPortNumber].NextExactMatchRlmt;
pAC->Addr.Port[FromPortNumber].NextExactMatchRlmt =
pAC->Addr.Port[ToPortNumber].NextExactMatchRlmt;
pAC->Addr.Port[ToPortNumber].NextExactMatchRlmt = DWord;
-
+
DWord = pAC->Addr.Port[FromPortNumber].FirstExactMatchDrv;
pAC->Addr.Port[FromPortNumber].FirstExactMatchDrv =
pAC->Addr.Port[ToPortNumber].FirstExactMatchDrv;
pAC->Addr.Port[ToPortNumber].FirstExactMatchDrv = DWord;
-
+
DWord = pAC->Addr.Port[FromPortNumber].NextExactMatchDrv;
pAC->Addr.Port[FromPortNumber].NextExactMatchDrv =
pAC->Addr.Port[ToPortNumber].NextExactMatchDrv;
pAC->Addr.Port[ToPortNumber].NextExactMatchDrv = DWord;
}
-
+
/* CAUTION: Solution works if only ports of one adapter are in use. */
for (i = 0; (SK_U32) i < pAC->Rlmt.Net[pAC->Rlmt.Port[ToPortNumber].
Net->NetNumber].NumPorts; i++) {
/* 20001207 RA: Was "ToPortNumber;". */
}
}
-
+
(void) SkAddrMcUpdate(pAC, IoC, FromPortNumber);
(void) SkAddrMcUpdate(pAC, IoC, ToPortNumber);
return (SK_ADDR_SUCCESS);
-
+
} /* SkAddrSwap */
#ifdef __cplusplus
* Fix in SkCsGetSendInfo():
* - function did not return ProtocolFlags in every case.
* - pseudo header csum calculated wrong for big endian.
- *
+ *
* Revision 1.9 2001/06/13 07:42:08 gklug
* fix: NetNumber was wrong in CLEAR_STAT event
* add: check for good NetNumber in Clear STAT
- *
+ *
* Revision 1.8 2001/02/06 11:15:36 rassmann
* Supporting two nets on dual-port adapters.
- *
+ *
* Revision 1.7 2000/06/29 13:17:05 rassmann
* Corrected reception of a packet with UDP checksum == 0 (which means there
* is no UDP checksum).
- *
+ *
* Revision 1.6 2000/02/21 12:35:10 cgoos
* Fixed license header comment.
- *
+ *
* Revision 1.5 2000/02/21 11:05:19 cgoos
* Merged changes back to common source.
* Fixed rx path for BIG ENDIAN architecture.
- *
+ *
* Revision 1.1 1999/07/26 15:28:12 mkarl
* added return SKCS_STATUS_IP_CSUM_ERROR_UDP and
* SKCS_STATUS_IP_CSUM_ERROR_TCP to pass the NidsTester
* changed from common source to windows specific source
* therefore restarting with v1.0
- *
+ *
* Revision 1.3 1999/05/10 08:39:33 mkarl
* prevent overflows in SKCS_HTON16
* fixed a bug in pseudo header checksum calculation
* added some comments
- *
+ *
* Revision 1.2 1998/10/22 11:53:28 swolf
* Now using SK_DBG_MSG.
- *
+ *
* Revision 1.1 1998/09/01 15:35:41 swolf
* initial revision
*
SKCS_OFS_IP_DESTINATION_ADDRESS + 2) +
(unsigned long) SKCS_HTON16(NextLevelProtocol) +
(unsigned long) SKCS_HTON16(IpDataLength);
-
+
/* Add-in any carries. */
SKCS_OC_ADD(PseudoHeaderChecksum, PseudoHeaderChecksum, 0);
* us to check upper-layer checksums, because we cannot do any further
* processing of the packet without a valid IP checksum.
*/
-
+
/* Get the next level protocol identifier. */
-
+
NextLevelProtocol = *(SK_U8 *)
SKCS_IDX(pIpHeader, SKCS_OFS_IP_NEXT_LEVEL_PROTOCOL);
*(SK_U16*)SKCS_IDX(pIpHeader, IpHeaderLength + 6) == 0x0000) {
NextLevelProtoStats->RxOkCts++;
-
+
return (SKCS_STATUS_IP_CSUM_OK_NO_UDP);
}
return (NextLevelProtocol == SKCS_PROTO_ID_TCP ?
SKCS_STATUS_TCP_CSUM_OK : SKCS_STATUS_UDP_CSUM_OK);
}
-
+
/* TCP/UDP checksum error. */
NextLevelProtoStats->RxErrCts++;
* Purpose: The main driver source module
*
******************************************************************************/
-
+
/******************************************************************************
*
* (C)Copyright 1998-2003 SysKonnect GmbH.
* SK-9843 (single link 1000Base-SX V2)
* SK-9821 (single link 1000Base-T V2)
*
- * Created 10-Feb-1999, based on Linux' acenic.c, 3c59x.c and
+ * Created 10-Feb-1999, based on Linux' acenic.c, 3c59x.c and
* SysKonnects GEnesis Solaris driver
* Author: Christoph Goos (cgoos@syskonnect.de)
* Mirko Lindner (mlindner@syskonnect.de)
* The technical manual for the adapters is available from SysKonnect's
* web pages: www.syskonnect.com
* Goto "Support" and search Knowledge Base for "manual".
- *
+ *
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* $Log: skge.c,v $
* Revision 1.46 2003/02/25 14:16:36 mlindner
* Fix: Copyright statement
- *
+ *
* Revision 1.45 2003/02/25 13:25:55 mlindner
* Add: Performance improvements
* Add: Support for various vendors
* Fix: Init function
- *
+ *
* Revision 1.44 2003/01/09 09:25:26 mlindner
* Fix: Remove useless init_module/cleanup_module forward declarations
- *
+ *
* Revision 1.43 2002/11/29 08:42:41 mlindner
* Fix: Boot message
- *
+ *
* Revision 1.42 2002/11/28 13:30:23 mlindner
* Add: New frame check
- *
+ *
* Revision 1.41 2002/11/27 13:55:18 mlindner
* Fix: Drop wrong csum packets
* Fix: Initialize proc_entry after hw check
- *
+ *
* Revision 1.40 2002/10/31 07:50:37 tschilli
* Function SkGeInitAssignRamToQueues() from common module inserted.
* Autonegotiation is set to ON for all adapters.
* Role parameter will show up for 1000 Mbps links only.
* GetConfiguration() inserted after init level 1 in SkGeChangeMtu().
* All return values of SkGeInit() and SkGeInitPort() are checked.
- *
+ *
* Revision 1.39 2002/10/02 12:56:05 mlindner
* Add: Support for Yukon
* Add: Support for ZEROCOPY, scatter-gather and hw checksum
* Add: Frame length check
* Fix: Transmit complete interrupt
* Fix: Interrupt moderation
- *
+ *
* Revision 1.29.2.13 2002/01/14 12:44:52 mlindner
* Fix: Rlmt modes
- *
+ *
* Revision 1.29.2.12 2001/12/07 12:06:18 mlindner
* Fix: malloc -> slab changes
- *
+ *
* Revision 1.29.2.11 2001/12/06 15:19:20 mlindner
* Add: DMA attributes
* Fix: Module initialisation
* Fix: pci_map_single and pci_unmap_single replaced
- *
+ *
* Revision 1.29.2.10 2001/12/06 09:56:50 mlindner
* Corrected some printk's
- *
+ *
* Revision 1.29.2.9 2001/09/05 12:15:34 mlindner
* Add: LBFO Changes
* Fix: Counter Errors (Jumbo == to long errors)
* Fix: Changed pAC->PciDev declaration
* Fix: too short counters
- *
+ *
* Revision 1.29.2.8 2001/06/25 12:10:44 mlindner
* fix: ReceiveIrq() changed.
- *
+ *
* Revision 1.29.2.7 2001/06/25 08:07:05 mlindner
* fix: RLMT locking in ReceiveIrq() changed.
- *
+ *
* Revision 1.29.2.6 2001/05/21 07:59:29 mlindner
* fix: MTU init problems
- *
+ *
* Revision 1.29.2.5 2001/05/08 11:25:08 mlindner
* fix: removed VLAN error message
- *
+ *
* Revision 1.29.2.4 2001/05/04 13:31:43 gklug
* fix: do not handle eth_copy on bad fragments received.
- *
+ *
* Revision 1.29.2.3 2001/04/23 08:06:43 mlindner
* Fix: error handling
- *
+ *
* Revision 1.29.2.2 2001/03/15 12:04:54 mlindner
* Fixed memory problem
- *
+ *
* Revision 1.29.2.1 2001/03/12 16:41:44 mlindner
* add: procfs function
* add: dual-net function
* add: RLMT networks
* add: extended PNMI features
- *
+ *
* Kernel 2.4.x specific:
* Revision 1.xx 2000/09/12 13:31:56 cgoos
* Fixed missign "dev=NULL in skge_probe.
* Added counting for jumbo frames (corrects error statistic).
* Removed VLAN tag check (enables VLAN support).
- *
+ *
* Kernel 2.2.x specific:
* Revision 1.29 2000/02/21 13:31:56 cgoos
* Fixed "unused" warning for UltraSPARC change.
- *
+ *
* Partially kernel 2.2.x specific:
* Revision 1.28 2000/02/21 10:32:36 cgoos
* Added fixes for UltraSPARC.
* Changed XmitFrame return value.
* Fixed rx checksum calculation for BIG ENDIAN systems.
* Fixed rx jumbo frames counted as ierrors.
- *
- *
+ *
+ *
* Revision 1.27 1999/11/25 09:06:28 cgoos
* Changed base_addr to unsigned long.
- *
+ *
* Revision 1.26 1999/11/22 13:29:16 cgoos
* Changed license header to GPL.
* Changes for inclusion in linux kernel (2.2.13).
* Removed 2.0.x defines.
* Changed SkGeProbe to skge_probe.
* Added checks in SkGeIoctl.
- *
+ *
* Revision 1.25 1999/10/07 14:47:52 cgoos
* Changed 984x to 98xx.
- *
+ *
* Revision 1.24 1999/09/30 07:21:01 cgoos
* Removed SK_RLMT_SLOW_LOOKAHEAD option.
* Giving spanning tree packets also to OS now.
- *
+ *
* Revision 1.23 1999/09/29 07:36:50 cgoos
* Changed assignment for IsBc/IsMc.
- *
+ *
* Revision 1.22 1999/09/28 12:57:09 cgoos
* Added CheckQueue also to Single-Port-ISR.
- *
+ *
* Revision 1.21 1999/09/28 12:42:41 cgoos
* Changed parameter strings for RlmtMode.
- *
+ *
* Revision 1.20 1999/09/28 12:37:57 cgoos
* Added CheckQueue for fast delivery of RLMT frames.
- *
+ *
* Revision 1.19 1999/09/16 07:57:25 cgoos
* Copperfield changes.
- *
+ *
* Revision 1.18 1999/09/03 13:06:30 cgoos
* Fixed RlmtMode=CheckSeg bug: wrong DEV_KFREE_SKB in RLMT_SEND caused
* double allocated skb's.
* Queue size for async. standby Tx queue was zero.
* FillRxLimit of 0 could cause problems with ReQueue, changed to 1.
* Removed debug output of checksum statistic.
- *
+ *
* Revision 1.17 1999/08/11 13:55:27 cgoos
* Transmit descriptor polling was not reenabled after SkGePortInit.
- *
+ *
* Revision 1.16 1999/07/27 15:17:29 cgoos
* Added some "\n" in output strings (removed while debuging...).
- *
+ *
* Revision 1.15 1999/07/23 12:09:30 cgoos
* Performance optimization, rx checksumming, large frame support.
- *
+ *
* Revision 1.14 1999/07/14 11:26:27 cgoos
* Removed Link LED settings (now in RLMT).
* Added status output at NET UP.
* Fixed SMP problems with Tx and SWITCH running in parallel.
* Fixed return code problem at RLMT_SEND event.
- *
+ *
* Revision 1.13 1999/04/07 10:11:42 cgoos
* Fixed Single Port problems.
* Fixed Multi-Adapter problems.
* Always display startup string.
- *
+ *
* Revision 1.12 1999/03/29 12:26:37 cgoos
* Reversed locking to fine granularity.
* Fixed skb double alloc problem (caused by incorrect xmit return code).
* Enhanced function descriptions.
- *
+ *
* Revision 1.11 1999/03/15 13:10:51 cgoos
* Changed device identifier in output string to ethX.
- *
+ *
* Revision 1.10 1999/03/15 12:12:34 cgoos
* Changed copyright notice.
- *
+ *
* Revision 1.9 1999/03/15 12:10:17 cgoos
* Changed locking to one driver lock.
* Added check of SK_AC-size (for consistency with library).
- *
+ *
* Revision 1.8 1999/03/08 11:44:02 cgoos
* Fixed missing dev->tbusy in SkGeXmit.
* Changed large frame (jumbo) buffer number.
* Added copying of short frames.
- *
+ *
* Revision 1.7 1999/03/04 13:26:57 cgoos
* Fixed spinlock calls for SMP.
- *
+ *
* Revision 1.6 1999/03/02 09:53:51 cgoos
* Added descriptor revertion for big endian machines.
- *
+ *
* Revision 1.5 1999/03/01 08:50:59 cgoos
* Fixed SkGeChangeMtu.
* Fixed pci config space accesses.
- *
+ *
* Revision 1.4 1999/02/18 15:48:44 cgoos
* Corrected some printk's.
- *
+ *
* Revision 1.3 1999/02/18 12:45:55 cgoos
* Changed SK_MAX_CARD_PARAM to default 16
- *
+ *
* Revision 1.2 1999/02/18 10:55:32 cgoos
* Removed SkGeDrvTimeStamp function.
* Printing "ethX:" before adapter type at adapter init.
- *
*
- * 10-Feb-1999 cg Created, based on Linux' acenic.c, 3c59x.c and
+ *
+ * 10-Feb-1999 cg Created, based on Linux' acenic.c, 3c59x.c and
* SysKonnects GEnesis Solaris driver
*
******************************************************************************/
*
* Possible compiler options (#define xxx / -Dxxx):
*
- * debugging can be enable by changing SK_DEBUG_CHKMOD and
+ * debugging can be enable by changing SK_DEBUG_CHKMOD and
* SK_DEBUG_CHKCAT in makefile (described there).
*
******************************************************************************/
-
+
/******************************************************************************
*
* Description:
*
* This is the main module of the Linux GE driver.
- *
+ *
* All source files except skge.c, skdrv1st.h, skdrv2nd.h and sktypes.h
* are part of SysKonnect's COMMON MODULES for the SK-98xx adapters.
* Those are used for drivers on multiple OS', so some thing may seem
/*
- * use those defines for a compile-in version of the driver instead
+ * use those defines for a compile-in version of the driver instead
* of command line parameters
*/
-// #define LINK_SPEED_A {"Auto", }
-// #define LINK_SPEED_B {"Auto", }
-// #define AUTO_NEG_A {"Sense", }
-// #define AUTO_NEG_B {"Sense", }
-// #define DUP_CAP_A {"Both", }
-// #define DUP_CAP_B {"Both", }
-// #define FLOW_CTRL_A {"SymOrRem", }
-// #define FLOW_CTRL_B {"SymOrRem", }
-// #define ROLE_A {"Auto", }
-// #define ROLE_B {"Auto", }
-// #define PREF_PORT {"A", }
-// #define RLMT_MODE {"CheckLinkState", }
+/* #define LINK_SPEED_A {"Auto", } */
+/* #define LINK_SPEED_B {"Auto", } */
+/* #define AUTO_NEG_A {"Sense", } */
+/* #define AUTO_NEG_B {"Sense", } */
+/* #define DUP_CAP_A {"Both", } */
+/* #define DUP_CAP_B {"Both", } */
+/* #define FLOW_CTRL_A {"SymOrRem", } */
+/* #define FLOW_CTRL_B {"SymOrRem", } */
+/* #define ROLE_A {"Auto", } */
+/* #define ROLE_B {"Auto", } */
+/* #define PREF_PORT {"A", } */
+/* #define RLMT_MODE {"CheckLinkState", } */
#define DEV_KFREE_SKB(skb) dev_kfree_skb(skb)
#define DEV_KFREE_SKB_IRQ(skb) dev_kfree_skb_irq(skb)
continue;
#endif
-/* if ((pdev->vendor != PCI_VENDOR_ID_SYSKONNECT) &&
- ((pdev->device != PCI_DEVICE_ID_SYSKONNECT_GE) ||
+/* if ((pdev->vendor != PCI_VENDOR_ID_SYSKONNECT) &&
+ ((pdev->device != PCI_DEVICE_ID_SYSKONNECT_GE) ||
(pdev->device != PCI_DEVICE_ID_SYSKONNECT_YU))){
continue;
}
base_address = pci_resource_start (pdev, 0);
#else
pci_write_config_dword(devno,
- PCI_COMMAND,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+ PCI_COMMAND,
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
pci_read_config_dword (devno, PCI_BASE_ADDRESS_0,
- &base_address);
+ &base_address);
#endif
#ifdef SK_BIG_ENDIAN
}
-
/* Create proc file */
pProcFile = create_proc_entry(dev->name,
S_IFREG | S_IXUSR | S_IWGRP | S_IROTH,
pSkRootDir);
-
+
pProcFile->read_proc = proc_read;
pProcFile->write_proc = NULL;
pProcFile->nlink = 1;
S_IFREG | S_IXUSR | S_IWGRP | S_IROTH,
pSkRootDir);
-
+
pProcFile->read_proc = proc_read;
pProcFile->write_proc = NULL;
pProcFile->nlink = 1;
memcpy((caddr_t) &dev->enetaddr,
(caddr_t) &pAC->Addr.Net[1].CurrentMacAddress, 6);
#endif
-
+
printk("%s: %s\n", dev->name, pAC->DeviceStr);
printk(" PrefPort:B RlmtMode:Dual Check Link State\n");
* frees the desriptor ring.
*
* Returns: N/A
- *
+ *
*/
static void FreeResources(struct SK_NET_DEVICE *dev)
{
BoardFreeMem(pAC);
}
}
-
+
} /* FreeResources */
#if 0
{
int cards;
SkGeRootDev = NULL;
-
+
/* just to avoid warnings ... */
debug = 0;
options[0] = 0;
SkEventDispatcher(pAC, pAC->IoBase);
/* disable interrupts */
SK_OUT32(pAC->IoBase, B0_IMSK, 0);
- SkGeDeInit(pAC, pAC->IoBase);
+ SkGeDeInit(pAC, pAC->IoBase);
spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
pAC->BoardLevel = 0;
/* We do NOT check here, if IRQ was pending, of course*/
if(pAC->BoardLevel == 1) {
/* board is still alive */
- SkGeDeInit(pAC, pAC->IoBase);
+ SkGeDeInit(pAC, pAC->IoBase);
pAC->BoardLevel = 0;
}
FreeResources(SkGeRootDev);
SkGeRootDev->get_stats = NULL;
- /*
+ /*
* otherwise unregister_netdev calls get_stats with
* invalid IO ... :-(
*/
spin_lock_init(&pAC->SlowPathLock);
/* level 0 init common modules here */
-
+
spin_lock_irqsave(&pAC->SlowPathLock, Flags);
/* Does a RESET on board ...*/
if (SkGeInit(pAC, pAC->IoBase, 0) != 0) {
SkAddrInit( pAC, pAC->IoBase, 0);
SkRlmtInit( pAC, pAC->IoBase, 0);
SkTimerInit(pAC, pAC->IoBase, 0);
-
+
pAC->BoardLevel = 0;
pAC->RxBufSize = ETH_BUF_SIZE;
/* Alloc memory for this board (Mem for RxD/TxD) : */
if(!BoardAllocMem(pAC)) {
printk("No memory for descriptor rings.\n");
- return(-EAGAIN);
+ return(-EAGAIN);
}
SkCsSetReceiveFlags(pAC,
if (pAC->RlmtNets == 2) {
DualNet = SK_TRUE;
}
-
+
if (SkGeInitAssignRamToQueues(
pAC,
pAC->ActivePort,
printk(" PrefPort:%c RlmtMode:%s\n",
'A' + pAC->Rlmt.Net[0].Port[pAC->Rlmt.Net[0].PrefPort]->PortNumber,
(pAC->RlmtMode==0) ? "Check Link State" :
- ((pAC->RlmtMode==1) ? "Check Link State" :
- ((pAC->RlmtMode==3) ? "Check Local Port" :
- ((pAC->RlmtMode==7) ? "Check Segmentation" :
+ ((pAC->RlmtMode==1) ? "Check Link State" :
+ ((pAC->RlmtMode==3) ? "Check Local Port" :
+ ((pAC->RlmtMode==7) ? "Check Segmentation" :
((pAC->RlmtMode==17) ? "Dual Check Link State" :"Error")))));
#endif
int i; /* loop counter */
unsigned long BusAddr;
-
+
/* rings plus one for alignment (do not cross 4 GB boundary) */
/* RX_RING_SIZE is assumed bigger than TX_RING_SIZE */
#if (BITS_PER_LONG == 32)
pAC->TxPort[i][0].VTxDescrRing = BusAddr;
pDescrMem += TX_RING_SIZE;
BusAddr += TX_RING_SIZE;
-
+
SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
("RX%d: pDescrMem: %lX, PhysDescrMem: %lX\n",
i, (unsigned long) pDescrMem,
pDescrMem += RX_RING_SIZE;
BusAddr += RX_RING_SIZE;
} /* for */
-
+
return (SK_TRUE);
} /* BoardAllocMem */
pAC->RxDescrPerRing = RX_RING_SIZE / RxDescrSize;
TxDescrSize = (((sizeof(TXD) - 1) / DESCR_ALIGN) + 1) * DESCR_ALIGN;
pAC->TxDescrPerRing = TX_RING_SIZE / RxDescrSize;
-
+
for (i=0; i<pAC->GIni.GIMacsFound; i++) {
SetupRing(
pAC,
DESCR_ALIGN;
DescrNum = RX_RING_SIZE / DescrSize;
}
-
+
SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_TX_PROGRESS,
("Descriptor size: %d Descriptor Number: %d\n",
DescrSize,DescrNum));
-
+
pDescr = (RXD*) pMemArea;
pPrevDescr = NULL;
pNextDescr = (RXD*) (((char*)pDescr) + DescrSize);
struct SK_NET_DEVICE *dev = (struct SK_NET_DEVICE *)dev_id;
DEV_NET *pNet;
SK_AC *pAC;
-SK_U32 IntSrc; /* interrupts source register contents */
+SK_U32 IntSrc; /* interrupts source register contents */
pNet = (DEV_NET*) dev->priv;
pAC = pNet->pAC;
-
+
/*
* Check and process if its our interrupt
*/
spin_unlock(&pAC->SlowPathLock);
}
/*
- * do it all again is case we cleared an interrupt that
+ * do it all again is case we cleared an interrupt that
* came in after handling the ring (OUTs may be delayed
* in hardware buffers, but are through after IN)
*/
struct SK_NET_DEVICE *dev = (struct SK_NET_DEVICE *)dev_id;
DEV_NET *pNet;
SK_AC *pAC;
-SK_U32 IntSrc; /* interrupts source register contents */
+SK_U32 IntSrc; /* interrupts source register contents */
pNet = (DEV_NET*) dev->priv;
pAC = pNet->pAC;
-
+
/*
* Check and process if its our interrupt
*/
if (IntSrc == 0) {
return;
}
-
+
while (((IntSrc & IRQ_MASK) & ~SPECIAL_IRQS) != 0) {
#if 0 /* software irq currently not used */
if (IntSrc & IRQ_SW) {
#endif
SK_IN32(pAC->IoBase, B0_ISRC, &IntSrc);
} /* while (IntSrc & IRQ_MASK != 0) */
-
+
if ((IntSrc & SPECIAL_IRQS) || pAC->CheckQueue) {
SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_INT_SRC,
("SPECIAL IRQ SP-Cards => %x\n", IntSrc));
spin_unlock(&pAC->SlowPathLock);
}
/*
- * do it all again is case we cleared an interrupt that
+ * do it all again is case we cleared an interrupt that
* came in after handling the ring (OUTs may be delayed
* in hardware buffers, but are through after IN)
*/
pNet = (DEV_NET*) dev->priv;
pAC = pNet->pAC;
-
+
SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
("SkGeOpen: pAC=0x%lX:\n", (unsigned long)pAC));
SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
("SkGeClose: pAC=0x%lX ", (unsigned long)pAC));
- /*
+ /*
* Clear multicast table, promiscuous mode ....
*/
SkAddrMcClear(pAC, pAC->IoBase, PortIdx, 0);
SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_STOP, EvPara);
SkEventDispatcher(pAC, pAC->IoBase);
spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
-
+
/* Stop port */
spin_lock_irqsave(&pAC->TxPort[pNet->PortNr]
[TX_PRIO_LOW].TxDesRingLock, Flags);
- SkGeStopPort(pAC, pAC->IoBase, pNet->PortNr,
+ SkGeStopPort(pAC, pAC->IoBase, pNet->PortNr,
SK_STOP_ALL, SK_HARD_RST);
spin_unlock_irqrestore(&pAC->TxPort[pNet->PortNr]
[TX_PRIO_LOW].TxDesRingLock, Flags);
pAC->MaxPorts--;
pNet->Up = 0;
MOD_DEC_USE_COUNT;
-
+
return (0);
} /* SkGeClose */
pAC = pNet->pAC;
#if 0
- if ((!skb_shinfo(skb)->nr_frags) ||
+ if ((!skb_shinfo(skb)->nr_frags) ||
#else
if (1 ||
#endif
pTxPort->pTxdRingHead = pTxd->pNextTxd;
pTxPort->TxdRingFree--;
/* the needed descriptor is reserved now */
-
- /*
+
+ /*
* everything allocated ok, so add buffer to descriptor
*/
#else
TX_CTRL_EOF | pMessage->len;
#endif
-
+
if ((pTxPort->pTxdRingPrev->TBControl & TX_CTRL_OWN_BMU) == 0) {
/* previous descriptor already done, so give tx start cmd */
/* StartTx(pAC, pTxPort->HwAddr); */
SK_OUT8(pTxPort->HwAddr, TX_Q_CTRL, TX_Q_CTRL_START);
}
pTxPort->pTxdRingPrev = pTxd;
-
-
+
+
BytesSend = pMessage->len;
spin_unlock_irqrestore(&pTxPort->TxDesRingLock, Flags);
/* after releasing the lock, the skb may be immidiately freed */
pTxd->TcpSumOfs = 0; /* PH-Checksum already claculated */
pTxd->TcpSumSt = 14+hlength+16;
pTxd->TcpSumWr = 14+hlength;
-
+
} else {
- pTxd->TBControl = TX_CTRL_CHECK_DEFAULT |
+ pTxd->TBControl = TX_CTRL_CHECK_DEFAULT |
TX_CTRL_SOFTWARE |
TX_CTRL_STF |
skb_headlen(pMessage);
/* Map SG fragments */
for (i = 0; i < skb_shinfo(pMessage)->nr_frags; i++) {
sk_frag = &skb_shinfo(pMessage)->frags[i];
-
+
/* we already have the proper value in entry */
PhysAddr = (SK_U64) pci_map_page(pAC->PciDev,
sk_frag->page,
pTxd->VDataLow = (SK_U32) (PhysAddr & 0xffffffff);
pTxd->VDataHigh = (SK_U32) (PhysAddr >> 32);
pTxd->pMBuf = pMessage;
-
+
/* HW checksum */
if (pMessage->ip_summed == CHECKSUM_HW) {
- pTxd->TBControl = TX_CTRL_OWN_BMU |
- TX_CTRL_SOFTWARE |
+ pTxd->TBControl = TX_CTRL_OWN_BMU |
+ TX_CTRL_SOFTWARE |
TX_CTRL_ST_FWD;
/* We have to use the opcode for tcp here because the opcode for
sk_frag->size;
#endif
pTxdFst->TBControl |= TX_CTRL_OWN_BMU |
- TX_CTRL_SOFTWARE;
+ TX_CTRL_SOFTWARE;
} else {
pTxd->TBControl |= sk_frag->size;
void dump_frag( SK_U8 *data, int length)
{
- int i;
+ int i;
- printk("Length: %d\n", length);
- for( i=0; i < length; i++ ) {
- printk(" %02x", (SK_U8)*(data + i) );
- if( !((i+1) % 20) )
- printk("\n");
- }
- printk("\n\n");
+ printk("Length: %d\n", length);
+ for( i=0; i < length; i++ ) {
+ printk(" %02x", (SK_U8)*(data + i) );
+ if( !((i+1) % 20) )
+ printk("\n");
+ }
+ printk("\n\n");
}
pNewTail = pTxPort->pTxdRingTail;
pTxd = pNewTail;
- /*
+ /*
* loop forever; exits if TX_CTRL_SOFTWARE bit not set in start frame
* or TX_CTRL_OWN_BMU bit set in any frame
*/
while (1) {
Control = pTxd->TBControl;
if ((Control & TX_CTRL_SOFTWARE) == 0) {
- /*
+ /*
* software controllable bit is set in first
* fragment when given to BMU. Not set means that
- * this fragment was never sent or is already
+ * this fragment was never sent or is already
* freed ( -> ring completely free now).
*/
pTxPort->pTxdRingTail = pTxd;
}
return;
}
-
+
/* release the DMA mapping */
PhysAddr = ((SK_U64) pTxd->VDataHigh) << (SK_U64) 32;
PhysAddr |= (SK_U64) pTxd->VDataLow;
* Description of rx ring structure:
* head - points to the descriptor which will be used next by the BMU
* tail - points to the next descriptor to give to the BMU
- *
+ *
* Returns: N/A
*/
static void FillRxRing(
struct sk_buff *pNewMsg; /* pointer to a new message for copying frame */
int FrameLength; /* total length of received frame */
SK_MBUF *pRlmtMbuf; /* ptr to a buffer for giving a frame to rlmt */
-SK_EVPARA EvPara; /* an event parameter union */
+SK_EVPARA EvPara; /* an event parameter union */
unsigned long Flags; /* for spin lock */
int PortIndex = pRxPort->PortIndex;
unsigned int Offset;
#endif
SK_U64 PhysAddr;
-rx_start:
+rx_start:
/* do forever; exit if RX_CTRL_OWN_BMU found */
for ( pRxd = pRxPort->pRxdRingHead ;
pRxPort->RxdRingFree < pAC->RxDescrPerRing ;
pRxPort->RxdRingFree ++) {
/*
- * For a better understanding of this loop
- * Go through every descriptor beginning at the head
+ * For a better understanding of this loop
+ * Go through every descriptor beginning at the head
* Please note: the ring might be completely received so the OWN bit
* set is not a good crirteria to leave that loop.
* Therefore the RingFree counter is used.
*/
Control = pRxd->RBControl;
-
+
/* check if this descriptor is ready */
if ((Control & RX_CTRL_OWN_BMU) != 0) {
/* this descriptor is not yet ready */
if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) {
IsBc = (FrameStat & XMR_FS_BC) != 0;
IsMc = (FrameStat & XMR_FS_MC) != 0;
- IsBadFrame = (FrameStat &
+ IsBadFrame = (FrameStat &
(XMR_FS_ANY_ERR | XMR_FS_2L_VLAN)) != 0;
} else {
IsBc = (FrameStat & GMR_FS_BC) != 0;
(pAC->GIni.GIChipId == CHIP_ID_GENESIS)) ||
(pAC->GIni.GIChipId == CHIP_ID_YUKON)) {
Result = SkCsGetReceiveInfo(pAC,
- &pMsg->data[14],
+ &pMsg->data[14],
Csum1, Csum2, pRxPort->PortIndex);
if (Result ==
SKCS_STATUS_IP_FRAGMENT ||
#endif
} /* IP frame */
} /* frame > SK_COPY_TRESHOLD */
-
+
SK_DBG_MSG(NULL, SK_DBGMOD_DRV, 1,("V"));
ForRlmt = SK_RLMT_RX_PROTOCOL;
#if 0
#if 0
IsMc = (FrameStat & XMR_FS_MC)==XMR_FS_MC;
#endif
- SK_RLMT_LOOKAHEAD(pAC, PortIndex,
+ SK_RLMT_LOOKAHEAD(pAC, PortIndex,
&pMsg->data[Offset],
IsBc, IsMc, &ForRlmt);
}
}
else {
/* drop frame */
- SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
SK_DBGCAT_DRV_RX_PROGRESS,
("D"));
DEV_KFREE_SKB(pMsg);
}
-
+
} /* if not for rlmt */
else {
/* packet for rlmt */
- SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
SK_DBGCAT_DRV_RX_PROGRESS, ("R"));
pRlmtMbuf = SkDrvAllocRlmtMbuf(pAC,
pAC->IoBase, FrameLength);
pAC->CheckQueue = SK_TRUE;
}
- SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
+ SK_DBG_MSG(NULL, SK_DBGMOD_DRV,
SK_DBGCAT_DRV_RX_PROGRESS,
("Q"));
}
#if 0
- if ((pAC->dev[pRxPort->PortIndex]->flags &
+ if ((pAC->dev[pRxPort->PortIndex]->flags &
(IFF_PROMISC | IFF_ALLMULTI)) != 0 ||
- (ForRlmt & SK_RLMT_RX_PROTOCOL) ==
- SK_RLMT_RX_PROTOCOL) {
+ (ForRlmt & SK_RLMT_RX_PROTOCOL) ==
+ SK_RLMT_RX_PROTOCOL) {
pMsg->dev = pAC->dev[pRxPort->PortIndex];
pMsg->protocol = eth_type_trans(pMsg,
pAC->dev[pRxPort->PortIndex]);
if (pAC->RlmtNets == 1) {
StandbyRam = SK_RLMT_STANDBY_QRXSIZE + SK_RLMT_STANDBY_QXASIZE +
SK_RLMT_STANDBY_QXSSIZE;
- RemainingRam = pAC->GIni.GIRamSize -
+ RemainingRam = pAC->GIni.GIRamSize -
(pAC->GIni.GIMacsFound-1) * StandbyRam;
for (i=0; i<pAC->GIni.GIMacsFound; i++) {
pAC->GIni.GP[i].PRxQSize = SK_RLMT_STANDBY_QRXSIZE;
pAC->GIni.GP[i].PXSQSize = 0;
pAC->GIni.GP[i].PXAQSize = (RemainingRam - RxRam) & ~7;
}
-
+
pAC->RxQueueSize = RxRam;
pAC->TxSQueueSize = 0;
pAC->TxAQueueSize = (RemainingRam - RxRam) & ~7;
struct sockaddr *addr = p;
unsigned long Flags;
-
+
SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
("SkGeSetMacAddr starts now...\n"));
if(netif_running(dev))
return -EBUSY;
memcpy(dev->dev_addr, addr->sa_data,dev->addr_len);
-
+
spin_lock_irqsave(&pAC->SlowPathLock, Flags);
if (pAC->RlmtNets == 2)
SkAddrOverride(pAC, pAC->IoBase, pAC->ActivePort,
(SK_MAC_ADDR*)dev->dev_addr, SK_ADDR_VIRTUAL_ADDRESS);
-
-
+
spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
return 0;
} /* SkGeSetMacAddr */
SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
("Number of MC entries: %d ", dev->mc_count));
-
+
pMcList = dev->mc_list;
for (i=0; i<dev->mc_count; i++, pMcList = pMcList->next) {
SkAddrMcAdd(pAC, pAC->IoBase, PortIdx,
SkAddrMcUpdate(pAC, pAC->IoBase, PortIdx);
}
spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
-
+
return;
} /* SkGeSetRxMode */
spin_lock_irqsave(&pAC->SlowPathLock, Flags);
/* Found more than one port */
- if ((pAC->GIni.GIMacsFound == 2 ) &&
+ if ((pAC->GIni.GIMacsFound == 2 ) &&
(pAC->RlmtNets == 2)) {
/* Stop both ports */
EvPara.Para32[0] = 0;
}
- /*
+ /*
* adjust number of rx buffers allocated
*/
if (NewMtu > 1500) {
/* use less rx buffers */
for (i=0; i<pAC->GIni.GIMacsFound; i++) {
/* Found more than one port */
- if ((pAC->GIni.GIMacsFound == 2 ) &&
+ if ((pAC->GIni.GIMacsFound == 2 ) &&
(pAC->RlmtNets == 2)) {
- pAC->RxPort[i].RxFillLimit =
+ pAC->RxPort[i].RxFillLimit =
pAC->RxDescrPerRing - 100;
} else {
if (i == pAC->ActivePort)
/* use normal amount of rx buffers */
for (i=0; i<pAC->GIni.GIMacsFound; i++) {
/* Found more than one port */
- if ((pAC->GIni.GIMacsFound == 2 ) &&
+ if ((pAC->GIni.GIMacsFound == 2 ) &&
(pAC->RlmtNets == 2)) {
pAC->RxPort[i].RxFillLimit = 1;
} else {
}
}
}
-
- SkGeDeInit(pAC, pAC->IoBase);
- /*
+ SkGeDeInit(pAC, pAC->IoBase);
+
+ /*
* enable/disable hardware support for long frames
*/
if (NewMtu > 1500) {
-// pAC->JumboActivated = SK_TRUE; /* is never set back !!! */
+/* pAC->JumboActivated = SK_TRUE; /#* is never set back !!! */
pAC->GIni.GIPortUsage = SK_JUMBO_LINK;
}
else {
- if ((pAC->GIni.GIMacsFound == 2 ) &&
+ if ((pAC->GIni.GIMacsFound == 2 ) &&
(pAC->RlmtNets == 2)) {
pAC->GIni.GIPortUsage = SK_MUL_LINK;
} else {
SkAddrInit( pAC, pAC->IoBase, 1);
SkRlmtInit( pAC, pAC->IoBase, 1);
SkTimerInit(pAC, pAC->IoBase, 1);
-
+
/*
* tschilling:
* Speed and others are set back to default in level 1 init!
*/
GetConfiguration(pAC);
-
+
SkGeInit( pAC, pAC->IoBase, 2);
SkI2cInit( pAC, pAC->IoBase, 2);
SkEventInit(pAC, pAC->IoBase, 2);
SkRlmtInit( pAC, pAC->IoBase, 2);
SkTimerInit(pAC, pAC->IoBase, 2);
- /*
+ /*
* clear and reinit the rx rings here
*/
for (i=0; i<pAC->GIni.GIMacsFound; i++) {
SkEventDispatcher(pAC, pAC->IoBase);
/* Found more than one port */
- if ((pAC->GIni.GIMacsFound == 2 ) &&
+ if ((pAC->GIni.GIMacsFound == 2 ) &&
(pAC->RlmtNets == 2)) {
/* Start both ports */
EvPara.Para32[0] = pAC->RlmtNets;
EvPara.Para32[1] = -1;
SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_SET_NETS,
EvPara);
-
-
+
+
EvPara.Para32[1] = -1;
EvPara.Para32[0] = pNet->PortNr;
SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_START, EvPara);
-
+
if (pOtherNet->Up) {
EvPara.Para32[0] = pOtherNet->PortNr;
- SkEventQueue(pAC, SKGE_RLMT,
+ SkEventQueue(pAC, SKGE_RLMT,
SK_RLMT_START, EvPara);
}
} else {
SkEventDispatcher(pAC, pAC->IoBase);
spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
-
+
return 0;
} /* SkGeChangeMtu */
SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_ENTRY,
("SkGeStats starts now...\n"));
pPnmiStruct = &pAC->PnmiStruct;
- memset(pPnmiStruct, 0, sizeof(SK_PNMI_STRUCT_DATA));
- spin_lock_irqsave(&pAC->SlowPathLock, Flags);
- Size = SK_PNMI_STRUCT_SIZE;
+ memset(pPnmiStruct, 0, sizeof(SK_PNMI_STRUCT_DATA));
+ spin_lock_irqsave(&pAC->SlowPathLock, Flags);
+ Size = SK_PNMI_STRUCT_SIZE;
SkPnmiGetStruct(pAC, pAC->IoBase, pPnmiStruct, &Size, pNet->NetNr);
- spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
- pPnmiStat = &pPnmiStruct->Stat[0];
- pPnmiConf = &pPnmiStruct->Conf[0];
+ spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
+ pPnmiStat = &pPnmiStruct->Stat[0];
+ pPnmiConf = &pPnmiStruct->Conf[0];
pAC->stats.rx_packets = (SK_U32) pPnmiStruct->RxDeliveredCts & 0xFFFFFFFF;
pAC->stats.tx_packets = (SK_U32) pPnmiStat->StatTxOkCts & 0xFFFFFFFF;
pAC->stats.rx_bytes = (SK_U32) pPnmiStruct->RxOctetsDeliveredCts;
pAC->stats.tx_bytes = (SK_U32) pPnmiStat->StatTxOctetsOkCts;
-
- if (pNet->Mtu <= 1500) {
- pAC->stats.rx_errors = (SK_U32) pPnmiStruct->InErrorsCts & 0xFFFFFFFF;
- } else {
- pAC->stats.rx_errors = (SK_U32) ((pPnmiStruct->InErrorsCts -
- pPnmiStat->StatRxTooLongCts) & 0xFFFFFFFF);
+
+ if (pNet->Mtu <= 1500) {
+ pAC->stats.rx_errors = (SK_U32) pPnmiStruct->InErrorsCts & 0xFFFFFFFF;
+ } else {
+ pAC->stats.rx_errors = (SK_U32) ((pPnmiStruct->InErrorsCts -
+ pPnmiStat->StatRxTooLongCts) & 0xFFFFFFFF);
}
pNet = (DEV_NET*) dev->priv;
pAC = pNet->pAC;
-
+
if(copy_from_user(&Ioctl, rq->ifr_data, sizeof(SK_GE_IOCTL))) {
return -EFAULT;
}
case SK_IOCTL_SETMIB:
case SK_IOCTL_PRESETMIB:
if (!capable(CAP_NET_ADMIN)) return -EPERM;
- case SK_IOCTL_GETMIB:
- if(copy_from_user(&pAC->PnmiStruct, Ioctl.pData,
+ case SK_IOCTL_GETMIB:
+ if(copy_from_user(&pAC->PnmiStruct, Ioctl.pData,
Ioctl.Len<sizeof(pAC->PnmiStruct)?
Ioctl.Len : sizeof(pAC->PnmiStruct))) {
return -EFAULT;
* -----------------------------------------------------------------
* Sense | AutoSense | AutoSense | AutoSense |
*/
-int Capabilities[3][3] =
- { { -1, SK_LMODE_FULL, SK_LMODE_HALF},
+int Capabilities[3][3] =
+ { { -1, SK_LMODE_FULL, SK_LMODE_HALF},
{SK_LMODE_AUTOBOTH, SK_LMODE_AUTOFULL, SK_LMODE_AUTOHALF},
{SK_LMODE_AUTOSENSE, SK_LMODE_AUTOSENSE, SK_LMODE_AUTOSENSE} };
#define DC_BOTH 0
/* Only copper type adapter and GE V2 cards */
if (((pAC->GIni.GIChipId != CHIP_ID_YUKON) ||
(pAC->GIni.GICopperType != SK_TRUE)) &&
- ((LinkSpeed != SK_LSPEED_AUTO) &&
+ ((LinkSpeed != SK_LSPEED_AUTO) &&
(LinkSpeed != SK_LSPEED_1000MBPS))) {
printk("%s: Illegal value for Speed_A. "
"Not a copper card or GE V2 card\n Using "
else printk("%s: Illegal value for DupCap_A\n",
pAC->dev[0]->name);
}
-
+
/* check for illegal combinations */
if (AutoSet && AutoNeg==AN_SENS && DupSet) {
printk("%s, Port A: DuplexCapabilities"
if (AutoSet && AutoNeg==AN_OFF && !DupSet) {
DuplexCap = DC_FULL;
}
-
+
if (!AutoSet && DupSet) {
printk("%s, Port A: Duplex setting not"
" possible in\n default AutoNegotiation mode"
pAC->dev[0]->name);
AutoNeg = AN_ON;
}
-
+
/* set the desired mode */
pAC->GIni.GP[0].PLinkModeConf =
Capabilities[AutoNeg][DuplexCap];
-
+
pAC->GIni.GP[0].PFlowCtrlMode = SK_FLOW_MODE_SYM_OR_REM;
if (FlowCtrl_A != NULL && pAC->Index<SK_MAX_CARD_PARAM &&
FlowCtrl_A[pAC->Index] != NULL) {
pAC->dev[0]->name);
}
pAC->GIni.GP[0].PMSMode = MSMode;
-
-
+
+
/* settings for port B */
/* settings link speed */
LinkSpeed = SK_LSPEED_AUTO; /* default: do auto select */
/* Only copper type adapter and GE V2 cards */
if (((pAC->GIni.GIChipId != CHIP_ID_YUKON) ||
(pAC->GIni.GICopperType != SK_TRUE)) &&
- ((LinkSpeed != SK_LSPEED_AUTO) &&
+ ((LinkSpeed != SK_LSPEED_AUTO) &&
(LinkSpeed != SK_LSPEED_1000MBPS))) {
printk("%s: Illegal value for Speed_B. "
"Not a copper card or GE V2 card\n Using "
}
else printk("Illegal value for DupCap_B\n");
}
-
+
/* check for illegal combinations */
if (AutoSet && AutoNeg==AN_SENS && DupSet) {
printk("%s, Port B: DuplexCapabilities"
if (AutoSet && AutoNeg==AN_OFF && !DupSet) {
DuplexCap = DC_FULL;
}
-
+
if (!AutoSet && DupSet) {
printk("%s, Port B: Duplex setting not"
" possible in\n default AutoNegotiation mode"
pAC->dev[1]->name);
}
pAC->GIni.GP[1].PMSMode = MSMode;
-
-
+
+
/* settings for both ports */
pAC->ActivePort = 0;
if (PrefPort != NULL && pAC->Index<SK_MAX_CARD_PARAM &&
}
else if (strcmp(RlmtMode[pAC->Index], "CheckSeg") == 0) {
pAC->RlmtMode = SK_RLMT_CHECK_LINK |
- SK_RLMT_CHECK_LOC_LINK |
+ SK_RLMT_CHECK_LOC_LINK |
SK_RLMT_CHECK_SEG;
}
else if ((strcmp(RlmtMode[pAC->Index], "DualNet") == 0) &&
} /* ProductStr */
-
-
/****************************************************************************/
/* functions for common modules *********************************************/
/****************************************************************************/
* Nothing
*/
void SkDrvFreeRlmtMbuf(
-SK_AC *pAC, /* pointer to adapter context */
-SK_IOC IoC, /* the IO-context */
+SK_AC *pAC, /* pointer to adapter context */
+SK_IOC IoC, /* the IO-context */
SK_MBUF *pMbuf) /* size of the requested buffer */
{
SK_MBUF *pFreeMbuf;
* Returns:
* 0 if everything ok
* < 0 on error
- *
+ *
*/
int SkDrvEvent(
SK_AC *pAC, /* pointer to adapter context */
spin_unlock_irqrestore(
&pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
Flags);
-
+
/* clear rx ring from received frames */
ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE);
-
+
ClearTxRing(pAC, &pAC->TxPort[FromPort][TX_PRIO_LOW]);
spin_lock_irqsave(
&pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
Flags);
-
+
/* tschilling: Handling of return value inserted. */
if (SkGeInitPort(pAC, IoC, FromPort)) {
if (FromPort == 0) {
else {
printk(" flowctrl: none\n");
}
-
+
/* tschilling: Check against CopperType now. */
if ((pAC->GIni.GICopperType == SK_TRUE) &&
(pAC->GIni.GP[FromPort].PLinkSpeedUsed ==
printk(" scatter-gather: disabled\n");
#endif
#endif /* SK98_INFO */
-
- if ((Param.Para32[0] != pAC->ActivePort) &&
+
+ if ((Param.Para32[0] != pAC->ActivePort) &&
(pAC->RlmtNets == 1)) {
NewPara.Para32[0] = pAC->ActivePort;
NewPara.Para32[1] = Param.Para32[0];
ReceiveIrq(pAC, &pAC->RxPort[FromPort], SK_FALSE); /* clears rx ring */
ReceiveIrq(pAC, &pAC->RxPort[ToPort], SK_FALSE); /* clears rx ring */
-
+
ClearTxRing(pAC, &pAC->TxPort[FromPort][TX_PRIO_LOW]);
ClearTxRing(pAC, &pAC->TxPort[ToPort][TX_PRIO_LOW]);
spin_lock_irqsave(
- &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
+ &pAC->TxPort[FromPort][TX_PRIO_LOW].TxDesRingLock,
Flags);
spin_lock_irqsave(
&pAC->TxPort[ToPort][TX_PRIO_LOW].TxDesRingLock, Flags);
if (pAC->RlmtNets == 2) {
DualNet = SK_TRUE;
}
-
+
if (SkGeInitAssignRamToQueues(
pAC,
pAC->ActivePort,
}
SK_DBG_MSG(NULL, SK_DBGMOD_DRV, SK_DBGCAT_DRV_EVENT,
("END EVENT "));
-
+
return (0);
} /* SkDrvEvent */
* Returns:
* 0 if everything ok
* < 0 on error
- *
+ *
*/
void SkErrorLog(
SK_AC *pAC,
* This function prints frames to the system logfile/to the console.
*
* Returns: N/A
- *
+ *
*/
static void DumpMsg(struct sk_buff *skb, char *str)
{
} /* DumpMsg */
-
/*****************************************************************************
*
* DumpData - print a data area
*
* Description:
- * This function prints a area of data to the system logfile/to the
+ * This function prints a area of data to the system logfile/to the
* console.
*
* Returns: N/A
- *
+ *
*/
static void DumpData(char *p, int size)
{
* DumpLong - print a data area as long values
*
* Description:
- * This function prints a area of data to the system logfile/to the
+ * This function prints a area of data to the system logfile/to the
* console.
*
* Returns: N/A
- *
+ *
*/
static void DumpLong(char *pc, int size)
{
#endif
#endif /* CONFIG_SK98 */
-
-/*
- * Local variables:
- * compile-command: "make"
- * End:
- */
-
* $Log: skgehwt.c,v $
* Revision 1.13 1999/11/22 13:31:12 cgoos
* Changed license header to GPL.
- *
+ *
* Revision 1.12 1998/10/15 15:11:34 gklug
* fix: ID_sccs to SysKonnectFileId
- *
+ *
* Revision 1.11 1998/10/08 15:27:51 gklug
* chg: correction factor is host clock dependent
- *
+ *
* Revision 1.10 1998/09/15 14:18:31 cgoos
* Changed more BOOLEANs to SK_xxx
*
* Revision 1.9 1998/09/15 14:16:06 cgoos
* Changed line 107: FALSE to SK_FALSE
- *
+ *
* Revision 1.8 1998/08/24 13:04:44 gklug
* fix: typo
- *
+ *
* Revision 1.7 1998/08/19 09:50:49 gklug
* fix: remove struct keyword from c-code (see CCC) add typedefs
- *
+ *
* Revision 1.6 1998/08/17 09:59:02 gklug
* fix: typos
- *
+ *
* Revision 1.5 1998/08/14 07:09:10 gklug
* fix: chg pAc -> pAC
- *
+ *
* Revision 1.4 1998/08/10 14:14:52 gklug
* rmv: unneccessary SK_ADDR macro
- *
+ *
* Revision 1.3 1998/08/07 12:53:44 gklug
* fix: first compiled version
- *
+ *
* Revision 1.2 1998/08/07 09:19:29 gklug
* adapt functions to the C coding conventions
* rmv unneccessary functions.
- *
+ *
* Revision 1.1 1998/08/05 11:28:36 gklug
* first version: adapted from SMT/FDDI
- *
- *
- *
+ *
+ *
+ *
*
******************************************************************************/
* Corrected setting of GIHstClkFact (Host Clock Factor) and
* GIPollTimerVal (Descr. Poll Timer Init Value) for YUKON.
* Editorial changes.
- *
+ *
* Revision 1.84 2003/01/28 09:57:25 rschmidt
* Added detection of YUKON-Lite Rev. A0 (stored in GIYukonLite).
* Disabled Rx GMAC FIFO Flush for YUKON-Lite Rev. A0.
* Added support for CLK_RUN (YUKON-Lite).
* Added additional check of PME from D3cold for setting GIVauxAvail.
* Editorial changes.
- *
+ *
* Revision 1.83 2002/12/17 16:15:41 rschmidt
* Added default setting of PhyType (Copper) for YUKON.
* Added define around check for HW self test results.
* Editorial changes.
- *
+ *
* Revision 1.82 2002/12/05 13:40:21 rschmidt
* Added setting of Rx GMAC FIFO Flush Mask register.
* Corrected PhyType with new define SK_PHY_MARV_FIBER when
* YUKON Fiber board was found.
* Editorial changes.
- *
+ *
* Revision 1.81 2002/11/15 12:48:35 rschmidt
* Replaced message SKERR_HWI_E018 with SKERR_HWI_E024 for Rx queue error
* in SkGeStopPort().
* Added init for pAC->GIni.GIGenesis with SK_FALSE in YUKON-branch.
* Editorial changes.
- *
+ *
* Revision 1.80 2002/11/12 17:28:30 rschmidt
* Initialized GIPciSlot64 and GIPciClock66 in SkGeInit1().
* Reduced PCI FIFO watermarks for 32bit/33MHz bus in SkGeInitBmu().
* Editorial changes.
- *
+ *
* Revision 1.79 2002/10/21 09:31:02 mkarl
* Changed SkGeInitAssignRamToQueues(), removed call to
* SkGeInitAssignRamToQueues in SkGeInit1 and fixed compiler warning in
* SkGeInit1.
- *
+ *
* Revision 1.78 2002/10/16 15:55:07 mkarl
* Fixed a bug in SkGeInitAssignRamToQueues.
- *
+ *
* Revision 1.77 2002/10/14 15:07:22 rschmidt
* Corrected timeout handling for Rx queue in SkGeStopPort() (#10748)
* Editorial changes.
- *
+ *
* Revision 1.76 2002/10/11 09:24:38 mkarl
* Added check for HW self test results.
- *
+ *
* Revision 1.75 2002/10/09 16:56:44 mkarl
* Now call SkGeInitAssignRamToQueues() in Init Level 1 in order to assign
* the adapter memory to the queues. This default assignment is not suitable
* for dual net mode.
- *
+ *
* Revision 1.74 2002/09/12 08:45:06 rwahl
* Set defaults for PMSCap, PLinkSpeed & PLinkSpeedCap dependent on PHY.
- *
+ *
* Revision 1.73 2002/08/16 15:19:45 rschmidt
* Corrected check for Tx queues in SkGeCheckQSize().
* Added init for new entry GIGenesis and GICopperType
* Replaced all if(GIChipId == CHIP_ID_GENESIS) with new entry GIGenesis.
* Replaced wrong 1st para pAC with IoC in SK_IN/OUT macros.
- *
+ *
* Revision 1.72 2002/08/12 13:38:55 rschmidt
* Added check if VAUX is available (stored in GIVauxAvail)
* Initialized PLinkSpeedCap in Port struct with SK_LSPEED_CAP_1000MBPS
* Editorial changes.
- *
+ *
* Revision 1.71 2002/08/08 16:32:58 rschmidt
* Added check for Tx queues in SkGeCheckQSize().
* Added start of Time Stamp Timer (YUKON) in SkGeInit2().
* Editorial changes.
- *
+ *
* Revision 1.70 2002/07/23 16:04:26 rschmidt
* Added init for GIWolOffs (HW-Bug in YUKON 1st rev.)
* Minor changes
- *
+ *
* Revision 1.69 2002/07/17 17:07:08 rwahl
* - SkGeInit1(): fixed PHY type debug output; corrected init of GIFunc
* table & GIMacType.
* - Editorial changes.
- *
+ *
* Revision 1.68 2002/07/15 18:38:31 rwahl
* Added initialization for MAC type dependent function table.
- *
+ *
* Revision 1.67 2002/07/15 15:45:39 rschmidt
* Added Tx Store & Forward for YUKON (GMAC Tx FIFO is only 1 kB)
* Replaced SK_PHY_MARV by SK_PHY_MARV_COPPER
* Editorial changes
- *
+ *
* Revision 1.66 2002/06/10 09:35:08 rschmidt
* Replaced C++ comments (//)
* Editorial changes
- *
+ *
* Revision 1.65 2002/06/05 08:33:37 rschmidt
* Changed GIRamSize and Reset sequence for YUKON.
* SkMacInit() replaced by SkXmInitMac() resp. SkGmInitMac()
- *
+ *
* Revision 1.64 2002/04/25 13:03:20 rschmidt
* Changes for handling YUKON.
* Removed reference to xmac_ii.h (not necessary).
* Use of SkGeXmitLED() only for GENESIS.
* Changes for V-CPU support.
* Editorial changes.
- *
+ *
* Revision 1.63 2001/04/05 11:02:09 rassmann
* Stop Port check of the STOP bit did not take 2/18 sec as wanted.
- *
+ *
* Revision 1.62 2001/02/07 07:54:21 rassmann
* Corrected copyright.
- *
+ *
* Revision 1.61 2001/01/31 15:31:40 gklug
* fix: problem with autosensing an SR8800 switch
- *
+ *
* Revision 1.60 2000/10/18 12:22:21 cgoos
* Added workaround for half duplex hangup.
- *
+ *
* Revision 1.59 2000/10/10 11:22:06 gklug
* add: in manual half duplex mode ignore carrier extension errors
- *
+ *
* Revision 1.58 2000/10/02 14:10:27 rassmann
* Reading BCOM PHY after releasing reset until it returns a valid value.
- *
+ *
* Revision 1.57 2000/08/03 14:55:28 rassmann
* Waiting for I2C to be ready before de-initializing adapter
* (prevents sensors from hanging up).
- *
+ *
* Revision 1.56 2000/07/27 12:16:48 gklug
* fix: Stop Port check of the STOP bit does now take 2/18 sec as wanted
- *
+ *
* Revision 1.55 1999/11/22 13:32:26 cgoos
* Changed license header to GPL.
- *
+ *
* Revision 1.54 1999/10/26 07:32:54 malthoff
* Initialize PHWLinkUp with SK_FALSE. Required for Diagnostics.
- *
+ *
* Revision 1.53 1999/08/12 19:13:50 malthoff
* Fix for 1000BT. Do not owerwrite XM_MMU_CMD when
* disabling receiver and transmitter. Other bits
* may be lost.
- *
+ *
* Revision 1.52 1999/07/01 09:29:54 gklug
* fix: DoInitRamQueue needs pAC
- *
+ *
* Revision 1.51 1999/07/01 08:42:21 gklug
* chg: use Store & forward for RAM buffer when Jumbos are used
- *
+ *
* Revision 1.50 1999/05/27 13:19:38 cgoos
* Added Tx PCI watermark initialization.
* Removed Tx RAM queue Store & Forward setting.
- *
+ *
* Revision 1.49 1999/05/20 14:32:45 malthoff
* SkGeLinkLED() is completly removed now.
- *
+ *
* Revision 1.48 1999/05/19 07:28:24 cgoos
* SkGeLinkLED no more available for drivers.
* Changes for 1000Base-T.
- *
+ *
* Revision 1.47 1999/04/08 13:57:45 gklug
* add: Init of new port struct fiels PLinkResCt
* chg: StopPort Timer check
- *
+ *
* Revision 1.46 1999/03/25 07:42:15 malthoff
* SkGeStopPort(): Add workaround for cache incoherency.
* Create error log entry, disable port, and
* exit loop if it does not terminate.
* Add XM_RX_LENERR_OK to the default value for the
* XMAC receive command register.
- *
+ *
* Revision 1.45 1999/03/12 16:24:47 malthoff
* Remove PPollRxD and PPollTxD.
* Add check for GIPollTimerVal.
if (pPrt->PXSQSize != 0) {
SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), DWord);
}
-
+
if (pPrt->PXAQSize != 0) {
SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), DWord);
}
SK_OUT8(IoC, Led + XMIT_LED_TST, LED_T_OFF);
break;
}
-
+
/*
* 1000BT: The Transmit LED is driven by the PHY.
* But the default LED configuration is used for
for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
pGePort = &pAC->GIni.GP[i];
-
+
/* take away the minimum memory for active queues */
ActivePortKilobytes -= (SK_MIN_RXQ_SIZE + SK_MIN_TXQ_SIZE);
SK_MIN_TXQ_SIZE);
}
}
- else {
+ else {
/* Rlmt Mode or single link adapter */
/* Set standby queue size defaults for all standby ports */
SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E011, SKERR_HWI_E011MSG);
return(1);
}
-
+
/*
* the size of at least one Tx queue (synch. or asynch.) has to be > 0.
* if Jumbo Frames are used, this size has to be >= 16 kB.
*/
if ((i == Port && pPrt->PXSQSize == 0 && pPrt->PXAQSize == 0) ||
(pAC->GIni.GIPortUsage == SK_JUMBO_LINK &&
- ((pPrt->PXSQSize > 0 && pPrt->PXSQSize < SK_MIN_TXQ_SIZE) ||
+ ((pPrt->PXSQSize > 0 && pPrt->PXSQSize < SK_MIN_TXQ_SIZE) ||
(pPrt->PXAQSize > 0 && pPrt->PXAQSize < SK_MIN_TXQ_SIZE)))) {
SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E023, SKERR_HWI_E023MSG);
return(1);
}
-
+
UsedMem += pPrt->PRxQSize + pPrt->PXSQSize + pPrt->PXAQSize;
}
-
+
if (UsedMem > pAC->GIni.GIRamSize) {
SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E012, SKERR_HWI_E012MSG);
return(1);
* - setup defaults for the control register
* - enable the FIFO
*/
-
+
Word = GMF_RX_CTRL_DEF;
-
+
if (pAC->GIni.GIGenesis) {
/* Configure Rx MAC FIFO */
SK_OUT8(IoC, MR_ADDR(Port, RX_MFF_CTRL2), MFF_RST_CLR);
SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_RX_CTRL_DEF);
SK_OUT8(IoC, MR_ADDR(Port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
-
+
/* Configure Tx MAC FIFO */
SK_OUT8(IoC, MR_ADDR(Port, TX_MFF_CTRL2), MFF_RST_CLR);
SK_OUT16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
SK_OUT8(IoC, MR_ADDR(Port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
-
+
/* Enable frame flushing if jumbo frames used */
if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK) {
SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_ENA_FLUSH);
else {
/* set Rx GMAC FIFO Flush Mask */
SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_MSK), (SK_U16)RX_FF_FL_DEF_MSK);
-
+
if (pAC->GIni.GIYukonLite && pAC->GIni.GIChipId == CHIP_ID_YUKON) {
Word &= ~GMF_RX_F_FL_ON;
}
-
+
/* Configure Rx MAC FIFO */
SK_OUT8(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), (SK_U8)GMF_RST_CLR);
SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_CTRL_T), Word);
-
+
/* set Rx GMAC FIFO Flush Threshold (default: 0x0a -> 56 bytes) */
SK_OUT16(IoC, MR_ADDR(Port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
-
+
/* Configure Tx MAC FIFO */
SK_OUT8(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U8)GMF_RST_CLR);
SK_OUT16(IoC, MR_ADDR(Port, TX_GMF_CTRL_T), (SK_U16)GMF_TX_CTRL_DEF);
-
+
#ifdef VCPU
SK_IN32(IoC, MR_ADDR(Port, RX_GMF_AF_THR), &DWord);
SK_IN32(IoC, MR_ADDR(Port, TX_GMF_AE_THR), &DWord);
#endif /* VCPU */
-
+
/* set Tx GMAC FIFO Almost Empty Threshold */
/* SK_OUT32(IoC, MR_ADDR(Port, TX_GMF_AE_THR), 0); */
}
SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E010, SKERR_HWI_E010MSG);
return(1);
}
-
+
if (pAC->GIni.GP[Port].PXSQSize == 0) {
SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E009, SKERR_HWI_E009MSG);
return(2);
}
-
+
/* calculate register values */
IntTime = (IntTime / 2) * pAC->GIni.GIHstClkFact / 100;
LimCount = LimCount / 8;
-
+
if (IntTime > TXA_MAX_VAL || LimCount > TXA_MAX_VAL) {
SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E010, SKERR_HWI_E010MSG);
return(1);
*/
SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL),
TXA_ENA_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
-
+
SK_OUT32(IoC, MR_ADDR(Port, TXA_ITI_INI), IntTime);
SK_OUT32(IoC, MR_ADDR(Port, TXA_LIM_INI), LimCount);
-
+
SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL),
(SK_U8)(SyncMode & (TXA_ENA_ALLOC | TXA_DIS_ALLOC)));
-
+
if (IntTime != 0 || LimCount != 0) {
SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL), TXA_DIS_FSYNC | TXA_START_RC);
}
DoInitRamQueue(pAC, IoC, pPrt->PRxQOff, pPrt->PRxQRamStart,
pPrt->PRxQRamEnd, RxQType);
-
+
DoInitRamQueue(pAC, IoC, pPrt->PXsQOff, pPrt->PXsQRamStart,
pPrt->PXsQRamEnd, SK_TX_RAM_Q);
-
+
DoInitRamQueue(pAC, IoC, pPrt->PXaQOff, pPrt->PXaQRamStart,
pPrt->PXaQRamEnd, SK_TX_RAM_Q);
RxWm = SK_BMU_RX_WM;
TxWm = SK_BMU_TX_WM;
-
+
if (!pAC->GIni.GIPciSlot64 && !pAC->GIni.GIPciClock66) {
/* for better performance */
RxWm /= 2;
SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_CSR), CSR_CLR_RESET);
SK_OUT32(IoC, Q_ADDR(pPrt->PXsQOff, Q_F), TxWm);
}
-
+
if (pPrt->PXAQSize != 0) {
SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_CSR), CSR_CLR_RESET);
SK_OUT32(IoC, Q_ADDR(pPrt->PXaQOff, Q_F), TxWm);
SK_U32 QuCsr; /* CSR contents */
SK_IN32(IoC, Q_ADDR(QuIoOffs, Q_CSR), &QuCsr);
-
+
if ((QuCsr & (CSR_STOP | CSR_SV_IDLE)) == 0) {
/* Stop Descriptor overridden by start command */
SK_OUT32(IoC, Q_ADDR(QuIoOffs, Q_CSR), CSR_STOP);
SK_IN32(IoC, Q_ADDR(QuIoOffs, Q_CSR), &QuCsr);
}
-
+
return(QuCsr);
} /* TestStopBit */
if ((Dir & SK_STOP_TX) != 0) {
/* disable receiver and transmitter */
SkMacRxTxDisable(pAC, IoC, Port);
-
+
/* stop both transmit queues */
/*
* If the BMU is in the reset state CSR_STOP will terminate
else {
SkMacHardRst(pAC, IoC, Port);
}
-
+
/* Disable Force Sync bit and Enable Alloc bit */
SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL),
TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
-
+
/* Stop Interval Timer and Limit Counter of Tx Arbiter */
SK_OUT32(IoC, MR_ADDR(Port, TXA_ITI_INI), 0L);
SK_OUT32(IoC, MR_ADDR(Port, TXA_LIM_INI), 0L);
SK_OUT8(IoC, RB_ADDR(pPrt->PXaQOff, RB_CTRL), RB_RST_SET);
/* Reset the RAM Buffer sync Tx queue */
SK_OUT8(IoC, RB_ADDR(pPrt->PXsQOff, RB_CTRL), RB_RST_SET);
-
+
/* Reset Tx MAC FIFO */
if (pAC->GIni.GIGenesis) {
/* Note: MFF_RST_SET does NOT reset the XMAC ! */
*/
/* stop the port's receive queue */
SK_OUT32(IoC, Q_ADDR(pPrt->PRxQOff, Q_CSR), CSR_STOP);
-
+
i = 100;
do {
/*
*/
SK_OUT16(IoC, B3_PA_CTRL, (Port == MAC_1) ? PA_CLR_TO_RX1 :
PA_CLR_TO_RX2);
-
+
DWord = TestStopBit(pAC, IoC, pPrt->PRxQOff);
/* timeout if i==0 (bug fix for #10748) */
/* Reset Rx MAC FIFO */
if (pAC->GIni.GIGenesis) {
-
+
SK_OUT8(IoC, MR_ADDR(Port, RX_MFF_CTRL2), MFF_RST_SET);
/* switch Rx LED off, stop the LED counter */
/* We know the RAM Interface Arbiter is enabled. */
SkPciWriteCfgWord(pAC, PCI_PM_CTL_STS, PCI_PM_STATE_D3);
SkPciReadCfgWord(pAC, PCI_PM_CTL_STS, &PmCtlSts);
-
+
if ((PmCtlSts & PCI_PM_STATE_MSK) != PCI_PM_STATE_D3) {
return(1);
}
/* Check for D0 state. */
SkPciReadCfgWord(pAC, PCI_PM_CTL_STS, &PmCtlSts);
-
+
if ((PmCtlSts & PCI_PM_STATE_MSK) != PCI_PM_STATE_D0) {
return(1);
}
SkPciReadCfgDWord(pAC, PCI_BASE_1ST, &Bp1);
SkPciReadCfgDWord(pAC, PCI_BASE_2ND, &Bp2);
SkPciReadCfgByte(pAC, PCI_LAT_TIM, &Lat);
-
+
if (PciCmd != 0 || Cls != 0 || (Bp1 & 0xfffffff0L) != 0 || Bp2 != 1 ||
Lat != 0) {
return(1);
* available on some platforms after 'boot time'.
*/
SK_IN16(IoC, PCI_C(PCI_STATUS), &Word);
-
+
SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
SK_OUT16(IoC, PCI_C(PCI_STATUS), Word | PCI_ERRBITS);
SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
/* restore CLK_RUN bits */
SK_OUT16(IoC, B0_CTST, CtrlStat &
(CS_CLK_RUN_HOT | CS_CLK_RUN_RST | CS_CLK_RUN_ENA));
-
+
/* read Chip Identification Number */
SK_IN8(IoC, B2_CHIP_ID, &Byte);
pAC->GIni.GIChipId = Byte;
-
+
/* read number of MACs */
SK_IN8(IoC, B2_MAC_CFG, &Byte);
pAC->GIni.GIMacsFound = (Byte & CFG_SNG_MAC) ? 1 : 2;
-
+
/* get Chip Revision Number */
pAC->GIni.GIChipRev = (SK_U8)((Byte & CFG_CHIP_R_MSK) >> 4);
/* get diff. PCI parameters */
SK_IN16(IoC, B0_CTST, &CtrlStat);
-
+
/* read the adapters RAM size */
SK_IN8(IoC, B2_E_0, &Byte);
-
+
if (pAC->GIni.GIChipId == CHIP_ID_GENESIS) {
pAC->GIni.GIGenesis = SK_TRUE;
- if (Byte == 3) {
+ if (Byte == 3) {
/* special case: 4 x 64k x 36, offset = 0x80000 */
pAC->GIni.GIRamSize = 1024;
pAC->GIni.GIRamOffs = (SK_U32)512 * 1024;
}
/* all GE adapters work with 53.125 MHz host clock */
pAC->GIni.GIHstClkFact = SK_FACT_53;
-
+
/* set Descr. Poll Timer Init Value to 250 ms */
pAC->GIni.GIPollTimerVal =
SK_DPOLL_DEF * (SK_U32)pAC->GIni.GIHstClkFact / 100;
pAC->GIni.GIRamSize = (Byte == 0) ? 128 : (int)Byte * 4;
#else
pAC->GIni.GIRamSize = 128;
-#endif
+#endif
pAC->GIni.GIRamOffs = 0;
-
+
/* WA for chip Rev. A */
pAC->GIni.GIWolOffs = (pAC->GIni.GIChipRev == 0) ? WOL_REG_OFFS : 0;
-
+
/* get PM Capabilities of PCI config space */
SK_IN16(IoC, PCI_C(PCI_PM_CAP_REG), &Word);
/* set entry in GE init struct */
pAC->GIni.GIVauxAvail = SK_TRUE;
}
-
+
/* save Flash-Address Register */
SK_IN32(IoC, B2_FAR, &FlashAddr);
/* test Flash-Address Register */
SK_OUT8(IoC, B2_FAR + 3, 0xff);
SK_IN8(IoC, B2_FAR + 3, &Byte);
-
+
pAC->GIni.GIYukonLite = (SK_BOOL)(Byte != 0);
-
+
/* restore Flash-Address Register */
SK_OUT32(IoC, B2_FAR, FlashAddr);
}
/* all YU chips work with 78.125 MHz host clock */
pAC->GIni.GIHstClkFact = SK_FACT_78;
-
+
pAC->GIni.GIPollTimerVal = SK_DPOLL_MAX; /* 215 ms */
}
/* check if 64-bit PCI Slot is present */
pAC->GIni.GIPciSlot64 = (SK_BOOL)((CtrlStat & CS_BUS_SLOT_SZ) != 0);
-
+
/* check if 66 MHz PCI Clock is active */
pAC->GIni.GIPciClock66 = (SK_BOOL)((CtrlStat & CS_BUS_CLOCK) != 0);
Byte &= 0x0f; /* the PHY type is stored in the lower nibble */
for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
-
+
if (pAC->GIni.GIGenesis) {
switch (Byte) {
case SK_PHY_XMAC:
pAC->GIni.GICopperType = SK_TRUE;
}
pAC->GIni.GP[i].PhyAddr = PHY_ADDR_MARV;
-
+
if (pAC->GIni.GICopperType) {
pAC->GIni.GP[i].PLinkSpeedCap = SK_LSPEED_CAP_AUTO |
SK_LSPEED_CAP_10MBPS | SK_LSPEED_CAP_100MBPS |
Byte = SK_PHY_MARV_FIBER;
}
}
-
+
pAC->GIni.GP[i].PhyType = Byte;
-
+
SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_INIT,
("PHY type: %d PHY addr: %04x\n", Byte,
pAC->GIni.GP[i].PhyAddr));
}
-
+
/* get Mac Type & set function pointers dependent on */
if (pAC->GIni.GIGenesis) {
pAC->GIni.GIMacType = SK_MAC_XMAC;
pAC->GIni.GIFunc.pFnMacStatistic = SkGmMacStatistic;
pAC->GIni.GIFunc.pFnMacResetCounter = SkGmResetCounter;
pAC->GIni.GIFunc.pFnMacOverflow = SkGmOverflowStatus;
-
+
#ifdef SPECIAL_HANDLING
if (pAC->GIni.GIChipId == CHIP_ID_YUKON) {
/* check HW self test result */
SkGeInit0(pAC, IoC);
pAC->GIni.GILevel = SK_INIT_DATA;
break;
-
+
case SK_INIT_IO:
/* Initialization Level 1 */
RetVal = SkGeInit1(pAC, IoC);
SK_OUT32(IoC, B2_IRQM_INI, 0x11335577L);
SK_IN32(IoC, B2_IRQM_INI, &DWord);
SK_OUT32(IoC, B2_IRQM_INI, 0L);
-
+
if (DWord != 0x11335577L) {
RetVal = 2;
break;
/* Level 1 successfully passed */
pAC->GIni.GILevel = SK_INIT_IO;
break;
-
+
case SK_INIT_RUN:
/* Initialization Level 2 */
if (pAC->GIni.GILevel != SK_INIT_IO) {
/* Level 2 successfully passed */
pAC->GIni.GILevel = SK_INIT_RUN;
break;
-
+
default:
SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E003, SKERR_HWI_E003MSG);
RetVal = 3;
* available on some platforms after 'boot time'.
*/
SK_IN16(IoC, PCI_C(PCI_STATUS), &Word);
-
+
SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
SK_OUT16(IoC, PCI_C(PCI_STATUS), Word | PCI_ERRBITS);
SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E004, SKERR_HWI_E004MSG);
return(1);
}
-
+
if (pPrt->PState == SK_PRT_INIT || pPrt->PState == SK_PRT_RUN) {
SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E005, SKERR_HWI_E005MSG);
return(2);
SkGeXmitLED(pAC, IoC, MR_ADDR(Port, TX_LED_INI), SK_LED_ENA);
SkGeXmitLED(pAC, IoC, MR_ADDR(Port, RX_LED_INI), SK_LED_ENA);
/* The Link LED is initialized by RLMT or Diagnostics itself */
-
+
SkXmInitMac(pAC, IoC, Port);
}
else {
SkGmInitMac(pAC, IoC, Port);
}
-
+
/* do NOT initialize the Link Sync Counter */
SkGeInitMacFifo(pAC, IoC, Port);
-
+
SkGeInitRamBufs(pAC, IoC, Port);
-
+
if (pPrt->PXSQSize != 0) {
/* enable Force Sync bit if synchronous queue available */
SK_OUT8(IoC, MR_ADDR(Port, TXA_CTRL), TXA_ENA_FSYNC);
}
-
+
SkGeInitBmu(pAC, IoC, Port);
/* mark port as initialized */
* $Log: skgemib.c,v $
* Revision 1.7 2002/12/16 09:04:34 tschilli
* Code for VCT handling added.
- *
+ *
* Revision 1.6 2002/08/09 15:40:21 rwahl
* Editorial change (renamed ConfSpeedCap).
- *
+ *
* Revision 1.5 2002/08/09 11:05:34 rwahl
* Added oid handling for link speed cap.
- *
+ *
* Revision 1.4 2002/08/09 09:40:27 rwahl
* Added support for NDIS OID_PNP_xxx.
- *
+ *
* Revision 1.3 2002/07/17 19:39:54 rwahl
* Added handler for OID_SKGE_SPEED_MODE & OID_SKGE_SPEED_STATUS.
- *
+ *
* Revision 1.2 2002/05/22 08:59:00 rwahl
* - static functions only for release build.
* - Source file must be included.
- *
+ *
* Revision 1.1 2002/05/22 08:12:42 rwahl
* Initial version.
- *
+ *
****************************************************************************/
#include <config.h>
#endif
-
/* defines *******************************************************************/
#define ID_TABLE_SIZE (sizeof(IdTable)/sizeof(IdTable[0]))
sizeof(SK_PNMI_VPD),
SK_PNMI_OFF(Vpd) + SK_PNMI_VPD_OFF(VpdAction),
SK_PNMI_RW, Vpd, 0},
- {OID_SKGE_PORT_NUMBER,
+ {OID_SKGE_PORT_NUMBER,
1,
0,
SK_PNMI_MAI_OFF(PortNumber),
* $Log: skgepnmi.c,v $
* Revision 1.102 2002/12/16 14:03:24 tschilli
* VCT code in Vct() changed.
- *
+ *
* Revision 1.101 2002/12/16 09:04:10 tschilli
* Code for VCT handling added.
- *
+ *
* Revision 1.100 2002/09/26 14:28:13 tschilli
* For XMAC the values in the SK_PNMI_PORT Port struct are copied to
* the new SK_PNMI_PORT BufPort struct during a MacUpdate() call.
* These values are used when GetPhysStatVal() is called. With this
* mechanism you get the best results when software corrections for
* counters are needed. Example: RX_LONGFRAMES.
- *
+ *
* Revision 1.99 2002/09/17 12:31:19 tschilli
* OID_SKGE_TX_HW_ERROR_CTS, OID_SKGE_OUT_ERROR_CTS, OID_GEN_XMIT_ERROR:
* Double count of SK_PNMI_HTX_EXCESS_COL in function General() removed.
* OID_PNP_CAPABILITIES: sizeof(SK_PM_WAKE_UP_CAPABILITIES) changed to
* sizeof(SK_PNP_CAPABILITIES) in function PowerManagement().
- *
+ *
* Revision 1.98 2002/09/10 09:00:03 rwahl
* Adapted boolean definitions according sktypes.
- *
+ *
* Revision 1.97 2002/09/05 15:07:03 rwahl
* Editorial changes.
- *
+ *
* Revision 1.96 2002/09/05 11:04:14 rwahl
* - Rx/Tx packets statistics of virtual port were zero on link down (#10750)
* - For GMAC the overflow IRQ for Rx longframe counter was not counted.
* OID_SKGE_IN_ERRORS_CTS, OID_GEN_RCV_ERROR.
* - Moved correction for OID_SKGE_STAT_RX_TOO_LONG to GetPhysStatVal().
* - Editorial changes.
- *
+ *
* Revision 1.95 2002/09/04 08:53:37 rwahl
* - Incorrect statistics for Rx_too_long counter with jumbo frame (#10751)
* - StatRxFrameTooLong & StatRxPMaccErr counters were not reset.
* - Fixed compiler warning for debug msg arg types.
- *
+ *
* Revision 1.94 2002/08/09 15:42:14 rwahl
* - Fixed StatAddr table for GMAC.
* - VirtualConf(): returned indeterminated status for speed oids if no
* active port.
- *
+ *
* Revision 1.93 2002/08/09 11:04:59 rwahl
* Added handler for link speed caps.
- *
+ *
* Revision 1.92 2002/08/09 09:43:03 rwahl
* - Added handler for NDIS OID_PNP_xxx ids.
- *
+ *
* Revision 1.91 2002/07/17 19:53:03 rwahl
* - Added StatOvrflwBit table for XMAC & GMAC.
* - Extended StatAddr table for GMAC. Added check of number of counters
* - Added handler for oids SKGE_SPEED_MODE & SKGE_SPEED_STATUS.
* - Extendet GetPhysStatVal() for GMAC.
* - Editorial changes.
- *
+ *
* Revision 1.90 2002/05/22 08:56:25 rwahl
* - Moved OID table to separate source file.
* - Fix: TX_DEFFERAL counter incremented in full-duplex mode.
* - Use string definitions for error msgs.
- *
+ *
* Revision 1.89 2001/09/18 10:01:30 mkunz
* some OID's fixed for dualnetmode
- *
+ *
* Revision 1.88 2001/08/02 07:58:08 rwahl
* - Fixed NetIndex to csum module at ResetCounter().
- *
+ *
* Revision 1.87 2001/04/06 13:35:09 mkunz
* -Bugs fixed in handling of OID_SKGE_MTU and the VPD OID's
- *
+ *
* Revision 1.86 2001/03/09 09:18:03 mkunz
* Changes in SK_DBG_MSG
- *
+ *
* Revision 1.85 2001/03/08 09:37:31 mkunz
* Bugfix in ResetCounter for Pnmi.Port structure
- *
+ *
* Revision 1.84 2001/03/06 09:04:55 mkunz
* Made some changes in instance calculation
- *
+ *
* Revision 1.83 2001/02/15 09:15:32 mkunz
* Necessary changes for dual net mode added
- *
+ *
* Revision 1.82 2001/02/07 08:24:19 mkunz
* -Made changes in handling of OID_SKGE_MTU
- *
+ *
* Revision 1.81 2001/02/06 09:58:00 mkunz
* -Vpd bug fixed
* -OID_SKGE_MTU added
* -pnmi support for dual net mode. Interface function and macros extended
- *
+ *
* Revision 1.80 2001/01/22 13:41:35 rassmann
* Supporting two nets on dual-port adapters.
- *
+ *
* Revision 1.79 2000/12/05 14:57:40 cgoos
* SetStruct failed before first Link Up (link mode of virtual
* port "INDETERMINATED").
- *
+ *
* Revision 1.78 2000/09/12 10:44:58 cgoos
* Fixed SK_PNMI_STORE_U32 calls with typecasted argument.
- *
+ *
* Revision 1.77 2000/09/07 08:10:19 rwahl
* - Modified algorithm for 64bit NDIS statistic counters;
* returns 64bit or 32bit value depending on passed buffer
* buffer size is zero. OID_GEN_XMIT_ERROR, OID_GEN_RCV_ERROR,
* and OID_GEN_RCV_NO_BUFFER handled as 64bit counter, too.
* - corrected OID_SKGE_RLMT_PORT_PREFERRED.
- *
+ *
* Revision 1.76 2000/08/03 15:23:39 rwahl
* - Correction for FrameTooLong counter has to be moved to OID handling
* routines (instead of statistic counter routine).
* - Fix in XMAC Reset Event handling: Only offset counter for hardware
* statistic registers are updated.
- *
+ *
* Revision 1.75 2000/08/01 16:46:05 rwahl
* - Added StatRxLongFrames counter and correction of FrameTooLong counter.
* - Added directive to control width (default = 32bit) of NDIS statistic
* counters (SK_NDIS_64BIT_CTR).
- *
+ *
* Revision 1.74 2000/07/04 11:41:53 rwahl
* - Added volition connector type.
- *
+ *
* Revision 1.73 2000/03/15 16:33:10 rwahl
* Fixed bug 10510; wrong reset of virtual port statistic counters.
- *
+ *
* Revision 1.72 1999/12/06 16:15:53 rwahl
* Fixed problem of instance range for current and factory MAC address.
- *
+ *
* Revision 1.71 1999/12/06 10:14:20 rwahl
* Fixed bug 10476; set operation for PHY_OPERATION_MODE.
- *
+ *
* Revision 1.70 1999/11/22 13:33:34 cgoos
* Changed license header to GPL.
- *
+ *
* Revision 1.69 1999/10/18 11:42:15 rwahl
* Added typecasts for checking event dependent param (debug only).
- *
+ *
* Revision 1.68 1999/10/06 09:35:59 cgoos
* Added state check to PHY_READ call (hanged if called during startup).
- *
+ *
* Revision 1.67 1999/09/22 09:53:20 rwahl
* - Read Broadcom register for updating fcs error counter (1000Base-T).
*
* Revision 1.66 1999/08/26 13:47:56 rwahl
* Added SK_DRIVER_SENDEVENT when queueing RLMT_CHANGE_THRES trap.
- *
+ *
* Revision 1.65 1999/07/26 07:49:35 cgoos
* Added two typecasts to avoid compiler warnings.
- *
+ *
* Revision 1.64 1999/05/20 09:24:12 cgoos
* Changes for 1000Base-T (sensors, Master/Slave).
*
* Revision 1.63 1999/04/13 15:11:58 mhaveman
* Moved include of rlmt.h to header skgepnmi.h because some macros
* are needed there.
- *
+ *
* Revision 1.62 1999/04/13 15:08:07 mhaveman
* Replaced again SK_RLMT_CHECK_LINK with SK_PNMI_RLMT_MODE_CHK_LINK
* to grant unified interface by only using the PNMI header file.
* SK_PNMI_RLMT_MODE_CHK_LINK is defined the same as SK_RLMT_CHECK_LINK.
- *
+ *
* Revision 1.61 1999/04/13 15:02:48 mhaveman
* Changes caused by review:
* -Changed some comments
* -Optimized PRESET check.
* -Meaning of error SK_ADDR_DUPLICATE_ADDRESS changed. Set of same
* address will now not cause this error. Removed corresponding check.
- *
+ *
* Revision 1.60 1999/03/23 10:41:23 mhaveman
* Added comments.
- *
+ *
* Revision 1.59 1999/02/19 08:01:28 mhaveman
* Fixed bug 10372 that after counter reset all ports were displayed
* as inactive.
- *
+ *
* Revision 1.58 1999/02/16 18:04:47 mhaveman
* Fixed problem of twisted OIDs SENSOR_WAR_TIME and SENSOR_ERR_TIME.
- *
+ *
* Revision 1.56 1999/01/27 12:29:11 mhaveman
* SkTimerStart was called with time value in milli seconds but needs
* micro seconds.
- *
+ *
* Revision 1.55 1999/01/25 15:00:38 mhaveman
* Added support to allow multiple ports to be active. If this feature in
* future will be used, the Management Data Base variables PORT_ACTIVE
* physical ports. A get returns the melted values of all active physical
* ports. If the port values differ a return value INDETERMINATED will
* be returned. This effects especially the CONF group.
- *
+ *
* Revision 1.54 1999/01/19 10:10:22 mhaveman
* -Fixed bug 10354: Counter values of virtual port were wrong after port
* switches
* -Added check if a switch to the same port is notified.
- *
+ *
* Revision 1.53 1999/01/07 09:25:21 mhaveman
* Forgot to initialize a variable.
- *
+ *
* Revision 1.52 1999/01/05 10:34:33 mhaveman
* Fixed little error in RlmtChangeEstimate calculation.
- *
+ *
* Revision 1.51 1999/01/05 09:59:07 mhaveman
* -Moved timer start to init level 2
* -Redesigned port switch average calculation to avoid 64bit
* arithmetic.
- *
+ *
* Revision 1.50 1998/12/10 15:13:59 mhaveman
* -Fixed: PHYS_CUR_ADDR returned wrong addresses
* -Fixed: RLMT_PORT_PREFERED and RLMT_CHANGE_THRES preset returned
* always BAD_VALUE.
* -Fixed: TRAP buffer seemed to sometimes suddenly empty
- *
+ *
* Revision 1.49 1998/12/09 16:17:07 mhaveman
* Fixed: Couldnot delete VPD keys on UNIX.
- *
+ *
* Revision 1.48 1998/12/09 14:11:10 mhaveman
* -Add: Debugmessage for XMAC_RESET supressed to minimize output.
* -Fixed: RlmtChangeThreshold will now be initialized.
* -Fixed: On VPD key creation an invalid key name could be created
* (e.g. A5)
* -Some minor changes in comments and code.
- *
+ *
* Revision 1.47 1998/12/08 16:00:31 mhaveman
* -Fixed: For RLMT_PORT_ACTIVE will now be returned a 0 if no port
* is active.
* to 0, an error should be returned by the caller.
* -Fixed: Wrong number of instances with RLMT statistic.
* -Fixed: Return now SK_LMODE_STAT_UNKNOWN if the LinkModeStatus is 0.
- *
+ *
* Revision 1.45 1998/12/03 17:17:24 mhaveman
* -Removed for VPD create action the buffer size limitation to 4 bytes.
* -Pass now physical/active physical port to ADDR for CUR_ADDR set
- *
+ *
* Revision 1.44 1998/12/03 15:14:35 mhaveman
* Another change to Vpd instance evaluation.
*
*
* Revision 1.42 1998/12/03 11:31:47 mhaveman
* Inserted cast to satisfy lint.
- *
+ *
* Revision 1.41 1998/12/03 11:28:16 mhaveman
* Removed SK_PNMI_CHECKPTR
- *
+ *
* Revision 1.40 1998/12/03 11:19:07 mhaveman
* Fixed problems
* -A set to virtual port will now be ignored. A set with broadcast
* address to any port will be ignored.
* -GetStruct function made VPD instance calculation wrong.
* -Prefered port returned -1 instead of 0.
- *
+ *
* Revision 1.39 1998/11/26 15:30:29 mhaveman
* Added sense mode to link mode.
- *
+ *
* Revision 1.38 1998/11/23 15:34:00 mhaveman
* -Fixed bug for RX counters. On an RX overflow interrupt the high
* words of all RX counters were incremented.
* -SET operations on FLOWCTRL_MODE and LINK_MODE accept now the
* value 0, which has no effect. It is usefull for multiple instance
* SETs.
- *
+ *
* Revision 1.37 1998/11/20 08:02:04 mhaveman
* -Fixed: Ports were compared with MAX_SENSORS
* -Fixed: Crash in GetTrapEntry with MEMSET macro
* -Fixed: Conversions between physical, logical port index and instance
- *
+ *
* Revision 1.36 1998/11/16 07:48:53 mhaveman
* Casted SK_DRIVER_SENDEVENT with (void) to eleminate compiler warnings
* on Solaris.
- *
+ *
* Revision 1.35 1998/11/16 07:45:34 mhaveman
* SkAddrOverride now returns value and will be checked.
*
* of needed buffer space on TOO_SHORT errors. Therefore all
* SkPnmiGet/Preset/Set functions now have a pointer to the length
* parameter, where the needed space on error is returned.
- *
+ *
* Revision 1.33 1998/11/03 13:52:46 mhaveman
* Made file lint conform.
- *
+ *
* Revision 1.32 1998/11/03 13:19:07 mhaveman
* The events SK_HWEV_SET_LMODE and SK_HWEV_SET_FLOWMODE pass now in
* Para32[0] the physical MAC index and in Para32[1] the new mode.
- *
+ *
* Revision 1.31 1998/11/03 12:30:40 gklug
* fix: compiler warning memset
*
*
* Revision 1.29 1998/11/02 11:23:54 mhaveman
* Corrected SK_ERROR_LOG to SK_ERR_LOG. Sorry.
- *
+ *
* Revision 1.28 1998/11/02 10:47:16 mhaveman
* Added syslog messages for internal errors.
- *
+ *
* Revision 1.27 1998/10/30 15:48:06 mhaveman
* Fixed problems after simulation of SK_PNMI_EVT_CHG_EST_TIMER and
* RlmtChangeThreshold calculation.
- *
+ *
* Revision 1.26 1998/10/29 15:36:55 mhaveman
* -Fixed bug in trap buffer handling.
* -OID_SKGE_DRIVER_DESCR, OID_SKGE_DRIVER_VERSION, OID_SKGE_HW_DESCR,
* -Perform a RlmtUpdate during SK_PNMI_EVT_XMAC_RESET to minimize
* RlmtUpdate calls in GetStatVal.
* -Inserted SK_PNMI_CHECKFLAGS macro increase readability.
- *
+ *
* Revision 1.25 1998/10/29 08:50:36 mhaveman
* Fixed problems after second event simulation.
- *
+ *
* Revision 1.24 1998/10/28 08:44:37 mhaveman
* -Fixed alignment problem
* -Fixed problems during event simulation
*
* Revision 1.23 1998/10/23 10:16:37 mhaveman
* Fixed bugs after buffer test simulation.
- *
+ *
* Revision 1.22 1998/10/21 13:23:52 mhaveman
* -Call syntax of SkOsGetTime() changed to SkOsGetTime(pAc).
* -Changed calculation of hundrets of seconds.
*
* Revision 1.20 1998/10/20 07:30:45 mhaveman
* Made type changes to unsigned integer where possible.
- *
+ *
* Revision 1.19 1998/10/19 10:51:30 mhaveman
* -Made Bug fixes after simulation run
* -Renamed RlmtMAC... to RlmtPort...
* -Marked workarounds with Errata comments
- *
+ *
* Revision 1.18 1998/10/14 07:50:08 mhaveman
* -For OID_SKGE_LINK_STATUS the link down detection has moved from RLMT
* to HWACCESS.
* Revision 1.16 1998/10/07 10:52:49 mhaveman
* -Inserted handling of some OID_GEN_ Ids for windows
* -Fixed problem with 803.2 statistic.
- *
+ *
* Revision 1.15 1998/10/01 09:16:29 mhaveman
* Added Debug messages for function call and UpdateFlag tracing.
- *
+ *
* Revision 1.14 1998/09/30 13:39:09 mhaveman
* -Reduced namings of 'MAC' by replacing them with 'PORT'.
* -Completed counting of OID_SKGE_RX_HW_ERROR_CTS,
* OID_SKGE_TX_HW_ERROR_CTS,
* OID_SKGE_IN_ERRORS_CTS, and OID_SKGE_OUT_ERROR_CTS.
* -SET check for RlmtMode
- *
+ *
* Revision 1.13 1998/09/28 13:13:08 mhaveman
* Hide strcmp, strlen, and strncpy behind macros SK_STRCMP, SK_STRLEN,
* and SK_STRNCPY. (Same reasons as for mem.. and MEM..)
- *
+ *
* Revision 1.12 1998/09/16 08:18:36 cgoos
* Fix: XM_INxx and XM_OUTxx called with different parameter order:
* sometimes IoC,Mac,... sometimes Mac,IoC,... Now always first variant.
* Revision 1.11 1998/09/04 17:01:45 mhaveman
* Added SyncCounter as macro and OID_SKGE_.._NO_DESCR_CTS to
* OID_SKGE_RX_NO_BUF_CTS.
- *
+ *
* Revision 1.10 1998/09/04 14:35:35 mhaveman
* Added macro counters, that are counted by driver.
- *
+ *
****************************************************************************/
unsigned int *pLen, SK_U32 Instance, SK_U32 NetIndex);
int SkPnmiGetStruct(SK_AC *pAC, SK_IOC IoC, void *pBuf,
unsigned int *pLen, SK_U32 NetIndex);
-int SkPnmiPreSetStruct(SK_AC *pAC, SK_IOC IoC, void *pBuf,
+int SkPnmiPreSetStruct(SK_AC *pAC, SK_IOC IoC, void *pBuf,
unsigned int *pLen, SK_U32 NetIndex);
-int SkPnmiSetStruct(SK_AC *pAC, SK_IOC IoC, void *pBuf,
+int SkPnmiSetStruct(SK_AC *pAC, SK_IOC IoC, void *pBuf,
unsigned int *pLen, SK_U32 NetIndex);
int SkPnmiEvent(SK_AC *pAC, SK_IOC IoC, SK_U32 Event, SK_EVPARA Param);
/*
* Overflow status register bit table and corresponding counter
* dependent on MAC type - the number relates to the size of overflow
- * mask returned by the pFnMacOverflow function
+ * mask returned by the pFnMacOverflow function
*/
PNMI_STATIC const SK_U16 StatOvrflwBit[][SK_PNMI_MAC_TYPES] = {
/* Bit0 */ { SK_PNMI_HTX, SK_PNMI_HTX_UNICAST},
#ifdef SK_PNMI_CHECK
if (SK_PNMI_MAX_IDX != SK_PNMI_CNT_NO) {
-
+
SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR049, SK_PNMI_ERR049MSG);
SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_INIT | SK_DBGCAT_FATAL,
if (SK_PNMI_MAX_IDX !=
(sizeof(StatAddr) / (sizeof(SK_PNMI_STATADDR) * SK_PNMI_MAC_TYPES))) {
-
+
SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR050, SK_PNMI_ERR050MSG);
SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_INIT | SK_DBGCAT_FATAL,
("StatAddr table size (%d) differs from "
"SK_PNMI_MAX_IDX (%d)\n",
- (sizeof(StatAddr) /
+ (sizeof(StatAddr) /
(sizeof(SK_PNMI_STATADDR) * SK_PNMI_MAC_TYPES)),
SK_PNMI_MAX_IDX));
BRK;
pAC->GIni.GIFunc.pFnMacResetCounter(pAC, IoC, PortIndex);
}
-
- /* Initialize DSP variables for Vct() to 0xff => Never written! */
+
+ /* Initialize DSP variables for Vct() to 0xff => Never written! */
for (PortIndex = 0; PortIndex < PortMax; PortIndex ++) {
pPrt = &pAC->GIni.GP[PortIndex];
pPrt->PCableLen =0xff;
pVctBackupData = &pAC->Pnmi.VctBackup[PortIndex];
pVctBackupData->PCableLen = 0xff;
}
-
+
/*
* Get pci bus speed
*/
default:
pAC->Pnmi.Connector = 1;
break;
- }
+ }
break;
-
+
case SK_INIT_RUN:
/*
* Start timer for RLMT change counter
* SK_PNMI_ERR_GENERAL A general severe internal error occured
* SK_PNMI_ERR_TOO_SHORT The passed buffer is too short to take
* the data.
- * SK_PNMI_ERR_UNKNOWN_NET The requested NetIndex doesn't exist
+ * SK_PNMI_ERR_UNKNOWN_NET The requested NetIndex doesn't exist
*/
int SkPnmiGetStruct(
SK_AC *pAC, /* Pointer to adapter context */
*/
if (Ret == SK_PNMI_ERR_UNKNOWN_INST) {
- break;
+ break;
}
if (Ret != SK_PNMI_ERR_OK) {
("PNMI: SkPnmiPreSetStruct: Called, BufLen=%d, NetIndex=%d\n",
*pLen, NetIndex));
- return (PnmiStruct(pAC, IoC, SK_PNMI_PRESET, (char *)pBuf,
- pLen, NetIndex));
+ return (PnmiStruct(pAC, IoC, SK_PNMI_PRESET, (char *)pBuf,
+ pLen, NetIndex));
}
/*****************************************************************************
("PNMI: SkPnmiSetStruct: Called, BufLen=%d, NetIndex=%d\n",
*pLen, NetIndex));
- return (PnmiStruct(pAC, IoC, SK_PNMI_SET, (char *)pBuf,
- pLen, NetIndex));
+ return (PnmiStruct(pAC, IoC, SK_PNMI_SET, (char *)pBuf,
+ pLen, NetIndex));
}
/*****************************************************************************
SK_PNMI_CHECKFLAGS("SkPnmiEvent: On call");
MacType = pAC->GIni.GIMacType;
-
+
switch (Event) {
case SK_PNMI_EVT_SIRQ_OVERFLOW:
(OverflowStatus == 0)) {
SK_PNMI_CHECKFLAGS("SkPnmiEvent: On return");
- return (0);
+ return (0);
}
/*
case SK_PNMI_HRX_OCTETLOW:
case SK_PNMI_HRX_IRLENGTH:
case SK_PNMI_HRX_RESERVED:
-
+
/*
* the following counters aren't be handled (id > 63)
*/
(unsigned int)Param.Para64);
(void)SK_DRIVER_SENDEVENT(pAC, IoC);
break;
-
+
case SK_PNMI_EVT_SEN_ERR_UPP:
#ifdef DEBUG
if ((unsigned int)Param.Para64 >= (unsigned int)pAC->I2c.MaxSens) {
* Set all counters and timestamps to zero
*/
ResetCounter(pAC, IoC, NetIndex); /* the according NetIndex is required
- as a Parameter of the Event */
+ as a Parameter of the Event */
break;
case SK_PNMI_EVT_XMAC_RESET:
/*
* To grant continuous counter values store the current
* XMAC statistic values to the entries 1..n of the
- * CounterOffset array. XMAC Errata #2
+ * CounterOffset array. XMAC Errata #2
*/
#ifdef DEBUG
if ((unsigned int)Param.Para64 >= SK_MAX_MACS) {
SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_RLMT_PORT_UP parameter"
- " wrong, PhysPortIndex=%d\n", PhysPortIndex));
+ " wrong, PhysPortIndex=%d\n", PhysPortIndex));
return (0);
}
/* Add incremental difference to offset (#10620)*/
(void)pAC->GIni.GIFunc.pFnMacStatistic(pAC, IoC, PhysPortIndex,
XM_RXE_SHT_ERR, &Val32);
-
+
Value = (((SK_U64)pAC->Pnmi.Port[PhysPortIndex].
CounterHigh[SK_PNMI_HRX_SHORTS] << 32) | (SK_U64)Val32);
pAC->Pnmi.Port[PhysPortIndex].CounterOffset[SK_PNMI_HRX_SHORTS] +=
Value - pAC->Pnmi.Port[PhysPortIndex].RxShortZeroMark;
}
-
+
/* Tell VctStatus() that a link was up meanwhile. */
- pAC->Pnmi.VctStatus[PhysPortIndex] |= SK_PNMI_VCT_LINK;
+ pAC->Pnmi.VctStatus[PhysPortIndex] |= SK_PNMI_VCT_LINK;
break;
case SK_PNMI_EVT_RLMT_PORT_DOWN:
SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_CTRL,
("PNMI: ERR: SkPnmiEvent: SK_PNMI_EVT_RLMT_PORT_DOWN parameter"
- " wrong, PhysPortIndex=%d\n", PhysPortIndex));
+ " wrong, PhysPortIndex=%d\n", PhysPortIndex));
return (0);
}
*/
QueueRlmtPortTrap(pAC, OID_SKGE_TRAP_RLMT_PORT_DOWN, PhysPortIndex);
(void)SK_DRIVER_SENDEVENT(pAC, IoC);
-
+
/* Bugfix #10620 - get zero level for incremental difference */
if ((pAC->GIni.GIMacType == SK_MAC_XMAC)) {
(void)pAC->GIni.GIFunc.pFnMacStatistic(pAC, IoC, PhysPortIndex,
XM_RXE_SHT_ERR, &Val32);
- pAC->Pnmi.Port[PhysPortIndex].RxShortZeroMark =
+ pAC->Pnmi.Port[PhysPortIndex].RxShortZeroMark =
(((SK_U64)pAC->Pnmi.Port[PhysPortIndex].
CounterHigh[SK_PNMI_HRX_SHORTS] << 32) | (SK_U64)Val32);
}
* Param.Para32[1] is reserved, contains -1.
*/
/*
- * Check number of nets
+ * Check number of nets
*/
MaxNetNumber = pAC->GIni.GIMacsFound;
if (((unsigned int)Param.Para32[0] < 1)
return (SK_PNMI_ERR_UNKNOWN_NET);
}
- if ((unsigned int)Param.Para32[0] == 1) { /* single net mode */
- pAC->Pnmi.DualNetActiveFlag = SK_FALSE;
- }
- else { /* dual net mode */
- pAC->Pnmi.DualNetActiveFlag = SK_TRUE;
- }
- break;
+ if ((unsigned int)Param.Para32[0] == 1) { /* single net mode */
+ pAC->Pnmi.DualNetActiveFlag = SK_FALSE;
+ }
+ else { /* dual net mode */
+ pAC->Pnmi.DualNetActiveFlag = SK_TRUE;
+ }
+ break;
case SK_PNMI_EVT_VCT_RESET:
PhysPortIndex = Param.Para32[0];
pPrt = &pAC->GIni.GP[PhysPortIndex];
pVctBackupData = &pAC->Pnmi.VctBackup[PhysPortIndex];
-
+
if (pAC->Pnmi.VctStatus[PhysPortIndex] & SK_PNMI_VCT_PENDING) {
RetCode = SkGmCableDiagStatus(pAC, IoC, PhysPortIndex, SK_FALSE);
if (RetCode == 2) {
pAC->Pnmi.VctStatus[PhysPortIndex] &= ~SK_PNMI_VCT_PENDING;
pAC->Pnmi.VctStatus[PhysPortIndex] |=
(SK_PNMI_VCT_NEW_VCT_DATA | SK_PNMI_VCT_TEST_DONE);
-
+
/* Copy results for later use to PNMI struct. */
for (i = 0; i < 4; i++) {
if (pPrt->PMdiPairLen[i] > 35) {
pVctBackupData->PMdiPairLen[i] = CableLength;
pVctBackupData->PMdiPairSts[i] = pPrt->PMdiPairSts[i];
}
-
+
Param.Para32[0] = PhysPortIndex;
Param.Para32[1] = -1;
SkEventQueue(pAC, SKGE_DRV, SK_DRV_PORT_RESET, Param);
SkEventDispatcher(pAC, IoC);
}
-
+
break;
default:
* Returns:
* SK_PNMI_ERR_XXX. For details have a look to the description of the
* calling functions.
- * SK_PNMI_ERR_UNKNOWN_NET The requested NetIndex doesn't exist
+ * SK_PNMI_ERR_UNKNOWN_NET The requested NetIndex doesn't exist
*/
PNMI_STATIC int PnmiVar(
SK_AC *pAC, /* Pointer to adapter context */
*pLen = 0;
return (SK_PNMI_ERR_UNKNOWN_OID);
}
-
- /*
- * Check NetIndex
+
+ /*
+ * Check NetIndex
*/
if (NetIndex >= pAC->Rlmt.NumNets) {
return (SK_PNMI_ERR_UNKNOWN_NET);
*
* Returns:
* SK_PNMI_ERR_XXX. The codes are described in the calling functions.
- * SK_PNMI_ERR_UNKNOWN_NET The requested NetIndex doesn't exist
+ * SK_PNMI_ERR_UNKNOWN_NET The requested NetIndex doesn't exist
*/
PNMI_STATIC int PnmiStruct(
SK_AC *pAC, /* Pointer to adapter context */
*pLen = SK_PNMI_STRUCT_SIZE;
return (SK_PNMI_ERR_TOO_SHORT);
}
-
- /*
- * Check NetIndex
+
+ /*
+ * Check NetIndex
*/
if (NetIndex >= pAC->Rlmt.NumNets) {
return (SK_PNMI_ERR_UNKNOWN_NET);
}
-
+
SK_PNMI_CHECKFLAGS("PnmiStruct: On call");
/*
*pLen = 0;
return (SK_PNMI_ERR_GENERAL);
}
-
+
Val32 = (SK_U32)pVpdStatus->vpd_free_rw;
SK_PNMI_STORE_U32(pBuf, Val32);
*pLen = sizeof(SK_U32);
*pLen = 0;
return (SK_PNMI_ERR_GENERAL);
}
- }
+ }
else {
/* The only OID which can be set is VPD_ACTION */
if (Id != OID_SKGE_VPD_ACTION) {
*pLen = 0;
return (SK_PNMI_ERR_READ_ONLY);
}
-
+
MacType = pAC->GIni.GIMacType;
-
+
/*
* Check length for the various supported OIDs
*/
GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_TOO_LONG, NetIndex) +
GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_FCS, NetIndex) +
GetStatVal(pAC, IoC, 0, SK_PNMI_HRX_CEXT, NetIndex);
- break;
+ break;
case OID_SKGE_TX_HW_ERROR_CTS:
case OID_SKGE_OUT_ERROR_CTS:
else {
Val64 = pAC->Pnmi.BufPort[0].TxSwQueueLen +
pAC->Pnmi.BufPort[1].TxSwQueueLen;
- }
+ }
}
else {
/* Dual net mode */
else {
Val64 = pAC->Pnmi.Port[0].TxSwQueueLen +
pAC->Pnmi.Port[1].TxSwQueueLen;
- }
+ }
}
SK_PNMI_STORE_U64(pBuf, Val64);
*pLen = sizeof(SK_U64);
}
/* Single net mode */
else {
- Val64 = Val64RxHwErrs +
+ Val64 = Val64RxHwErrs +
pAC->Pnmi.BufPort[0].RxNoBufCts +
pAC->Pnmi.BufPort[1].RxNoBufCts;
}
}
/* Single net mode */
else {
- Val64 = Val64RxHwErrs +
+ Val64 = Val64RxHwErrs +
pAC->Pnmi.Port[0].RxNoBufCts +
pAC->Pnmi.Port[1].RxNoBufCts;
}
}
/* Single net mode */
else {
- Val64 = Val64TxHwErrs +
+ Val64 = Val64TxHwErrs +
pAC->Pnmi.BufPort[0].TxNoBufCts +
pAC->Pnmi.BufPort[1].TxNoBufCts;
}
}
/* Single net mode */
else {
- Val64 = Val64TxHwErrs +
+ Val64 = Val64TxHwErrs +
pAC->Pnmi.Port[0].TxNoBufCts +
pAC->Pnmi.Port[1].TxNoBufCts;
}
}
break;
- case OID_SKGE_MTU:
+ case OID_SKGE_MTU:
if (*pLen < sizeof(SK_U32)) {
*pLen = sizeof(SK_U32);
case OID_SKGE_LINK_CAP:
if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
if (LogPortIndex == 0) {
-
+
/* Get value for virtual port */
VirtualConf(pAC, IoC, Id, pBuf +
Offset);
Offset += sizeof(char);
}
else { /* DualNetMode */
-
+
*(pBuf + Offset) = pAC->GIni.GP[NetIndex].PLinkCap;
Offset += sizeof(char);
}
case OID_SKGE_LINK_MODE:
if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
if (LogPortIndex == 0) {
-
+
/* Get value for virtual port */
VirtualConf(pAC, IoC, Id, pBuf +
Offset);
}
Offset += sizeof(char);
}
- else { /* DualNetMode */
-
+ else { /* DualNetMode */
+
*(pBuf + Offset) = pAC->GIni.GP[NetIndex].PLinkModeConf;
Offset += sizeof(char);
}
case OID_SKGE_LINK_MODE_STATUS:
if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
if (LogPortIndex == 0) {
-
+
/* Get value for virtual port */
VirtualConf(pAC, IoC, Id, pBuf +
Offset);
case OID_SKGE_LINK_STATUS:
if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
if (LogPortIndex == 0) {
-
+
/* Get value for virtual port */
VirtualConf(pAC, IoC, Id, pBuf +
Offset);
/* Get value for physical ports */
PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
pAC, LogPortIndex);
-
+
*(pBuf + Offset) =
CalculateLinkStatus(pAC,
IoC, PhysPortIndex);
case OID_SKGE_FLOWCTRL_CAP:
if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
if (LogPortIndex == 0) {
-
+
/* Get value for virtual port */
VirtualConf(pAC, IoC, Id, pBuf +
Offset);
/* Get value for physical ports */
PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
pAC, LogPortIndex);
-
+
*(pBuf + Offset) = pAC->GIni.GP[
PhysPortIndex].PFlowCtrlCap;
}
Offset += sizeof(char);
}
else { /* DualNetMode */
-
+
*(pBuf + Offset) = pAC->GIni.GP[NetIndex].PFlowCtrlCap;
Offset += sizeof(char);
}
case OID_SKGE_FLOWCTRL_MODE:
if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
if (LogPortIndex == 0) {
-
+
/* Get value for virtual port */
VirtualConf(pAC, IoC, Id, pBuf +
Offset);
/* Get value for physical port */
PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
pAC, LogPortIndex);
-
+
*(pBuf + Offset) = pAC->GIni.GP[
PhysPortIndex].PFlowCtrlMode;
}
case OID_SKGE_FLOWCTRL_STATUS:
if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
if (LogPortIndex == 0) {
-
+
/* Get value for virtual port */
VirtualConf(pAC, IoC, Id, pBuf +
Offset);
/* Get value for physical port */
PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
pAC, LogPortIndex);
-
+
*(pBuf + Offset) = pAC->GIni.GP[
PhysPortIndex].PFlowCtrlStatus;
}
case OID_SKGE_PHY_OPERATION_CAP:
if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
if (LogPortIndex == 0) {
-
+
/* Get value for virtual port */
VirtualConf(pAC, IoC, Id, pBuf +
Offset);
/* Get value for physical ports */
PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
pAC, LogPortIndex);
-
+
*(pBuf + Offset) = pAC->GIni.GP[
PhysPortIndex].PMSCap;
}
Offset += sizeof(char);
}
else { /* DualNetMode */
-
+
*(pBuf + Offset) = pAC->GIni.GP[NetIndex].PMSCap;
Offset += sizeof(char);
}
Offset += sizeof(char);
}
else { /* DualNetMode */
-
+
*(pBuf + Offset) = pAC->GIni.GP[NetIndex].PMSMode;
Offset += sizeof(char);
}
/* Get value for physical port */
PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
pAC, LogPortIndex);
-
+
*(pBuf + Offset) = pAC->GIni.GP[
PhysPortIndex].PMSStatus;
}
Offset += sizeof(char);
}
else {
-
+
*(pBuf + Offset) = pAC->GIni.GP[NetIndex].PMSStatus;
Offset += sizeof(char);
}
case OID_SKGE_SPEED_CAP:
if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
if (LogPortIndex == 0) {
-
+
/* Get value for virtual port */
VirtualConf(pAC, IoC, Id, pBuf +
Offset);
/* Get value for physical ports */
PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
pAC, LogPortIndex);
-
+
*(pBuf + Offset) = pAC->GIni.GP[
PhysPortIndex].PLinkSpeedCap;
}
Offset += sizeof(char);
}
else { /* DualNetMode */
-
+
*(pBuf + Offset) = pAC->GIni.GP[NetIndex].PLinkSpeedCap;
Offset += sizeof(char);
}
case OID_SKGE_SPEED_MODE:
if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
if (LogPortIndex == 0) {
-
+
/* Get value for virtual port */
VirtualConf(pAC, IoC, Id, pBuf + Offset);
}
/* Get value for physical port */
PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
pAC, LogPortIndex);
-
+
*(pBuf + Offset) = pAC->GIni.GP[
PhysPortIndex].PLinkSpeed;
}
case OID_SKGE_SPEED_STATUS:
if (!pAC->Pnmi.DualNetActiveFlag) { /* SingleNetMode */
if (LogPortIndex == 0) {
-
+
/* Get value for virtual port */
VirtualConf(pAC, IoC, Id, pBuf + Offset);
}
/* Get value for physical port */
PhysPortIndex = SK_PNMI_PORT_LOG2PHYS(
pAC, LogPortIndex);
-
+
*(pBuf + Offset) = pAC->GIni.GP[
PhysPortIndex].PLinkSpeedUsed;
}
Offset += sizeof(char);
}
break;
-
+
case OID_SKGE_MTU:
Val32 = SK_DRIVER_GET_MTU(pAC, IoC, NetIndex);
SK_PNMI_STORE_U32(pBuf + Offset, Val32);
break;
default:
- SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_ERR,
- ("MacPrivateConf: Unknown OID should be handled before set"));
+ SK_DBG_MSG(pAC, SK_DBGMOD_PNMI, SK_DBGCAT_ERR,
+ ("MacPrivateConf: Unknown OID should be handled before set"));
*pLen = 0;
return (SK_PNMI_ERR_GENERAL);
unsigned int Offset;
unsigned int Entries;
-
+
/*
* Calculate instance if wished.
*/
*pBuf = SK_FLOW_STAT_INDETERMINATED;
}
break;
-
+
case OID_SKGE_PHY_OPERATION_CAP:
/* Check if it is the first active port */
if (*pBuf == 0) {
*pBuf = SK_MS_STAT_INDETERMINATED;
}
break;
-
+
case OID_SKGE_SPEED_MODE:
/* Check if it is the first active port */
if (*pBuf == 0) {
*pBuf = SK_LSPEED_INDETERMINATED;
}
break;
-
+
case OID_SKGE_SPEED_STATUS:
/* Check if it is the first active port */
if (*pBuf == 0) {
case OID_SKGE_FLOWCTRL_STATUS:
*pBuf = SK_FLOW_STAT_INDETERMINATED;
break;
-
+
case OID_SKGE_PHY_OPERATION_CAP:
*pBuf = SK_MS_CAP_INDETERMINATED;
break;
if (Result < SK_LMODE_STAT_HALF) {
Result = SK_LMODE_STAT_UNKNOWN;
- }
+ }
else if (pAC->GIni.GP[PhysPortIndex].PLinkMode >= SK_LMODE_AUTOHALF) {
/*
* Description:
* The XMAC holds its statistic internally. To obtain the current
* values we send a command so that the statistic data will
- * be written to apredefined memory area on the adapter.
+ * be written to apredefined memory area on the adapter.
*
* Returns:
* SK_PNMI_ERR_OK Task successfully performed.
for (MacIndex = FirstMac; MacIndex <= LastMac; MacIndex ++) {
/*
- * 2002-09-13 pweber: Freeze the current sw counters.
- * (That should be done as close as
- * possible to the update of the
+ * 2002-09-13 pweber: Freeze the current sw counters.
+ * (That should be done as close as
+ * possible to the update of the
* hw counters)
*/
if (pAC->GIni.GIMacType == SK_MAC_XMAC) {
pAC->Pnmi.BufPort[MacIndex] = pAC->Pnmi.Port[MacIndex];
}
-
+
/* 2002-09-13 pweber: Update the hw counter */
if (pAC->GIni.GIFunc.pFnMacUpdateStats(pAC, IoC, MacIndex) != 0) {
SK_U32 HighVal = 0;
SK_U16 Word;
int MacType;
-
+
SK_PNMI_PORT *pPnmiPrt;
SK_GEMACFUNC *pFnMac;
-
+
MacType = pAC->GIni.GIMacType;
-
+
/* 2002-09-17 pweber: For XMAC, use the frozen sw counters (BufPort) */
if (pAC->GIni.GIMacType == SK_MAC_XMAC) {
pPnmiPrt = &pAC->Pnmi.BufPort[PhysPortIndex];
else {
pPnmiPrt = &pAC->Pnmi.Port[PhysPortIndex];
}
-
+
pFnMac = &pAC->GIni.GIFunc;
switch (StatIndex) {
case SK_PNMI_HRX:
/* Not supported by GMAC */
if (MacType == SK_MAC_GMAC) {
- return (Val);
+ return (Val);
}
-
+
(void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
StatAddr[StatIndex][MacType].Reg,
&LowVal);
if (MacType == SK_MAC_GMAC) {
Val = GetPhysStatVal(pAC, IoC, PhysPortIndex, SK_PNMI_HTX_PMACC);
- return (Val);
+ return (Val);
}
(void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
break;
-
case SK_PNMI_HTX_DEFFERAL:
/* Not supported by GMAC */
if (MacType == SK_MAC_GMAC) {
- return (Val);
+ return (Val);
}
-
+
/*
* XMAC counts frames with deferred transmission
* even in full-duplex mode.
&HighVal);
(void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
StatAddr[StatIndex + 1][MacType].Reg,
- &LowVal);
+ &LowVal);
break;
case SK_PNMI_HTX_OCTETLOW:
case SK_PNMI_HRX_LONGFRAMES:
/* For XMAC the SW counter is managed by PNMI */
if (MacType == SK_MAC_XMAC) {
- return (pPnmiPrt->StatRxLongFrameCts);
+ return (pPnmiPrt->StatRxLongFrameCts);
}
-
+
(void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
StatAddr[StatIndex][MacType].Reg,
&LowVal);
HighVal = pPnmiPrt->CounterHigh[StatIndex];
break;
-
+
case SK_PNMI_HRX_TOO_LONG:
(void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
StatAddr[StatIndex][MacType].Reg,
&LowVal);
HighVal = pPnmiPrt->CounterHigh[StatIndex];
-
+
Val = (((SK_U64)HighVal << 32) | (SK_U64)LowVal);
switch (MacType) {
LowVal = (SK_U32)Val;
HighVal = (SK_U32)(Val >> 32);
break;
-
+
case SK_PNMI_HRX_SHORTS:
/* Not supported by GMAC */
if (MacType == SK_MAC_GMAC) {
/* GM_RXE_FRAG?? */
- return (Val);
+ return (Val);
}
-
+
/*
* XMAC counts short frame errors even if link down (#10620)
*
/* Not supported by GMAC */
if (MacType == SK_MAC_GMAC) {
/* GM_RXE_FRAG?? */
- return (Val);
+ return (Val);
}
(void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
case SK_PNMI_HRX_PMACC_ERR:
/* For GMAC the SW counter is managed by PNMI */
if (MacType == SK_MAC_GMAC) {
- return (pPnmiPrt->StatRxPMaccErr);
+ return (pPnmiPrt->StatRxPMaccErr);
}
-
+
(void)pFnMac->pFnMacStatistic(pAC, IoC, PhysPortIndex,
StatAddr[StatIndex][MacType].Reg,
&LowVal);
break;
case SK_PNMI_HRX_FCS:
- /*
- * Broadcom filters fcs errors and counts it in
+ /*
+ * Broadcom filters fcs errors and counts it in
* Receive Error Counter register
*/
if (pAC->GIni.GP[PhysPortIndex].PhyType == SK_PHY_BCOM) {
PHY_READ(IoC, &pAC->GIni.GP[PhysPortIndex],
PhysPortIndex, PHY_BCOM_RE_CTR,
&Word);
-
+
LowVal = Word;
}
HighVal = pPnmiPrt->CounterHigh[StatIndex];
}
}
- /*
+ /*
* Insert new entry as first entry. Newest entries are
* stored at the beginning of the queue.
*/
Val32 = (SK_U32)SensorIndex;
SK_PNMI_STORE_U32(pBuf + Offset + 5, Val32);
Offset += 9;
-
+
Val32 = (SK_U32)OID_SKGE_SENSOR_DESCR;
SK_PNMI_STORE_U32(pBuf + Offset, Val32);
*(pBuf + Offset + 4) = (char)DescrLen;
unsigned int TableIndex, /* Index to the Id table */
SK_U32 NetIndex) /* NetIndex (0..n), in single net mode allways zero */
{
-
+
SK_U32 RetCode = SK_PNMI_ERR_GENERAL;
/*
case OID_PNP_ADD_WAKE_UP_PATTERN:
case OID_PNP_REMOVE_WAKE_UP_PATTERN:
break;
-
+
default:
SK_ERR_LOG(pAC, SK_ERRCL_SW, SK_PNMI_ERR040,
SK_PNMI_ERR040MSG);
case OID_PNP_QUERY_POWER:
/* The Windows DDK describes: An OID_PNP_QUERY_POWER requests
- the miniport to indicate whether it can transition its NIC
- to the low-power state.
+ the miniport to indicate whether it can transition its NIC
+ to the low-power state.
A miniport driver must always return NDIS_STATUS_SUCCESS
to a query of OID_PNP_QUERY_POWER. */
RetCode = SK_PNMI_ERR_OK;
case OID_PNP_SET_POWER:
case OID_PNP_ADD_WAKE_UP_PATTERN:
case OID_PNP_REMOVE_WAKE_UP_PATTERN:
- *pLen = 0;
+ *pLen = 0;
RetCode = SK_PNMI_ERR_OK;
break;
break;
}
- return (RetCode);
+ return (RetCode);
}
-
+
/*
* From here SET or PRESET action. Check if the passed
* buffer length is plausible.
if (*pLen < sizeof(SK_PM_PACKET_PATTERN)) {
*pLen = 0;
- return (SK_PNMI_ERR_BAD_VALUE);
+ return (SK_PNMI_ERR_BAD_VALUE);
}
break;
/*
* Perform preset or set
*/
-
+
/* POWER module does not support PRESET action */
if (Action == SK_PNMI_PRESET) {
- return (SK_PNMI_ERR_OK);
+ return (SK_PNMI_ERR_OK);
}
switch (Id) {
case OID_PNP_SET_POWER:
- RetCode = SkPowerSetPower(pAC, IoC, pBuf, pLen);
+ RetCode = SkPowerSetPower(pAC, IoC, pBuf, pLen);
break;
case OID_PNP_ADD_WAKE_UP_PATTERN:
- RetCode = SkPowerAddWakeUpPattern(pAC, IoC, pBuf, pLen);
+ RetCode = SkPowerAddWakeUpPattern(pAC, IoC, pBuf, pLen);
break;
-
+
case OID_PNP_REMOVE_WAKE_UP_PATTERN:
- RetCode = SkPowerRemoveWakeUpPattern(pAC, IoC, pBuf, pLen);
+ RetCode = SkPowerRemoveWakeUpPattern(pAC, IoC, pBuf, pLen);
break;
-
+
case OID_PNP_ENABLE_WAKE_UP:
RetCode = SkPowerSetEnableWakeUp(pAC, IoC, pBuf, pLen);
break;
-
+
default:
RetCode = SK_PNMI_ERR_GENERAL;
}
-
+
return (RetCode);
}
#endif /* SK_POWER_MGMT */
int i;
SK_EVPARA Para;
SK_U32 CableLength;
-
+
/*
* Calculate the port indexes from the instance.
*/
PhysPortMax = pAC->GIni.GIMacsFound;
LogPortMax = SK_PNMI_PORT_PHYS2LOG(PhysPortMax);
-
+
/* Dual net mode? */
if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
LogPortMax--;
}
-
+
if ((Instance != (SK_U32) (-1))) {
/* Check instance range. */
if ((Instance < 2) || (Instance > LogPortMax)) {
*pLen = 0;
return (SK_PNMI_ERR_UNKNOWN_INST);
}
-
+
if (pAC->Pnmi.DualNetActiveFlag == SK_TRUE) {
PhysPortIndex = NetIndex;
}
PhysPortIndex = 0;
Limit = PhysPortMax;
}
-
+
pPrt = &pAC->GIni.GP[PhysPortIndex];
if (pPrt->PHWLinkUp) {
Link = SK_TRUE;
else {
Link = SK_FALSE;
}
-
+
/*
* Check MAC type.
*/
*pLen = 0;
return (SK_PNMI_ERR_GENERAL);
}
-
+
/* Initialize backup data pointer. */
pVctBackupData = &pAC->Pnmi.VctBackup[PhysPortIndex];
-
+
/*
* Check action type.
*/
* Check length.
*/
switch (Id) {
-
+
case OID_SKGE_VCT_GET:
if (*pLen < (Limit - PhysPortIndex) * sizeof(SK_PNMI_VCT)) {
*pLen = (Limit - PhysPortIndex) * sizeof(SK_PNMI_VCT);
return (SK_PNMI_ERR_TOO_SHORT);
}
break;
-
+
case OID_SKGE_VCT_STATUS:
if (*pLen < (Limit - PhysPortIndex) * sizeof(SK_U8)) {
*pLen = (Limit - PhysPortIndex) * sizeof(SK_U8);
return (SK_PNMI_ERR_TOO_SHORT);
}
break;
-
+
default:
*pLen = 0;
return (SK_PNMI_ERR_GENERAL);
- }
-
+ }
+
/*
* Get value.
*/
Offset = 0;
for (; PhysPortIndex < Limit; PhysPortIndex++) {
switch (Id) {
-
- case OID_SKGE_VCT_GET:
+
+ case OID_SKGE_VCT_GET:
if ((Link == SK_FALSE) &&
(pAC->Pnmi.VctStatus[PhysPortIndex] & SK_PNMI_VCT_PENDING)) {
RetCode = SkGmCableDiagStatus(pAC, IoC, PhysPortIndex, SK_FALSE);
pAC->Pnmi.VctStatus[PhysPortIndex] &= ~SK_PNMI_VCT_PENDING;
pAC->Pnmi.VctStatus[PhysPortIndex] |=
(SK_PNMI_VCT_NEW_VCT_DATA | SK_PNMI_VCT_TEST_DONE);
-
+
/* Copy results for later use to PNMI struct. */
for (i = 0; i < 4; i++) {
if (pPrt->PMdiPairSts[i] == SK_PNMI_VCT_NORMAL_CABLE) {
; /* VCT test is running. */
}
}
-
+
/* Get all results. */
CheckVctStatus(pAC, IoC, pBuf, Offset, PhysPortIndex);
Offset += sizeof(SK_U8);
*(pBuf + Offset) = pVctBackupData->PMdiPairSts[i];
Offset += sizeof(SK_U8);
}
-
+
RetCode = SK_PNMI_ERR_OK;
break;
-
+
case OID_SKGE_VCT_STATUS:
CheckVctStatus(pAC, IoC, pBuf, Offset, PhysPortIndex);
Offset += sizeof(SK_U8);
RetCode = SK_PNMI_ERR_OK;
break;
-
+
default:
*pLen = 0;
return (SK_PNMI_ERR_GENERAL);
} /* for */
*pLen = Offset;
return (RetCode);
-
+
} /* if SK_PNMI_GET */
-
+
/*
* From here SET or PRESET action. Check if the passed
* buffer length is plausible.
*/
-
+
/*
* Check length.
*/
return (SK_PNMI_ERR_TOO_SHORT);
}
break;
-
+
default:
*pLen = 0;
return (SK_PNMI_ERR_GENERAL);
}
-
+
/*
* Perform preset or set.
*/
-
+
/* VCT does not support PRESET action. */
if (Action == SK_PNMI_PRESET) {
return (SK_PNMI_ERR_OK);
}
-
+
Offset = 0;
for (; PhysPortIndex < Limit; PhysPortIndex++) {
switch (Id) {
case OID_SKGE_VCT_SET: /* Start VCT test. */
if (Link == SK_FALSE) {
SkGeStopPort(pAC, IoC, PhysPortIndex, SK_STOP_ALL, SK_SOFT_RST);
-
+
RetCode = SkGmCableDiagStatus(pAC, IoC, PhysPortIndex, SK_TRUE);
if (RetCode == 0) { /* RetCode: 0 => Start! */
pAC->Pnmi.VctStatus[PhysPortIndex] |= SK_PNMI_VCT_PENDING;
pAC->Pnmi.VctStatus[PhysPortIndex] &= ~SK_PNMI_VCT_NEW_VCT_DATA;
pAC->Pnmi.VctStatus[PhysPortIndex] &= ~SK_PNMI_VCT_LINK;
-
+
/*
* Start VCT timer counter.
*/
}
Offset += sizeof(SK_U32);
break;
-
+
default:
*pLen = 0;
return (SK_PNMI_ERR_GENERAL);
SK_PNMI_VCT *pVctData;
SK_U32 RetCode;
SK_U8 LinkSpeedUsed;
-
+
pPrt = &pAC->GIni.GP[PhysPortIndex];
-
+
pVctData = (SK_PNMI_VCT *) (pBuf + Offset);
pVctData->VctStatus = SK_PNMI_VCT_NONE;
-
+
if (!pPrt->PHWLinkUp) {
-
+
/* Was a VCT test ever made before? */
if (pAC->Pnmi.VctStatus[PhysPortIndex] & SK_PNMI_VCT_TEST_DONE) {
if ((pAC->Pnmi.VctStatus[PhysPortIndex] & SK_PNMI_VCT_LINK)) {
pVctData->VctStatus |= SK_PNMI_VCT_NEW_VCT_DATA;
}
}
-
+
/* Check VCT test status. */
RetCode = SkGmCableDiagStatus(pAC,IoC, PhysPortIndex, SK_FALSE);
if (RetCode == 2) { /* VCT test is running. */
pVctData->VctStatus |= SK_PNMI_VCT_NEW_VCT_DATA;
}
}
-
+
if (pPrt->PCableLen != 0xff) { /* Old DSP value. */
pVctData->VctStatus |= SK_PNMI_VCT_OLD_DSP_DATA;
}
}
else {
-
+
/* Was a VCT test ever made before? */
if (pAC->Pnmi.VctStatus[PhysPortIndex] & SK_PNMI_VCT_TEST_DONE) {
pVctData->VctStatus &= ~SK_PNMI_VCT_NEW_VCT_DATA;
pVctData->VctStatus |= SK_PNMI_VCT_OLD_VCT_DATA;
}
-
+
/* DSP only valid in 100/1000 modes. */
LinkSpeedUsed = pAC->GIni.GP[PhysPortIndex].PLinkSpeedUsed;
- if (LinkSpeedUsed != SK_LSPEED_STAT_10MBPS) {
+ if (LinkSpeedUsed != SK_LSPEED_STAT_10MBPS) {
pVctData->VctStatus |= SK_PNMI_VCT_NEW_DSP_DATA;
}
}
* Fixed setting of PLinkSpeedUsed in SkHWLinkUp() when
* auto-negotiation is disabled.
* Editorial changes.
- *
+ *
* Revision 1.82 2003/01/29 13:34:33 rschmidt
* Added some typecasts to avoid compiler warnings.
- *
+ *
* Revision 1.81 2002/12/05 10:49:51 rschmidt
* Fixed missing Link Down Event for fiber (Bug Id #10768)
* Added reading of cable length when link is up
* Removed testing of unused error bits in PHY ISR
* Editorial changes.
- *
+ *
* Revision 1.80 2002/11/12 17:15:21 rschmidt
* Replaced SkPnmiGetVar() by ...MacStatistic() in SkMacParity().
* Editorial changes.
- *
+ *
* Revision 1.79 2002/10/14 15:14:51 rschmidt
* Changed clearing of IS_M1_PAR_ERR (MAC 1 Parity Error) in
* SkMacParity() depending on GIChipRev (HW-Bug #8).
* Added error messages for GPHY Auto-Negotiation Error and
* FIFO Overflow/Underrun in SkPhyIsrGmac().
* Editorial changes.
- *
+ *
* Revision 1.78 2002/10/10 15:54:29 mkarl
* changes for PLinkSpeedUsed
- *
+ *
* Revision 1.77 2002/09/12 08:58:51 rwahl
* Retrieve counters needed for XMAC errata workarounds directly because
* PNMI returns corrected counter values (e.g. #10620).
- *
+ *
* Revision 1.76 2002/08/16 15:21:54 rschmidt
* Replaced all if(GIChipId == CHIP_ID_GENESIS) with new entry GIGenesis.
* Replaced wrong 1st para pAC with IoC in SK_IN/OUT macros.
* Editorial changes.
- *
+ *
* Revision 1.75 2002/08/12 13:50:47 rschmidt
* Changed clearing of IS_M1_PAR_ERR (MAC 1 Parity Error) in
* SkMacParity() by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE (HW-Bug #8).
* Corrected handling of Link Up and Auto-Negotiation Over for GPHY.
* in SkGePortCheckUpGmac().
* Editorial changes.
- *
+ *
* Revision 1.74 2002/08/08 16:17:04 rschmidt
* Added PhyType check for SK_HWEV_SET_ROLE event (copper only)
* Changed Link Up check reading PHY Specific Status (YUKON)
* Editorial changes
- *
+ *
* Revision 1.73 2002/07/15 18:36:53 rwahl
* Editorial changes.
- *
+ *
* Revision 1.72 2002/07/15 15:46:26 rschmidt
* Added new event: SK_HWEV_SET_SPEED
* Editorial changes
- *
+ *
* Revision 1.71 2002/06/10 09:34:19 rschmidt
* Editorial changes
- *
+ *
* Revision 1.70 2002/06/05 08:29:18 rschmidt
* SkXmRxTxEnable() replaced by SkMacRxTxEnable().
* Editorial changes.
- *
+ *
* Revision 1.69 2002/04/25 13:03:49 rschmidt
* Changes for handling YUKON.
* Use of #ifdef OTHER_PHY to eliminate code for unused Phy types.
* Removed status parameter from MAC IRQ handler SkMacIrq().
* Added SkGePortCheckUpGmac(), SkPhyIsrGmac() for GMAC.
* Editorial changes
- *
+ *
* Revision 1.68 2002/02/26 15:24:53 rwahl
* Fix: no link with manual configuration (#10673). The previous fix for
* #10639 was removed. So for RLMT mode = CLS the RLMT may switch to
* misconfigured port. It should not occur for the other RLMT modes.
- *
+ *
* Revision 1.67 2001/11/20 09:19:58 rwahl
* Reworked bugfix #10639 (no dependency to RLMT mode).
- *
+ *
* Revision 1.66 2001/10/26 07:52:53 afischer
* Port switching bug in `check local link` mode
- *
+ *
* Revision 1.65 2001/02/23 13:41:51 gklug
* fix: PHYS2INST should be used correctly for Dual Net operation
* chg: do no longer work with older PNMI
- *
+ *
* Revision 1.64 2001/02/15 11:27:04 rassmann
* Working with RLMT v1 if SK_MAX_NETS undefined.
- *
+ *
* Revision 1.63 2001/02/06 10:44:23 mkunz
* - NetIndex added to interface functions of pnmi V4 with dual net support
- *
+ *
* Revision 1.62 2001/01/31 15:31:41 gklug
* fix: problem with autosensing an SR8800 switch
- *
+ *
* Revision 1.61 2000/11/09 11:30:09 rassmann
* WA: Waiting after releasing reset until BCom chip is accessible.
*
* Revision 1.60 2000/10/18 12:37:48 cgoos
* Reinserted the comment for version 1.56.
- *
+ *
* Revision 1.59 2000/10/18 12:22:20 cgoos
* Added workaround for half duplex hangup.
- *
+ *
* Revision 1.58 2000/09/28 13:06:04 gklug
* fix: BCom may NOT be touched if XMAC is in RESET state
- *
+ *
* Revision 1.57 2000/09/08 12:38:39 cgoos
* Added forgotten variable declaration.
- *
+ *
* Revision 1.56 2000/09/08 08:12:13 cgoos
* Changed handling of parity errors in SkGeHwErr (correct reset of error).
*
* Revision 1.55 2000/06/19 08:36:25 cgoos
* Changed comment.
- *
+ *
* Revision 1.54 2000/05/22 08:45:57 malthoff
* Fix: #10523 is valid for all BCom PHYs.
- *
+ *
* Revision 1.53 2000/05/19 10:20:30 cgoos
* Removed Solaris debug output code.
- *
+ *
* Revision 1.52 2000/05/19 10:19:37 cgoos
* Added PHY state check in HWLinkDown.
* Move PHY interrupt code to IS_EXT_REG case in SkGeSirqIsr.
- *
+ *
* Revision 1.51 2000/05/18 05:56:20 cgoos
* Fixed typo.
- *
+ *
* Revision 1.50 2000/05/17 12:49:49 malthoff
* Fixes BCom link bugs (#10523).
- *
+ *
* Revision 1.49 1999/12/17 11:02:50 gklug
* fix: read PHY_STAT of Broadcom chip more often to assure good status
- *
+ *
* Revision 1.48 1999/12/06 10:01:17 cgoos
* Added SET function for Role.
- *
+ *
* Revision 1.47 1999/11/22 13:34:24 cgoos
* Changed license header to GPL.
- *
+ *
* Revision 1.46 1999/09/16 10:30:07 cgoos
* Removed debugging output statement from Linux.
- *
+ *
* Revision 1.45 1999/09/16 07:32:55 cgoos
* Fixed dual-port copperfield bug (PHY_READ from resetted port).
* Removed some unused variables.
- *
+ *
* Revision 1.44 1999/08/03 15:25:04 cgoos
* Removed workaround for disabled interrupts in half duplex mode.
- *
+ *
* Revision 1.43 1999/08/03 14:27:58 cgoos
* Removed SENSE mode code from SkGePortCheckUpBcom.
- *
+ *
* Revision 1.42 1999/07/26 09:16:54 cgoos
* Added some typecasts to avoid compiler warnings.
- *
+ *
* Revision 1.41 1999/05/19 07:28:59 cgoos
* Changes for 1000Base-T.
- *
+ *
* Revision 1.40 1999/04/08 13:59:39 gklug
* fix: problem with 3Com switches endless RESTARTs
- *
+ *
* Revision 1.39 1999/03/08 10:10:52 gklug
* fix: AutoSensing did switch to next mode even if LiPa indicated offline
- *
+ *
* Revision 1.38 1999/03/08 09:49:03 gklug
* fix: Bug using pAC instead of IoC, causing AIX problems
* fix: change compare for Linux compiler bug workaround
- *
+ *
* Revision 1.37 1999/01/28 14:51:33 gklug
* fix: monitor for autosensing and extra RESETS the RX on wire counters
- *
+ *
* Revision 1.36 1999/01/22 09:19:55 gklug
* fix: Init DupMode and InitPauseMd are now called in RxTxEnable
- *
+ *
* Revision 1.35 1998/12/11 15:22:59 gklug
* chg: autosensing: check for receive if manual mode was guessed
* chg: simplified workaround for XMAC errata
* chg: wait additional 100 ms before link goes up.
* chg: autoneg timeout to 600 ms
* chg: restart autoneg even if configured to autonegotiation
- *
+ *
* Revision 1.34 1998/12/10 10:33:14 gklug
* add: more debug messages
* fix: do a new InitPhy if link went down (AutoSensing problem)
* chg: reset Port if link goes down
* chg: wait additional 100 ms when link comes up to check shorts
* fix: dummy read extended autoneg status to prevent link going down immediately
- *
+ *
* Revision 1.33 1998/12/07 12:18:29 gklug
* add: refinement of autosense mode: take into account the autoneg cap of LiPa
- *
+ *
* Revision 1.32 1998/12/07 07:11:21 gklug
* fix: compiler warning
- *
+ *
* Revision 1.31 1998/12/02 09:29:05 gklug
* fix: WA XMAC Errata: FCSCt check was not correct.
* fix: WA XMAC Errata: Prec Counter were NOT updated in case of short checks.
* fix: Clear Stat : now clears the Prev counters of all known Ports
- *
+ *
* Revision 1.30 1998/12/01 10:54:15 gklug
* dd: workaround for XMAC errata changed. Check RX count and CRC err Count, too.
- *
+ *
* Revision 1.29 1998/12/01 10:01:53 gklug
* fix: if MAC IRQ occurs during port down, this will be handled correctly
- *
+ *
* Revision 1.28 1998/11/26 16:22:11 gklug
* fix: bug in autosense if manual modes are used
- *
+ *
* Revision 1.27 1998/11/26 15:50:06 gklug
* fix: PNMI needs to set PLinkModeConf
- *
+ *
* Revision 1.26 1998/11/26 14:51:58 gklug
* add: AutoSensing functionalty
- *
+ *
* Revision 1.25 1998/11/26 07:34:37 gklug
* fix: Init PrevShorts when restarting port due to Link connection
- *
+ *
* Revision 1.24 1998/11/25 10:57:32 gklug
* fix: remove unreferenced local vars
- *
+ *
* Revision 1.23 1998/11/25 08:26:40 gklug
* fix: don't do a RESET on a starting or stopping port
- *
+ *
* Revision 1.22 1998/11/24 13:29:44 gklug
* add: Workaround for MAC parity errata
- *
+ *
* Revision 1.21 1998/11/18 15:31:06 gklug
* fix: lint bugs
- *
+ *
* Revision 1.20 1998/11/18 12:58:54 gklug
* fix: use PNMI query instead of hardware access
- *
+ *
* Revision 1.19 1998/11/18 12:54:55 gklug
* chg: add new workaround for XMAC Errata
* add: short event counter monitoring on active link too
- *
+ *
* Revision 1.18 1998/11/13 14:27:41 malthoff
* Bug Fix: Packet Arbiter Timeout was not cleared correctly
* for timeout on TX1 and TX2.
- *
+ *
* Revision 1.17 1998/11/04 07:01:59 cgoos
* Moved HW link poll sequence.
* Added call to SkXmRxTxEnable.
- *
+ *
* Revision 1.16 1998/11/03 13:46:03 gklug
* add: functionality of SET_LMODE and SET_FLOW_MODE
* fix: send RLMT LinkDown event when Port stop is given with LinkUp
- *
+ *
* Revision 1.15 1998/11/03 12:56:47 gklug
* fix: Needs more events
- *
+ *
* Revision 1.14 1998/10/30 07:36:35 gklug
* rmv: unnecessary code
- *
+ *
* Revision 1.13 1998/10/29 15:21:57 gklug
* add: Poll link feature for activating HW link
* fix: Deactivate HWLink when Port STOP is given
- *
+ *
* Revision 1.12 1998/10/28 07:38:57 cgoos
* Checking link status at begin of SkHWLinkUp.
- *
+ *
* Revision 1.11 1998/10/22 09:46:50 gklug
* fix SysKonnectFileId typo
- *
+ *
* Revision 1.10 1998/10/14 13:57:47 gklug
* add: Port start/stop event
- *
+ *
* Revision 1.9 1998/10/14 05:48:29 cgoos
* Added definition for Para.
- *
+ *
* Revision 1.8 1998/10/14 05:40:09 gklug
* add: Hardware Linkup signal used
- *
+ *
* Revision 1.7 1998/10/09 06:50:20 malthoff
* Remove ID_sccs by SysKonnectFileId.
*
* Revision 1.6 1998/10/08 09:11:49 gklug
* add: clear IRQ commands
- *
+ *
* Revision 1.5 1998/10/02 14:27:35 cgoos
* Fixed some typos and wrong event names.
- *
+ *
* Revision 1.4 1998/10/02 06:24:17 gklug
* add: HW error function
* fix: OUT macros
- *
+ *
* Revision 1.3 1998/10/01 07:03:00 gklug
* add: ISR for the usual interrupt source register
- *
+ *
* Revision 1.2 1998/09/03 13:50:33 gklug
* add: function prototypes
- *
+ *
* Revision 1.1 1998/08/27 11:50:21 gklug
* initial revision
- *
+ *
*
*
******************************************************************************/
/* Disable Receiver and Transmitter */
SkMacRxTxDisable(pAC, IoC, Port);
-
+
/* Init default sense mode */
SkHWInitDefSense(pAC, IoC, Port);
if (pAC->GIni.GIGenesis) {
/* Snap statistic counters */
(void)SkXmUpdateStats(pAC, IoC, Port);
-
+
(void)SkXmMacStatistic(pAC, IoC, Port, XM_TXF_MAX_SZ, &TxMax);
}
else {
(void)SkGmMacStatistic(pAC, IoC, Port, GM_TXF_1518B, &TxMax);
}
-
+
if (TxMax > 0) {
/* From now on check the parity */
pPrt->PCheckPar = SK_TRUE;
/* Reset all bits in the PCI STATUS register */
SK_IN16(IoC, PCI_C(PCI_STATUS), &Word);
-
+
SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_ON);
SK_OUT16(IoC, PCI_C(PCI_STATUS), Word | PCI_ERRBITS);
SK_OUT8(IoC, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
/* This situation is also indicated in the descriptor */
SK_OUT16(IoC, MR_ADDR(MAC_1, RX_MFF_CTRL1), MFF_CLR_INSTAT);
}
-
+
if ((HwStatus & IS_NO_STAT_M2) != 0) {
/* Ignore it */
/* This situation is also indicated in the descriptor */
SK_OUT16(IoC, MR_ADDR(MAC_2, RX_MFF_CTRL1), MFF_CLR_INSTAT);
}
-
+
if ((HwStatus & IS_NO_TIST_M1) != 0) {
/* Ignore it */
/* This situation is also indicated in the descriptor */
SK_OUT16(IoC, MR_ADDR(MAC_1, RX_MFF_CTRL1), MFF_CLR_INTIST);
}
-
+
if ((HwStatus & IS_NO_TIST_M2) != 0) {
/* Ignore it */
/* This situation is also indicated in the descriptor */
if ((Istatus & IS_HW_ERR) != 0) {
/* read the HW Error Interrupt source */
SK_IN32(IoC, B0_HWE_ISRC, &RegVal32);
-
+
SkGeHwErr(pAC, IoC, RegVal32);
}
}
if ((Istatus & IS_PA_TO_TX1) != 0) {
-
+
pPrt = &pAC->GIni.GP[0];
/* May be a normal situation in a server with a slow network */
SkPnmiGetVar(pAC, IoC, OID_SKGE_STAT_TX_OCTETS, (char *)&Octets,
&Len, (SK_U32) SK_PNMI_PORT_PHYS2INST(pAC, 0),
pAC->Rlmt.Port[0].Net->NetNumber);
-
+
pPrt->LastOctets = Octets;
-
+
Para.Para32[0] = 0;
SkTimerStart(pAC, IoC, &pPrt->HalfDupChkTimer, SK_HALFDUP_CHK_TIME,
SKGE_HWAC, SK_HWEV_HALFDUP_CHK, Para);
}
if ((Istatus & IS_PA_TO_TX2) != 0) {
-
+
pPrt = &pAC->GIni.GP[1];
/* May be a normal situation in a server with a slow network */
SkPnmiGetVar(pAC, IoC, OID_SKGE_STAT_TX_OCTETS, (char *)&Octets,
&Len, (SK_U32) SK_PNMI_PORT_PHYS2INST(pAC, 1),
pAC->Rlmt.Port[1].Net->NetNumber);
-
+
pPrt->LastOctets = Octets;
-
+
Para.Para32[0] = 1;
SkTimerStart(pAC, IoC, &pPrt->HalfDupChkTimer, SK_HALFDUP_CHK_TIME,
SKGE_HWAC, SK_HWEV_HALFDUP_CHK, Para);
if ((Istatus & IS_EXT_REG) != 0) {
/* Test IRQs from PHY */
for (i = 0; i < pAC->GIni.GIMacsFound; i++) {
-
+
pPrt = &pAC->GIni.GP[i];
-
+
if (pPrt->PState == SK_PRT_RESET) {
continue;
}
-
+
switch (pPrt->PhyType) {
-
+
case SK_PHY_XMAC:
break;
-
+
case SK_PHY_BCOM:
SkXmPhyRead(pAC, IoC, i, PHY_BCOM_INT_STAT, &PhyInt);
SkXmPhyRead(pAC, IoC, i, PHY_BCOM_INT_MASK, &PhyIMsk);
SkPhyIsrBcom(pAC, IoC, i, PhyInt);
}
break;
-
+
case SK_PHY_MARV_COPPER:
case SK_PHY_MARV_FIBER:
SkGmPhyRead(pAC, IoC, i, PHY_MARV_INT_STAT, &PhyInt);
case SK_PHY_LONE:
SkXmPhyRead(pAC, IoC, i, PHY_LONE_INT_STAT, &PhyInt);
SkXmPhyRead(pAC, IoC, i, PHY_LONE_INT_ENAB, &PhyIMsk);
-
+
if ((PhyInt & PhyIMsk) != 0) {
SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
("Port %d Lone Int: %x Mask: %x\n",
CheckShorts = 2;
(void)SkXmMacStatistic(pAC, IoC, Port, XM_RXF_FCS_ERR, &FcsErrCts);
-
+
if (pPrt->PLinkModeConf == SK_LMODE_AUTOSENSE &&
pPrt->PLipaAutoNeg == SK_LIPA_UNKNOWN &&
(pPrt->PLinkMode == SK_LMODE_HALF ||
/* Nothing received, restart link */
pPrt->PPrevFcs = FcsErrCts;
pPrt->PPrevShorts = Shorts;
-
+
return(SK_HW_PS_RESTART);
}
else {
XM_IN16(IoC, Port, XM_ISRC, &Isrc);
IsrcSum |= Isrc;
SkXmAutoNegLipaXmac(pAC, IoC, Port, IsrcSum);
-
+
if ((Isrc & XM_IS_INP_ASS) == 0) {
/* It has been in sync since last time */
/* Restart the PORT */
* check whether the link is now o.k.
*/
pPrt->PLinkResCt++;
-
+
pPrt->PAutoNegTimeOut = 0;
if (pPrt->PLinkResCt < SK_MAX_LRESTART) {
}
pPrt->PLinkResCt = 0;
-
+
SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
("Do NOT restart on Port %d %x %x\n", Port, Isrc, IsrcSum));
}
else {
pPrt->PIsave = (SK_U16)(IsrcSum & XM_IS_AND);
-
+
SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
("Save Sync/nosync Port %d %x %x\n", Port, Isrc, IsrcSum));
IsrcSum |= Isrc;
SkXmAutoNegLipaXmac(pAC, IoC, Port, IsrcSum);
-
+
if ((GpReg & XM_GP_INP_ASS) != 0 || (IsrcSum & XM_IS_INP_ASS) != 0) {
if ((GpReg & XM_GP_INP_ASS) == 0) {
/* Save Auto-negotiation Done interrupt only if link is in sync */
SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
("AutoNeg FAIL Port %d (LpAb %x, ResAb %x)\n",
Port, LpAb, ResAb));
-
+
/* Try next possible mode */
NextMode = SkHWSenseGetNext(pAC, IoC, Port);
SkHWLinkDown(pAC, IoC, Port);
("AutoNeg done Port %d\n", Port));
return(SK_HW_PS_LINK);
}
-
+
/* AutoNeg not done, but HW link is up. Check for timeouts */
pPrt->PAutoNegTimeOut++;
if (pPrt->PAutoNegTimeOut >= SK_AND_MAX_TO) {
SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
("Link sync(GP), Port %d\n", Port));
SkHWLinkUp(pAC, IoC, Port);
-
+
/*
* Link sync (GP) and so assume a good connection. But if not received
* a bunch of frames received in a time slot (maybe broken tx cable)
SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_STAT, &PhyStat);
SkMacAutoNegLipaPhy(pAC, IoC, Port, PhyStat);
-
+
SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
("AutoNeg: %d, PhyStat: 0x%04x\n", AutoNeg, PhyStat));
("Master/Slave Fault port %d\n", Port));
pPrt->PAutoNegFail = SK_TRUE;
pPrt->PMSStatus = SK_MS_STAT_FAULT;
-
+
return(SK_HW_PS_RESTART);
}
if ((PhyStat & PHY_ST_LSYNC) == 0) {
return(SK_HW_PS_NONE);
}
-
+
pPrt->PMSStatus = ((ResAb & PHY_B_1000S_MSR) != 0) ?
SK_MS_STAT_MASTER : SK_MS_STAT_SLAVE;
-
+
SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
("AutoNeg: %d, PhyStat: 0x%04x\n", AutoNeg, PhyStat));
(void *)NULL);
}
#endif /* DEBUG */
-
+
SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
("AutoNeg done Port %d\n", Port));
return(SK_HW_PS_LINK);
(void *)NULL);
}
#endif /* DEBUG */
-
+
SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
("Link sync(GP), Port %d\n", Port));
SkHWLinkUp(pAC, IoC, Port);
("AutoNeg: %d, PhyStat: 0x%04x\n", AutoNeg, PhyStat));
SkMacAutoNegLipaPhy(pAC, IoC, Port, PhyStat);
-
+
SkGmPhyRead(pAC, IoC, Port, PHY_MARV_1000T_STAT, &ResAb);
if ((ResAb & PHY_B_1000S_MSF) != 0) {
("Master/Slave Fault port %d\n", Port));
pPrt->PAutoNegFail = SK_TRUE;
pPrt->PMSStatus = SK_MS_STAT_FAULT;
-
+
return(SK_HW_PS_RESTART);
}
/* Read PHY Specific Status */
SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_STAT, &PhySpecStat);
-
+
SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
("AutoNeg: %d, PhySpecStat: 0x%04x\n", AutoNeg, PhySpecStat));
if ((PhySpecStat & PHY_M_PS_LINK_UP) == 0) {
return(SK_HW_PS_NONE);
}
-
+
pPrt->PMSStatus = ((ResAb & PHY_B_1000S_MSR) != 0) ?
SK_MS_STAT_MASTER : SK_MS_STAT_SLAVE;
-
+
pPrt->PCableLen = (SK_U8)((PhySpecStat & PHY_M_PS_CABLE_MSK) >> 7);
-
+
if (AutoNeg) {
/* Auto-Negotiation Over ? */
if ((PhyStat & PHY_ST_AN_OVER) != 0) {
-
+
SkHWLinkUp(pAC, IoC, Port);
-
+
Done = SkMacAutoNegDone(pAC, IoC, Port);
-
+
if (Done != SK_AND_OK) {
return(SK_HW_PS_RESTART);
}
-
+
SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
("AutoNeg done Port %d\n", Port));
return(SK_HW_PS_LINK);
SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
("Link sync, Port %d\n", Port));
SkHWLinkUp(pAC, IoC, Port);
-
+
return(SK_HW_PS_LINK);
}
StatSum |= PhyStat;
SkMacAutoNegLipaPhy(pAC, IoC, Port, PhyStat);
-
+
if ((PhyStat & PHY_ST_LSYNC) == 0) {
/* Save Auto-negotiation Done bit */
pPrt->PIsave = (SK_U16)(StatSum & PHY_ST_AN_OVER);
SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
("AutoNeg FAIL Port %d (LpAb %x, 1000TStat %x)\n",
Port, LpAb, ExtStat));
-
+
/* Try next possible mode */
NextMode = SkHWSenseGetNext(pAC, IoC, Port);
SkHWLinkDown(pAC, IoC, Port);
return(SK_HW_PS_LINK);
}
}
-
+
/* AutoNeg not done, but HW link is up. Check for timeouts */
pPrt->PAutoNegTimeOut++;
if (pPrt->PAutoNegTimeOut >= SK_AND_MAX_TO) {
* extra link down/ups
*/
SkXmPhyRead(pAC, IoC, Port, PHY_LONE_INT_STAT, &ExtStat);
-
+
SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
("Link sync(GP), Port %d\n", Port));
SkHWLinkUp(pAC, IoC, Port);
break;
}
-
+
/* Start again the check Timer */
if (pPrt->PHWLinkUp) {
Time = SK_WA_ACT_TIME;
pPrt->HalfDupTimerActive = SK_FALSE;
if (pPrt->PLinkModeStatus == SK_LMODE_STAT_HALF ||
pPrt->PLinkModeStatus == SK_LMODE_STAT_AUTOHALF) {
-
+
Len = sizeof(SK_U64);
SkPnmiGetVar(pAC, IoC, OID_SKGE_STAT_TX_OCTETS, (char *)&Octets,
&Len, (SK_U32)SK_PNMI_PORT_PHYS2INST(pAC, Port),
pAC->Rlmt.Port[Port].Net->NetNumber);
-
+
if (pPrt->LastOctets == Octets) {
/* Tx hanging, a FIFO flush restarts it */
SkMacFlushTxFifo(pAC, IoC, Port);
}
}
break;
-
+
default:
SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_SIRQ_E001, SKERR_SIRQ_E001MSG);
break;
SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_SIRQ_E022,
SKERR_SIRQ_E022MSG);
}
-
+
if ((IStatus & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE)) != 0) {
Para.Para32[0] = (SK_U32)Port;
/* Signal to RLMT */
SkEventQueue(pAC, SKGE_RLMT, SK_RLMT_LINK_DOWN, Para);
}
-
+
if ((IStatus & PHY_M_IS_AN_ERROR) != 0) {
/* Auto-Negotiation Error */
SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E023, SKERR_SIRQ_E023MSG);
}
-
+
if ((IStatus & PHY_M_IS_LSP_CHANGE) != 0) {
/* TBD */
}
-
+
if ((IStatus & PHY_M_IS_FIFO_ERROR) != 0) {
/* FIFO Overflow/Underrun Error */
SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_SIRQ_E024, SKERR_SIRQ_E024MSG);
* Revision 1.57 2003/01/28 09:17:38 rschmidt
* Fixed handling for sensors on YUKON Fiber.
* Editorial changes.
- *
+ *
* Revision 1.56 2002/12/19 14:20:41 rschmidt
* Added debugging code in SkI2cWait().
* Replaced all I2C-write operations with function SkI2cWrite().
* Fixed compiler warning because of uninitialized 'Time' in SkI2cEvent().
* Editorial changes.
- *
+ *
* Revision 1.55 2002/10/15 07:23:55 rschmidt
* Added setting of the GIYukon32Bit bool variable to distinguish
* 32-bit adapters.
* Editorial changes (TWSI).
- *
+ *
* Revision 1.54 2002/08/13 09:05:06 rschmidt
* Added new thresholds if VAUX is not available (GIVauxAvail).
* Merged defines for PHY PLL 3V3 voltage (A and B).
* Editorial changes.
- *
+ *
* Revision 1.53 2002/08/08 11:04:53 rwahl
* Added missing comment for revision 1.51
- *
+ *
* Revision 1.52 2002/08/08 10:09:02 jschmalz
* Sensor init state caused wrong error log entry
- *
+ *
* Revision 1.51 2002/08/06 09:43:03 jschmalz
* Extensions and changes for Yukon
- *
+ *
* Revision 1.50 2002/08/02 12:09:22 rschmidt
* Added support for YUKON sensors.
* Editorial changes.
- *
+ *
* Revision 1.49 2002/07/30 11:07:52 rschmidt
* Replaced MaxSens init by update for Copper in SkI2cInit1(),
* because it was already initialized in SkI2cInit0().
* Editorial changes.
- *
+ *
* Revision 1.48 2001/08/16 12:44:33 afischer
* LM80 sensor init values corrected
- *
+ *
* Revision 1.47 2001/04/05 11:38:09 rassmann
* Set SenState to idle in SkI2cWaitIrq().
* Changed error message in SkI2cWaitIrq().
- *
+ *
* Revision 1.46 2001/04/02 14:03:35 rassmann
* Changed pAC to IoC in SK_IN32().
- *
+ *
* Revision 1.45 2001/03/21 12:12:49 rassmann
* Resetting I2C_READY interrupt in SkI2cInit1().
- *
+ *
* Revision 1.44 2000/08/07 15:49:03 gklug
* Fix: SK_INFAST only in NetWare driver.
- *
+ *
* Revision 1.43 2000/08/03 14:28:17 rassmann
* Added function to wait for I2C being ready before resetting the board.
* Replaced one duplicate "out of range" message with correct one.
- *
+ *
* Revision 1.42 1999/11/22 13:35:12 cgoos
* Changed license header to GPL.
- *
+ *
* Revision 1.41 1999/09/14 14:11:30 malthoff
* The 1000BT Dual Link adapter has got only one Fan.
* The second Fan has been removed.
- *
+ *
* Revision 1.40 1999/05/27 13:37:27 malthoff
* Set divisor of 1 for fan count calculation.
- *
+ *
* Revision 1.39 1999/05/20 14:54:43 malthoff
* I2c.DummyReads is not used in Diagnostics.
- *
+ *
* Revision 1.38 1999/05/20 09:20:56 cgoos
* Changes for 1000Base-T (up to 9 sensors and fans).
- *
+ *
* Revision 1.37 1999/03/25 15:11:36 gklug
* fix: reset error flag if sensor reads correct value
- *
+ *
* Revision 1.36 1999/01/07 14:11:16 gklug
* fix: break added
- *
+ *
* Revision 1.35 1999/01/05 15:31:49 gklug
* fix: CLEAR STAT command is now added correctly
- *
+ *
* Revision 1.34 1998/12/01 13:45:16 gklug
* fix: introduced Init level, because we don't need reinits
- *
+ *
* Revision 1.33 1998/11/09 14:54:25 malthoff
* Modify I2C Transfer Timeout handling for Diagnostics.
- *
+ *
* Revision 1.32 1998/11/03 06:54:35 gklug
* fix: Need dummy reads at the beginning to init sensors
*
* Revision 1.31 1998/11/03 06:42:42 gklug
* fix: select correctVIO range only if between warning levels
- *
+ *
* Revision 1.30 1998/11/02 07:36:53 gklug
* fix: Error should not include WARNING message
- *
+ *
* Revision 1.29 1998/10/30 15:07:43 malthoff
* Disable 'I2C does not compelete' error log for diagnostics.
- *
+ *
* Revision 1.28 1998/10/22 09:48:11 gklug
* fix: SysKonnectFileId typo
- *
+ *
* Revision 1.27 1998/10/20 09:59:46 gklug
* add: parameter to SkOsGetTime
- *
+ *
* Revision 1.26 1998/10/09 06:10:59 malthoff
* Remove ID_sccs by SysKonnectFileId.
- *
+ *
* Revision 1.25 1998/09/08 12:40:26 gklug
* fix: syntax error in if clause
- *
+ *
* Revision 1.24 1998/09/08 12:19:42 gklug
* chg: INIT Level checking
- *
+ *
* Revision 1.23 1998/09/08 07:37:20 gklug
* fix: log error if PCI_IO voltage sensor could not be initialized
- *
+ *
* Revision 1.22 1998/09/04 08:30:03 malthoff
* Bugfixes during SK_DIAG testing:
* - correct NS2BCLK() macro
* - correct SkI2cSndDev()
* - correct SkI2cWait() loop waiting for an event
- *
+ *
* Revision 1.21 1998/08/27 14:46:01 gklug
* chg: if-then-else replaced by switch
*
* Revision 1.20 1998/08/27 14:40:07 gklug
* test: integral types
- *
+ *
* Revision 1.19 1998/08/25 07:51:54 gklug
* fix: typos for compiling
- *
+ *
* Revision 1.18 1998/08/25 06:12:24 gklug
* add: count errors and warnings
* fix: check not the sensor state but the ErrFlag!
- *
+ *
* Revision 1.17 1998/08/25 05:56:48 gklug
* add: CheckSensor function
- *
+ *
* Revision 1.16 1998/08/20 11:41:10 gklug
* chg: omit STRCPY macro by using char * as Sensor Description
- *
+ *
* Revision 1.15 1998/08/20 11:37:35 gklug
* chg: change Ioc to IoC
- *
+ *
* Revision 1.14 1998/08/20 11:32:52 gklug
* fix: Para compile error
- *
+ *
* Revision 1.13 1998/08/20 11:27:41 gklug
* fix: Compile bugs with new awrning constants
- *
+ *
* Revision 1.12 1998/08/20 08:53:05 gklug
* fix: compiler errors
* add: Threshold values
- *
+ *
* Revision 1.11 1998/08/19 12:39:22 malthoff
* Compiler Fix: Some names have changed.
- *
+ *
* Revision 1.10 1998/08/19 12:20:56 gklug
* fix: remove struct from C files (see CCC)
- *
+ *
* Revision 1.9 1998/08/19 06:28:46 malthoff
* SkOsGetTime returns SK_U64 now.
- *
+ *
* Revision 1.8 1998/08/17 13:53:33 gklug
* fix: Parameter of event function and its result
- *
+ *
* Revision 1.7 1998/08/17 07:02:15 malthoff
* Modify the functions for accessing the I2C SW Registers.
* Modify SkI2cWait().
* Put Lm80RcvReg into sklm80.c
* Remove Compiler Errors.
- *
+ *
* Revision 1.6 1998/08/14 07:13:20 malthoff
* remove pAc with pAC
* remove smc with pAC
SkDgWaitTime(IoC, NS2BCLK(T_CLK_HIGH));
SK_I2C_GET_SW(IoC, &I2cSwCtrl);
-
+
Bit = (I2cSwCtrl & I2C_DATA) ? 1 : 0;
I2C_CLK_LOW(IoC);
SK_U32 I2cCtrl;
StartTime = SkOsGetTime(pAC);
-
+
do {
CurrentTime = SkOsGetTime(pAC);
if (CurrentTime - StartTime > SK_TICKS_PER_SEC / 8) {
-
+
SK_I2C_STOP(IoC);
#ifndef SK_DIAG
SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_I2C_E002, SKERR_I2C_E002MSG);
#endif /* !SK_DIAG */
return(1);
}
-
+
SK_I2C_GET_CTL(IoC, &I2cCtrl);
#ifdef xYUKON_DBG
return(1);
}
#endif /* YUKON_DBG */
-
+
} while ((I2cCtrl & I2C_FLAG) == (SK_U32)Event << 31);
return(0);
{
SK_OUT32(IoC, B2_I2C_DATA, I2cData);
SK_I2C_CTL(IoC, I2C_WRITE, I2cDev, I2cReg, I2cBurst);
-
+
return(SkI2cWait(pAC, IoC, I2C_WRITE));
} /* SkI2cWrite*/
SK_OUT32(IoC, B2_I2C_DATA, 0);
SK_I2C_CTL(IoC, I2C_READ, I2cDev, I2cReg, I2cBurst);
-
+
if (SkI2cWait(pAC, IoC, I2C_READ) != 0) {
w_print("%s\n", SKERR_I2C_E002MSG);
}
-
+
SK_IN32(IoC, B2_I2C_DATA, &Data);
return(Data);
} /* SkI2cRead */
SK_SENSOR *pSen) /* Sensor to be read */
{
if (pSen->SenRead != NULL) {
- return((*pSen->SenRead)(pAC, IoC, pSen));
+ return((*pSen->SenRead)(pAC, IoC, pSen));
}
else
- return(0); /* no success */
+ return(0); /* no success */
} /* SkI2cReadSensor*/
/*
/* Begin with first sensor */
pAC->I2c.CurrSens = 0;
-
+
/* Begin with timeout control for state machine */
pAC->I2c.TimerMode = SK_TIMER_WATCH_STATEMACHINE;
-
+
/* Set sensor number to zero */
pAC->I2c.MaxSens = 0;
if ((I2cSwCtrl & I2C_DATA) == 0) {
/* this is a 32-Bit board */
pAC->GIni.GIYukon32Bit = SK_TRUE;
- return(0);
+ return(0);
}
/* Check for 64 Bit Yukon without sensors */
if (SkI2cWrite(pAC, IoC, 0, LM80_ADDR, LM80_CFG, 0) != 0) {
- return(0);
+ return(0);
}
(void)SkI2cWrite(pAC, IoC, 0xff, LM80_ADDR, LM80_IMSK_1, 0);
-
+
(void)SkI2cWrite(pAC, IoC, 0xff, LM80_ADDR, LM80_IMSK_2, 0);
-
+
(void)SkI2cWrite(pAC, IoC, 0, LM80_ADDR, LM80_FAN_CTRL, 0);
-
+
(void)SkI2cWrite(pAC, IoC, 0, LM80_ADDR, LM80_TEMP_CTRL, 0);
-
+
(void)SkI2cWrite(pAC, IoC, LM80_CFG_START, LM80_ADDR, LM80_CFG, 0);
-
+
/*
* MaxSens has to be updated here, because PhyType is not
* set when performing Init Level 0
*/
pAC->I2c.MaxSens = 5;
-
+
pPrt = &pAC->GIni.GP[0];
-
+
if (pAC->GIni.GIGenesis) {
if (pPrt->PhyType == SK_PHY_BCOM) {
if (pAC->GIni.GIMacsFound == 1) {
else {
pAC->I2c.MaxSens += 3;
}
-
+
for (i = 0; i < pAC->I2c.MaxSens; i++) {
switch (i) {
case 0:
#ifndef SK_DIAG
pAC->I2c.DummyReads = pAC->I2c.MaxSens;
#endif /* !SK_DIAG */
-
+
/* Clear I2C IRQ */
SK_OUT32(IoC, B2_I2C_IRQ, I2C_CLR_IRQ);
-
+
/* Now we are I/O initialized */
pAC->I2c.InitLevel = SK_INIT_IO;
return(0);
/* Check the Value against the thresholds. First: Error Thresholds */
TooHigh = (pSen->SenValue > pSen->SenThreErrHigh);
TooLow = (pSen->SenValue < pSen->SenThreErrLow);
-
+
IsError = SK_FALSE;
if (TooHigh || TooLow) {
/* Error condition is satisfied */
/* 2nd: Warning thresholds */
TooHigh = (pSen->SenValue > pSen->SenThreWarnHigh);
TooLow = (pSen->SenValue < pSen->SenThreWarnLow);
-
+
if (!IsError && (TooHigh || TooLow)) {
/* Error condition is satisfied */
DoTrapSend = SK_TRUE;
*/
if (pSen->SenInit == SK_SEN_DYN_INIT_PCI_IO) {
- pSen->SenInit = SK_SEN_DYN_INIT_NONE;
+ pSen->SenInit = SK_SEN_DYN_INIT_NONE;
if (pSen->SenValue > SK_SEN_PCI_IO_RANGE_LIMITER) {
/* 5V PCI-IO Voltage */
pSen->SenThreErrHigh = SK_SEN_PCI_IO_3V3_HIGH_ERR;
}
}
-
+
#if 0
/* Dynamic thresholds also for VAUX of LM80 sensor */
if (pSen->SenInit == SK_SEN_DYN_INIT_VAUX) {
- pSen->SenInit = SK_SEN_DYN_INIT_NONE;
+ pSen->SenInit = SK_SEN_DYN_INIT_NONE;
/* 3.3V VAUX Voltage */
if (pSen->SenValue > SK_SEN_VAUX_RANGE_LIMITER) {
ParaLocal.Para64 = (SK_U64)0;
pAC->I2c.TimerMode = SK_TIMER_NEW_GAUGING;
-
+
SkTimerStart(pAC, IoC, &pAC->I2c.SenTimer, Time,
SKGE_I2C, SK_I2CEV_TIM, ParaLocal);
}
- else {
+ else {
/* Start Timer */
ParaLocal.Para64 = (SK_U64)0;
pAC->I2c.TimerMode = SK_TIMER_WATCH_STATEMACHINE;
- SkTimerStart(pAC, IoC, &pAC->I2c.SenTimer, SK_I2C_TIM_WATCH,
+ SkTimerStart(pAC, IoC, &pAC->I2c.SenTimer, SK_I2C_TIM_WATCH,
SKGE_I2C, SK_I2CEV_TIM, ParaLocal);
}
break;
* Revision 1.20 2002/08/13 09:16:27 rschmidt
* Changed return value for SkLm80ReadSensor() back to 'int'
* Editorial changes
- *
+ *
* Revision 1.19 2002/08/06 09:43:31 jschmalz
* Extensions and changes for Yukon
- *
+ *
* Revision 1.18 2002/08/02 12:26:57 rschmidt
* Editorial changes
- *
+ *
* Revision 1.17 1999/11/22 13:35:51 cgoos
* Changed license header to GPL.
- *
+ *
* Revision 1.16 1999/05/27 14:05:47 malthoff
* Fans: Set SenVal to 0 if the fan value is 0 or 0xff. Both values
* are outside the limits (0: div zero error, 0xff: value not in
* range, assume 0).
- *
+ *
* Revision 1.15 1999/05/27 13:38:51 malthoff
* Pervent from Division by zero errors.
- *
+ *
* Revision 1.14 1999/05/20 09:20:01 cgoos
* Changes for 1000Base-T (Fan sensors).
- *
+ *
* Revision 1.13 1998/10/22 09:48:14 gklug
* fix: SysKonnectFileId typo
- *
+ *
* Revision 1.12 1998/10/09 06:12:06 malthoff
* Remove ID_sccs by SysKonnectFileId.
- *
+ *
* Revision 1.11 1998/09/04 08:33:48 malthoff
* bug fix: SenState = SK_SEN_IDLE when
* leaving SK_SEN_VALEXT state
- *
+ *
* Revision 1.10 1998/08/20 12:02:10 gklug
* fix: compiler warnings type mismatch
*
* Revision 1.9 1998/08/20 11:37:38 gklug
* chg: change Ioc to IoC
- *
+ *
* Revision 1.8 1998/08/19 12:20:58 gklug
* fix: remove struct from C files (see CCC)
- *
+ *
* Revision 1.7 1998/08/17 07:04:57 malthoff
* Take SkLm80RcvReg() function from ski2c.c.
* Add IoC parameter to BREAK_OR_WAIT() macro.
- *
+ *
* Revision 1.6 1998/08/14 07:11:28 malthoff
* remove pAc with pAC.
*
}
Val = Val * SK_LM80_TEMP_LSB;
SkI2cStop(IoC);
-
+
TempExt = (int)SkLm80RcvReg(IoC, LM80_ADDR, LM80_TEMP_CTRL);
-
+
if (Val > 0) {
Val += ((TempExt >> 7) * SK_LM80_TEMPEXT_LSB);
}
case LM80_VT3_IN:
Val = (int)SkI2cRcvByte(IoC, 1) * SK_LM80_VT_LSB;
break;
-
+
default:
Val = (int)SkI2cRcvByte(IoC, 1);
break;
pSen->SenState = SK_SEN_VALUE ;
BREAK_OR_WAIT(pAC, IoC, I2C_READ);
-
+
case SK_SEN_VALUE:
/* Read value from data register */
SK_IN32(IoC, B2_I2C_DATA, ((SK_U32 *)&Value));
-
+
Value &= 0xff; /* only least significant byte is valid */
/* Do NOT check the Value against the thresholds */
pSen->SenState = SK_SEN_VALEXT ;
BREAK_OR_WAIT(pAC, IoC, I2C_READ);
-
+
case SK_SEN_VALEXT:
/* Read value from data register */
SK_IN32(IoC, B2_I2C_DATA, ((SK_U32 *)&Value));
pSen->SenState = SK_SEN_IDLE ;
return(1);
-
+
default:
SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_I2C_E007, SKERR_I2C_E007MSG);
return(1);
* Purpose: Funktions to display statictic data
*
******************************************************************************/
-
+
/******************************************************************************
*
* (C)Copyright 1998-2003 SysKonnect GmbH.
* $Log: skproc.c,v $
* Revision 1.4 2003/02/25 14:16:37 mlindner
* Fix: Copyright statement
- *
+ *
* Revision 1.3 2002/10/02 12:59:51 mlindner
* Add: Support for Yukon
* Add: Speed check and setup
* Add: Merge source for kernel 2.2.x and 2.4.x
* Add: Read sensor names directly from VPD
* Fix: Volt values
- *
+ *
* Revision 1.2.2.7 2002/01/14 12:45:15 mlindner
* Fix: Editorial changes
- *
+ *
* Revision 1.2.2.6 2001/12/06 15:26:07 mlindner
* Fix: Return value of proc_read
- *
+ *
* Revision 1.2.2.5 2001/12/06 09:57:39 mlindner
* New ProcFs entries
- *
+ *
* Revision 1.2.2.4 2001/09/05 12:16:02 mlindner
* Add: New ProcFs entries
* Fix: Counter Errors (Jumbo == to long errors)
* Fix: Kernel error compilation
* Fix: too short counters
- *
+ *
* Revision 1.2.2.3 2001/06/25 07:26:26 mlindner
* Add: More error messages
- *
+ *
* Revision 1.2.2.2 2001/03/15 12:50:13 mlindner
* fix: ProcFS owner protection
- *
+ *
* Revision 1.2.2.1 2001/03/12 16:43:48 mlindner
* chg: 2.4 requirements for procfs
- *
+ *
* Revision 1.1 2001/01/22 14:15:31 mlindner
* added ProcFs functionality
* Dual Net functionality integrated
* Rlmt networks added
- *
+ *
*
******************************************************************************/
/*****************************************************************************
*
- * proc_read - print "summaries" entry
+ * proc_read - print "summaries" entry
*
* Description:
- * This function fills the proc entry with statistic data about
+ * This function fills the proc entry with statistic data about
* the ethernet device.
- *
+ *
*
* Returns: buffer with statistic data
- *
+ *
*/
int proc_read(char *buffer,
char **buffer_location,
SK_AC *pAC;
char test_buf[100];
char sens_msg[50];
- unsigned long Flags;
+ unsigned long Flags;
unsigned int Size;
struct SK_NET_DEVICE *next;
struct SK_NET_DEVICE *SkgeProcDev = SkGeRootDev;
spin_lock_irqsave(&pAC->SlowPathLock, Flags);
Size = SK_PNMI_STRUCT_SIZE;
- SkPnmiGetStruct(pAC, pAC->IoBase,
+ SkPnmiGetStruct(pAC, pAC->IoBase,
pPnmiStruct, &Size, t-1);
spin_unlock_irqrestore(&pAC->SlowPathLock, Flags);
-
+
if (strcmp(pAC->dev[t-1]->name, file->name) == 0) {
pPnmiStat = &pPnmiStruct->Stat[0];
- len = sprintf(buffer,
+ len = sprintf(buffer,
"\nDetailed statistic for device %s\n",
pAC->dev[t-1]->name);
len += sprintf(buffer + len,
"=======================================\n");
-
+
/* Board statistics */
- len += sprintf(buffer + len,
+ len += sprintf(buffer + len,
"\nBoard statistics\n\n");
len += sprintf(buffer + len,
"Active Port %c\n",
break;
}
}
-
+
/*Receive statistics */
- len += sprintf(buffer + len,
+ len += sprintf(buffer + len,
"\nReceive statistics\n\n");
len += sprintf(buffer + len,
SkNumber(test_buf, pPnmiStat->StatRxOkCts,
10,0,-1,0));
#if 0
- if (pAC->GIni.GP[0].PhyType == SK_PHY_XMAC &&
+ if (pAC->GIni.GP[0].PhyType == SK_PHY_XMAC &&
pAC->HWRevision < 12) {
- pPnmiStruct->InErrorsCts = pPnmiStruct->InErrorsCts -
+ pPnmiStruct->InErrorsCts = pPnmiStruct->InErrorsCts -
pPnmiStat->StatRxShortsCts;
pPnmiStat->StatRxShortsCts = 0;
}
#endif
- if (pNet->Mtu > 1500)
+ if (pNet->Mtu > 1500)
pPnmiStruct->InErrorsCts = pPnmiStruct->InErrorsCts -
pPnmiStat->StatRxTooLongCts;
len += sprintf(buffer + len,
" too long %s\n",
SkNumber(test_buf, pPnmiStat->StatRxTooLongCts,
- 10, 0, -1, 0));
+ 10, 0, -1, 0));
len += sprintf(buffer + len,
" carrier extension %s\n",
SkNumber(test_buf, pPnmiStat->StatRxCextCts,
- 10, 0, -1, 0));
+ 10, 0, -1, 0));
len += sprintf(buffer + len,
" too short %s\n",
SkNumber(test_buf, pPnmiStat->StatRxShortsCts,
- 10, 0, -1, 0));
+ 10, 0, -1, 0));
len += sprintf(buffer + len,
" symbol %s\n",
SkNumber(test_buf, pPnmiStat->StatRxSymbolCts,
- 10, 0, -1, 0));
+ 10, 0, -1, 0));
len += sprintf(buffer + len,
" LLC MAC size %s\n",
SkNumber(test_buf, pPnmiStat->StatRxIRLengthCts,
- 10, 0, -1, 0));
+ 10, 0, -1, 0));
len += sprintf(buffer + len,
" carrier event %s\n",
SkNumber(test_buf, pPnmiStat->StatRxCarrierCts,
- 10, 0, -1, 0));
+ 10, 0, -1, 0));
len += sprintf(buffer + len,
" jabber %s\n",
SkNumber(test_buf, pPnmiStat->StatRxJabberCts,
- 10, 0, -1, 0));
+ 10, 0, -1, 0));
/*Transmit statistics */
- len += sprintf(buffer + len,
+ len += sprintf(buffer + len,
"\nTransmit statistics\n\n");
-
+
len += sprintf(buffer + len,
"Transmited bytes %s\n",
SkNumber(test_buf, pPnmiStat->StatTxOctetsOkCts,
len += sprintf(buffer + len,
" window %ld\n",
pAC->stats.tx_window_errors);
-
+
}
}
SkgeProcDev = next;
}
-
-
-
/*****************************************************************************
*
* SkDoDiv - convert 64bit number
*str++ = tmp[i];
while (size-- > 0)
*str++ = ' ';
-
+
str[0] = '\0';
-
+
return strorg;
}
* $Log: skqueue.c,v $
* Revision 1.18 2002/05/07 14:11:11 rwahl
* Fixed Watcom Precompiler error.
- *
+ *
* Revision 1.17 2002/03/25 10:06:41 mkunz
* SkIgnoreEvent deleted
- *
+ *
* Revision 1.16 2002/03/15 10:51:59 mkunz
* Added event classes for link aggregation
- *
+ *
* Revision 1.15 1999/11/22 13:36:29 cgoos
* Changed license header to GPL.
- *
+ *
* Revision 1.14 1998/10/15 15:11:35 gklug
* fix: ID_sccs to SysKonnectFileId
- *
+ *
* Revision 1.13 1998/09/08 08:47:52 gklug
* add: init level handling
- *
+ *
* Revision 1.12 1998/09/08 07:43:20 gklug
* fix: Sirq Event function name
- *
+ *
* Revision 1.11 1998/09/08 05:54:34 gklug
* chg: define SK_CSUM is replaced by SK_USE_CSUM
- *
+ *
* Revision 1.10 1998/09/03 14:14:49 gklug
* add: CSUM and HWAC Eventclass and function.
- *
+ *
* Revision 1.9 1998/08/19 09:50:50 gklug
* fix: remove struct keyword from c-code (see CCC) add typedefs
- *
+ *
* Revision 1.8 1998/08/17 13:43:11 gklug
* chg: Parameter will be union of 64bit para, 2 times SK_U32 or SK_PTR
- *
+ *
* Revision 1.7 1998/08/14 07:09:11 gklug
* fix: chg pAc -> pAC
- *
+ *
* Revision 1.6 1998/08/11 12:13:14 gklug
* add: return code feature of Event service routines
* add: correct Error log calls
- *
+ *
* Revision 1.5 1998/08/07 12:53:45 gklug
* fix: first compiled version
- *
+ *
* Revision 1.4 1998/08/07 09:20:48 gklug
* adapt functions to C coding conventions.
- *
+ *
* Revision 1.3 1998/08/05 11:29:32 gklug
* rmv: Timer event entry. Timer will queue event directly
- *
+ *
* Revision 1.2 1998/07/31 11:22:40 gklug
* Initial version
- *
+ *
* Revision 1.1 1998/07/30 15:14:01 gklug
* Initial version. Adapted from SMT
- *
- *
+ *
+ *
*
******************************************************************************/
while (pEv != pAC->Event.EvPut) {
PRINTF("dispatch Class %d Event %d\n",pEv->Class,pEv->Event) ;
switch(Class = pEv->Class) {
-#ifndef SK_USE_LAC_EV
+#ifndef SK_USE_LAC_EV
case SKGE_RLMT : /* RLMT Event */
Rtv = SkRlmtEvent(pAC,Ioc,pEv->Event,pEv->Para);
break ;
case SKGE_DRV : /* Driver Event */
Rtv = SkDrvEvent(pAC,Ioc,pEv->Event,pEv->Para);
break ;
-#ifndef SK_USE_SW_TIMER
+#ifndef SK_USE_SW_TIMER
case SKGE_HWAC :
Rtv = SkGeSirqEvent(pAC,Ioc,pEv->Event,pEv->Para);
break ;
#else /* !SK_USE_SW_TIMER */
- case SKGE_SWT :
+ case SKGE_SWT :
Rtv = SkSwtEvent(pAC,Ioc,pEv->Event,pEv->Para);
break ;
#endif /* !SK_USE_SW_TIMER */
-#ifdef SK_USE_LAC_EV
+#ifdef SK_USE_LAC_EV
case SKGE_LACP :
Rtv = SkLacpEvent(pAC,Ioc,pEv->Event,pEv->Para);
break ;
* $Log: skrlmt.c,v $
* Revision 1.68 2003/01/31 15:26:56 rschmidt
* Added init for local variables in RlmtInit().
- *
+ *
* Revision 1.67 2003/01/31 14:12:41 mkunz
* single port adapter runs now with two identical MAC addresses
- *
+ *
* Revision 1.66 2002/09/23 15:14:19 rwahl
* - Reset broadcast timestamp on link down.
* - Editorial corrections.
- *
+ *
* Revision 1.65 2002/07/22 14:29:48 rwahl
* - Removed BRK statement from debug check.
- *
+ *
* Revision 1.64 2001/11/28 19:36:14 rwahl
* - RLMT Packets sent to an invalid MAC address in CLP/CLPSS mode
* (#10650).
* (no dependency to RLMT module).
* - Enabled dbg output for entry/exit of event functions.
* - Editorial changes.
- *
+ *
* Revision 1.63 2001/10/26 07:53:18 afischer
* Port switching bug in `check local link` mode
- *
+ *
* Revision 1.62 2001/07/03 12:16:30 mkunz
* New Flag ChgBcPrio (Change priority of last broadcast received)
- *
+ *
* Revision 1.61 2001/03/14 12:52:08 rassmann
* Fixed reporting of active port up/down to PNMI.
- *
+ *
* Revision 1.60 2001/02/21 16:02:25 gklug
* fix: when RLMT starts set Active Port for PNMI
- *
+ *
* Revision 1.59 2001/02/16 14:38:19 rassmann
* Initializing some pointers earlier in the init phase.
* Rx Mbufs are freed if the net which they belong to is stopped.
- *
+ *
* Revision 1.58 2001/02/14 14:06:31 rassmann
* Editorial changes.
- *
+ *
* Revision 1.57 2001/02/05 14:25:26 rassmann
* Prepared RLMT for transparent operation.
- *
+ *
* Revision 1.56 2001/01/30 10:29:09 rassmann
* Not checking switching befor RlmtStart.
* Editorial changes.
- *
+ *
* Revision 1.55 2001/01/22 13:41:38 rassmann
* Supporting two nets on dual-port adapters.
- *
+ *
* Revision 1.54 2000/11/30 13:25:07 rassmann
* Setting SK_TICK_INCR to 1 by default.
- *
+ *
* Revision 1.53 2000/11/30 10:48:07 cgoos
* Changed definition of SK_RLMT_BC_DELTA.
- *
+ *
* Revision 1.52 2000/11/27 12:50:03 rassmann
* Checking ports after receiving broadcasts.
- *
+ *
* Revision 1.51 2000/11/17 08:58:00 rassmann
* Moved CheckSwitch from SK_RLMT_PACKET_RECEIVED to SK_RLMT_TIM event.
- *
+ *
* Revision 1.50 2000/11/09 12:24:34 rassmann
* Indicating that segmentation check is not running anymore after
* SkRlmtCheckSeg().
* Restarting segmentation timer after segmentation log.
* Editorial changes.
- *
+ *
* Revision 1.49 1999/11/22 13:38:02 cgoos
* Changed license header to GPL.
* Added initialization to some variables to avoid compiler warnings.
- *
+ *
* Revision 1.48 1999/10/04 14:01:17 rassmann
* Corrected reaction to reception of BPDU frames (#10441).
- *
+ *
* Revision 1.47 1999/07/20 12:53:36 rassmann
* Fixed documentation errors for lookahead macros.
- *
+ *
* Revision 1.46 1999/05/28 13:29:16 rassmann
* Replaced C++-style comment.
- *
+ *
* Revision 1.45 1999/05/28 13:28:08 rassmann
* Corrected syntax error (xxx).
- *
+ *
* Revision 1.44 1999/05/28 11:15:54 rassmann
* Changed behaviour to reflect Design Spec v1.2.
* Controlling Link LED(s).
* Introduced RLMT Packet Version field in RLMT Packet.
* Newstyle lookahead macros (checking meta-information before looking at
* the packet).
- *
+ *
* Revision 1.43 1999/01/28 13:12:43 rassmann
* Corrected Lookahead (bug introduced in previous Rev.).
- *
+ *
* Revision 1.42 1999/01/28 12:50:41 rassmann
* Not using broadcast time stamps in CheckLinkState mode.
- *
+ *
* Revision 1.41 1999/01/27 14:13:02 rassmann
* Monitoring broadcast traffic.
* Switching more reliably and not too early if switch is
* configured for spanning tree.
- *
+ *
* Revision 1.40 1999/01/22 13:17:30 rassmann
* Informing PNMI of NET_UP.
* Clearing RLMT multicast addresses before setting them for the first time.
* Reporting segmentation earlier, setting a "quiet time"
* after a report.
- *
+ *
* Revision 1.39 1998/12/10 15:29:53 rassmann
* Corrected SuspectStatus in SkRlmtBuildCheckChain().
* Corrected CHECK_SEG mode.
- *
+ *
* Revision 1.38 1998/12/08 13:11:23 rassmann
* Stopping SegTimer at RlmtStop.
- *
+ *
* Revision 1.37 1998/12/07 16:51:42 rassmann
* Corrected comments.
- *
+ *
* Revision 1.36 1998/12/04 10:58:56 rassmann
* Setting next pointer to NULL when receiving.
- *
+ *
* Revision 1.35 1998/12/03 16:12:42 rassmann
* Ignoring/correcting illegal PrefPort values.
- *
+ *
* Revision 1.34 1998/12/01 11:45:35 rassmann
* Code cleanup.
- *
+ *
* Revision 1.33 1998/12/01 10:29:32 rassmann
* Starting standby ports before getting the net up.
* Checking if a port is started when the link comes up.
- *
+ *
* Revision 1.32 1998/11/30 16:19:50 rassmann
* New default for PortNoRx.
- *
+ *
* Revision 1.31 1998/11/27 19:17:13 rassmann
* Corrected handling of LINK_DOWN coming shortly after LINK_UP.
- *
+ *
* Revision 1.30 1998/11/24 12:37:31 rassmann
* Implemented segmentation check.
- *
+ *
* Revision 1.29 1998/11/18 13:04:32 rassmann
* Secured PortUpTimer event.
* Waiting longer before starting standby port(s).
- *
+ *
* Revision 1.28 1998/11/17 13:43:04 rassmann
* Handling (logical) tx failure.
* Sending packet on logical address after PORT_SWITCH.
- *
+ *
* Revision 1.27 1998/11/13 17:09:50 rassmann
* Secured some events against being called in wrong state.
- *
+ *
* Revision 1.26 1998/11/13 16:56:54 rassmann
* Added macro version of SkRlmtLookaheadPacket.
- *
+ *
* Revision 1.25 1998/11/06 18:06:04 rassmann
* Corrected timing when RLMT checks fail.
* Clearing tx counter earlier in periodical checks.
- *
+ *
* Revision 1.24 1998/11/05 10:37:27 rassmann
* Checking destination address in Lookahead.
- *
+ *
* Revision 1.23 1998/11/03 13:53:49 rassmann
* RLMT should switch now (at least in mode 3).
- *
+ *
* Revision 1.22 1998/10/29 14:34:49 rassmann
* Clearing SK_RLMT struct at startup.
* Initializing PortsUp during SK_RLMT_START.
- *
+ *
* Revision 1.21 1998/10/28 11:30:17 rassmann
* Default mode is now SK_RLMT_CHECK_LOC_LINK.
- *
+ *
* Revision 1.20 1998/10/26 16:02:03 rassmann
* Ignoring LINK_DOWN for links that are down.
- *
+ *
* Revision 1.19 1998/10/22 15:54:01 rassmann
* Corrected EtherLen.
* Starting Link Check when second port comes up.
- *
+ *
* Revision 1.18 1998/10/22 11:39:50 rassmann
* Corrected signed/unsigned mismatches.
* Corrected receive list handling and address recognition.
- *
+ *
* Revision 1.17 1998/10/19 17:01:20 rassmann
* More detailed checking of received packets.
- *
+ *
* Revision 1.16 1998/10/15 15:16:34 rassmann
* Finished Spanning Tree checking.
* Checked with lint.
- *
+ *
* Revision 1.15 1998/09/24 19:16:07 rassmann
* Code cleanup.
* Introduced Timer for PORT_DOWN due to no RX.
- *
+ *
* Revision 1.14 1998/09/18 20:27:14 rassmann
* Added address override.
- *
+ *
* Revision 1.13 1998/09/16 11:31:48 rassmann
* Including skdrv1st.h again. :(
- *
+ *
* Revision 1.12 1998/09/16 11:09:50 rassmann
* Syntax corrections.
- *
+ *
* Revision 1.11 1998/09/15 12:32:03 rassmann
* Syntax correction.
- *
+ *
* Revision 1.10 1998/09/15 11:28:49 rassmann
* Syntax corrections.
- *
+ *
* Revision 1.9 1998/09/14 17:07:37 rassmann
* Added code for port checking via LAN.
* Changed Mbuf definition.
- *
+ *
* Revision 1.8 1998/09/07 11:14:14 rassmann
* Syntax corrections.
- *
+ *
* Revision 1.7 1998/09/07 09:06:07 rassmann
* Syntax corrections.
- *
+ *
* Revision 1.6 1998/09/04 19:41:33 rassmann
* Syntax corrections.
* Started entering code for checking local links.
- *
+ *
* Revision 1.5 1998/09/04 12:14:27 rassmann
* Interface cleanup.
- *
+ *
* Revision 1.4 1998/09/02 16:55:28 rassmann
* Updated to reflect new DRV/HWAC/RLMT interface.
- *
+ *
* Revision 1.3 1998/08/27 14:29:03 rassmann
* Code cleanup.
- *
+ *
* Revision 1.2 1998/08/27 14:26:24 rassmann
* Updated interface.
- *
+ *
* Revision 1.1 1998/08/21 08:26:49 rassmann
* First public version.
*
}
(void)SkAddrMcClear(pAC, IoC, i, SK_ADDR_PERMANENT | SK_MC_SW_ONLY);
-
+
/* Add RLMT MC address. */
(void)SkAddrMcAdd(pAC, IoC, i, &SkRlmtMcAddr, SK_ADDR_PERMANENT);
(void)SkAddrMcUpdate(pAC, IoC, i);
}
- VirtualMacAddressSet = SK_FALSE;
+ VirtualMacAddressSet = SK_FALSE;
/* Read virtual MAC address from Control Register File. */
for (j = 0; j < SK_MAC_ADDR_LEN; j++) {
-
- SK_IN8(IoC, B2_MAC_1 + j, &VirtualMacAddress.a[j]);
- VirtualMacAddressSet |= VirtualMacAddress.a[j];
+
+ SK_IN8(IoC, B2_MAC_1 + j, &VirtualMacAddress.a[j]);
+ VirtualMacAddressSet |= VirtualMacAddress.a[j];
}
-
- PhysicalAMacAddressSet = SK_FALSE;
+
+ PhysicalAMacAddressSet = SK_FALSE;
/* Read physical MAC address for MAC A from Control Register File. */
for (j = 0; j < SK_MAC_ADDR_LEN; j++) {
-
- SK_IN8(IoC, B2_MAC_2 + j, &PhysicalAMacAddress.a[j]);
- PhysicalAMacAddressSet |= PhysicalAMacAddress.a[j];
+
+ SK_IN8(IoC, B2_MAC_2 + j, &PhysicalAMacAddress.a[j]);
+ PhysicalAMacAddressSet |= PhysicalAMacAddress.a[j];
}
- /* check if the two mac addresses contain reasonable values */
- if (!VirtualMacAddressSet || !PhysicalAMacAddressSet) {
+ /* check if the two mac addresses contain reasonable values */
+ if (!VirtualMacAddressSet || !PhysicalAMacAddressSet) {
- pAC->Rlmt.RlmtOff = SK_TRUE;
- }
+ pAC->Rlmt.RlmtOff = SK_TRUE;
+ }
- /* if the two mac addresses are equal switch off the RLMT_PRE_LOOKAHEAD
- and the RLMT_LOOKAHEAD macros */
- else if (SK_ADDR_EQUAL(PhysicalAMacAddress.a, VirtualMacAddress.a)) {
+ /* if the two mac addresses are equal switch off the RLMT_PRE_LOOKAHEAD
+ and the RLMT_LOOKAHEAD macros */
+ else if (SK_ADDR_EQUAL(PhysicalAMacAddress.a, VirtualMacAddress.a)) {
- pAC->Rlmt.RlmtOff = SK_TRUE;
- }
+ pAC->Rlmt.RlmtOff = SK_TRUE;
+ }
else {
pAC->Rlmt.RlmtOff = SK_FALSE;
}
FirstMacUp = NULL;
PrevMacUp = NULL;
-
+
if (!(pAC->Rlmt.Net[NetIdx].RlmtMode & SK_RLMT_CHECK_LOC_LINK)) {
for (i = 0; i < pAC->Rlmt.Net[i].NumPorts; i++) {
pAC->Rlmt.Net[NetIdx].Port[i]->PortsChecked = 0;
}
return; /* Done. */
}
-
+
SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
("SkRlmtBuildCheckChain.\n"))
#ifdef DEBUG
SK_U8 CheckSrc = 0;
SK_U8 CheckDest = 0;
-
+
for (i = 0; i < SK_MAC_ADDR_LEN; ++i) {
CheckSrc |= SrcAddr->a[i];
CheckDest |= DestAddr->a[i];
for (i = 0; i < 4; i++) {
pPacket->Random[i] = pAC->Rlmt.Port[PortNumber].Random[i];
}
-
+
SK_U16_TO_NETWORK_ORDER(
SK_RLMT_PACKET_VERSION, &pPacket->RlmtPacketVersion[0]);
if ((pRPort->PacketsPerTimeSlot - pRPort->BpduPacketsPerTimeSlot) != 0) {
SkRlmtPortReceives(pAC, IoC, PortNumber);
}
-
+
/* Check destination address. */
if (!SK_ADDR_EQUAL(pAPort->CurrentMacAddress.a, pRPacket->DstAddr) &&
PortNumber,
pRPort->PacketsPerTimeSlot - pRPort->BpduPacketsPerTimeSlot,
pRPort->PacketsPerTimeSlot))
-
+
SkRlmtPortReceives(pAC, IoC, PortNumber);
if (pAC->Rlmt.CheckSwitch) {
SkRlmtCheckSwitch(pAC, IoC, pRPort->Net->NetNumber);
BcTimeStamp = 0; /* Not totally necessary, but feeling better. */
PortFound = SK_FALSE;
-
+
/* Select port with the latest TimeStamp. */
for (i = 0; i < (SK_U32)pAC->GIni.GIMacsFound; i++) {
SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
("TimeStamp Port %d (Down: %d, NoRx: %d): %08x %08x.\n",
i,
- pAC->Rlmt.Port[i].PortDown, pAC->Rlmt.Port[i].PortNoRx,
+ pAC->Rlmt.Port[i].PortDown, pAC->Rlmt.Port[i].PortNoRx,
*((SK_U32*)(&pAC->Rlmt.Port[i].BcTimeStamp) + OFFS_HI32),
*((SK_U32*)(&pAC->Rlmt.Port[i].BcTimeStamp) + OFFS_LO32)))
pAC->Rlmt.Port[i].BcTimeStamp +
SK_RLMT_BC_DELTA > BcTimeStamp)) {
PortFound = SK_FALSE;
-
+
SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
("Port %d received a broadcast at a similar time.\n", i))
break;
/* check of ChgBcPrio flag added */
if ((pAC->Rlmt.Net[0].RlmtMode != SK_RLMT_MODE_CLS) &&
(!pAC->Rlmt.Net[0].ChgBcPrio)) {
-
+
if (!PortFound) {
PortFound = SkRlmtSelectBcRx(
pAC, IoC, Active, PrefPort, &Para.Para32[1]);
break;
}
}
-
+
if (!Equal) {
SK_ERR_LOG(pAC, SK_ERRCL_COMM, SKERR_RLMT_E005, SKERR_RLMT_E005_MSG);
Para.Para32[0] = NetIdx;
Para2.Para32[1] = (SK_U32)-1;
SkTimerStart(pAC, IoC, &pRPort->UpTimer, SK_RLMT_PORTUP_TIM_VAL,
SKGE_RLMT, SK_RLMT_PORTUP_TIM, Para2);
-
+
/* Later: if (pAC->Rlmt.RlmtMode & SK_RLMT_CHECK_LOC_LINK) && */
if ((pRPort->Net->RlmtMode & SK_RLMT_TRANSPARENT) == 0 &&
(pRPort->Net->RlmtMode & SK_RLMT_CHECK_LINK) != 0 &&
("SK_RLMT_PORTDOWN* Event (%d) EMPTY.\n", Event))
return;
}
-
+
/* Stop port's timers. */
SkTimerStop(pAC, IoC, &pRPort->UpTimer);
SkTimerStop(pAC, IoC, &pRPort->DownRxTimer);
}
}
#endif /* xDEBUG */
-
+
SkRlmtCheckSeg(pAC, IoC, Para.Para32[0]);
SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
SK_MBUF *pNextMb;
SK_U32 NetNumber;
-
+
SK_DBG_MSG(pAC, SK_DBGMOD_RLMT, SK_DBGCAT_CTRL,
("SK_RLMT_PACKET_RECEIVED Event BEGIN.\n"))
pAC->Rlmt.Net[1].NumPorts = pAC->GIni.GIMacsFound - 1;
pAC->Rlmt.Net[0].NumPorts =
pAC->GIni.GIMacsFound - pAC->Rlmt.Net[1].NumPorts;
-
+
pAC->Rlmt.NumNets = Para.Para32[0];
for (i = 0; (SK_U32)i < pAC->Rlmt.NumNets; i++) {
pAC->Rlmt.Net[i].RlmtState = SK_RLMT_RS_INIT;
SK_EVPARA Para) /* Event-specific parameter */
{
switch (Event) {
-
+
/* ----- PORT events ----- */
case SK_RLMT_PORTSTART_TIM: /* From RLMT via TIME. */
* $Log: sktimer.c,v $
* Revision 1.12 1999/11/22 13:38:51 cgoos
* Changed license header to GPL.
- *
+ *
* Revision 1.11 1998/12/17 13:24:13 gklug
* fix: restart problem: do NOT destroy timer queue if init 1 is done
- *
+ *
* Revision 1.10 1998/10/15 15:11:36 gklug
* fix: ID_sccs to SysKonnectFileId
- *
+ *
* Revision 1.9 1998/09/15 15:15:04 cgoos
* Changed TRUE/FALSE to SK_TRUE/SK_FALSE
- *
+ *
* Revision 1.8 1998/09/08 08:47:55 gklug
* add: init level handling
- *
+ *
* Revision 1.7 1998/08/19 09:50:53 gklug
* fix: remove struct keyword from c-code (see CCC) add typedefs
- *
+ *
* Revision 1.6 1998/08/17 13:43:13 gklug
* chg: Parameter will be union of 64bit para, 2 times SK_U32 or SK_PTR
- *
+ *
* Revision 1.5 1998/08/14 07:09:14 gklug
* fix: chg pAc -> pAC
- *
+ *
* Revision 1.4 1998/08/07 12:53:46 gklug
* fix: first compiled version
- *
+ *
* Revision 1.3 1998/08/07 09:31:53 gklug
* fix: delta spelling
- *
+ *
* Revision 1.2 1998/08/07 09:31:02 gklug
* adapt functions to new c coding conventions
* rmv: "fast" handling
* chg: inserting of new timer in queue.
* chg: event queue generation when timer runs out
- *
+ *
* Revision 1.1 1998/08/05 11:27:55 gklug
* first version: adapted from SMT
- *
- *
- *
+ *
+ *
+ *
*
******************************************************************************/
* Replaced check for PCI device Id from YUKON with GENESIS
* to set the VPD size in VpdInit()
* Editorial changes
- *
+ *
* Revision 1.36 2002/11/14 15:16:56 gheinig
* Added const specifier to key and buf parameters for VpdPara, VpdRead
* and VpdWrite for Diag 7 GUI
- *
+ *
* Revision 1.35 2002/10/21 14:31:59 gheinig
* Took out CVS web garbage at head of file
- *
+ *
* Revision 1.34 2002/10/21 11:47:24 gheinig
* Reverted to version 1.32 due to unwanted commit
- *
+ *
* Revision 1.32 2002/10/14 16:04:29 rschmidt
* Added saving of VPD ROM Size from PCI_OUR_REG_2
* Avoid reading of PCI_OUR_REG_2 in VpdTransferBlock()
* Editorial changes
- *
+ *
* Revision 1.31 2002/09/10 09:21:32 mkarl
* Replaced all if(GIChipId == CHIP_ID_GENESIS) with new entry GIGenesis
- *
+ *
* Revision 1.30 2002/09/09 14:43:03 mkarl
* changes for diagnostics in order to read VPD data before the adapter
* has been initialized
* editorial changes
- *
+ *
* Revision 1.29 2002/07/26 13:20:43 mkarl
* added Yukon support
* save size of VPD in pAC->vpd.vpd_size
- *
+ *
* Revision 1.28 2002/04/02 15:31:47 afischer
* Bug fix in VpdWait()
- *
+ *
* Revision 1.27 2000/08/10 11:29:06 rassmann
* Editorial changes.
* Preserving 32-bit alignment in structs for the adapter context.
* Removed unused function VpdWriteDword() (#if 0).
* Made VpdReadKeyword() available for SKDIAG only.
- *
+ *
* Revision 1.26 2000/06/13 08:00:01 mkarl
* additional cast to avoid compile problems in 64 bit environment
- *
+ *
* Revision 1.25 1999/11/22 13:39:32 cgoos
* Changed license header to GPL.
- *
+ *
* Revision 1.24 1999/03/11 14:25:49 malthoff
* Replace __STDC__ with SK_KR_PROTO.
- *
+ *
* Revision 1.23 1999/01/11 15:13:11 gklug
* fix: syntax error
- *
+ *
* Revision 1.22 1998/10/30 06:41:15 gklug
* rmv: WARNING
- *
+ *
* Revision 1.21 1998/10/29 07:15:14 gklug
* fix: Write Stream function needs verify.
- *
+ *
* Revision 1.20 1998/10/28 18:05:08 gklug
* chg: no DEBUG in VpdMayWrite
- *
+ *
* Revision 1.19 1998/10/28 15:56:11 gklug
* fix: Return len at end of ReadStream
* fix: Write even less than 4 bytes correctly
- *
+ *
* Revision 1.18 1998/10/28 09:00:47 gklug
* fix: unreferenced local vars
- *
+ *
* Revision 1.17 1998/10/28 08:25:45 gklug
* fix: WARNING
- *
+ *
* Revision 1.16 1998/10/28 08:17:30 gklug
* fix: typo
- *
+ *
* Revision 1.15 1998/10/28 07:50:32 gklug
* fix: typo
- *
+ *
* Revision 1.14 1998/10/28 07:20:38 gklug
* chg: Interface functions to use IoC as parameter as well
* fix: VpdRead/WriteDWord now returns SK_U32
* add: VpdRead/Write Stream functions to r/w a stream of data
* fix: VpdTransferBlock swapped illegal
* add: VpdMayWrite
- *
+ *
* Revision 1.13 1998/10/22 10:02:37 gklug
* fix: SysKonnectFileId typo
- *
+ *
* Revision 1.12 1998/10/20 10:01:01 gklug
* fix: parameter to SkOsGetTime
- *
+ *
* Revision 1.11 1998/10/15 12:51:48 malthoff
* Remove unrequired parameter p in vpd_setup_para().
- *
+ *
* Revision 1.10 1998/10/08 14:52:43 malthoff
* Remove CvsId by SysKonnectFileId.
- *
+ *
* Revision 1.9 1998/09/16 07:33:52 malthoff
* replace memcmp() by SK_MEMCMP and
* memcpy() by SK_MEMCPY() to be
* independent from the 'C' Standard Library.
- *
+ *
* Revision 1.8 1998/08/19 12:52:35 malthoff
* compiler fix: use SK_VPD_KEY instead of S_VPD.
- *
+ *
* Revision 1.7 1998/08/19 08:14:01 gklug
* fix: remove struct keyword as much as possible from the C-code (see CCC)
- *
+ *
* Revision 1.6 1998/08/18 13:03:58 gklug
* SkOsGetTime now returns SK_U64
- *
+ *
* Revision 1.5 1998/08/18 08:17:29 malthoff
* Ensure we issue a VPD read in vpd_read_dword().
* Discard all VPD keywords other than Vx or Yx, where
* x is '0..9' or 'A..Z'.
- *
+ *
* Revision 1.4 1998/07/03 14:52:19 malthoff
* Add category SK_DBGCAT_FATAL to some debug macros.
* bug fix: correct the keyword name check in vpd_write().
- *
+ *
* Revision 1.3 1998/06/26 11:16:53 malthoff
* Correct the modified File Identifier.
- *
+ *
* Revision 1.2 1998/06/26 11:13:43 malthoff
* Modify the File Identifier.
- *
+ *
* Revision 1.1 1998/06/19 14:11:08 malthoff
* Created, Tests with AIX were performed successfully
- *
+ *
*
******************************************************************************/
("ERROR:VPD wait timeout\n"));
return(1);
}
-
+
VPD_IN16(pAC, IoC, PCI_VPD_ADR_REG, &state);
-
+
SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
("state = %x, event %x\n",state,event));
} while((int)(state & PCI_VPD_FLAG) == event);
Rtv = 0;
VPD_IN32(pAC, IoC, PCI_VPD_DAT_REG, &Rtv);
-
+
SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
("VPD read dword data = 0x%x\n",Rtv));
return(Rtv);
}
for (j = 0; j <= (int)(i%sizeof(SK_U32)); j++, pComp++) {
-
+
VPD_IN8(pAC, IoC, PCI_VPD_DAT_REG + j, &Data);
-
+
if (Data != *pComp) {
/* Verify Error */
SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
return(Len);
}
-
+
/*
* Read one Stream of 'len' bytes of VPD data, starting at 'addr' from
return(0);
vpd_rom_size = pAC->vpd.rom_size;
-
+
if (addr > vpd_rom_size - 4) {
SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
("Address error: 0x%x, exp. < 0x%x\n",
addr, vpd_rom_size - 4));
return(0);
}
-
+
if (addr + len > vpd_rom_size) {
len = vpd_rom_size - addr;
SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR,
SK_U32 our_reg2;
SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_INIT, ("VpdInit .. "));
-
+
VPD_IN16(pAC, IoC, PCI_DEVICE_ID, &dev_id);
-
+
VPD_IN32(pAC, IoC, PCI_OUR_REG_2, &our_reg2);
-
+
pAC->vpd.rom_size = 256 << ((our_reg2 & PCI_VPD_ROM_SZ) >> 14);
-
+
/*
* this function might get used before the hardware is initialized
* therefore we cannot always trust in GIChipId
("Block Read Error\n"));
return(1);
}
-
+
pAC->vpd.vpd_size = vpd_size;
/* find the end tag of the RO area */
("Encoding Error: RV Tag not found\n"));
return(1);
}
-
+
if (r->p_val + r->p_len > pAC->vpd.vpd_buf + vpd_size/2) {
SK_DBG_MSG(pAC,SK_DBGMOD_VPD,SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
("Encoding Error: Invalid VPD struct size\n"));
for (i = 0, x = 0; (unsigned)i <= (unsigned)vpd_size/2 - r->p_len; i++) {
x += pAC->vpd.vpd_buf[i];
}
-
+
if (x != 0) {
/* checksum error */
SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
("Encoding Error: RV Tag not found\n"));
return(1);
}
-
+
if (r->p_val < pAC->vpd.vpd_buf + vpd_size/2) {
SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_ERR | SK_DBGCAT_FATAL,
("Encoding Error: Invalid VPD struct size\n"));
SK_DBG_MSG(pAC, SK_DBGMOD_VPD, SK_DBGCAT_CTRL,
("VPD setup para key = %s, val = %s\n",key,buf));
-
+
vpd_size = pAC->vpd.vpd_size;
rtv = 0;
}
-
/*
* Read the contents of the VPD EEPROM and copy it to the VPD buffer
* if not already done. If the keyword "VF" is not present it will be
* Disabled auto-update for speed, duplex and flow-control when
* auto-negotiation is not enabled (Bug Id #10766).
* Editorial changes.
- *
+ *
* Revision 1.90 2003/01/29 13:35:19 rschmidt
* Increment Rx FIFO Overflow counter only in DEBUG-mode.
* Corrected define for blinking active LED.
- *
+ *
* Revision 1.89 2003/01/28 16:37:45 rschmidt
* Changed init for blinking active LED
- *
+ *
* Revision 1.88 2003/01/28 10:09:38 rschmidt
* Added debug outputs in SkGmInitMac().
* Added customized init of LED registers in SkGmInitPhyMarv(),
* for blinking active LED (#ifdef ACT_LED_BLINK) and
* for normal duplex LED (#ifdef DUP_LED_NORMAL).
* Editorial changes.
- *
+ *
* Revision 1.87 2002/12/10 14:39:05 rschmidt
* Improved initialization of GPHY in SkGmInitPhyMarv().
* Editorial changes.
- *
+ *
* Revision 1.86 2002/12/09 15:01:12 rschmidt
* Added setup of Ext. PHY Specific Ctrl Reg (downshift feature).
- *
+ *
* Revision 1.85 2002/12/05 14:09:16 rschmidt
* Improved avoiding endless loop in SkGmPhyWrite(), SkGmPhyWrite().
* Added additional advertising for 10Base-T when 100Base-T is selected.
* Added case SK_PHY_MARV_FIBER for YUKON Fiber adapter.
* Editorial changes.
- *
+ *
* Revision 1.84 2002/11/15 12:50:09 rschmidt
* Changed SkGmCableDiagStatus() when getting results.
- *
+ *
* Revision 1.83 2002/11/13 10:28:29 rschmidt
* Added some typecasts to avoid compiler warnings.
- *
+ *
* Revision 1.82 2002/11/13 09:20:46 rschmidt
* Replaced for(..) with do {} while (...) in SkXmUpdateStats().
* Replaced 2 macros GM_IN16() with 1 GM_IN32() in SkGmMacStatistic().
* Added SkGmCableDiagStatus() for Virtual Cable Test (VCT).
* Editorial changes.
- *
+ *
* Revision 1.81 2002/10/28 14:28:08 rschmidt
* Changed MAC address setup for GMAC in SkGmInitMac().
* Optimized handling of counter overflow IRQ in SkGmOverflowStatus().
* Editorial changes.
- *
+ *
* Revision 1.80 2002/10/14 15:29:44 rschmidt
* Corrected disabling of all PHY IRQs.
* Added WA for deviation #16 (address used for pause packets).
* SkXmTimeStamp() replaced by SkMacTimeStamp().
* Added clearing of GMAC Tx FIFO Underrun IRQ in SkGmIrq().
* Editorial changes.
- *
+ *
* Revision 1.79 2002/10/10 15:55:36 mkarl
* changes for PLinkSpeedUsed
- *
+ *
* Revision 1.78 2002/09/12 09:39:51 rwahl
* Removed deactivate code for SIRQ overflow event separate for TX/RX.
- *
+ *
* Revision 1.77 2002/09/09 12:26:37 mkarl
* added handling for Yukon to SkXmTimeStamp
- *
+ *
* Revision 1.76 2002/08/21 16:41:16 rschmidt
* Added bit GPC_ENA_XC (Enable MDI crossover) in HWCFG_MODE.
* Added forced speed settings in SkGmInitPhyMarv().
* Added settings of full/half duplex capabilities for YUKON Fiber.
* Editorial changes.
- *
+ *
* Revision 1.75 2002/08/16 15:12:01 rschmidt
* Replaced all if(GIChipId == CHIP_ID_GENESIS) with new entry GIGenesis.
* Added function SkMacHashing() for ADDR-Module.
* Changed initialization of GPHY in SkGmInitPhyMarv().
* Changed check of parameter in SkXmMacStatistic().
* Editorial changes.
- *
+ *
* Revision 1.74 2002/08/12 14:00:17 rschmidt
* Replaced usage of Broadcom PHY Ids with defines.
* Corrected error messages in SkGmMacStatistic().
* Made SkMacPromiscMode() public for ADDR-Modul.
* Editorial changes.
- *
+ *
* Revision 1.73 2002/08/08 16:26:24 rschmidt
* Improved reset sequence for YUKON in SkGmHardRst() and SkGmInitMac().
* Replaced XMAC Rx High Watermark init value with SK_XM_RX_HI_WM.
* Editorial changes.
- *
+ *
* Revision 1.72 2002/07/24 15:11:19 rschmidt
* Fixed wrong placement of parenthesis.
* Editorial changes.
- *
+ *
* Revision 1.71 2002/07/23 16:05:18 rschmidt
* Added global functions for PHY: SkGePhyRead(), SkGePhyWrite().
* Fixed Tx Counter Overflow IRQ (Bug ID #10730).
* Editorial changes.
- *
+ *
* Revision 1.70 2002/07/18 14:27:27 rwahl
* Fixed syntax error.
- *
+ *
* Revision 1.69 2002/07/17 17:08:47 rwahl
* Fixed check in SkXmMacStatistic().
- *
+ *
* Revision 1.68 2002/07/16 07:35:24 rwahl
* Removed check for cleared mib counter in SkGmResetCounter().
- *
+ *
* Revision 1.67 2002/07/15 18:35:56 rwahl
* Added SkXmUpdateStats(), SkGmUpdateStats(), SkXmMacStatistic(),
* SkGmMacStatistic(), SkXmResetCounter(), SkGmResetCounter(),
* RX & TX.
* Changes to SkGmInitMac(): call to SkGmResetCounter().
* Editorial changes.
- *
+ *
* Revision 1.66 2002/07/15 15:59:30 rschmidt
* Added PHY Address in SkXmPhyRead(), SkXmPhyWrite().
* Added MIB Clear Counter in SkGmInitMac().
* Reset all Multicast filtering Hash reg. in SkGmInitMac().
* Added new function: SkGmGetMuxConfig().
* Editorial changes.
- *
+ *
* Revision 1.65 2002/06/10 09:35:39 rschmidt
* Replaced C++ comments (//).
* Added #define VCPU around VCPUwaitTime.
* Editorial changes.
- *
+ *
* Revision 1.64 2002/06/05 08:41:10 rschmidt
* Added function for XMAC2: SkXmTimeStamp().
* Added function for YUKON: SkGmSetRxCmd().
* Fixed wrong variable in SkXmAutoNegLipaXmac() (debug mode).
* SkXmRxTxEnable() replaced by SkMacRxTxEnable().
* Editorial changes.
- *
+ *
* Revision 1.63 2002/04/25 13:04:44 rschmidt
* Changes for handling YUKON.
* Use of #ifdef OTHER_PHY to eliminate code for unused Phy types.
* SkGmAutoNegDoneMarv(), SkGmPhyRead(), SkGmPhyWrite().
* Changes for V-CPU support.
* Editorial changes.
- *
+ *
* Revision 1.62 2001/08/06 09:50:14 rschmidt
* Workaround BCOM Errata #1 for the C5 type.
* Editorial changes.
- *
+ *
* Revision 1.61 2001/02/09 15:40:59 rassmann
* Editorial changes.
- *
+ *
* Revision 1.60 2001/02/07 15:02:01 cgoos
* Added workaround for Fujitsu switch link down.
- *
+ *
* Revision 1.59 2001/01/10 09:38:06 cgoos
* Fixed Broadcom C0/A1 Id check for workaround.
- *
+ *
* Revision 1.58 2000/11/29 11:30:38 cgoos
* Changed DEBUG sections with NW output to xDEBUG
- *
+ *
* Revision 1.57 2000/11/27 12:40:40 rassmann
* Suppressing preamble after first access to BCom, not before (#10556).
- *
+ *
* Revision 1.56 2000/11/09 12:32:48 rassmann
* Renamed variables.
- *
+ *
* Revision 1.55 2000/11/09 11:30:10 rassmann
* WA: Waiting after releasing reset until BCom chip is accessible.
- *
+ *
* Revision 1.54 2000/10/02 14:10:27 rassmann
* Reading BCOM PHY after releasing reset until it returns a valid value.
- *
+ *
* Revision 1.53 2000/07/27 12:22:11 gklug
* fix: possible endless loop in XmHardRst.
- *
+ *
* Revision 1.52 2000/05/22 08:48:31 malthoff
* Fix: #10523 errata valid for all BCOM PHYs.
- *
+ *
* Revision 1.51 2000/05/17 12:52:18 malthoff
* Fixes BCom link errata (#10523).
- *
+ *
* Revision 1.50 1999/11/22 13:40:14 cgoos
* Changed license header to GPL.
- *
+ *
* Revision 1.49 1999/11/22 08:12:13 malthoff
* Add workaround for power consumption feature of BCom C0 chip.
- *
+ *
* Revision 1.48 1999/11/16 08:39:01 malthoff
* Fix: MDIO preamble suppression is port dependent.
- *
+ *
* Revision 1.47 1999/08/27 08:55:35 malthoff
* 1000BT: Optimizing MDIO transfer by oppressing MDIO preamble.
- *
+ *
* Revision 1.46 1999/08/13 11:01:12 malthoff
* Fix for 1000BT: pFlowCtrlMode was not set correctly.
- *
+ *
* Revision 1.45 1999/08/12 19:18:28 malthoff
* 1000BT Fixes: Do not owerwrite XM_MMU_CMD.
* Do not execute BCOM A1 workaround for B1 chips.
* Fix pause frame setting.
* Always set PHY_B_AC_TX_TST in PHY_BCOM_AUX_CTRL.
- *
+ *
* Revision 1.44 1999/08/03 15:23:48 cgoos
* Fixed setting of PHY interrupt mask in half duplex mode.
- *
+ *
* Revision 1.43 1999/08/03 15:22:17 cgoos
* Added some debug output.
* Disabled XMac GP0 interrupt for external PHYs.
- *
+ *
* Revision 1.42 1999/08/02 08:39:23 malthoff
* BCOM PHY: TX LED: To get the mono flop behaviour it is required
* to set the LED Traffic Mode bit in PHY_BCOM_P_EXT_CTRL.
- *
+ *
* Revision 1.41 1999/07/30 06:54:31 malthoff
* Add temp. workarounds for the BCOM Phy revision A1.
- *
+ *
* Revision 1.40 1999/06/01 07:43:26 cgoos
* Changed Link Mode Status in SkXmAutoNegDone... from FULL/HALF to
* AUTOFULL/AUTOHALF.
- *
+ *
* Revision 1.39 1999/05/19 07:29:51 cgoos
* Changes for 1000Base-T.
- *
+ *
* Revision 1.38 1999/04/08 14:35:10 malthoff
* Add code for enabling signal detect. Enabling signal detect is disabled.
- *
+ *
* Revision 1.37 1999/03/12 13:42:54 malthoff
* Add: Jumbo Frame Support.
* Add: Receive modes SK_LENERR_OK_ON/OFF and
* SK_BIG_PK_OK_ON/OFF in SkXmSetRxCmd().
- *
+ *
* Revision 1.36 1999/03/08 10:10:55 gklug
* fix: AutoSensing did switch to next mode even if LiPa indicated offline
*
#endif /* OTHER_PHY */
-
/******************************************************************************
*
* SkXmPhyRead() - Read from XMAC PHY register
SK_GEPORT *pPrt;
pPrt = &pAC->GIni.GP[Port];
-
+
/* write the PHY register's address */
XM_OUT16(IoC, Port, XM_PHY_ADDR, PhyReg | pPrt->PhyAddr);
-
+
/* get the PHY register's value */
XM_IN16(IoC, Port, XM_PHY_DATA, pVal);
-
+
if (pPrt->PhyType != SK_PHY_XMAC) {
do {
XM_IN16(IoC, Port, XM_MMU_CMD, &Mmu);
SK_GEPORT *pPrt;
pPrt = &pAC->GIni.GP[Port];
-
+
if (pPrt->PhyType != SK_PHY_XMAC) {
do {
XM_IN16(IoC, Port, XM_MMU_CMD, &Mmu);
/* wait until 'Busy' is cleared */
} while ((Mmu & XM_MMU_PHY_BUSY) != 0);
}
-
+
/* write the PHY register's address */
XM_OUT16(IoC, Port, XM_PHY_ADDR, PhyReg | pPrt->PhyAddr);
-
+
/* write the PHY register's value */
XM_OUT16(IoC, Port, XM_PHY_DATA, Val);
-
+
if (pPrt->PhyType != SK_PHY_XMAC) {
do {
XM_IN16(IoC, Port, XM_MMU_CMD, &Mmu);
#ifdef VCPU
u_long SimCyle;
u_long SimLowTime;
-
+
VCPUgetTime(&SimCyle, &SimLowTime);
VCPUprintf(0, "SkGmPhyRead(%u), SimCyle=%u, SimLowTime=%u\n",
PhyReg, SimCyle, SimLowTime);
#endif /* VCPU */
-
+
pPrt = &pAC->GIni.GP[Port];
-
+
/* set PHY-Register offset and 'Read' OpCode (= 1) */
*pVal = (SK_U16)(GM_SMI_CT_PHY_AD(pPrt->PhyAddr) |
GM_SMI_CT_REG_AD(PhyReg) | GM_SMI_CT_OP_RD);
GM_OUT16(IoC, Port, GM_SMI_CTRL, *pVal);
GM_IN16(IoC, Port, GM_SMI_CTRL, &Ctrl);
-
+
/* additional check for MDC/MDIO activity */
if ((Ctrl & GM_SMI_CT_BUSY) == 0) {
*pVal = 0;
}
*pVal |= GM_SMI_CT_BUSY;
-
+
do {
#ifdef VCPU
VCPUwaitTime(1000);
/* wait until 'ReadValid' is set */
} while (Ctrl == *pVal);
-
+
/* get the PHY register's value */
GM_IN16(IoC, Port, GM_SMI_DATA, pVal);
SK_U32 DWord;
u_long SimCyle;
u_long SimLowTime;
-
+
VCPUgetTime(&SimCyle, &SimLowTime);
VCPUprintf(0, "SkGmPhyWrite(Reg=%u, Val=0x%04x), SimCyle=%u, SimLowTime=%u\n",
PhyReg, Val, SimCyle, SimLowTime);
#endif /* VCPU */
-
+
pPrt = &pAC->GIni.GP[Port];
-
+
/* write the PHY register's value */
GM_OUT16(IoC, Port, GM_SMI_DATA, Val);
-
+
/* set PHY-Register offset and 'Write' OpCode (= 0) */
Val = GM_SMI_CT_PHY_AD(pPrt->PhyAddr) | GM_SMI_CT_REG_AD(PhyReg);
GM_OUT16(IoC, Port, GM_SMI_CTRL, Val);
GM_IN16(IoC, Port, GM_SMI_CTRL, &Ctrl);
-
+
/* additional check for MDC/MDIO activity */
if ((Ctrl & GM_SMI_CT_BUSY) == 0) {
return;
}
-
+
Val |= GM_SMI_CT_BUSY;
do {
/* wait until 'Busy' is cleared */
} while (Ctrl == Val);
-
+
#ifdef VCPU
VCPUgetTime(&SimCyle, &SimLowTime);
VCPUprintf(0, "VCPUgetTime(), SimCyle=%u, SimLowTime=%u\n",
else {
r_func = SkGmPhyRead;
}
-
+
r_func(pAC, IoC, Port, PhyReg, pVal);
} /* SkGePhyRead */
else {
w_func = SkGmPhyWrite;
}
-
+
w_func(pAC, IoC, Port, PhyReg, Val);
} /* SkGePhyWrite */
*
* Description:
* enables / disables promiscuous mode by setting Mode Register (XMAC) or
- * Receive Control Register (GMAC) dep. on board type
+ * Receive Control Register (GMAC) dep. on board type
*
* Returns:
* nothing
SK_U32 MdReg;
if (pAC->GIni.GIGenesis) {
-
+
XM_IN32(IoC, Port, XM_MODE, &MdReg);
/* enable or disable promiscuous mode */
if (Enable) {
XM_OUT32(IoC, Port, XM_MODE, MdReg);
}
else {
-
+
GM_IN16(IoC, Port, GM_RX_CTRL, &RcReg);
-
+
/* enable or disable unicast and multicast filtering */
if (Enable) {
RcReg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
*
* Description:
* enables / disables hashing by setting Mode Register (XMAC) or
- * Receive Control Register (GMAC) dep. on board type
+ * Receive Control Register (GMAC) dep. on board type
*
* Returns:
* nothing
SK_U32 MdReg;
if (pAC->GIni.GIGenesis) {
-
+
XM_IN32(IoC, Port, XM_MODE, &MdReg);
/* enable or disable hashing */
if (Enable) {
XM_OUT32(IoC, Port, XM_MODE, MdReg);
}
else {
-
+
GM_IN16(IoC, Port, GM_RX_CTRL, &RcReg);
-
+
/* enable or disable multicast filtering */
if (Enable) {
RcReg |= GM_RXCR_MCF_ENA;
XM_IN16(IoC, Port, XM_RX_CMD, &OldRxCmd);
RxCmd = OldRxCmd;
-
+
switch (Mode & (SK_STRIP_FCS_ON | SK_STRIP_FCS_OFF)) {
case SK_STRIP_FCS_ON:
RxCmd |= XM_RX_STRIP_FCS;
SK_U16 RxCmd;
if ((Mode & (SK_STRIP_FCS_ON | SK_STRIP_FCS_OFF)) != 0) {
-
+
GM_IN16(IoC, Port, GM_RX_CTRL, &OldRxCmd);
RxCmd = OldRxCmd;
}
if ((Mode & (SK_BIG_PK_OK_ON | SK_BIG_PK_OK_OFF)) != 0) {
-
+
GM_IN16(IoC, Port, GM_SERIAL_MODE, &OldRxCmd);
RxCmd = OldRxCmd;
int Mode) /* Rx Mode */
{
if (pAC->GIni.GIGenesis) {
-
+
SkXmSetRxCmd(pAC, IoC, Port, Mode);
}
else {
-
+
SkGmSetRxCmd(pAC, IoC, Port, Mode);
}
} /* SkMacSetRxCmd */
SK_U16 Word;
if (pAC->GIni.GIGenesis) {
-
+
XM_IN16(IoC, Port, XM_TX_CMD, &Word);
if (Enable) {
XM_OUT16(pAC, Port, XM_TX_CMD, Word);
}
else {
-
+
GM_IN16(IoC, Port, GM_TX_CTRL, &Word);
-
+
if (Enable) {
Word &= ~GM_TXCR_CRC_DIS;
}
SK_U32 MdReg;
if (pAC->GIni.GIGenesis) {
-
+
XM_IN32(IoC, Port, XM_MODE, &MdReg);
XM_OUT32(IoC, Port, XM_MODE, MdReg | XM_MD_FTF);
int Port) /* Port Index (MAC_1 + n) */
{
SK_U16 ZeroAddr[4] = {0x0000, 0x0000, 0x0000, 0x0000};
-
+
/* reset the statistics module */
XM_OUT32(IoC, Port, XM_GP_PORT, XM_GP_RES_STAT);
/* disable all XMAC IRQs */
XM_OUT16(IoC, Port, XM_IMSK, 0xffff);
-
+
XM_OUT32(IoC, Port, XM_MODE, 0); /* clear Mode Reg */
-
+
XM_OUT16(IoC, Port, XM_TX_CMD, 0); /* reset TX CMD Reg */
XM_OUT16(IoC, Port, XM_RX_CMD, 0); /* reset RX CMD Reg */
-
+
/* disable all PHY IRQs */
switch (pAC->GIni.GP[Port].PhyType) {
case SK_PHY_BCOM:
/* clear the Exact Match Address registers */
SkXmClrExactAddr(pAC, IoC, Port, 0, 15);
-
+
/* clear the Source Check Address registers */
XM_OUTHASH(IoC, Port, XM_SRC_CHK, &ZeroAddr);
}
SK_OUT16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
-
+
SK_IN16(IoC, MR_ADDR(Port, TX_MFF_CTRL1), &Word);
-
+
} while ((Word & MFF_SET_MAC_RST) == 0);
}
/* disable all GMAC IRQs */
SK_OUT8(IoC, GMAC_IRQ_MSK, 0);
-
+
/* disable all PHY IRQs */
SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_INT_MASK, 0);
-
+
/* clear the Hash Register */
GM_OUTHASH(IoC, Port, GM_MC_ADDR_H1, EmptyHash);
/* Enable Unicast and Multicast filtering */
GM_IN16(IoC, Port, GM_RX_CTRL, &RxCtrl);
-
+
GM_OUT16(IoC, Port, GM_RX_CTRL,
RxCtrl | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
SkMacRxTxDisable(pAC, IoC, Port);
if (pAC->GIni.GIGenesis) {
-
+
SkXmSoftRst(pAC, IoC, Port);
}
else {
-
+
SkGmSoftRst(pAC, IoC, Port);
}
/* flush the MAC's Rx and Tx FIFOs */
SkMacFlushTxFifo(pAC, IoC, Port);
-
+
SkMacFlushRxFifo(pAC, IoC, Port);
pPrt->PState = SK_PRT_STOP;
SK_IOC IoC, /* IO context */
int Port) /* Port Index (MAC_1 + n) */
{
-
+
if (pAC->GIni.GIGenesis) {
-
+
SkXmHardRst(pAC, IoC, Port);
}
else {
-
+
SkGmHardRst(pAC, IoC, Port);
}
} /* SkMacHardRst */
-
/******************************************************************************
*
* SkXmInitMac() - Initialize the XMAC II
if (pPrt->PhyType != SK_PHY_XMAC) {
SK_IN32(IoC, B2_GP_IO, &Reg);
-
+
if (Port == 0) {
Reg |= (GP_DIR_0 | GP_IO_0); /* set to output */
}
* Must be done AFTER first access to BCOM chip.
*/
XM_IN16(IoC, Port, XM_MMU_CMD, &SWord);
-
+
XM_OUT16(IoC, Port, XM_MMU_CMD, SWord | XM_MMU_NO_PRE);
if (pPrt->PhyId1 == PHY_BCOM_ID1_C0) {
* Disable Power Management after reset.
*/
SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_CTRL, &SWord);
-
+
SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_AUX_CTRL,
(SK_U16)(SWord | PHY_B_AC_DIS_PM));
/* Dummy read the Interrupt source register */
XM_IN16(IoC, Port, XM_ISRC, &SWord);
-
+
/*
* The auto-negotiation process starts immediately after
* clearing the reset. The auto-negotiation process should be
* independent. Remember this when changing.
*/
SK_IN16(IoC, (B2_MAC_2 + Port * 8 + i * 2), &SWord);
-
+
XM_OUT16(IoC, Port, (XM_SA + i * 2), SWord);
}
*/
SWord |= XM_RX_DIS_CEXT;
}
-
+
XM_OUT16(IoC, Port, XM_RX_CMD, SWord);
/*
/* Port State: SK_PRT_STOP */
/* Verify that the reset bit is cleared */
SK_IN32(IoC, MR_ADDR(Port, GMAC_CTRL), &DWord);
-
+
if ((DWord & GMC_RST_SET) != 0) {
/* PState does not match HW state */
SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E006, SKERR_HWI_E006MSG);
/* Dummy read the Interrupt source register */
SK_IN16(IoC, GMAC_IRQ_SRC, &SWord);
-
+
#ifndef VCPU
/* read Id from PHY */
SkGmPhyRead(pAC, IoC, Port, PHY_MARV_ID1, &pPrt->PhyId1);
-
+
SkGmInitPhyMarv(pAC, IoC, Port, SK_FALSE);
#endif /* VCPU */
}
case SK_LSPEED_10MBPS:
break;
}
-
+
/* duplex settings */
if (pPrt->PLinkMode != SK_LMODE_HALF) {
/* set full duplex */
/* disable auto-update for speed, duplex and flow-control */
SWord |= GM_GPCR_AU_ALL_DIS;
}
-
+
/* setup General Purpose Control Register */
GM_OUT16(IoC, Port, GM_GP_CTRL, SWord);
#endif /* VCPU */
SWord = JAM_LEN_VAL(3) | JAM_IPG_VAL(11) | IPG_JAM_DATA(26);
-
+
GM_OUT16(IoC, Port, GM_TX_PARAM, SWord);
/* configure the Serial Mode Register */
#ifdef VCPU
GM_IN16(IoC, Port, GM_SERIAL_MODE, &SWord);
#endif /* VCPU */
-
+
SWord = GM_SMOD_VLAN_ENA | IPG_VAL_FAST_ETH;
if (pAC->GIni.GIPortUsage == SK_JUMBO_LINK) {
/* enable jumbo mode (Max. Frame Length = 9018) */
SWord |= GM_SMOD_JUMBO_ENA;
}
-
+
GM_OUT16(IoC, Port, GM_SERIAL_MODE, SWord);
-
+
/*
* configure the GMACs Station Addresses
* in PROM you can find our addresses at:
else {
GM_OUT16(IoC, Port, (GM_SRC_ADDR_1L + i * 4), SWord);
}
-#else
+#else
GM_OUT16(IoC, Port, (GM_SRC_ADDR_1L + i * 4), SWord);
#endif /* WA_DEV_16 */
-
+
/* virtual address: will be used for data */
SK_IN16(IoC, (B2_MAC_1 + Port * 8 + i * 2), &SWord);
GM_OUT16(IoC, Port, (GM_SRC_ADDR_2L + i * 4), SWord);
-
+
/* reset Multicast filtering Hash registers 1-3 */
GM_OUT16(IoC, Port, GM_MC_ADDR_H1 + 4*i, 0);
}
/* read General Purpose Status */
GM_IN16(IoC, Port, GM_GP_STAT, &SWord);
-
+
SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
("MAC Stat Reg=0x%04X\n", SWord));
pPrt = &pAC->GIni.GP[Port];
XM_IN16(IoC, Port, XM_MMU_CMD, &Word);
-
+
if (pPrt->PFlowCtrlStatus == SK_FLOW_STAT_NONE ||
pPrt->PFlowCtrlStatus == SK_FLOW_STAT_LOC_SEND) {
*/
/* Enable Pause Frame Reception */
Word &= ~XM_MMU_IGN_PF;
- }
-
+ }
+
XM_OUT16(IoC, Port, XM_MMU_CMD, Word);
XM_IN32(IoC, Port, XM_MODE, &DWord);
/* Disable Pause Mode in MAC Rx FIFO */
SK_OUT16(IoC, MR_ADDR(Port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
}
-
+
XM_OUT32(IoC, Port, XM_MODE, DWord);
} /* SkXmInitPauseMd*/
pPrt = &pAC->GIni.GP[Port];
Ctrl = 0;
-
+
/* Auto-negotiation ? */
if (pPrt->PLinkMode == SK_LMODE_HALF || pPrt->PLinkMode == SK_LMODE_FULL) {
SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
/* manually Master/Slave ? */
if (pPrt->PMSMode != SK_MS_MODE_AUTO) {
Ctrl2 |= PHY_B_1000C_MSE;
-
+
if (pPrt->PMSMode == SK_MS_MODE_MASTER) {
Ctrl2 |= PHY_B_1000C_MSC;
}
* Set Repeater/DTE bit 10 of the 1000Base-T Control Register
*/
Ctrl2 |= PHY_B_1000C_RD;
-
+
/* Set Full/half duplex capabilities */
switch (pPrt->PLinkMode) {
case SK_LMODE_AUTOHALF:
/* Restart Auto-negotiation */
Ctrl1 |= PHY_CT_ANE | PHY_CT_RE_CFG;
}
-
+
/* Initialize LED register here? */
/* No. Please do it in SkDgXmitLed() (if required) and swap
init order of LEDs and XMAC. (MAl) */
-
+
/* Write 1000Base-T Control Register */
SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_1000T_CTRL, Ctrl2);
SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
("1000B-T Ctrl Reg=0x%04X\n", Ctrl2));
-
+
/* Write AutoNeg Advertisement Register */
SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_AUNE_ADV, Ctrl3);
SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
("Auto-Neg. Adv. Reg=0x%04X\n", Ctrl3));
-
+
if (DoLoop) {
/* Set the Phy Loopback bit, too */
Ctrl1 |= PHY_CT_LOOP;
/* Configure LED Traffic Mode and Jumbo Frame usage if specified */
SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_P_EXT_CTRL, Ctrl4);
-
+
/* Write to the Phy control register */
SkXmPhyWrite(pAC, IoC, Port, PHY_BCOM_CTRL, Ctrl1);
SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
VCPUprintf(0, "SkGmInitPhyMarv(), Port=%u, DoLoop=%u\n",
Port, DoLoop);
#else /* VCPU */
-
+
pPrt = &pAC->GIni.GP[Port];
/* Auto-negotiation ? */
else {
AutoNeg = SK_TRUE;
}
-
+
if (!DoLoop) {
/* Read Ext. PHY Specific Control */
SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_CTRL, &ExtPhyCtrl);
-
+
ExtPhyCtrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
PHY_M_EC_MAC_S_MSK);
-
+
ExtPhyCtrl |= PHY_M_EC_M_DSC(1) | PHY_M_EC_S_DSC(1) |
PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
-
+
SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_EXT_CTRL, ExtPhyCtrl);
SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
("Ext.PHYCtrl=0x%04X\n", ExtPhyCtrl));
-
+
/* Read PHY Control */
SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &PhyCtrl);
-
+
/* Assert software reset */
SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CTRL,
(SK_U16)(PhyCtrl | PHY_CT_RESET));
if (pPrt->PMSMode != SK_MS_MODE_AUTO) {
/* enable Manual Master/Slave */
C1000BaseT |= PHY_M_1000C_MSE;
-
+
if (pPrt->PMSMode == SK_MS_MODE_MASTER) {
C1000BaseT |= PHY_M_1000C_MSC; /* set it to Master */
}
}
-
+
/* Auto-negotiation ? */
if (!AutoNeg) {
SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
("InitPhyMarv: no auto-negotiation Port %d\n", Port));
-
+
if (pPrt->PLinkMode == SK_LMODE_FULL) {
/* Set Full Duplex Mode */
PhyCtrl |= PHY_CT_DUP_MD;
else {
SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
("InitPhyMarv: with auto-negotiation Port %d\n", Port));
-
+
PhyCtrl |= PHY_CT_ANE;
-
+
if (pAC->GIni.GICopperType) {
/* Set Speed capabilities */
switch (pPrt->PLinkSpeed) {
SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E015,
SKERR_HWI_E015MSG);
}
-
+
/* Set Auto-negotiation advertisement */
switch (pPrt->PFlowCtrlMode) {
case SK_FLOW_MODE_NONE:
}
}
else { /* special defines for FIBER (88E1011S only) */
-
+
/* Set Full/half duplex capabilities */
switch (pPrt->PLinkMode) {
case SK_LMODE_AUTOHALF:
SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E015,
SKERR_HWI_E015MSG);
}
-
+
/* Set Auto-negotiation advertisement */
switch (pPrt->PFlowCtrlMode) {
case SK_FLOW_MODE_NONE:
PhyCtrl |= PHY_CT_RE_CFG;
}
}
-
+
#ifdef VCPU
/*
* E-mail from Gu Lin (08-03-2002):
*/
-
+
/* Program PHY register 30 as 16'h0708 for simulation speed up */
SkGmPhyWrite(pAC, IoC, Port, 30, 0x0708);
-
+
VCpuWait(2000);
#else /* VCPU */
-
+
/* Write 1000Base-T Control Register */
SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_1000T_CTRL, C1000BaseT);
SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
("1000B-T Ctrl=0x%04X\n", C1000BaseT));
-
+
/* Write AutoNeg Advertisement Register */
SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_AUNE_ADV, AutoNegAdv);
SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
("Auto-Neg.Ad.=0x%04X\n", AutoNegAdv));
#endif /* VCPU */
-
+
if (DoLoop) {
/* Set the PHY Loopback bit */
PhyCtrl |= PHY_CT_LOOP;
SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CTRL, &PhyCtrl);
SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
("PHY Ctrl Reg.=0x%04X\n", PhyCtrl));
-
+
/* Read 1000Base-T Control Register */
SkGmPhyRead(pAC, IoC, Port, PHY_MARV_1000T_CTRL, &C1000BaseT);
SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
("1000B-T Ctrl =0x%04X\n", C1000BaseT));
-
+
/* Read AutoNeg Advertisement Register */
SkGmPhyRead(pAC, IoC, Port, PHY_MARV_AUNE_ADV, &AutoNegAdv);
SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
("Auto-Neg. Ad.=0x%04X\n", AutoNegAdv));
-
+
/* Read Ext. PHY Specific Control */
SkGmPhyRead(pAC, IoC, Port, PHY_MARV_EXT_CTRL, &ExtPhyCtrl);
SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
("Ext PHY Ctrl=0x%04X\n", ExtPhyCtrl));
-
+
/* Read PHY Status */
SkGmPhyRead(pAC, IoC, Port, PHY_MARV_STAT, &PhyStat);
SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
SkGmPhyRead(pAC, IoC, Port, PHY_MARV_STAT, &PhyStat1);
SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
("PHY Stat Reg.=0x%04X\n", PhyStat1));
-
+
/* Read PHY Specific Status */
SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_STAT, &PhySpecStat);
SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
/* manually Master/Slave ? */
if (pPrt->PMSMode != SK_MS_MODE_AUTO) {
Ctrl2 |= PHY_L_1000C_MSE;
-
+
if (pPrt->PMSMode == SK_MS_MODE_MASTER) {
Ctrl2 |= PHY_L_1000C_MSC;
}
Ctrl1 = PHY_CT_ANE | PHY_CT_RE_CFG;
}
-
+
/* Initialize LED register here ? */
/* No. Please do it in SkDgXmitLed() (if required) and swap
init order of LEDs and XMAC. (MAl) */
-
+
/* Write 1000Base-T Control Register */
SkXmPhyWrite(pAC, IoC, Port, PHY_LONE_1000T_CTRL, Ctrl2);
SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
("1000B-T Ctrl Reg=0x%04X\n", Ctrl2));
-
+
/* Write AutoNeg Advertisement Register */
SkXmPhyWrite(pAC, IoC, Port, PHY_LONE_AUNE_ADV, Ctrl3);
SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
("Auto-Neg. Adv. Reg=0x%04X\n", Ctrl3));
-
+
if (DoLoop) {
/* Set the Phy Loopback bit, too */
01-Sep-2000 RA;:;:
SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_1000T_STAT, &ResAb);
#endif /* 0 */
-
+
SkXmPhyRead(pAC, IoC, Port, PHY_BCOM_AUX_STAT, &AuxStat);
if ((LPAb & PHY_B_AN_RF) != 0) {
pPrt->PAutoNegFail = SK_TRUE;
return(SK_AND_DUP_CAP);
}
-
+
#if 0
01-Sep-2000 RA;:;:
/* Check Master/Slave resolution */
pPrt->PMSStatus = SK_MS_STAT_FAULT;
return(SK_AND_OTHER);
}
-
+
pPrt->PMSStatus = ((ResAb & PHY_B_1000S_MSR) != 0) ?
SK_MS_STAT_MASTER : SK_MS_STAT_SLAVE;
#endif /* 0 */
/* Get PHY parameters */
SkGmPhyRead(pAC, IoC, Port, PHY_MARV_AUNE_LP, &LPAb);
-
+
if ((LPAb & PHY_M_AN_RF) != 0) {
SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
("AutoNegFail: Remote fault bit set Port %d\n", Port));
}
SkGmPhyRead(pAC, IoC, Port, PHY_MARV_1000T_STAT, &ResAb);
-
+
/* Check Master/Slave resolution */
if ((ResAb & PHY_B_1000S_MSF) != 0) {
SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
pPrt->PMSStatus = SK_MS_STAT_FAULT;
return(SK_AND_OTHER);
}
-
+
pPrt->PMSStatus = ((ResAb & PHY_B_1000S_MSR) != 0) ?
(SK_U8)SK_MS_STAT_MASTER : (SK_U8)SK_MS_STAT_SLAVE;
-
+
/* Read PHY Specific Status */
SkGmPhyRead(pAC, IoC, Port, PHY_MARV_PHY_STAT, &AuxStat);
-
+
/* Check Speed & Duplex resolved */
if ((AuxStat & PHY_M_PS_SPDUP_RES) == 0) {
SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
pPrt->PLinkModeStatus = SK_LMODE_STAT_UNKNOWN;
return(SK_AND_DUP_CAP);
}
-
+
if ((AuxStat & PHY_M_PS_FULL_DUP) != 0) {
pPrt->PLinkModeStatus = SK_LMODE_STAT_AUTOFULL;
}
else {
pPrt->PLinkModeStatus = SK_LMODE_STAT_AUTOHALF;
}
-
+
/* Check PAUSE mismatch */
/* We are using IEEE 802.3z/D5.0 Table 37-4 */
if ((AuxStat & PHY_M_PS_PAUSE_MSK) == PHY_M_PS_PAUSE_MSK) {
/* PAUSE mismatch -> no PAUSE */
pPrt->PFlowCtrlStatus = SK_FLOW_STAT_NONE;
}
-
+
/* set used link speed */
switch ((unsigned)(AuxStat & PHY_M_PS_SPEED_MSK)) {
case (unsigned)PHY_M_PS_SPEED_1000:
else {
pPrt->PLinkModeStatus = SK_LMODE_STAT_AUTOHALF;
}
-
+
/* Check Master/Slave resolution */
if ((ResAb & PHY_L_1000S_MSF) != 0) {
/* Error */
SK_ERR_LOG(pAC, SK_ERRCL_SW | SK_ERRCL_INIT, SKERR_HWI_E016,
SKERR_HWI_E016MSG);
}
-
+
return(SK_AND_OK);
} /* SkXmAutoNegDoneLone */
default:
return(SK_AND_OTHER);
}
-
+
if (Rtv != SK_AND_OK) {
return(Rtv);
}
pPrt->PAutoNegFail = SK_FALSE;
SkMacRxTxEnable(pAC, IoC, Port);
-
+
return(SK_AND_OK);
} /* SkMacAutoNegDone */
Word &= ~XM_MMU_GMII_LOOP;
break;
}
-
+
switch (Para & (SK_PHY_FULLD_ON | SK_PHY_FULLD_OFF)) {
case SK_PHY_FULLD_ON:
Word |= XM_MMU_GMII_FD;
Word &= ~XM_MMU_GMII_FD;
break;
}
-
+
XM_OUT16(IoC, Port, XM_MMU_CMD, Word | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
/* dummy read to ensure writing */
int Para) /* Parameter to set: MAC LoopBack, Duplex Mode */
{
SK_U16 Ctrl;
-
+
GM_IN16(IoC, Port, GM_GP_CTRL, &Ctrl);
switch (Para & (SK_MAC_LOOPB_ON | SK_MAC_LOOPB_OFF)) {
Ctrl &= ~GM_GPCR_DUP_FULL;
break;
}
-
+
GM_OUT16(IoC, Port, GM_GP_CTRL, Ctrl | GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
/* dummy read to ensure writing */
int Para)
{
if (pAC->GIni.GIGenesis) {
-
+
SkXmSetRxTxEn(pAC, IoC, Port, Para);
}
else {
-
+
SkGmSetRxTxEn(pAC, IoC, Port, Para);
}
if (pAC->GIni.GIGenesis) {
/* set Duplex Mode and Pause Mode */
SkXmInitDupMd(pAC, IoC, Port);
-
+
SkXmInitPauseMd(pAC, IoC, Port);
-
+
/*
* Initialize the Interrupt Mask Register. Default IRQs are...
* - Link Asynchronous Event
/* add IRQ for Receive FIFO Overflow */
IntMask &= ~XM_IS_RXF_OV;
#endif /* DEBUG */
-
+
if (pPrt->PhyType != SK_PHY_XMAC) {
/* disable GP0 interrupt bit */
IntMask |= XM_IS_INP_ASS;
}
XM_OUT16(IoC, Port, XM_IMSK, IntMask);
-
+
/* get MMU Command Reg. */
XM_IN16(IoC, Port, XM_MMU_CMD, &Reg);
-
+
if (pPrt->PhyType != SK_PHY_XMAC &&
(pPrt->PLinkModeStatus == SK_LMODE_STAT_FULL ||
pPrt->PLinkModeStatus == SK_LMODE_STAT_AUTOFULL)) {
/* set to Full Duplex */
Reg |= XM_MMU_GMII_FD;
}
-
+
switch (pPrt->PhyType) {
case SK_PHY_BCOM:
/*
break;
#endif /* OTHER_PHY */
}
-
+
/* enable Rx/Tx */
XM_OUT16(IoC, Port, XM_MMU_CMD, Reg | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
}
/* add IRQ for Receive FIFO Overrun */
IntMask |= GM_IS_RX_FF_OR;
#endif /* DEBUG */
-
+
SK_OUT8(IoC, GMAC_IRQ_MSK, (SK_U8)IntMask);
-
+
/* get General Purpose Control */
GM_IN16(IoC, Port, GM_GP_CTRL, &Reg);
-
+
if (pPrt->PLinkModeStatus == SK_LMODE_STAT_FULL ||
pPrt->PLinkModeStatus == SK_LMODE_STAT_AUTOFULL) {
/* set to Full Duplex */
Reg |= GM_GPCR_DUP_FULL;
}
-
+
/* enable Rx/Tx */
GM_OUT16(IoC, Port, GM_GP_CTRL, Reg | GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
#endif /* VCPU */
}
-
+
return(0);
} /* SkMacRxTxEnable */
SK_U16 Word;
if (pAC->GIni.GIGenesis) {
-
+
XM_IN16(IoC, Port, XM_MMU_CMD, &Word);
-
+
XM_OUT16(IoC, Port, XM_MMU_CMD, Word & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
-
+
/* dummy read to ensure writing */
XM_IN16(IoC, Port, XM_MMU_CMD, &Word);
}
else {
-
+
GM_IN16(IoC, Port, GM_GP_CTRL, &Word);
GM_OUT16(IoC, Port, GM_GP_CTRL, Word & ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA));
pPrt = &pAC->GIni.GP[Port];
if (pAC->GIni.GIGenesis) {
-
+
/* disable all XMAC IRQs */
- XM_OUT16(IoC, Port, XM_IMSK, 0xffff);
-
+ XM_OUT16(IoC, Port, XM_IMSK, 0xffff);
+
/* Disable all PHY interrupts */
switch (pPrt->PhyType) {
case SK_PHY_BCOM:
else {
/* disable all GMAC IRQs */
SK_OUT8(IoC, GMAC_IRQ_MSK, 0);
-
+
#ifndef VCPU
/* Disable all PHY interrupts */
SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_INT_MASK, 0);
SK_U16 IStatus2;
pPrt = &pAC->GIni.GP[Port];
-
+
XM_IN16(IoC, Port, XM_ISRC, &IStatus);
-
+
/* LinkPartner Auto-negable? */
if (pPrt->PhyType == SK_PHY_XMAC) {
SkXmAutoNegLipaXmac(pAC, IoC, Port, IStatus);
XM_IS_RX_PAGE | XM_IS_TX_PAGE |
XM_IS_AND | XM_IS_INP_ASS);
}
-
+
SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
("XmacIrq Port %d Isr 0x%04x\n", Port, IStatus));
SK_U8 IStatus; /* Interrupt status */
pPrt = &pAC->GIni.GP[Port];
-
+
SK_IN8(IoC, GMAC_IRQ_SRC, &IStatus);
-
+
/* LinkPartner Auto-negable? */
SkMacAutoNegLipaPhy(pAC, IoC, Port, IStatus);
-
+
SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_IRQ,
("GmacIrq Port %d Isr 0x%04x\n", Port, IStatus));
do {
XM_IN16(IoC, Port, XM_STAT_CMD, &StatReg);
-
+
if (++WaitIndex > 10) {
SK_ERR_LOG(pAC, SK_ERRCL_HW, SKERR_HWI_E021, SKERR_HWI_E021MSG);
return(1);
}
} while ((StatReg & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) != 0);
-
+
return(0);
} /* SkXmUpdateStats */
SK_U32 *pVal) /* ptr to return statistic value */
{
if ((StatAddr < XM_TXF_OK) || (StatAddr > XM_RXF_MAX_SZ)) {
-
+
SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E022, SKERR_HWI_E022MSG);
-
+
return(1);
}
-
+
XM_IN32(IoC, Port, StatAddr, pVal);
return(0);
{
if ((StatAddr < GM_RXF_UC_OK) || (StatAddr > GM_TXE_FIFO_UR)) {
-
+
SK_ERR_LOG(pAC, SK_ERRCL_SW, SKERR_HWI_E022, SKERR_HWI_E022MSG);
-
+
SK_DBG_MSG(pAC, SK_DBGMOD_HWM, SK_DBGCAT_CTRL,
("SkGmMacStat: wrong MIB counter 0x%04X\n", StatAddr));
return(1);
}
-
+
GM_IN32(IoC, Port, StatAddr, pVal);
return(0);
#ifndef VCPU
/* set MIB Clear Counter Mode */
GM_OUT16(IoC, Port, GM_PHY_ADDR, Reg | GM_PAR_MIB_CLR);
-
+
/* read all MIB Counters with Clear Mode set */
for (i = 0; i < GM_MIB_CNT_SIZE; i++) {
/* the reset is performed only when the lower 16 bits are read */
GM_IN16(IoC, Port, GM_MIB_CNT_BASE + 8*i, &Word);
}
-
+
/* clear MIB Clear Counter Mode */
GM_OUT16(IoC, Port, GM_PHY_ADDR, Reg);
#endif /* !VCPU */
-
+
return(0);
} /* SkGmResetCounter */
XM_IN32(IoC, Port, XM_RX_CNT_EV, &RegVal);
Status |= (SK_U64)RegVal << 32;
}
-
+
if ((IStatus & XM_IS_TXC_OV) != 0) {
XM_IN32(IoC, Port, XM_TX_CNT_EV, &RegVal);
GM_IN16(IoC, Port, GM_RX_IRQ_SRC, &RegVal);
Status |= (SK_U64)RegVal << 32;
}
-
+
if ((IStatus & GM_IS_TX_CO_OV) != 0) {
/* this register is self-clearing after read */
GM_IN16(IoC, Port, GM_TX_IRQ_SRC, &RegVal);
Status |= (SK_U64)RegVal;
}
-
+
/* this register is self-clearing after read */
GM_IN16(IoC, Port, GM_TR_IRQ_SRC, &RegVal);
/* Rx overflow interrupt register bits (LoByte)*/
* gets the results if 'StartTest' is true
*
* NOTE: this test is meaningful only when link is down
- *
+ *
* Returns:
* 0: success
* 1: no YUKON copper
pPrt = &pAC->GIni.GP[Port];
if (pPrt->PhyType != SK_PHY_MARV_COPPER) {
-
+
return(1);
}
if ((pPrt->PhyId1 & PHY_I1_REV_MSK) < 4) {
/* apply TDR workaround from Marvell */
SkGmPhyWrite(pAC, IoC, Port, 29, 0x001e);
-
+
SkGmPhyWrite(pAC, IoC, Port, 30, 0xcc00);
SkGmPhyWrite(pAC, IoC, Port, 30, 0xc800);
SkGmPhyWrite(pAC, IoC, Port, 30, 0xc400);
/* start Cable Diagnostic Test */
SkGmPhyWrite(pAC, IoC, Port, PHY_MARV_CABLE_DIAG,
(SK_U16)(RegVal | PHY_M_CABD_ENA_TEST));
-
+
return(0);
}
-
+
/* Read Cable Diagnostic Reg */
SkGmPhyRead(pAC, IoC, Port, PHY_MARV_CABLE_DIAG, &RegVal);
static int skge_send(struct eth_device *dev, volatile void *packet,
- int length)
+ int length)
{
int ret = -1;
struct sk_buff * skb = alloc_skb(length, 0);
sk_table[i]->data += 16 - ((u32)sk_table[i]->data & 15);
sk_table[i]->len = size;
-
+
break;
}
{
*(.text)
}
- __text_end = .;
+ __text_end = .;
- . = ALIGN(4);
- .rodata :
+ . = ALIGN(4);
+ .rodata :
{
*(.rodata)
}
__rodata_end = .;
- . = ALIGN(4);
- .data :
+ . = ALIGN(4);
+ .data :
{
*(.data)
}
__data_end = .;
__bss_start = .;
- . = ALIGN(4);
- .bss :
+ . = ALIGN(4);
+ .bss :
{
*(.bss)
}
. = ALIGN(4);
__bss_end = .;
}
-
jOld->ino = 0;
return 1;
}
-
+
return 0;
}
#endif
/*
- * include/asm-arm/arch-ixp425/ixp425.h
+ * include/asm-arm/arch-ixp425/ixp425.h
*
- * Register definitions for IXP425
+ * Register definitions for IXP425
*
* Copyright (C) 2002 Intel Corporation.
*
# ifndef __ASSEMBLY__
# define io_p2v(PhAdd) (PhAdd)
# define __REG(x) (*((volatile u32 *)io_p2v(x)))
-# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y)))
+# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y)))
# else
-# define __REG(x) (x)
+# define __REG(x) (x)
# endif
#endif /* UBOOT_REG_FIX */
/*
- *
+ *
* IXP425 Memory map:
*
* Phy Phy Size Map Size Virt Description
* =========================================================================
*
- * 0x00000000 0x10000000 SDRAM 1
+ * 0x00000000 0x10000000 SDRAM 1
*
* 0x10000000 0x10000000 SDRAM 2
*
* 0x20000000 0x10000000 SDRAM 3
*
- * 0x30000000 0x10000000 SDRAM 4
+ * 0x30000000 0x10000000 SDRAM 4
*
* The above four are aliases to the same memory location (0x00000000)
*
*
* 0x6000000 0x00004000 0x4000 0xFFFEB000 QMgr
*
- * 0xC0000000 0x100 0x1000 0xFFFDD000 PCI CFG
+ * 0xC0000000 0x100 0x1000 0xFFFDD000 PCI CFG
*
- * 0xC4000000 0x100 0x1000 0xFFFDE000 EXP CFG
+ * 0xC4000000 0x100 0x1000 0xFFFDE000 EXP CFG
*
* 0xC8000000 0xC000 0xC000 0xFFFDF000 PERIPHERAL
*
- * 0xCC000000 0x100 0x1000 Not Mapped SDRAM CFG
+ * 0xCC000000 0x100 0x1000 Not Mapped SDRAM CFG
*/
/*
*/
#define IXP425_SDRAM_CFG_BASE_PHYS (0xCC000000)
-/*
+/*
* Q Manager space .. not static mapped
*/
#define IXP425_QMGR_BASE_PHYS (0x60000000)
#define IXP425_EXP_CS0 IXP425_EXP_REG(IXP425_EXP_CS0_OFFSET)
#define IXP425_EXP_CS1 IXP425_EXP_REG(IXP425_EXP_CS1_OFFSET)
-#define IXP425_EXP_CS2 IXP425_EXP_REG(IXP425_EXP_CS2_OFFSET)
+#define IXP425_EXP_CS2 IXP425_EXP_REG(IXP425_EXP_CS2_OFFSET)
#define IXP425_EXP_CS3 IXP425_EXP_REG(IXP425_EXP_CS3_OFFSET)
#define IXP425_EXP_CS4 IXP425_EXP_REG(IXP425_EXP_CS4_OFFSET)
#define IXP425_EXP_CS5 IXP425_EXP_REG(IXP425_EXP_CS5_OFFSET)
-#define IXP425_EXP_CS6 IXP425_EXP_REG(IXP425_EXP_CS6_OFFSET)
+#define IXP425_EXP_CS6 IXP425_EXP_REG(IXP425_EXP_CS6_OFFSET)
#define IXP425_EXP_CS7 IXP425_EXP_REG(IXP425_EXP_CS7_OFFSET)
-#define IXP425_EXP_CFG0 IXP425_EXP_REG(IXP425_EXP_CFG0_OFFSET)
-#define IXP425_EXP_CFG1 IXP425_EXP_REG(IXP425_EXP_CFG1_OFFSET)
-#define IXP425_EXP_CFG2 IXP425_EXP_REG(IXP425_EXP_CFG2_OFFSET)
+#define IXP425_EXP_CFG0 IXP425_EXP_REG(IXP425_EXP_CFG0_OFFSET)
+#define IXP425_EXP_CFG1 IXP425_EXP_REG(IXP425_EXP_CFG1_OFFSET)
+#define IXP425_EXP_CFG2 IXP425_EXP_REG(IXP425_EXP_CFG2_OFFSET)
#define IXP425_EXP_CFG3 IXP425_EXP_REG(IXP425_EXP_CFG3_OFFSET)
/*
#define LSR_OE (1 << 1) /* Overrun Error */
#define LSR_DR (1 << 0) /* Data Ready */
-#define MCR_LOOP (1 << 4) */
+#define MCR_LOOP (1 << 4) */
#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */
#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */
#define MCR_RTS (1 << 1) /* Request to Send */
#define IXP425_CONSOLE_UART_BASE_VIRT IXP425_UART1_BASE_VIRT
#define IXP425_CONSOLE_UART_BASE_PHYS IXP425_UART1_BASE_PHYS
/*
- * Peripheral Space Registers
+ * Peripheral Space Registers
*/
#define IXP425_UART1_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x0000)
#define IXP425_UART2_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x1000)
#define IXP425_USB_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0xB000)
-/*
+/*
* UART Register Definitions , Offsets only as there are 2 UARTS.
* IXP425_UART1_BASE , IXP425_UART2_BASE.
*/
#define IXP425_ICIP IXP425_INTC_REG(IXP425_ICIP_OFFSET)
#define IXP425_ICFP IXP425_INTC_REG(IXP425_ICFP_OFFSET)
#define IXP425_ICHR IXP425_INTC_REG(IXP425_ICHR_OFFSET)
-#define IXP425_ICIH IXP425_INTC_REG(IXP425_ICIH_OFFSET)
+#define IXP425_ICIH IXP425_INTC_REG(IXP425_ICIH_OFFSET)
#define IXP425_ICFH IXP425_INTC_REG(IXP425_ICFH_OFFSET)
-
+
/*
* Constants to make it easy to access GPIO registers
*/
#define IXP425_GPIO_GPCLKR_OFFSET 0x18
#define IXP425_GPIO_GPDBSELR_OFFSET 0x1C
-/*
+/*
* GPIO Register Definitions.
* [Only perform 32bit reads/writes]
*/
#define IXP425_OSST IXP425_TIMER_REG(IXP425_OSST_OFFSET)
/*
- * Timer register values and bit definitions
+ * Timer register values and bit definitions
*/
#define IXP425_OST_ENABLE BIT(0)
#define IXP425_OST_ONE_SHOT BIT(1)
/* Low order bits of reload value ignored */
-#define IXP425_OST_RELOAD_MASK (0x3)
+#define IXP425_OST_RELOAD_MASK (0x3)
#define IXP425_OST_DISABLED (0x0)
#define IXP425_OSST_TIMER_1_PEND BIT(0)
#define IXP425_OSST_TIMER_2_PEND BIT(1)
#define PCI_CRP_AD_CBE IXP425_PCI_CSR(PCI_CRP_AD_CBE_OFFSET)
#define PCI_CRP_WDATA IXP425_PCI_CSR(PCI_CRP_WDATA_OFFSET)
#define PCI_CRP_RDATA IXP425_PCI_CSR(PCI_CRP_RDATA_OFFSET)
-#define PCI_CSR IXP425_PCI_CSR(PCI_CSR_OFFSET)
+#define PCI_CSR IXP425_PCI_CSR(PCI_CSR_OFFSET)
#define PCI_ISR IXP425_PCI_CSR(PCI_ISR_OFFSET)
#define PCI_INTEN IXP425_PCI_CSR(PCI_INTEN_OFFSET)
#define PCI_DMACTRL IXP425_PCI_CSR(PCI_DMACTRL_OFFSET)
#define PCI_ATPDMA1_LENADDR IXP425_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET)
/*
- * PCI register values and bit definitions
+ * PCI register values and bit definitions
*/
/* CSR bit definitions */
/*
* Clock Speed Definitions.
*/
-#define IXP425_PERIPHERAL_BUS_CLOCK (66) /* 66Mhzi APB BUS */
+#define IXP425_PERIPHERAL_BUS_CLOCK (66) /* 66Mhzi APB BUS */
#endif
#define RX_MISSED_FRAME (1<<31)
#define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \
- RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
- RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
+ RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
+ RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
#define MAC_RX_BUFF0_ADDR 0x4
#define RX_DMA_ENABLE (1<<0)
#define RX_T_DONE (1<<1)
#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
-
/* SSIO */
#define SSI0_STATUS 0xB1600000
#define SSI_STATUS_BF (1<<4)
#define IR_TX_ENABLE (1<<12)
#define IR_LOOPBACK (1<<14)
#define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \
- IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC)
+ IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC)
#define IR_SIR_FLAGS (IRDA_BASE+0x24)
#define IR_ENABLE (IRDA_BASE+0x28)
#define IR_RX_STATUS (1<<9)
#include <linux/byteorder/little_endian.h>
#endif
-
#define _NIOS_PSR_H
-
#endif /* _NIOS_PSR_H */
--- /dev/null
+
+/*
+ * MPC85xx Communication Processor Module
+ * Copyright (c) 2003,Motorola Inc.
+ * Xianghua Xiao (X.Xiao@motorola.com)
+ *
+ * MPC8260 Communication Processor Module.
+ * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
+ *
+ * This file contains structures and information for the communication
+ * processor channels found in the dual port RAM or parameter RAM.
+ * All CPM control and status is available through the MPC8260 internal
+ * memory map. See immap.h for details.
+ */
+#ifndef __CPM_85XX__
+#define __CPM_85XX__
+
+#include <asm/immap_85xx.h>
+
+/* CPM Command register.
+*/
+#define CPM_CR_RST ((uint)0x80000000)
+#define CPM_CR_PAGE ((uint)0x7c000000)
+#define CPM_CR_SBLOCK ((uint)0x03e00000)
+#define CPM_CR_FLG ((uint)0x00010000)
+#define CPM_CR_MCN ((uint)0x00003fc0)
+#define CPM_CR_OPCODE ((uint)0x0000000f)
+
+/* Device sub-block and page codes.
+*/
+#define CPM_CR_SCC1_SBLOCK (0x04)
+#define CPM_CR_SCC2_SBLOCK (0x05)
+#define CPM_CR_SCC3_SBLOCK (0x06)
+#define CPM_CR_SCC4_SBLOCK (0x07)
+#define CPM_CR_SMC1_SBLOCK (0x08)
+#define CPM_CR_SMC2_SBLOCK (0x09)
+#define CPM_CR_SPI_SBLOCK (0x0a)
+#define CPM_CR_I2C_SBLOCK (0x0b)
+#define CPM_CR_TIMER_SBLOCK (0x0f)
+#define CPM_CR_RAND_SBLOCK (0x0e)
+#define CPM_CR_FCC1_SBLOCK (0x10)
+#define CPM_CR_FCC2_SBLOCK (0x11)
+#define CPM_CR_FCC3_SBLOCK (0x12)
+#define CPM_CR_MCC1_SBLOCK (0x1c)
+
+#define CPM_CR_SCC1_PAGE (0x00)
+#define CPM_CR_SCC2_PAGE (0x01)
+#define CPM_CR_SCC3_PAGE (0x02)
+#define CPM_CR_SCC4_PAGE (0x03)
+#define CPM_CR_SPI_PAGE (0x09)
+#define CPM_CR_I2C_PAGE (0x0a)
+#define CPM_CR_TIMER_PAGE (0x0a)
+#define CPM_CR_RAND_PAGE (0x0a)
+#define CPM_CR_FCC1_PAGE (0x04)
+#define CPM_CR_FCC2_PAGE (0x05)
+#define CPM_CR_FCC3_PAGE (0x06)
+#define CPM_CR_MCC1_PAGE (0x07)
+#define CPM_CR_MCC2_PAGE (0x08)
+
+/* Some opcodes (there are more...later)
+*/
+#define CPM_CR_INIT_TRX ((ushort)0x0000)
+#define CPM_CR_INIT_RX ((ushort)0x0001)
+#define CPM_CR_INIT_TX ((ushort)0x0002)
+#define CPM_CR_HUNT_MODE ((ushort)0x0003)
+#define CPM_CR_STOP_TX ((ushort)0x0004)
+#define CPM_CR_RESTART_TX ((ushort)0x0006)
+#define CPM_CR_SET_GADDR ((ushort)0x0008)
+
+#define mk_cr_cmd(PG, SBC, MCN, OP) \
+ ((PG << 26) | (SBC << 21) | (MCN << 6) | OP)
+
+/* Dual Port RAM addresses. The first 16K is available for almost
+ * any CPM use, so we put the BDs there. The first 128 bytes are
+ * used for SMC1 and SMC2 parameter RAM, so we start allocating
+ * BDs above that. All of this must change when we start
+ * downloading RAM microcode.
+ */
+#define CPM_DATAONLY_BASE ((uint)128)
+#define CPM_DATAONLY_SIZE ((uint)(16 * 1024) - CPM_DATAONLY_BASE)
+#define CPM_DP_NOSPACE ((uint)0x7fffffff)
+#define CPM_FCC_SPECIAL_BASE ((uint)0x0000b000)
+
+/* The number of pages of host memory we allocate for CPM. This is
+ * done early in kernel initialization to get physically contiguous
+ * pages.
+ */
+#define NUM_CPM_HOST_PAGES 2
+
+/* Export the base address of the communication processor registers
+ * and dual port ram.
+ */
+/*extern cpm8560_t *cpmp; Pointer to comm processor */
+uint m8560_cpm_dpalloc(uint size, uint align);
+uint m8560_cpm_hostalloc(uint size, uint align);
+void m8560_cpm_setbrg(uint brg, uint rate);
+void m8560_cpm_fastbrg(uint brg, uint rate, int div16);
+void m8560_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel);
+
+/* Buffer descriptors used by many of the CPM protocols.
+*/
+typedef struct cpm_buf_desc {
+ ushort cbd_sc; /* Status and Control */
+ ushort cbd_datlen; /* Data length in buffer */
+ uint cbd_bufaddr; /* Buffer address in host memory */
+} cbd_t;
+
+#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */
+#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
+#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
+#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
+#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
+#define BD_SC_CM ((ushort)0x0200) /* Continous mode */
+#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
+#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
+#define BD_SC_BR ((ushort)0x0020) /* Break received */
+#define BD_SC_FR ((ushort)0x0010) /* Framing error */
+#define BD_SC_PR ((ushort)0x0008) /* Parity error */
+#define BD_SC_OV ((ushort)0x0002) /* Overrun */
+#define BD_SC_CD ((ushort)0x0001) /* ?? */
+
+/* Function code bits, usually generic to devices.
+*/
+#define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */
+#define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */
+#define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */
+#define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */
+#define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */
+
+/* Parameter RAM offsets from the base.
+*/
+#define CPM_POST_WORD_ADDR 0x80FC /* steal a long at the end of SCC1 */
+#define PROFF_SCC1 ((uint)0x8000)
+#define PROFF_SCC2 ((uint)0x8100)
+#define PROFF_SCC3 ((uint)0x8200)
+#define PROFF_SCC4 ((uint)0x8300)
+#define PROFF_FCC1 ((uint)0x8400)
+#define PROFF_FCC2 ((uint)0x8500)
+#define PROFF_FCC3 ((uint)0x8600)
+#define PROFF_MCC1 ((uint)0x8700)
+#define PROFF_MCC2 ((uint)0x8800)
+#define PROFF_SPI_BASE ((uint)0x89fc)
+#define PROFF_TIMERS ((uint)0x8ae0)
+#define PROFF_REVNUM ((uint)0x8af0)
+#define PROFF_RAND ((uint)0x8af8)
+#define PROFF_I2C_BASE ((uint)0x8afc)
+
+/* Baud rate generators.
+*/
+#define CPM_BRG_RST ((uint)0x00020000)
+#define CPM_BRG_EN ((uint)0x00010000)
+#define CPM_BRG_EXTC_INT ((uint)0x00000000)
+#define CPM_BRG_EXTC_CLK3_9 ((uint)0x00004000)
+#define CPM_BRG_EXTC_CLK5_15 ((uint)0x00008000)
+#define CPM_BRG_ATB ((uint)0x00002000)
+#define CPM_BRG_CD_MASK ((uint)0x00001ffe)
+#define CPM_BRG_DIV16 ((uint)0x00000001)
+
+/* SCCs.
+*/
+#define SCC_GSMRH_IRP ((uint)0x00040000)
+#define SCC_GSMRH_GDE ((uint)0x00010000)
+#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
+#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
+#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
+#define SCC_GSMRH_REVD ((uint)0x00002000)
+#define SCC_GSMRH_TRX ((uint)0x00001000)
+#define SCC_GSMRH_TTX ((uint)0x00000800)
+#define SCC_GSMRH_CDP ((uint)0x00000400)
+#define SCC_GSMRH_CTSP ((uint)0x00000200)
+#define SCC_GSMRH_CDS ((uint)0x00000100)
+#define SCC_GSMRH_CTSS ((uint)0x00000080)
+#define SCC_GSMRH_TFL ((uint)0x00000040)
+#define SCC_GSMRH_RFW ((uint)0x00000020)
+#define SCC_GSMRH_TXSY ((uint)0x00000010)
+#define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
+#define SCC_GSMRH_SYNL8 ((uint)0x00000008)
+#define SCC_GSMRH_SYNL4 ((uint)0x00000004)
+#define SCC_GSMRH_RTSM ((uint)0x00000002)
+#define SCC_GSMRH_RSYN ((uint)0x00000001)
+
+#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
+#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
+#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
+#define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
+#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
+#define SCC_GSMRL_TCI ((uint)0x10000000)
+#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
+#define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
+#define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
+#define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
+#define SCC_GSMRL_RINV ((uint)0x02000000)
+#define SCC_GSMRL_TINV ((uint)0x01000000)
+#define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
+#define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
+#define SCC_GSMRL_TPL_48 ((uint)0x00800000)
+#define SCC_GSMRL_TPL_32 ((uint)0x00600000)
+#define SCC_GSMRL_TPL_16 ((uint)0x00400000)
+#define SCC_GSMRL_TPL_8 ((uint)0x00200000)
+#define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
+#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
+#define SCC_GSMRL_TPP_01 ((uint)0x00100000)
+#define SCC_GSMRL_TPP_10 ((uint)0x00080000)
+#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
+#define SCC_GSMRL_TEND ((uint)0x00040000)
+#define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
+#define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
+#define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
+#define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
+#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
+#define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
+#define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
+#define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
+#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
+#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
+#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
+#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
+#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
+#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
+#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
+#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
+#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
+#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
+#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
+#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
+#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
+#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
+#define SCC_GSMRL_ENR ((uint)0x00000020)
+#define SCC_GSMRL_ENT ((uint)0x00000010)
+#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
+#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
+#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
+#define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
+#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
+#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
+#define SCC_GSMRL_MODE_UART ((uint)0x00000004)
+#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
+#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
+#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
+
+#define SCC_TODR_TOD ((ushort)0x8000)
+
+/* SCC Event and Mask register.
+*/
+#define SCCM_TXE ((unsigned char)0x10)
+#define SCCM_BSY ((unsigned char)0x04)
+#define SCCM_TX ((unsigned char)0x02)
+#define SCCM_RX ((unsigned char)0x01)
+
+typedef struct scc_param {
+ ushort scc_rbase; /* Rx Buffer descriptor base address */
+ ushort scc_tbase; /* Tx Buffer descriptor base address */
+ u_char scc_rfcr; /* Rx function code */
+ u_char scc_tfcr; /* Tx function code */
+ ushort scc_mrblr; /* Max receive buffer length */
+ uint scc_rstate; /* Internal */
+ uint scc_idp; /* Internal */
+ ushort scc_rbptr; /* Internal */
+ ushort scc_ibc; /* Internal */
+ uint scc_rxtmp; /* Internal */
+ uint scc_tstate; /* Internal */
+ uint scc_tdp; /* Internal */
+ ushort scc_tbptr; /* Internal */
+ ushort scc_tbc; /* Internal */
+ uint scc_txtmp; /* Internal */
+ uint scc_rcrc; /* Internal */
+ uint scc_tcrc; /* Internal */
+} sccp_t;
+
+/* CPM Ethernet through SCC1.
+ */
+typedef struct scc_enet {
+ sccp_t sen_genscc;
+ uint sen_cpres; /* Preset CRC */
+ uint sen_cmask; /* Constant mask for CRC */
+ uint sen_crcec; /* CRC Error counter */
+ uint sen_alec; /* alignment error counter */
+ uint sen_disfc; /* discard frame counter */
+ ushort sen_pads; /* Tx short frame pad character */
+ ushort sen_retlim; /* Retry limit threshold */
+ ushort sen_retcnt; /* Retry limit counter */
+ ushort sen_maxflr; /* maximum frame length register */
+ ushort sen_minflr; /* minimum frame length register */
+ ushort sen_maxd1; /* maximum DMA1 length */
+ ushort sen_maxd2; /* maximum DMA2 length */
+ ushort sen_maxd; /* Rx max DMA */
+ ushort sen_dmacnt; /* Rx DMA counter */
+ ushort sen_maxb; /* Max BD byte count */
+ ushort sen_gaddr1; /* Group address filter */
+ ushort sen_gaddr2;
+ ushort sen_gaddr3;
+ ushort sen_gaddr4;
+ uint sen_tbuf0data0; /* Save area 0 - current frame */
+ uint sen_tbuf0data1; /* Save area 1 - current frame */
+ uint sen_tbuf0rba; /* Internal */
+ uint sen_tbuf0crc; /* Internal */
+ ushort sen_tbuf0bcnt; /* Internal */
+ ushort sen_paddrh; /* physical address (MSB) */
+ ushort sen_paddrm;
+ ushort sen_paddrl; /* physical address (LSB) */
+ ushort sen_pper; /* persistence */
+ ushort sen_rfbdptr; /* Rx first BD pointer */
+ ushort sen_tfbdptr; /* Tx first BD pointer */
+ ushort sen_tlbdptr; /* Tx last BD pointer */
+ uint sen_tbuf1data0; /* Save area 0 - current frame */
+ uint sen_tbuf1data1; /* Save area 1 - current frame */
+ uint sen_tbuf1rba; /* Internal */
+ uint sen_tbuf1crc; /* Internal */
+ ushort sen_tbuf1bcnt; /* Internal */
+ ushort sen_txlen; /* Tx Frame length counter */
+ ushort sen_iaddr1; /* Individual address filter */
+ ushort sen_iaddr2;
+ ushort sen_iaddr3;
+ ushort sen_iaddr4;
+ ushort sen_boffcnt; /* Backoff counter */
+
+ /* NOTE: Some versions of the manual have the following items
+ * incorrectly documented. Below is the proper order.
+ */
+ ushort sen_taddrh; /* temp address (MSB) */
+ ushort sen_taddrm;
+ ushort sen_taddrl; /* temp address (LSB) */
+} scc_enet_t;
+
+
+/* SCC Event register as used by Ethernet.
+*/
+#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
+#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
+#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
+#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
+#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
+#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
+
+/* SCC Mode Register (PSMR) as used by Ethernet.
+*/
+#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */
+#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */
+#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */
+#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */
+#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
+#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */
+#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
+#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */
+#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */
+#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */
+#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */
+#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */
+#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */
+
+/* Buffer descriptor control/status used by Ethernet receive.
+ * Common to SCC and FCC.
+ */
+#define BD_ENET_RX_EMPTY ((ushort)0x8000)
+#define BD_ENET_RX_WRAP ((ushort)0x2000)
+#define BD_ENET_RX_INTR ((ushort)0x1000)
+#define BD_ENET_RX_LAST ((ushort)0x0800)
+#define BD_ENET_RX_FIRST ((ushort)0x0400)
+#define BD_ENET_RX_MISS ((ushort)0x0100)
+#define BD_ENET_RX_BC ((ushort)0x0080) /* FCC Only */
+#define BD_ENET_RX_MC ((ushort)0x0040) /* FCC Only */
+#define BD_ENET_RX_LG ((ushort)0x0020)
+#define BD_ENET_RX_NO ((ushort)0x0010)
+#define BD_ENET_RX_SH ((ushort)0x0008)
+#define BD_ENET_RX_CR ((ushort)0x0004)
+#define BD_ENET_RX_OV ((ushort)0x0002)
+#define BD_ENET_RX_CL ((ushort)0x0001)
+#define BD_ENET_RX_STATS ((ushort)0x01ff) /* All status bits */
+
+/* Buffer descriptor control/status used by Ethernet transmit.
+ * Common to SCC and FCC.
+ */
+#define BD_ENET_TX_READY ((ushort)0x8000)
+#define BD_ENET_TX_PAD ((ushort)0x4000)
+#define BD_ENET_TX_WRAP ((ushort)0x2000)
+#define BD_ENET_TX_INTR ((ushort)0x1000)
+#define BD_ENET_TX_LAST ((ushort)0x0800)
+#define BD_ENET_TX_TC ((ushort)0x0400)
+#define BD_ENET_TX_DEF ((ushort)0x0200)
+#define BD_ENET_TX_HB ((ushort)0x0100)
+#define BD_ENET_TX_LC ((ushort)0x0080)
+#define BD_ENET_TX_RL ((ushort)0x0040)
+#define BD_ENET_TX_RCMASK ((ushort)0x003c)
+#define BD_ENET_TX_UN ((ushort)0x0002)
+#define BD_ENET_TX_CSL ((ushort)0x0001)
+#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
+
+/* SCC as UART
+*/
+typedef struct scc_uart {
+ sccp_t scc_genscc;
+ uint scc_res1; /* Reserved */
+ uint scc_res2; /* Reserved */
+ ushort scc_maxidl; /* Maximum idle chars */
+ ushort scc_idlc; /* temp idle counter */
+ ushort scc_brkcr; /* Break count register */
+ ushort scc_parec; /* receive parity error counter */
+ ushort scc_frmec; /* receive framing error counter */
+ ushort scc_nosec; /* receive noise counter */
+ ushort scc_brkec; /* receive break condition counter */
+ ushort scc_brkln; /* last received break length */
+ ushort scc_uaddr1; /* UART address character 1 */
+ ushort scc_uaddr2; /* UART address character 2 */
+ ushort scc_rtemp; /* Temp storage */
+ ushort scc_toseq; /* Transmit out of sequence char */
+ ushort scc_char1; /* control character 1 */
+ ushort scc_char2; /* control character 2 */
+ ushort scc_char3; /* control character 3 */
+ ushort scc_char4; /* control character 4 */
+ ushort scc_char5; /* control character 5 */
+ ushort scc_char6; /* control character 6 */
+ ushort scc_char7; /* control character 7 */
+ ushort scc_char8; /* control character 8 */
+ ushort scc_rccm; /* receive control character mask */
+ ushort scc_rccr; /* receive control character register */
+ ushort scc_rlbc; /* receive last break character */
+} scc_uart_t;
+
+/* SCC Event and Mask registers when it is used as a UART.
+*/
+#define UART_SCCM_GLR ((ushort)0x1000)
+#define UART_SCCM_GLT ((ushort)0x0800)
+#define UART_SCCM_AB ((ushort)0x0200)
+#define UART_SCCM_IDL ((ushort)0x0100)
+#define UART_SCCM_GRA ((ushort)0x0080)
+#define UART_SCCM_BRKE ((ushort)0x0040)
+#define UART_SCCM_BRKS ((ushort)0x0020)
+#define UART_SCCM_CCR ((ushort)0x0008)
+#define UART_SCCM_BSY ((ushort)0x0004)
+#define UART_SCCM_TX ((ushort)0x0002)
+#define UART_SCCM_RX ((ushort)0x0001)
+
+/* The SCC PSMR when used as a UART.
+*/
+#define SCU_PSMR_FLC ((ushort)0x8000)
+#define SCU_PSMR_SL ((ushort)0x4000)
+#define SCU_PSMR_CL ((ushort)0x3000)
+#define SCU_PSMR_UM ((ushort)0x0c00)
+#define SCU_PSMR_FRZ ((ushort)0x0200)
+#define SCU_PSMR_RZS ((ushort)0x0100)
+#define SCU_PSMR_SYN ((ushort)0x0080)
+#define SCU_PSMR_DRT ((ushort)0x0040)
+#define SCU_PSMR_PEN ((ushort)0x0010)
+#define SCU_PSMR_RPM ((ushort)0x000c)
+#define SCU_PSMR_REVP ((ushort)0x0008)
+#define SCU_PSMR_TPM ((ushort)0x0003)
+#define SCU_PSMR_TEVP ((ushort)0x0003)
+
+/* CPM Transparent mode SCC.
+ */
+typedef struct scc_trans {
+ sccp_t st_genscc;
+ uint st_cpres; /* Preset CRC */
+ uint st_cmask; /* Constant mask for CRC */
+} scc_trans_t;
+
+#define BD_SCC_TX_LAST ((ushort)0x0800)
+
+/* How about some FCCs.....
+*/
+#define FCC_GFMR_DIAG_NORM ((uint)0x00000000)
+#define FCC_GFMR_DIAG_LE ((uint)0x40000000)
+#define FCC_GFMR_DIAG_AE ((uint)0x80000000)
+#define FCC_GFMR_DIAG_ALE ((uint)0xc0000000)
+#define FCC_GFMR_TCI ((uint)0x20000000)
+#define FCC_GFMR_TRX ((uint)0x10000000)
+#define FCC_GFMR_TTX ((uint)0x08000000)
+#define FCC_GFMR_TTX ((uint)0x08000000)
+#define FCC_GFMR_CDP ((uint)0x04000000)
+#define FCC_GFMR_CTSP ((uint)0x02000000)
+#define FCC_GFMR_CDS ((uint)0x01000000)
+#define FCC_GFMR_CTSS ((uint)0x00800000)
+#define FCC_GFMR_SYNL_NONE ((uint)0x00000000)
+#define FCC_GFMR_SYNL_AUTO ((uint)0x00004000)
+#define FCC_GFMR_SYNL_8 ((uint)0x00008000)
+#define FCC_GFMR_SYNL_16 ((uint)0x0000c000)
+#define FCC_GFMR_RTSM ((uint)0x00002000)
+#define FCC_GFMR_RENC_NRZ ((uint)0x00000000)
+#define FCC_GFMR_RENC_NRZI ((uint)0x00000800)
+#define FCC_GFMR_REVD ((uint)0x00000400)
+#define FCC_GFMR_TENC_NRZ ((uint)0x00000000)
+#define FCC_GFMR_TENC_NRZI ((uint)0x00000100)
+#define FCC_GFMR_TCRC_16 ((uint)0x00000000)
+#define FCC_GFMR_TCRC_32 ((uint)0x00000080)
+#define FCC_GFMR_ENR ((uint)0x00000020)
+#define FCC_GFMR_ENT ((uint)0x00000010)
+#define FCC_GFMR_MODE_ENET ((uint)0x0000000c)
+#define FCC_GFMR_MODE_ATM ((uint)0x0000000a)
+#define FCC_GFMR_MODE_HDLC ((uint)0x00000000)
+
+/* Generic FCC parameter ram.
+*/
+typedef struct fcc_param {
+ ushort fcc_riptr; /* Rx Internal temp pointer */
+ ushort fcc_tiptr; /* Tx Internal temp pointer */
+ ushort fcc_res1;
+ ushort fcc_mrblr; /* Max receive buffer length, mod 32 bytes */
+ uint fcc_rstate; /* Upper byte is Func code, must be set */
+ uint fcc_rbase; /* Receive BD base */
+ ushort fcc_rbdstat; /* RxBD status */
+ ushort fcc_rbdlen; /* RxBD down counter */
+ uint fcc_rdptr; /* RxBD internal data pointer */
+ uint fcc_tstate; /* Upper byte is Func code, must be set */
+ uint fcc_tbase; /* Transmit BD base */
+ ushort fcc_tbdstat; /* TxBD status */
+ ushort fcc_tbdlen; /* TxBD down counter */
+ uint fcc_tdptr; /* TxBD internal data pointer */
+ uint fcc_rbptr; /* Rx BD Internal buf pointer */
+ uint fcc_tbptr; /* Tx BD Internal buf pointer */
+ uint fcc_rcrc; /* Rx temp CRC */
+ uint fcc_res2;
+ uint fcc_tcrc; /* Tx temp CRC */
+} fccp_t;
+
+
+/* Ethernet controller through FCC.
+*/
+typedef struct fcc_enet {
+ fccp_t fen_genfcc;
+ uint fen_statbuf; /* Internal status buffer */
+ uint fen_camptr; /* CAM address */
+ uint fen_cmask; /* Constant mask for CRC */
+ uint fen_cpres; /* Preset CRC */
+ uint fen_crcec; /* CRC Error counter */
+ uint fen_alec; /* alignment error counter */
+ uint fen_disfc; /* discard frame counter */
+ ushort fen_retlim; /* Retry limit */
+ ushort fen_retcnt; /* Retry counter */
+ ushort fen_pper; /* Persistence */
+ ushort fen_boffcnt; /* backoff counter */
+ uint fen_gaddrh; /* Group address filter, high 32-bits */
+ uint fen_gaddrl; /* Group address filter, low 32-bits */
+ ushort fen_tfcstat; /* out of sequence TxBD */
+ ushort fen_tfclen;
+ uint fen_tfcptr;
+ ushort fen_mflr; /* Maximum frame length (1518) */
+ ushort fen_paddrh; /* MAC address */
+ ushort fen_paddrm;
+ ushort fen_paddrl;
+ ushort fen_ibdcount; /* Internal BD counter */
+ ushort fen_ibdstart; /* Internal BD start pointer */
+ ushort fen_ibdend; /* Internal BD end pointer */
+ ushort fen_txlen; /* Internal Tx frame length counter */
+ uint fen_ibdbase[8]; /* Internal use */
+ uint fen_iaddrh; /* Individual address filter */
+ uint fen_iaddrl;
+ ushort fen_minflr; /* Minimum frame length (64) */
+ ushort fen_taddrh; /* Filter transfer MAC address */
+ ushort fen_taddrm;
+ ushort fen_taddrl;
+ ushort fen_padptr; /* Pointer to pad byte buffer */
+ ushort fen_cftype; /* control frame type */
+ ushort fen_cfrange; /* control frame range */
+ ushort fen_maxb; /* maximum BD count */
+ ushort fen_maxd1; /* Max DMA1 length (1520) */
+ ushort fen_maxd2; /* Max DMA2 length (1520) */
+ ushort fen_maxd; /* internal max DMA count */
+ ushort fen_dmacnt; /* internal DMA counter */
+ uint fen_octc; /* Total octect counter */
+ uint fen_colc; /* Total collision counter */
+ uint fen_broc; /* Total broadcast packet counter */
+ uint fen_mulc; /* Total multicast packet count */
+ uint fen_uspc; /* Total packets < 64 bytes */
+ uint fen_frgc; /* Total packets < 64 bytes with errors */
+ uint fen_ospc; /* Total packets > 1518 */
+ uint fen_jbrc; /* Total packets > 1518 with errors */
+ uint fen_p64c; /* Total packets == 64 bytes */
+ uint fen_p65c; /* Total packets 64 < bytes <= 127 */
+ uint fen_p128c; /* Total packets 127 < bytes <= 255 */
+ uint fen_p256c; /* Total packets 256 < bytes <= 511 */
+ uint fen_p512c; /* Total packets 512 < bytes <= 1023 */
+ uint fen_p1024c; /* Total packets 1024 < bytes <= 1518 */
+ uint fen_cambuf; /* Internal CAM buffer poiner */
+ ushort fen_rfthr; /* Received frames threshold */
+ ushort fen_rfcnt; /* Received frames count */
+} fcc_enet_t;
+
+/* FCC Event/Mask register as used by Ethernet.
+*/
+#define FCC_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
+#define FCC_ENET_RXC ((ushort)0x0040) /* Control Frame Received */
+#define FCC_ENET_TXC ((ushort)0x0020) /* Out of seq. Tx sent */
+#define FCC_ENET_TXE ((ushort)0x0010) /* Transmit Error */
+#define FCC_ENET_RXF ((ushort)0x0008) /* Full frame received */
+#define FCC_ENET_BSY ((ushort)0x0004) /* Busy. Rx Frame dropped */
+#define FCC_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
+#define FCC_ENET_RXB ((ushort)0x0001) /* A buffer was received */
+
+/* FCC Mode Register (FPSMR) as used by Ethernet.
+*/
+#define FCC_PSMR_HBC ((uint)0x80000000) /* Enable heartbeat */
+#define FCC_PSMR_FC ((uint)0x40000000) /* Force Collision */
+#define FCC_PSMR_SBT ((uint)0x20000000) /* Stop backoff timer */
+#define FCC_PSMR_LPB ((uint)0x10000000) /* Local protect. 1 = FDX */
+#define FCC_PSMR_LCW ((uint)0x08000000) /* Late collision select */
+#define FCC_PSMR_FDE ((uint)0x04000000) /* Full Duplex Enable */
+#define FCC_PSMR_MON ((uint)0x02000000) /* RMON Enable */
+#define FCC_PSMR_PRO ((uint)0x00400000) /* Promiscuous Enable */
+#define FCC_PSMR_FCE ((uint)0x00200000) /* Flow Control Enable */
+#define FCC_PSMR_RSH ((uint)0x00100000) /* Receive Short Frames */
+#define FCC_PSMR_CAM ((uint)0x00000400) /* CAM enable */
+#define FCC_PSMR_BRO ((uint)0x00000200) /* Broadcast pkt discard */
+#define FCC_PSMR_ENCRC ((uint)0x00000080) /* Use 32-bit CRC */
+
+/* IIC parameter RAM.
+*/
+typedef struct iic {
+ ushort iic_rbase; /* Rx Buffer descriptor base address */
+ ushort iic_tbase; /* Tx Buffer descriptor base address */
+ u_char iic_rfcr; /* Rx function code */
+ u_char iic_tfcr; /* Tx function code */
+ ushort iic_mrblr; /* Max receive buffer length */
+ uint iic_rstate; /* Internal */
+ uint iic_rdp; /* Internal */
+ ushort iic_rbptr; /* Internal */
+ ushort iic_rbc; /* Internal */
+ uint iic_rxtmp; /* Internal */
+ uint iic_tstate; /* Internal */
+ uint iic_tdp; /* Internal */
+ ushort iic_tbptr; /* Internal */
+ ushort iic_tbc; /* Internal */
+ uint iic_txtmp; /* Internal */
+} iic_t;
+
+/* SPI parameter RAM.
+*/
+typedef struct spi {
+ ushort spi_rbase; /* Rx Buffer descriptor base address */
+ ushort spi_tbase; /* Tx Buffer descriptor base address */
+ u_char spi_rfcr; /* Rx function code */
+ u_char spi_tfcr; /* Tx function code */
+ ushort spi_mrblr; /* Max receive buffer length */
+ uint spi_rstate; /* Internal */
+ uint spi_rdp; /* Internal */
+ ushort spi_rbptr; /* Internal */
+ ushort spi_rbc; /* Internal */
+ uint spi_rxtmp; /* Internal */
+ uint spi_tstate; /* Internal */
+ uint spi_tdp; /* Internal */
+ ushort spi_tbptr; /* Internal */
+ ushort spi_tbc; /* Internal */
+ uint spi_txtmp; /* Internal */
+ uint spi_res; /* Tx temp. */
+ uint spi_res1[4]; /* SDMA temp. */
+} spi_t;
+
+/* SPI Mode register.
+*/
+#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */
+#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */
+#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */
+#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */
+#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */
+#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */
+#define SPMODE_EN ((ushort)0x0100) /* Enable */
+#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */
+#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */
+
+#define SPMODE_LEN(x) ((((x)-1)&0xF)<<4)
+#define SPMODE_PM(x) ((x) &0xF)
+
+#define SPI_EB ((u_char)0x10) /* big endian byte order */
+
+#define BD_IIC_START ((ushort)0x0400)
+
+/*-----------------------------------------------------------------------
+ * CMXFCR - CMX FCC Clock Route Register 15-12
+ */
+#define CMXFCR_FC1 0x40000000 /* FCC1 connection */
+#define CMXFCR_RF1CS_MSK 0x38000000 /* Receive FCC1 Clock Source Mask */
+#define CMXFCR_TF1CS_MSK 0x07000000 /* Transmit FCC1 Clock Source Mask */
+#define CMXFCR_FC2 0x00400000 /* FCC2 connection */
+#define CMXFCR_RF2CS_MSK 0x00380000 /* Receive FCC2 Clock Source Mask */
+#define CMXFCR_TF2CS_MSK 0x00070000 /* Transmit FCC2 Clock Source Mask */
+#define CMXFCR_FC3 0x00004000 /* FCC3 connection */
+#define CMXFCR_RF3CS_MSK 0x00003800 /* Receive FCC3 Clock Source Mask */
+#define CMXFCR_TF3CS_MSK 0x00000700 /* Transmit FCC3 Clock Source Mask */
+
+#define CMXFCR_RF1CS_BRG5 0x00000000 /* Receive FCC1 Clock Source is BRG5 */
+#define CMXFCR_RF1CS_BRG6 0x08000000 /* Receive FCC1 Clock Source is BRG6 */
+#define CMXFCR_RF1CS_BRG7 0x10000000 /* Receive FCC1 Clock Source is BRG7 */
+#define CMXFCR_RF1CS_BRG8 0x18000000 /* Receive FCC1 Clock Source is BRG8 */
+#define CMXFCR_RF1CS_CLK9 0x20000000 /* Receive FCC1 Clock Source is CLK9 */
+#define CMXFCR_RF1CS_CLK10 0x28000000 /* Receive FCC1 Clock Source is CLK10 */
+#define CMXFCR_RF1CS_CLK11 0x30000000 /* Receive FCC1 Clock Source is CLK11 */
+#define CMXFCR_RF1CS_CLK12 0x38000000 /* Receive FCC1 Clock Source is CLK12 */
+
+#define CMXFCR_TF1CS_BRG5 0x00000000 /* Transmit FCC1 Clock Source is BRG5 */
+#define CMXFCR_TF1CS_BRG6 0x01000000 /* Transmit FCC1 Clock Source is BRG6 */
+#define CMXFCR_TF1CS_BRG7 0x02000000 /* Transmit FCC1 Clock Source is BRG7 */
+#define CMXFCR_TF1CS_BRG8 0x03000000 /* Transmit FCC1 Clock Source is BRG8 */
+#define CMXFCR_TF1CS_CLK9 0x04000000 /* Transmit FCC1 Clock Source is CLK9 */
+#define CMXFCR_TF1CS_CLK10 0x05000000 /* Transmit FCC1 Clock Source is CLK10 */
+#define CMXFCR_TF1CS_CLK11 0x06000000 /* Transmit FCC1 Clock Source is CLK11 */
+#define CMXFCR_TF1CS_CLK12 0x07000000 /* Transmit FCC1 Clock Source is CLK12 */
+
+#define CMXFCR_RF2CS_BRG5 0x00000000 /* Receive FCC2 Clock Source is BRG5 */
+#define CMXFCR_RF2CS_BRG6 0x00080000 /* Receive FCC2 Clock Source is BRG6 */
+#define CMXFCR_RF2CS_BRG7 0x00100000 /* Receive FCC2 Clock Source is BRG7 */
+#define CMXFCR_RF2CS_BRG8 0x00180000 /* Receive FCC2 Clock Source is BRG8 */
+#define CMXFCR_RF2CS_CLK13 0x00200000 /* Receive FCC2 Clock Source is CLK13 */
+#define CMXFCR_RF2CS_CLK14 0x00280000 /* Receive FCC2 Clock Source is CLK14 */
+#define CMXFCR_RF2CS_CLK15 0x00300000 /* Receive FCC2 Clock Source is CLK15 */
+#define CMXFCR_RF2CS_CLK16 0x00380000 /* Receive FCC2 Clock Source is CLK16 */
+
+#define CMXFCR_TF2CS_BRG5 0x00000000 /* Transmit FCC2 Clock Source is BRG5 */
+#define CMXFCR_TF2CS_BRG6 0x00010000 /* Transmit FCC2 Clock Source is BRG6 */
+#define CMXFCR_TF2CS_BRG7 0x00020000 /* Transmit FCC2 Clock Source is BRG7 */
+#define CMXFCR_TF2CS_BRG8 0x00030000 /* Transmit FCC2 Clock Source is BRG8 */
+#define CMXFCR_TF2CS_CLK13 0x00040000 /* Transmit FCC2 Clock Source is CLK13 */
+#define CMXFCR_TF2CS_CLK14 0x00050000 /* Transmit FCC2 Clock Source is CLK14 */
+#define CMXFCR_TF2CS_CLK15 0x00060000 /* Transmit FCC2 Clock Source is CLK15 */
+#define CMXFCR_TF2CS_CLK16 0x00070000 /* Transmit FCC2 Clock Source is CLK16 */
+
+#define CMXFCR_RF3CS_BRG5 0x00000000 /* Receive FCC3 Clock Source is BRG5 */
+#define CMXFCR_RF3CS_BRG6 0x00000800 /* Receive FCC3 Clock Source is BRG6 */
+#define CMXFCR_RF3CS_BRG7 0x00001000 /* Receive FCC3 Clock Source is BRG7 */
+#define CMXFCR_RF3CS_BRG8 0x00001800 /* Receive FCC3 Clock Source is BRG8 */
+#define CMXFCR_RF3CS_CLK13 0x00002000 /* Receive FCC3 Clock Source is CLK13 */
+#define CMXFCR_RF3CS_CLK14 0x00002800 /* Receive FCC3 Clock Source is CLK14 */
+#define CMXFCR_RF3CS_CLK15 0x00003000 /* Receive FCC3 Clock Source is CLK15 */
+#define CMXFCR_RF3CS_CLK16 0x00003800 /* Receive FCC3 Clock Source is CLK16 */
+
+#define CMXFCR_TF3CS_BRG5 0x00000000 /* Transmit FCC3 Clock Source is BRG5 */
+#define CMXFCR_TF3CS_BRG6 0x00000100 /* Transmit FCC3 Clock Source is BRG6 */
+#define CMXFCR_TF3CS_BRG7 0x00000200 /* Transmit FCC3 Clock Source is BRG7 */
+#define CMXFCR_TF3CS_BRG8 0x00000300 /* Transmit FCC3 Clock Source is BRG8 */
+#define CMXFCR_TF3CS_CLK13 0x00000400 /* Transmit FCC3 Clock Source is CLK13 */
+#define CMXFCR_TF3CS_CLK14 0x00000500 /* Transmit FCC3 Clock Source is CLK14 */
+#define CMXFCR_TF3CS_CLK15 0x00000600 /* Transmit FCC3 Clock Source is CLK15 */
+#define CMXFCR_TF3CS_CLK16 0x00000700 /* Transmit FCC3 Clock Source is CLK16 */
+
+/*-----------------------------------------------------------------------
+ * CMXSCR - CMX SCC Clock Route Register 15-14
+ */
+#define CMXSCR_GR1 0x80000000 /* Grant Support of SCC1 */
+#define CMXSCR_SC1 0x40000000 /* SCC1 connection */
+#define CMXSCR_RS1CS_MSK 0x38000000 /* Receive SCC1 Clock Source Mask */
+#define CMXSCR_TS1CS_MSK 0x07000000 /* Transmit SCC1 Clock Source Mask */
+#define CMXSCR_GR2 0x00800000 /* Grant Support of SCC2 */
+#define CMXSCR_SC2 0x00400000 /* SCC2 connection */
+#define CMXSCR_RS2CS_MSK 0x00380000 /* Receive SCC2 Clock Source Mask */
+#define CMXSCR_TS2CS_MSK 0x00070000 /* Transmit SCC2 Clock Source Mask */
+#define CMXSCR_GR3 0x00008000 /* Grant Support of SCC3 */
+#define CMXSCR_SC3 0x00004000 /* SCC3 connection */
+#define CMXSCR_RS3CS_MSK 0x00003800 /* Receive SCC3 Clock Source Mask */
+#define CMXSCR_TS3CS_MSK 0x00000700 /* Transmit SCC3 Clock Source Mask */
+#define CMXSCR_GR4 0x00000080 /* Grant Support of SCC4 */
+#define CMXSCR_SC4 0x00000040 /* SCC4 connection */
+#define CMXSCR_RS4CS_MSK 0x00000038 /* Receive SCC4 Clock Source Mask */
+#define CMXSCR_TS4CS_MSK 0x00000007 /* Transmit SCC4 Clock Source Mask */
+
+#define CMXSCR_RS1CS_BRG1 0x00000000 /* SCC1 Rx Clock Source is BRG1 */
+#define CMXSCR_RS1CS_BRG2 0x08000000 /* SCC1 Rx Clock Source is BRG2 */
+#define CMXSCR_RS1CS_BRG3 0x10000000 /* SCC1 Rx Clock Source is BRG3 */
+#define CMXSCR_RS1CS_BRG4 0x18000000 /* SCC1 Rx Clock Source is BRG4 */
+#define CMXSCR_RS1CS_CLK11 0x20000000 /* SCC1 Rx Clock Source is CLK11 */
+#define CMXSCR_RS1CS_CLK12 0x28000000 /* SCC1 Rx Clock Source is CLK12 */
+#define CMXSCR_RS1CS_CLK3 0x30000000 /* SCC1 Rx Clock Source is CLK3 */
+#define CMXSCR_RS1CS_CLK4 0x38000000 /* SCC1 Rx Clock Source is CLK4 */
+
+#define CMXSCR_TS1CS_BRG1 0x00000000 /* SCC1 Tx Clock Source is BRG1 */
+#define CMXSCR_TS1CS_BRG2 0x01000000 /* SCC1 Tx Clock Source is BRG2 */
+#define CMXSCR_TS1CS_BRG3 0x02000000 /* SCC1 Tx Clock Source is BRG3 */
+#define CMXSCR_TS1CS_BRG4 0x03000000 /* SCC1 Tx Clock Source is BRG4 */
+#define CMXSCR_TS1CS_CLK11 0x04000000 /* SCC1 Tx Clock Source is CLK11 */
+#define CMXSCR_TS1CS_CLK12 0x05000000 /* SCC1 Tx Clock Source is CLK12 */
+#define CMXSCR_TS1CS_CLK3 0x06000000 /* SCC1 Tx Clock Source is CLK3 */
+#define CMXSCR_TS1CS_CLK4 0x07000000 /* SCC1 Tx Clock Source is CLK4 */
+
+#define CMXSCR_RS2CS_BRG1 0x00000000 /* SCC2 Rx Clock Source is BRG1 */
+#define CMXSCR_RS2CS_BRG2 0x00080000 /* SCC2 Rx Clock Source is BRG2 */
+#define CMXSCR_RS2CS_BRG3 0x00100000 /* SCC2 Rx Clock Source is BRG3 */
+#define CMXSCR_RS2CS_BRG4 0x00180000 /* SCC2 Rx Clock Source is BRG4 */
+#define CMXSCR_RS2CS_CLK11 0x00200000 /* SCC2 Rx Clock Source is CLK11 */
+#define CMXSCR_RS2CS_CLK12 0x00280000 /* SCC2 Rx Clock Source is CLK12 */
+#define CMXSCR_RS2CS_CLK3 0x00300000 /* SCC2 Rx Clock Source is CLK3 */
+#define CMXSCR_RS2CS_CLK4 0x00380000 /* SCC2 Rx Clock Source is CLK4 */
+
+#define CMXSCR_TS2CS_BRG1 0x00000000 /* SCC2 Tx Clock Source is BRG1 */
+#define CMXSCR_TS2CS_BRG2 0x00010000 /* SCC2 Tx Clock Source is BRG2 */
+#define CMXSCR_TS2CS_BRG3 0x00020000 /* SCC2 Tx Clock Source is BRG3 */
+#define CMXSCR_TS2CS_BRG4 0x00030000 /* SCC2 Tx Clock Source is BRG4 */
+#define CMXSCR_TS2CS_CLK11 0x00040000 /* SCC2 Tx Clock Source is CLK11 */
+#define CMXSCR_TS2CS_CLK12 0x00050000 /* SCC2 Tx Clock Source is CLK12 */
+#define CMXSCR_TS2CS_CLK3 0x00060000 /* SCC2 Tx Clock Source is CLK3 */
+#define CMXSCR_TS2CS_CLK4 0x00070000 /* SCC2 Tx Clock Source is CLK4 */
+
+#define CMXSCR_RS3CS_BRG1 0x00000000 /* SCC3 Rx Clock Source is BRG1 */
+#define CMXSCR_RS3CS_BRG2 0x00000800 /* SCC3 Rx Clock Source is BRG2 */
+#define CMXSCR_RS3CS_BRG3 0x00001000 /* SCC3 Rx Clock Source is BRG3 */
+#define CMXSCR_RS3CS_BRG4 0x00001800 /* SCC3 Rx Clock Source is BRG4 */
+#define CMXSCR_RS3CS_CLK5 0x00002000 /* SCC3 Rx Clock Source is CLK5 */
+#define CMXSCR_RS3CS_CLK6 0x00002800 /* SCC3 Rx Clock Source is CLK6 */
+#define CMXSCR_RS3CS_CLK7 0x00003000 /* SCC3 Rx Clock Source is CLK7 */
+#define CMXSCR_RS3CS_CLK8 0x00003800 /* SCC3 Rx Clock Source is CLK8 */
+
+#define CMXSCR_TS3CS_BRG1 0x00000000 /* SCC3 Tx Clock Source is BRG1 */
+#define CMXSCR_TS3CS_BRG2 0x00000100 /* SCC3 Tx Clock Source is BRG2 */
+#define CMXSCR_TS3CS_BRG3 0x00000200 /* SCC3 Tx Clock Source is BRG3 */
+#define CMXSCR_TS3CS_BRG4 0x00000300 /* SCC3 Tx Clock Source is BRG4 */
+#define CMXSCR_TS3CS_CLK5 0x00000400 /* SCC3 Tx Clock Source is CLK5 */
+#define CMXSCR_TS3CS_CLK6 0x00000500 /* SCC3 Tx Clock Source is CLK6 */
+#define CMXSCR_TS3CS_CLK7 0x00000600 /* SCC3 Tx Clock Source is CLK7 */
+#define CMXSCR_TS3CS_CLK8 0x00000700 /* SCC3 Tx Clock Source is CLK8 */
+
+#define CMXSCR_RS4CS_BRG1 0x00000000 /* SCC4 Rx Clock Source is BRG1 */
+#define CMXSCR_RS4CS_BRG2 0x00000008 /* SCC4 Rx Clock Source is BRG2 */
+#define CMXSCR_RS4CS_BRG3 0x00000010 /* SCC4 Rx Clock Source is BRG3 */
+#define CMXSCR_RS4CS_BRG4 0x00000018 /* SCC4 Rx Clock Source is BRG4 */
+#define CMXSCR_RS4CS_CLK5 0x00000020 /* SCC4 Rx Clock Source is CLK5 */
+#define CMXSCR_RS4CS_CLK6 0x00000028 /* SCC4 Rx Clock Source is CLK6 */
+#define CMXSCR_RS4CS_CLK7 0x00000030 /* SCC4 Rx Clock Source is CLK7 */
+#define CMXSCR_RS4CS_CLK8 0x00000038 /* SCC4 Rx Clock Source is CLK8 */
+
+#define CMXSCR_TS4CS_BRG1 0x00000000 /* SCC4 Tx Clock Source is BRG1 */
+#define CMXSCR_TS4CS_BRG2 0x00000001 /* SCC4 Tx Clock Source is BRG2 */
+#define CMXSCR_TS4CS_BRG3 0x00000002 /* SCC4 Tx Clock Source is BRG3 */
+#define CMXSCR_TS4CS_BRG4 0x00000003 /* SCC4 Tx Clock Source is BRG4 */
+#define CMXSCR_TS4CS_CLK5 0x00000004 /* SCC4 Tx Clock Source is CLK5 */
+#define CMXSCR_TS4CS_CLK6 0x00000005 /* SCC4 Tx Clock Source is CLK6 */
+#define CMXSCR_TS4CS_CLK7 0x00000006 /* SCC4 Tx Clock Source is CLK7 */
+#define CMXSCR_TS4CS_CLK8 0x00000007 /* SCC4 Tx Clock Source is CLK8 */
+
+#endif /* __CPM_85XX__ */
unsigned long baudrate;
unsigned long cpu_clk; /* CPU clock in Hz! */
unsigned long bus_clk;
-#if defined(CONFIG_8260)
+#if defined(CONFIG_8260) || defined(CONFIG_MPC8560)
/* There are many clocks on the MPC8260 - see page 9-5 */
unsigned long vco_out;
unsigned long cpm_clk;
unsigned long env_addr; /* Address of Environment struct */
unsigned long env_valid; /* Checksum of Environment valid? */
unsigned long have_console; /* serial_init() was called */
-#if defined(CFG_ALLOC_DPRAM) || defined(CONFIG_8260)
+#if defined(CFG_ALLOC_DPRAM) || defined(CONFIG_8260) || defined(CONFIG_MPC8560)
unsigned int dp_alloc_base;
unsigned int dp_alloc_top;
#endif
--- /dev/null
+/*
+ * MPC85xx Internal Memory Map
+ *
+ * Copyright(c) 2002,2003 Motorola Inc.
+ * Xianghua Xiao (x.xiao@motorola.com)
+ *
+ */
+
+#ifndef __IMMAP_85xx__
+#define __IMMAP_85xx__
+
+
+/* Local-Access Registers and ECM Registers(0x0000-0x2000) */
+
+typedef struct ccsr_local_ecm {
+ uint ccsrbar; /* 0x0 - Control Configuration Status Registers Base Address Register */
+ char res1[4];
+ uint altcbar; /* 0x8 - Alternate Configuration Base Address Register */
+ char res2[4];
+ uint altcar; /* 0x10 - Alternate Configuration Attribute Register */
+ char res3[12];
+ uint bptr; /* 0x20 - Boot Page Translation Register */
+ char res4[3044];
+ uint lawbar0; /* 0xc08 - Local Access Window 0 Base Address Register */
+ char res5[4];
+ uint lawar0; /* 0xc10 - Local Access Window 0 Attributes Register */
+ char res6[20];
+ uint lawbar1; /* 0xc28 - Local Access Window 1 Base Address Register */
+ char res7[4];
+ uint lawar1; /* 0xc30 - Local Access Window 1 Attributes Register */
+ char res8[20];
+ uint lawbar2; /* 0xc48 - Local Access Window 2 Base Address Register */
+ char res9[4];
+ uint lawar2; /* 0xc50 - Local Access Window 2 Attributes Register */
+ char res10[20];
+ uint lawbar3; /* 0xc68 - Local Access Window 3 Base Address Register */
+ char res11[4];
+ uint lawar3; /* 0xc70 - Local Access Window 3 Attributes Register */
+ char res12[20];
+ uint lawbar4; /* 0xc88 - Local Access Window 4 Base Address Register */
+ char res13[4];
+ uint lawar4; /* 0xc90 - Local Access Window 4 Attributes Register */
+ char res14[20];
+ uint lawbar5; /* 0xca8 - Local Access Window 5 Base Address Register */
+ char res15[4];
+ uint lawar5; /* 0xcb0 - Local Access Window 5 Attributes Register */
+ char res16[20];
+ uint lawbar6; /* 0xcc8 - Local Access Window 6 Base Address Register */
+ char res17[4];
+ uint lawar6; /* 0xcd0 - Local Access Window 6 Attributes Register */
+ char res18[20];
+ uint lawbar7; /* 0xce8 - Local Access Window 7 Base Address Register */
+ char res19[4];
+ uint lawar7; /* 0xcf0 - Local Access Window 7 Attributes Register */
+ char res20[780];
+ uint eebacr; /* 0x1000 - ECM CCB Address Configuration Register */
+ char res21[12];
+ uint eebpcr; /* 0x1010 - ECM CCB Port Configuration Register */
+ char res22[3564];
+ uint eedr; /* 0x1e00 - ECM Error Detect Register */
+ char res23[4];
+ uint eeer; /* 0x1e08 - ECM Error Enable Register */
+ uint eeatr; /* 0x1e0c - ECM Error Attributes Capture Register */
+ uint eeadr; /* 0x1e10 - ECM Error Address Capture Register */
+ char res24[492];
+} ccsr_local_ecm_t;
+
+
+/* DDR memory controller registers(0x2000-0x3000) */
+
+typedef struct ccsr_ddr {
+ uint cs0_bnds; /* 0x2000 - DDR Chip Select 0 Memory Bounds */
+ char res1[4];
+ uint cs1_bnds; /* 0x2008 - DDR Chip Select 1 Memory Bounds */
+ char res2[4];
+ uint cs2_bnds; /* 0x2010 - DDR Chip Select 2 Memory Bounds */
+ char res3[4];
+ uint cs3_bnds; /* 0x2018 - DDR Chip Select 3 Memory Bounds */
+ char res4[100];
+ uint cs0_config; /* 0x2080 - DDR Chip Select Configuration */
+ uint cs1_config; /* 0x2084 - DDR Chip Select Configuration */
+ uint cs2_config; /* 0x2088 - DDR Chip Select Configuration */
+ uint cs3_config; /* 0x208c - DDR Chip Select Configuration */
+ char res5[120];
+ uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */
+ uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */
+ uint sdram_cfg; /* 0x2110 - DDR SDRAM Control Configuration */
+ char res6[4];
+ uint sdram_mode; /* 0x2118 - DDR SDRAM Mode Configuration */
+ char res7[8];
+ uint sdram_interval; /* 0x2124 - DDR SDRAM Interval Configuration */
+ char res8[3288];
+ uint data_err_inject_hi; /* 0x2e00 - DDR Memory Data Path Error Injection Mask High */
+ uint data_err_inject_lo; /* 0x2e04 - DDR Memory Data Path Error Injection Mask Low */
+ uint ecc_err_inject; /* 0x2e08 - DDR Memory Data Path Error Injection Mask ECC */
+ char res9[20];
+ uint capture_data_hi; /* 0x2e20 - DDR Memory Data Path Read Capture High */
+ uint capture_data_lo; /* 0x2e24 - DDR Memory Data Path Read Capture Low */
+ uint capture_ecc; /* 0x2e28 - DDR Memory Data Path Read Capture ECC */
+ char res10[20];
+ uint err_detect; /* 0x2e40 - DDR Memory Error Detect */
+ uint err_disable; /* 0x2e44 - DDR Memory Error Disable */
+ uint err_int_en; /* 0x2e48 - DDR */
+ uint capture_attributes; /* 0x2e4c - DDR Memory Error Attributes Capture */
+ uint capture_address; /* 0x2e50 - DDR Memory Error Address Capture */
+ uint capture_ext_address; /* 0x2e54 - DDR Memory Error Extended Address Capture */
+ uint err_sbe; /* 0x2e58 - DDR Memory Single-Bit ECC Error Management */
+ char res11[164];
+ uint debug_1; /* 0x2f00 */
+ uint debug_2;
+ uint debug_3;
+ uint debug_4;
+ char res12[240];
+} ccsr_ddr_t;
+
+
+/* I2C Registers(0x3000-0x4000) */
+
+typedef struct ccsr_i2c {
+ u_char i2cadr; /* 0x3000 - I2C Address Register */
+#define MPC85xx_I2CADR_MASK 0xFE
+ char res1[3];
+ u_char i2cfdr; /* 0x3004 - I2C Frequency Divider Register */
+#define MPC85xx_I2CFDR_MASK 0x3F
+ char res2[3];
+ u_char i2ccr; /* 0x3008 - I2C Control Register */
+#define MPC85xx_I2CCR_MEN 0x80
+#define MPC85xx_I2CCR_MIEN 0x40
+#define MPC85xx_I2CCR_MSTA 0x20
+#define MPC85xx_I2CCR_MTX 0x10
+#define MPC85xx_I2CCR_TXAK 0x08
+#define MPC85xx_I2CCR_RSTA 0x04
+#define MPC85xx_I2CCR_BCST 0x01
+ char res3[3];
+ u_char i2csr; /* 0x300c - I2C Status Register */
+#define MPC85xx_I2CSR_MCF 0x80
+#define MPC85xx_I2CSR_MAAS 0x40
+#define MPC85xx_I2CSR_MBB 0x20
+#define MPC85xx_I2CSR_MAL 0x10
+#define MPC85xx_I2CSR_BCSTM 0x08
+#define MPC85xx_I2CSR_SRW 0x04
+#define MPC85xx_I2CSR_MIF 0x02
+#define MPC85xx_I2CSR_RXAK 0x01
+ char res4[3];
+ u_char i2cdr; /* 0x3010 - I2C Data Register */
+#define MPC85xx_I2CDR_DATA 0xFF
+ char res5[3];
+ u_char i2cdfsrr; /* 0x3014 - I2C Digital Filtering Sampling Rate Register */
+#define MPC85xx_I2CDFSRR 0x3F
+ char res6[4075];
+} ccsr_i2c_t;
+
+#ifdef CONFIG_MPC8540
+/* DUART Registers(0x4000-0x5000) */
+typedef struct ccsr_duart {
+ char res1[1280];
+ u_char urbr1_uthr1_udlb1;/* 0x4500 - URBR1, UTHR1, UDLB1 with the same address offset of 0x04500 */
+ u_char uier1_udmb1; /* 0x4501 - UIER1, UDMB1 with the same address offset of 0x04501 */
+ u_char uiir1_ufcr1_uafr1;/* 0x4502 - UIIR1, UFCR1, UAFR1 with the same address offset of 0x04502 */
+ u_char ulcr1; /* 0x4503 - UART1 Line Control Register */
+ u_char umcr1; /* 0x4504 - UART1 Modem Control Register */
+ u_char ulsr1; /* 0x4505 - UART1 Line Status Register */
+ u_char umsr1; /* 0x4506 - UART1 Modem Status Register */
+ u_char uscr1; /* 0x4507 - UART1 Scratch Register */
+ char res2[8];
+ u_char udsr1; /* 0x4510 - UART1 DMA Status Register */
+ char res3[239];
+ u_char urbr2_uthr2_udlb2;/* 0x4600 - URBR2, UTHR2, UDLB2 with the same address offset of 0x04600 */
+ u_char uier2_udmb2; /* 0x4601 - UIER2, UDMB2 with the same address offset of 0x04601 */
+ u_char uiir2_ufcr2_uafr2;/* 0x4602 - UIIR2, UFCR2, UAFR2 with the same address offset of 0x04602 */
+ u_char ulcr2; /* 0x4603 - UART2 Line Control Register */
+ u_char umcr2; /* 0x4604 - UART2 Modem Control Register */
+ u_char ulsr2; /* 0x4605 - UART2 Line Status Register */
+ u_char umsr2; /* 0x4606 - UART2 Modem Status Register */
+ u_char uscr2; /* 0x4607 - UART2 Scratch Register */
+ char res4[8];
+ u_char udsr2; /* 0x4610 - UART2 DMA Status Register */
+ char res5[2543];
+} ccsr_duart_t;
+#else /* MPC8560 uses UART on its CPM */
+typedef struct ccsr_duart {
+ char res[4096];
+} ccsr_duart_t;
+#endif
+
+/* Local Bus Controller Registers(0x5000-0x6000) */
+/* Omitting OCeaN(0x6000) and Reserved(0x7000) block */
+
+typedef struct ccsr_lbc {
+ uint br0; /* 0x5000 - LBC Base Register 0 */
+ uint or0; /* 0x5004 - LBC Options Register 0 */
+ uint br1; /* 0x5008 - LBC Base Register 1 */
+ uint or1; /* 0x500c - LBC Options Register 1 */
+ uint br2; /* 0x5010 - LBC Base Register 2 */
+ uint or2; /* 0x5014 - LBC Options Register 2 */
+ uint br3; /* 0x5018 - LBC Base Register 3 */
+ uint or3; /* 0x501c - LBC Options Register 3 */
+ uint br4; /* 0x5020 - LBC Base Register 4 */
+ uint or4; /* 0x5024 - LBC Options Register 4 */
+ uint br5; /* 0x5028 - LBC Base Register 5 */
+ uint or5; /* 0x502c - LBC Options Register 5 */
+ uint br6; /* 0x5030 - LBC Base Register 6 */
+ uint or6; /* 0x5034 - LBC Options Register 6 */
+ uint br7; /* 0x5038 - LBC Base Register 7 */
+ uint or7; /* 0x503c - LBC Options Register 7 */
+ char res1[40];
+ uint mar; /* 0x5068 - LBC UPM Address Register */
+ char res2[4];
+ uint mamr; /* 0x5070 - LBC UPMA Mode Register */
+ uint mbmr; /* 0x5074 - LBC UPMB Mode Register */
+ uint mcmr; /* 0x5078 - LBC UPMC Mode Register */
+ char res3[8];
+ uint mrtpr; /* 0x5084 - LBC Memory Refresh Timer Prescaler Register */
+ uint mdr; /* 0x5088 - LBC UPM Data Register */
+ char res4[8];
+ uint lsdmr; /* 0x5094 - LBC SDRAM Mode Register */
+ char res5[8];
+ uint lurt; /* 0x50a0 - LBC UPM Refresh Timer */
+ uint lsrt; /* 0x50a4 - LBC SDRAM Refresh Timer */
+ char res6[8];
+ uint ltesr; /* 0x50b0 - LBC Transfer Error Status Register */
+ uint ltedr; /* 0x50b4 - LBC Transfer Error Disable Register */
+ uint lteir; /* 0x50b8 - LBC Transfer Error Interrupt Register */
+ uint lteatr; /* 0x50bc - LBC Transfer Error Attributes Register */
+ uint ltear; /* 0x50c0 - LBC Transfer Error Address Register */
+ char res7[12];
+ uint lbcr; /* 0x50d0 - LBC Configuration Register */
+ uint lcrr; /* 0x50d4 - LBC Clock Ratio Register */
+ char res8[12072];
+} ccsr_lbc_t;
+
+
+/* PCI Registers(0x8000-0x9000) */
+/* Omitting Reserved(0x9000-0x2_0000) */
+
+typedef struct ccsr_pcix {
+ uint cfg_addr; /* 0x8000 - PCIX Configuration Address Register */
+ uint cfg_data; /* 0x8004 - PCIX Configuration Data Register */
+ uint int_ack; /* 0x8008 - PCIX Interrupt Acknowledge Register */
+ char res1[3060];
+ uint potar0; /* 0x8c00 - PCIX Outbound Transaction Address Register 0 */
+ uint potear0; /* 0x8c04 - PCIX Outbound Translation Extended Address Register 0 */
+ uint powbar0; /* 0x8c08 - PCIX Outbound Window Base Address Register 0 */
+ uint powbear0; /* 0x8c0c - PCIX Outbound Window Base Extended Address Register 0 */
+ uint powar0; /* 0x8c10 - PCIX Outbound Window Attributes Register 0 */
+ char res2[12];
+ uint potar1; /* 0x8c20 - PCIX Outbound Transaction Address Register 1 */
+ uint potear1; /* 0x8c24 - PCIX Outbound Translation Extended Address Register 1 */
+ uint powbar1; /* 0x8c28 - PCIX Outbound Window Base Address Register 1 */
+ uint powbear1; /* 0x8c2c - PCIX Outbound Window Base Extended Address Register 1 */
+ uint powar1; /* 0x8c30 - PCIX Outbound Window Attributes Register 1 */
+ char res3[12];
+ uint potar2; /* 0x8c40 - PCIX Outbound Transaction Address Register 2 */
+ uint potear2; /* 0x8c44 - PCIX Outbound Translation Extended Address Register 2 */
+ uint powbar2; /* 0x8c48 - PCIX Outbound Window Base Address Register 2 */
+ uint powbear2; /* 0x8c4c - PCIX Outbound Window Base Extended Address Register 2 */
+ uint powar2; /* 0x8c50 - PCIX Outbound Window Attributes Register 2 */
+ char res4[12];
+ uint potar3; /* 0x8c60 - PCIX Outbound Transaction Address Register 3 */
+ uint potear3; /* 0x8c64 - PCIX Outbound Translation Extended Address Register 3 */
+ uint powbar3; /* 0x8c68 - PCIX Outbound Window Base Address Register 3 */
+ uint powbear3; /* 0x8c6c - PCIX Outbound Window Base Extended Address Register 3 */
+ uint powar3; /* 0x8c70 - PCIX Outbound Window Attributes Register 3 */
+ char res5[12];
+ uint potar4; /* 0x8c80 - PCIX Outbound Transaction Address Register 4 */
+ uint potear4; /* 0x8c84 - PCIX Outbound Translation Extended Address Register 4 */
+ uint powbar4; /* 0x8c88 - PCIX Outbound Window Base Address Register 4 */
+ uint powbear4; /* 0x8c8c - PCIX Outbound Window Base Extended Address Register 4 */
+ uint powar4; /* 0x8c90 - PCIX Outbound Window Attributes Register 4 */
+ char res6[268];
+ uint pitar3; /* 0x8da0 - PCIX Inbound Translation Address Register 3 */
+ uint pitear3; /* 0x8da4 - PCIX Inbound Translation Extended Address Register 3 */
+ uint piwbar3; /* 0x8da8 - PCIX Inbound Window Base Address Register 3 */
+ uint piwbear3; /* 0x8dac - PCIX Inbound Window Base Extended Address Register 3 */
+ uint piwar3; /* 0x8db0 - PCIX Inbound Window Attributes Register 3 */
+ char res7[12];
+ uint pitar2; /* 0x8dc0 - PCIX Inbound Translation Address Register 2 */
+ uint pitear2; /* 0x8dc4 - PCIX Inbound Translation Extended Address Register 2 */
+ uint piwbar2; /* 0x8dc8 - PCIX Inbound Window Base Address Register 2 */
+ uint piwbear2; /* 0x8dcc - PCIX Inbound Window Base Extended Address Register 2 */
+ uint piwar2; /* 0x8dd0 - PCIX Inbound Window Attributes Register 2 */
+ char res8[12];
+ uint pitar1; /* 0x8de0 - PCIX Inbound Translation Address Register 1 */
+ uint pitear1; /* 0x8de4 - PCIX Inbound Translation Extended Address Register 1 */
+ uint piwbar1; /* 0x8de8 - PCIX Inbound Window Base Address Register 1 */
+ char res9[4];
+ uint piwar1; /* 0x8df0 - PCIX Inbound Window Attributes Register 1 */
+ char res10[12];
+ uint pedr; /* 0x8e00 - PCIX Error Detect Register */
+ uint pecdr; /* 0x8e04 - PCIX Error Capture Disable Register */
+ uint peer; /* 0x8e08 - PCIX Error Enable Register */
+ uint peattrcr; /* 0x8e0c - PCIX Error Attributes Capture Register */
+ uint peaddrcr; /* 0x8e10 - PCIX Error Address Capture Register */
+ uint peextaddrcr; /* 0x8e14 - PCIX Error Extended Address Capture Register */
+ uint pedlcr; /* 0x8e18 - PCIX Error Data Low Capture Register */
+ uint pedhcr; /* 0x8e1c - PCIX Error Error Data High Capture Register */
+ char res11[94688];
+} ccsr_pcix_t;
+
+
+/* L2 Cache Registers(0x2_0000-0x2_1000) */
+
+typedef struct ccsr_l2cache {
+ uint l2ctl; /* 0x20000 - L2 configuration register 0 */
+ char res1[12];
+ uint l2cewar0; /* 0x20010 - L2 cache external write address register 0 */
+ char res2[4];
+ uint l2cewcr0; /* 0x20018 - L2 cache external write control register 0 */
+ char res3[4];
+ uint l2cewar1; /* 0x20020 - L2 cache external write address register 1 */
+ char res4[4];
+ uint l2cewcr1; /* 0x20028 - L2 cache external write control register 1 */
+ char res5[4];
+ uint l2cewar2; /* 0x20030 - L2 cache external write address register 2 */
+ char res6[4];
+ uint l2cewcr2; /* 0x20038 - L2 cache external write control register 2 */
+ char res7[4];
+ uint l2cewar3; /* 0x20040 - L2 cache external write address register 3 */
+ char res8[4];
+ uint l2cewcr3; /* 0x20048 - L2 cache external write control register 3 */
+ char res9[180];
+ uint l2srbar0; /* 0x20100 - L2 memory-mapped SRAM base address register 0 */
+ char res10[4];
+ uint l2srbar1; /* 0x20108 - L2 memory-mapped SRAM base address register 1 */
+ char res11[3316];
+ uint l2errinjhi; /* 0x20e00 - L2 error injection mask high register */
+ uint l2errinjlo; /* 0x20e04 - L2 error injection mask low register */
+ uint l2errinjctl; /* 0x20e08 - L2 error injection tag/ECC control register */
+ char res12[20];
+ uint l2captdatahi; /* 0x20e20 - L2 error data high capture register */
+ uint l2captdatalo; /* 0x20e24 - L2 error data low capture register */
+ uint l2captecc; /* 0x20e28 - L2 error ECC capture register */
+ char res13[20];
+ uint l2errdet; /* 0x20e40 - L2 error detect register */
+ uint l2errdis; /* 0x20e44 - L2 error disable register */
+ uint l2errinten; /* 0x20e48 - L2 error interrupt enable register */
+ uint l2errattr; /* 0x20e4c - L2 error attributes capture register */
+ uint l2erraddr; /* 0x20e50 - L2 error address capture register */
+ char res14[4];
+ uint l2errctl; /* 0x20e58 - L2 error control register */
+ char res15[420];
+} ccsr_l2cache_t;
+
+
+/* DMA Registers(0x2_1000-0x2_2000) */
+
+typedef struct ccsr_dma {
+ char res1[256];
+ uint mr0; /* 0x21100 - DMA 0 Mode Register */
+ uint sr0; /* 0x21104 - DMA 0 Status Register */
+ char res2[4];
+ uint clndar0; /* 0x2110c - DMA 0 Current Link Descriptor Address Register */
+ uint satr0; /* 0x21110 - DMA 0 Source Attributes Register */
+ uint sar0; /* 0x21114 - DMA 0 Source Address Register */
+ uint datr0; /* 0x21118 - DMA 0 Destination Attributes Register */
+ uint dar0; /* 0x2111c - DMA 0 Destination Address Register */
+ uint bcr0; /* 0x21120 - DMA 0 Byte Count Register */
+ char res3[4];
+ uint nlndar0; /* 0x21128 - DMA 0 Next Link Descriptor Address Register */
+ char res4[8];
+ uint clabdar0; /* 0x21134 - DMA 0 Current List - Alternate Base Descriptor Address Register */
+ char res5[4];
+ uint nlsdar0; /* 0x2113c - DMA 0 Next List Descriptor Address Register */
+ uint ssr0; /* 0x21140 - DMA 0 Source Stride Register */
+ uint dsr0; /* 0x21144 - DMA 0 Destination Stride Register */
+ char res6[56];
+ uint mr1; /* 0x21180 - DMA 1 Mode Register */
+ uint sr1; /* 0x21184 - DMA 1 Status Register */
+ char res7[4];
+ uint clndar1; /* 0x2118c - DMA 1 Current Link Descriptor Address Register */
+ uint satr1; /* 0x21190 - DMA 1 Source Attributes Register */
+ uint sar1; /* 0x21194 - DMA 1 Source Address Register */
+ uint datr1; /* 0x21198 - DMA 1 Destination Attributes Register */
+ uint dar1; /* 0x2119c - DMA 1 Destination Address Register */
+ uint bcr1; /* 0x211a0 - DMA 1 Byte Count Register */
+ char res8[4];
+ uint nlndar1; /* 0x211a8 - DMA 1 Next Link Descriptor Address Register */
+ char res9[8];
+ uint clabdar1; /* 0x211b4 - DMA 1 Current List - Alternate Base Descriptor Address Register */
+ char res10[4];
+ uint nlsdar1; /* 0x211bc - DMA 1 Next List Descriptor Address Register */
+ uint ssr1; /* 0x211c0 - DMA 1 Source Stride Register */
+ uint dsr1; /* 0x211c4 - DMA 1 Destination Stride Register */
+ char res11[56];
+ uint mr2; /* 0x21200 - DMA 2 Mode Register */
+ uint sr2; /* 0x21204 - DMA 2 Status Register */
+ char res12[4];
+ uint clndar2; /* 0x2120c - DMA 2 Current Link Descriptor Address Register */
+ uint satr2; /* 0x21210 - DMA 2 Source Attributes Register */
+ uint sar2; /* 0x21214 - DMA 2 Source Address Register */
+ uint datr2; /* 0x21218 - DMA 2 Destination Attributes Register */
+ uint dar2; /* 0x2121c - DMA 2 Destination Address Register */
+ uint bcr2; /* 0x21220 - DMA 2 Byte Count Register */
+ char res13[4];
+ uint nlndar2; /* 0x21228 - DMA 2 Next Link Descriptor Address Register */
+ char res14[8];
+ uint clabdar2; /* 0x21234 - DMA 2 Current List - Alternate Base Descriptor Address Register */
+ char res15[4];
+ uint nlsdar2; /* 0x2123c - DMA 2 Next List Descriptor Address Register */
+ uint ssr2; /* 0x21240 - DMA 2 Source Stride Register */
+ uint dsr2; /* 0x21244 - DMA 2 Destination Stride Register */
+ char res16[56];
+ uint mr3; /* 0x21280 - DMA 3 Mode Register */
+ uint sr3; /* 0x21284 - DMA 3 Status Register */
+ char res17[4];
+ uint clndar3; /* 0x2128c - DMA 3 Current Link Descriptor Address Register */
+ uint satr3; /* 0x21290 - DMA 3 Source Attributes Register */
+ uint sar3; /* 0x21294 - DMA 3 Source Address Register */
+ uint datr3; /* 0x21298 - DMA 3 Destination Attributes Register */
+ uint dar3; /* 0x2129c - DMA 3 Destination Address Register */
+ uint bcr3; /* 0x212a0 - DMA 3 Byte Count Register */
+ char res18[4];
+ uint nlndar3; /* 0x212a8 - DMA 3 Next Link Descriptor Address Register */
+ char res19[8];
+ uint clabdar3; /* 0x212b4 - DMA 3 Current List - Alternate Base Descriptor Address Register */
+ char res20[4];
+ uint nlsdar3; /* 0x212bc - DMA 3 Next List Descriptor Address Register */
+ uint ssr3; /* 0x212c0 - DMA 3 Source Stride Register */
+ uint dsr3; /* 0x212c4 - DMA 3 Destination Stride Register */
+ char res21[56];
+ uint dgsr; /* 0x21300 - DMA General Status Register */
+ char res22[11516];
+} ccsr_dma_t;
+
+/* tsec1 tsec2: 24000-26000 */
+typedef struct ccsr_tsec {
+ char res1[16];
+ uint ievent; /* 0x24010 - Interrupt Event Register */
+ uint imask; /* 0x24014 - Interrupt Mask Register */
+ uint edis; /* 0x24018 - Error Disabled Register */
+ char res2[4];
+ uint ecntrl; /* 0x24020 - Ethernet Control Register */
+ uint minflr; /* 0x24024 - Minimum Frame Length Register */
+ uint ptv; /* 0x24028 - Pause Time Value Register */
+ uint dmactrl; /* 0x2402c - DMA Control Register */
+ uint tbipa; /* 0x24030 - TBI PHY Address Register */
+ char res3[88];
+ uint fifo_tx_thr; /* 0x2408c - FIFO transmit threshold register */
+ char res4[8];
+ uint fifo_tx_starve; /* 0x24098 - FIFO transmit starve register */
+ uint fifo_tx_starve_shutoff; /* 0x2409c - FIFO transmit starve shutoff register */
+ char res5[96];
+ uint tctrl; /* 0x24100 - Transmit Control Register */
+ uint tstat; /* 0x24104 - Transmit Status Register */
+ char res6[4];
+ uint tbdlen; /* 0x2410c - Transmit Buffer Descriptor Data Length Register */
+ char res7[16];
+ uint ctbptrh; /* 0x24120 - Current Transmit Buffer Descriptor Pointer High Register */
+ uint ctbptr; /* 0x24124 - Current Transmit Buffer Descriptor Pointer Register */
+ char res8[88];
+ uint tbptrh; /* 0x24180 - Transmit Buffer Descriptor Pointer High Register */
+ uint tbptr; /* 0x24184 - Transmit Buffer Descriptor Pointer Low Register */
+ char res9[120];
+ uint tbaseh; /* 0x24200 - Transmit Descriptor Base Address High Register */
+ uint tbase; /* 0x24204 - Transmit Descriptor Base Address Register */
+ char res10[168];
+ uint ostbd; /* 0x242b0 - Out-of-Sequence Transmit Buffer Descriptor Register */
+ uint ostbdp; /* 0x242b4 - Out-of-Sequence Transmit Data Buffer Pointer Register */
+ uint os32tbdp; /* 0x242b8 - Out-of-Sequence 32 Bytes Transmit Data Buffer Pointer Low Register */
+ uint os32iptrh; /* 0x242bc - Out-of-Sequence 32 Bytes Transmit Insert Pointer High Register */
+ uint os32iptrl; /* 0x242c0 - Out-of-Sequence 32 Bytes Transmit Insert Pointer Low Register */
+ uint os32tbdr; /* 0x242c4 - Out-of-Sequence 32 Bytes Transmit Reserved Register */
+ uint os32iil; /* 0x242c8 - Out-of-Sequence 32 Bytes Transmit Insert Index/Length Register */
+ char res11[52];
+ uint rctrl; /* 0x24300 - Receive Control Register */
+ uint rstat; /* 0x24304 - Receive Status Register */
+ char res12[4];
+ uint rbdlen; /* 0x2430c - RxBD Data Length Register */
+ char res13[16];
+ uint crbptrh; /* 0x24320 - Current Receive Buffer Descriptor Pointer High */
+ uint crbptr; /* 0x24324 - Current Receive Buffer Descriptor Pointer */
+ char res14[24];
+ uint mrblr; /* 0x24340 - Maximum Receive Buffer Length Register */
+ uint mrblr2r3; /* 0x24344 - Maximum Receive Buffer Length R2R3 Register */
+ char res15[56];
+ uint rbptrh; /* 0x24380 - Receive Buffer Descriptor Pointer High 0 */
+ uint rbptr; /* 0x24384 - Receive Buffer Descriptor Pointer */
+ uint rbptrh1; /* 0x24388 - Receive Buffer Descriptor Pointer High 1 */
+ uint rbptrl1; /* 0x2438c - Receive Buffer Descriptor Pointer Low 1 */
+ uint rbptrh2; /* 0x24390 - Receive Buffer Descriptor Pointer High 2 */
+ uint rbptrl2; /* 0x24394 - Receive Buffer Descriptor Pointer Low 2 */
+ uint rbptrh3; /* 0x24398 - Receive Buffer Descriptor Pointer High 3 */
+ uint rbptrl3; /* 0x2439c - Receive Buffer Descriptor Pointer Low 3 */
+ char res16[96];
+ uint rbaseh; /* 0x24400 - Receive Descriptor Base Address High 0 */
+ uint rbase; /* 0x24404 - Receive Descriptor Base Address */
+ uint rbaseh1; /* 0x24408 - Receive Descriptor Base Address High 1 */
+ uint rbasel1; /* 0x2440c - Receive Descriptor Base Address Low 1 */
+ uint rbaseh2; /* 0x24410 - Receive Descriptor Base Address High 2 */
+ uint rbasel2; /* 0x24414 - Receive Descriptor Base Address Low 2 */
+ uint rbaseh3; /* 0x24418 - Receive Descriptor Base Address High 3 */
+ uint rbasel3; /* 0x2441c - Receive Descriptor Base Address Low 3 */
+ char res17[224];
+ uint maccfg1; /* 0x24500 - MAC Configuration 1 Register */
+ uint maccfg2; /* 0x24504 - MAC Configuration 2 Register */
+ uint ipgifg; /* 0x24508 - Inter Packet Gap/Inter Frame Gap Register */
+ uint hafdup; /* 0x2450c - Half Duplex Register */
+ uint maxfrm; /* 0x24510 - Maximum Frame Length Register */
+ char res18[12];
+ uint miimcfg; /* 0x24520 - MII Management Configuration Register */
+ uint miimcom; /* 0x24524 - MII Management Command Register */
+ uint miimadd; /* 0x24528 - MII Management Address Register */
+ uint miimcon; /* 0x2452c - MII Management Control Register */
+ uint miimstat; /* 0x24530 - MII Management Status Register */
+ uint miimind; /* 0x24534 - MII Management Indicator Register */
+ char res19[4];
+ uint ifstat; /* 0x2453c - Interface Status Register */
+ uint macstnaddr1; /* 0x24540 - Station Address Part 1 Register */
+ uint macstnaddr2; /* 0x24544 - Station Address Part 2 Register */
+ char res20[312];
+ uint tr64; /* 0x24680 - Transmit and Receive 64-byte Frame Counter */
+ uint tr127; /* 0x24684 - Transmit and Receive 65-127 byte Frame Counter */
+ uint tr255; /* 0x24688 - Transmit and Receive 128-255 byte Frame Counter */
+ uint tr511; /* 0x2468c - Transmit and Receive 256-511 byte Frame Counter */
+ uint tr1k; /* 0x24690 - Transmit and Receive 512-1023 byte Frame Counter */
+ uint trmax; /* 0x24694 - Transmit and Receive 1024-1518 byte Frame Counter */
+ uint trmgv; /* 0x24698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
+ uint rbyt; /* 0x2469c - Receive Byte Counter */
+ uint rpkt; /* 0x246a0 - Receive Packet Counter */
+ uint rfcs; /* 0x246a4 - Receive FCS Error Counter */
+ uint rmca; /* 0x246a8 - Receive Multicast Packet Counter */
+ uint rbca; /* 0x246ac - Receive Broadcast Packet Counter */
+ uint rxcf; /* 0x246b0 - Receive Control Frame Packet Counter */
+ uint rxpf; /* 0x246b4 - Receive Pause Frame Packet Counter */
+ uint rxuo; /* 0x246b8 - Receive Unknown OP Code Counter */
+ uint raln; /* 0x246bc - Receive Alignment Error Counter */
+ uint rflr; /* 0x246c0 - Receive Frame Length Error Counter */
+ uint rcde; /* 0x246c4 - Receive Code Error Counter */
+ uint rcse; /* 0x246c8 - Receive Carrier Sense Error Counter */
+ uint rund; /* 0x246cc - Receive Undersize Packet Counter */
+ uint rovr; /* 0x246d0 - Receive Oversize Packet Counter */
+ uint rfrg; /* 0x246d4 - Receive Fragments Counter */
+ uint rjbr; /* 0x246d8 - Receive Jabber Counter */
+ uint rdrp; /* 0x246dc - Receive Drop Counter */
+ uint tbyt; /* 0x246e0 - Transmit Byte Counter Counter */
+ uint tpkt; /* 0x246e4 - Transmit Packet Counter */
+ uint tmca; /* 0x246e8 - Transmit Multicast Packet Counter */
+ uint tbca; /* 0x246ec - Transmit Broadcast Packet Counter */
+ uint txpf; /* 0x246f0 - Transmit Pause Control Frame Counter */
+ uint tdfr; /* 0x246f4 - Transmit Deferral Packet Counter */
+ uint tedf; /* 0x246f8 - Transmit Excessive Deferral Packet Counter */
+ uint tscl; /* 0x246fc - Transmit Single Collision Packet Counter */
+ uint tmcl; /* 0x24700 - Transmit Multiple Collision Packet Counter */
+ uint tlcl; /* 0x24704 - Transmit Late Collision Packet Counter */
+ uint txcl; /* 0x24708 - Transmit Excessive Collision Packet Counter */
+ uint tncl; /* 0x2470c - Transmit Total Collision Counter */
+ char res21[4];
+ uint tdrp; /* 0x24714 - Transmit Drop Frame Counter */
+ uint tjbr; /* 0x24718 - Transmit Jabber Frame Counter */
+ uint tfcs; /* 0x2471c - Transmit FCS Error Counter */
+ uint txcf; /* 0x24720 - Transmit Control Frame Counter */
+ uint tovr; /* 0x24724 - Transmit Oversize Frame Counter */
+ uint tund; /* 0x24728 - Transmit Undersize Frame Counter */
+ uint tfrg; /* 0x2472c - Transmit Fragments Frame Counter */
+ uint car1; /* 0x24730 - Carry Register One */
+ uint car2; /* 0x24734 - Carry Register Two */
+ uint cam1; /* 0x24738 - Carry Mask Register One */
+ uint cam2; /* 0x2473c - Carry Mask Register Two */
+ char res22[192];
+ uint iaddr0; /* 0x24800 - Indivdual address register 0 */
+ uint iaddr1; /* 0x24804 - Indivdual address register 1 */
+ uint iaddr2; /* 0x24808 - Indivdual address register 2 */
+ uint iaddr3; /* 0x2480c - Indivdual address register 3 */
+ uint iaddr4; /* 0x24810 - Indivdual address register 4 */
+ uint iaddr5; /* 0x24814 - Indivdual address register 5 */
+ uint iaddr6; /* 0x24818 - Indivdual address register 6 */
+ uint iaddr7; /* 0x2481c - Indivdual address register 7 */
+ char res23[96];
+ uint gaddr0; /* 0x24880 - Global address register 0 */
+ uint gaddr1; /* 0x24884 - Global address register 1 */
+ uint gaddr2; /* 0x24888 - Global address register 2 */
+ uint gaddr3; /* 0x2488c - Global address register 3 */
+ uint gaddr4; /* 0x24890 - Global address register 4 */
+ uint gaddr5; /* 0x24894 - Global address register 5 */
+ uint gaddr6; /* 0x24898 - Global address register 6 */
+ uint gaddr7; /* 0x2489c - Global address register 7 */
+ char res24[96];
+ uint pmd0; /* 0x24900 - Pattern Match Data Register */
+ char res25[4];
+ uint pmask0; /* 0x24908 - Pattern Mask Register */
+ char res26[4];
+ uint pcntrl0; /* 0x24910 - Pattern Match Control Register */
+ char res27[4];
+ uint pattrb0; /* 0x24918 - Pattern Match Attributes Register */
+ uint pattrbeli0; /* 0x2491c - Pattern Match Attributes Extract Length and Extract Index Register */
+ uint pmd1; /* 0x24920 - Pattern Match Data Register */
+ char res28[4];
+ uint pmask1; /* 0x24928 - Pattern Mask Register */
+ char res29[4];
+ uint pcntrl1; /* 0x24930 - Pattern Match Control Register */
+ char res30[4];
+ uint pattrb1; /* 0x24938 - Pattern Match Attributes Register */
+ uint pattrbeli1; /* 0x2493c - Pattern Match Attributes Extract Length and Extract Index Register */
+ uint pmd2; /* 0x24940 - Pattern Match Data Register */
+ char res31[4];
+ uint pmask2; /* 0x24948 - Pattern Mask Register */
+ char res32[4];
+ uint pcntrl2; /* 0x24950 - Pattern Match Control Register */
+ char res33[4];
+ uint pattrb2; /* 0x24958 - Pattern Match Attributes Register */
+ uint pattrbeli2; /* 0x2495c - Pattern Match Attributes Extract Length and Extract Index Register */
+ uint pmd3; /* 0x24960 - Pattern Match Data Register */
+ char res34[4];
+ uint pmask3; /* 0x24968 - Pattern Mask Register */
+ char res35[4];
+ uint pcntrl3; /* 0x24970 - Pattern Match Control Register */
+ char res36[4];
+ uint pattrb3; /* 0x24978 - Pattern Match Attributes Register */
+ uint pattrbeli3; /* 0x2497c - Pattern Match Attributes Extract Length and Extract Index Register */
+ uint pmd4; /* 0x24980 - Pattern Match Data Register */
+ char res37[4];
+ uint pmask4; /* 0x24988 - Pattern Mask Register */
+ char res38[4];
+ uint pcntrl4; /* 0x24990 - Pattern Match Control Register */
+ char res39[4];
+ uint pattrb4; /* 0x24998 - Pattern Match Attributes Register */
+ uint pattrbeli4; /* 0x2499c - Pattern Match Attributes Extract Length and Extract Index Register */
+ uint pmd5; /* 0x249a0 - Pattern Match Data Register */
+ char res40[4];
+ uint pmask5; /* 0x249a8 - Pattern Mask Register */
+ char res41[4];
+ uint pcntrl5; /* 0x249b0 - Pattern Match Control Register */
+ char res42[4];
+ uint pattrb5; /* 0x249b8 - Pattern Match Attributes Register */
+ uint pattrbeli5; /* 0x249bc - Pattern Match Attributes Extract Length and Extract Index Register */
+ uint pmd6; /* 0x249c0 - Pattern Match Data Register */
+ char res43[4];
+ uint pmask6; /* 0x249c8 - Pattern Mask Register */
+ char res44[4];
+ uint pcntrl6; /* 0x249d0 - Pattern Match Control Register */
+ char res45[4];
+ uint pattrb6; /* 0x249d8 - Pattern Match Attributes Register */
+ uint pattrbeli6; /* 0x249dc - Pattern Match Attributes Extract Length and Extract Index Register */
+ uint pmd7; /* 0x249e0 - Pattern Match Data Register */
+ char res46[4];
+ uint pmask7; /* 0x249e8 - Pattern Mask Register */
+ char res47[4];
+ uint pcntrl7; /* 0x249f0 - Pattern Match Control Register */
+ char res48[4];
+ uint pattrb7; /* 0x249f8 - Pattern Match Attributes Register */
+ uint pattrbeli7; /* 0x249fc - Pattern Match Attributes Extract Length and Extract Index Register */
+ uint pmd8; /* 0x24a00 - Pattern Match Data Register */
+ char res49[4];
+ uint pmask8; /* 0x24a08 - Pattern Mask Register */
+ char res50[4];
+ uint pcntrl8; /* 0x24a10 - Pattern Match Control Register */
+ char res51[4];
+ uint pattrb8; /* 0x24a18 - Pattern Match Attributes Register */
+ uint pattrbeli8; /* 0x24a1c - Pattern Match Attributes Extract Length and Extract Index Register */
+ uint pmd9; /* 0x24a20 - Pattern Match Data Register */
+ char res52[4];
+ uint pmask9; /* 0x24a28 - Pattern Mask Register */
+ char res53[4];
+ uint pcntrl9; /* 0x24a30 - Pattern Match Control Register */
+ char res54[4];
+ uint pattrb9; /* 0x24a38 - Pattern Match Attributes Register */
+ uint pattrbeli9; /* 0x24a3c - Pattern Match Attributes Extract Length and Extract Index Register */
+ uint pmd10; /* 0x24a40 - Pattern Match Data Register */
+ char res55[4];
+ uint pmask10; /* 0x24a48 - Pattern Mask Register */
+ char res56[4];
+ uint pcntrl10; /* 0x24a50 - Pattern Match Control Register */
+ char res57[4];
+ uint pattrb10; /* 0x24a58 - Pattern Match Attributes Register */
+ uint pattrbeli10; /* 0x24a5c - Pattern Match Attributes Extract Length and Extract Index Register */
+ uint pmd11; /* 0x24a60 - Pattern Match Data Register */
+ char res58[4];
+ uint pmask11; /* 0x24a68 - Pattern Mask Register */
+ char res59[4];
+ uint pcntrl11; /* 0x24a70 - Pattern Match Control Register */
+ char res60[4];
+ uint pattrb11; /* 0x24a78 - Pattern Match Attributes Register */
+ uint pattrbeli11; /* 0x24a7c - Pattern Match Attributes Extract Length and Extract Index Register */
+ uint pmd12; /* 0x24a80 - Pattern Match Data Register */
+ char res61[4];
+ uint pmask12; /* 0x24a88 - Pattern Mask Register */
+ char res62[4];
+ uint pcntrl12; /* 0x24a90 - Pattern Match Control Register */
+ char res63[4];
+ uint pattrb12; /* 0x24a98 - Pattern Match Attributes Register */
+ uint pattrbeli12; /* 0x24a9c - Pattern Match Attributes Extract Length and Extract Index Register */
+ uint pmd13; /* 0x24aa0 - Pattern Match Data Register */
+ char res64[4];
+ uint pmask13; /* 0x24aa8 - Pattern Mask Register */
+ char res65[4];
+ uint pcntrl13; /* 0x24ab0 - Pattern Match Control Register */
+ char res66[4];
+ uint pattrb13; /* 0x24ab8 - Pattern Match Attributes Register */
+ uint pattrbeli13; /* 0x24abc - Pattern Match Attributes Extract Length and Extract Index Register */
+ uint pmd14; /* 0x24ac0 - Pattern Match Data Register */
+ char res67[4];
+ uint pmask14; /* 0x24ac8 - Pattern Mask Register */
+ char res68[4];
+ uint pcntrl14; /* 0x24ad0 - Pattern Match Control Register */
+ char res69[4];
+ uint pattrb14; /* 0x24ad8 - Pattern Match Attributes Register */
+ uint pattrbeli14; /* 0x24adc - Pattern Match Attributes Extract Length and Extract Index Register */
+ uint pmd15; /* 0x24ae0 - Pattern Match Data Register */
+ char res70[4];
+ uint pmask15; /* 0x24ae8 - Pattern Mask Register */
+ char res71[4];
+ uint pcntrl15; /* 0x24af0 - Pattern Match Control Register */
+ char res72[4];
+ uint pattrb15; /* 0x24af8 - Pattern Match Attributes Register */
+ uint pattrbeli15; /* 0x24afc - Pattern Match Attributes Extract Length and Extract Index Register */
+ char res73[248];
+ uint attr; /* 0x24bf8 - Attributes Register */
+ uint attreli; /* 0x24bfc - Attributes Extract Length and Extract Index Register */
+ char res74[1024];
+} ccsr_tsec_t;
+
+/* PIC Registers(0x2_6000-0x4_0000-0x8_0000) */
+
+typedef struct ccsr_pic {
+ char res0[106496]; /* 0x26000-0x40000 */
+ char res1[64];
+ uint ipidr0; /* 0x40040 - Interprocessor Interrupt Dispatch Register 0 */
+ char res2[12];
+ uint ipidr1; /* 0x40050 - Interprocessor Interrupt Dispatch Register 1 */
+ char res3[12];
+ uint ipidr2; /* 0x40060 - Interprocessor Interrupt Dispatch Register 2 */
+ char res4[12];
+ uint ipidr3; /* 0x40070 - Interprocessor Interrupt Dispatch Register 3 */
+ char res5[12];
+ uint ctpr; /* 0x40080 - Current Task Priority Register */
+ char res6[12];
+ uint whoami; /* 0x40090 - Who Am I Register */
+ char res7[12];
+ uint iack; /* 0x400a0 - Interrupt Acknowledge Register */
+ char res8[12];
+ uint eoi; /* 0x400b0 - End Of Interrupt Register */
+ char res9[3916];
+ uint frr; /* 0x41000 - Feature Reporting Register */
+ char res10[28];
+ uint gcr; /* 0x41020 - Global Configuration Register */
+ char res11[92];
+ uint vir; /* 0x41080 - Vendor Identification Register */
+ char res12[12];
+ uint pir; /* 0x41090 - Processor Initialization Register */
+ char res13[12];
+ uint ipivpr0; /* 0x410a0 - IPI Vector/Priority Register 0 */
+ char res14[12];
+ uint ipivpr1; /* 0x410b0 - IPI Vector/Priority Register 1 */
+ char res15[12];
+ uint ipivpr2; /* 0x410c0 - IPI Vector/Priority Register 2 */
+ char res16[12];
+ uint ipivpr3; /* 0x410d0 - IPI Vector/Priority Register 3 */
+ char res17[12];
+ uint svr; /* 0x410e0 - Spurious Vector Register */
+ char res18[12];
+ uint tfrr; /* 0x410f0 - Timer Frequency Reporting Register */
+ char res19[12];
+ uint gtccr0; /* 0x41100 - Global Timer Current Count Register 0 */
+ char res20[12];
+ uint gtbcr0; /* 0x41110 - Global Timer Base Count Register 0 */
+ char res21[12];
+ uint gtvpr0; /* 0x41120 - Global Timer Vector/Priority Register 0 */
+ char res22[12];
+ uint gtdr0; /* 0x41130 - Global Timer Destination Register 0 */
+ char res23[12];
+ uint gtccr1; /* 0x41140 - Global Timer Current Count Register 1 */
+ char res24[12];
+ uint gtbcr1; /* 0x41150 - Global Timer Base Count Register 1 */
+ char res25[12];
+ uint gtvpr1; /* 0x41160 - Global Timer Vector/Priority Register 1 */
+ char res26[12];
+ uint gtdr1; /* 0x41170 - Global Timer Destination Register 1 */
+ char res27[12];
+ uint gtccr2; /* 0x41180 - Global Timer Current Count Register 2 */
+ char res28[12];
+ uint gtbcr2; /* 0x41190 - Global Timer Base Count Register 2 */
+ char res29[12];
+ uint gtvpr2; /* 0x411a0 - Global Timer Vector/Priority Register 2 */
+ char res30[12];
+ uint gtdr2; /* 0x411b0 - Global Timer Destination Register 2 */
+ char res31[12];
+ uint gtccr3; /* 0x411c0 - Global Timer Current Count Register 3 */
+ char res32[12];
+ uint gtbcr3; /* 0x411d0 - Global Timer Base Count Register 3 */
+ char res33[12];
+ uint gtvpr3; /* 0x411e0 - Global Timer Vector/Priority Register 3 */
+ char res34[12];
+ uint gtdr3; /* 0x411f0 - Global Timer Destination Register 3 */
+ char res35[268];
+ uint tcr; /* 0x41300 - Timer Control Register */
+ char res36[12];
+ uint irqsr0; /* 0x41310 - IRQ_OUT Summary Register 0 */
+ char res37[12];
+ uint irqsr1; /* 0x41320 - IRQ_OUT Summary Register 1 */
+ char res38[12];
+ uint cisr0; /* 0x41330 - Critical Interrupt Summary Register 0 */
+ char res39[12];
+ uint cisr1; /* 0x41340 - Critical Interrupt Summary Register 1 */
+ char res40[188];
+ uint msgr0; /* 0x41400 - Message Register 0 */
+ char res41[12];
+ uint msgr1; /* 0x41410 - Message Register 1 */
+ char res42[12];
+ uint msgr2; /* 0x41420 - Message Register 2 */
+ char res43[12];
+ uint msgr3; /* 0x41430 - Message Register 3 */
+ char res44[204];
+ uint mer; /* 0x41500 - Message Enable Register */
+ char res45[12];
+ uint msr; /* 0x41510 - Message Status Register */
+ char res46[60140];
+ uint eivpr0; /* 0x50000 - External Interrupt Vector/Priority Register 0 */
+ char res47[12];
+ uint eidr0; /* 0x50010 - External Interrupt Destination Register 0 */
+ char res48[12];
+ uint eivpr1; /* 0x50020 - External Interrupt Vector/Priority Register 1 */
+ char res49[12];
+ uint eidr1; /* 0x50030 - External Interrupt Destination Register 1 */
+ char res50[12];
+ uint eivpr2; /* 0x50040 - External Interrupt Vector/Priority Register 2 */
+ char res51[12];
+ uint eidr2; /* 0x50050 - External Interrupt Destination Register 2 */
+ char res52[12];
+ uint eivpr3; /* 0x50060 - External Interrupt Vector/Priority Register 3 */
+ char res53[12];
+ uint eidr3; /* 0x50070 - External Interrupt Destination Register 3 */
+ char res54[12];
+ uint eivpr4; /* 0x50080 - External Interrupt Vector/Priority Register 4 */
+ char res55[12];
+ uint eidr4; /* 0x50090 - External Interrupt Destination Register 4 */
+ char res56[12];
+ uint eivpr5; /* 0x500a0 - External Interrupt Vector/Priority Register 5 */
+ char res57[12];
+ uint eidr5; /* 0x500b0 - External Interrupt Destination Register 5 */
+ char res58[12];
+ uint eivpr6; /* 0x500c0 - External Interrupt Vector/Priority Register 6 */
+ char res59[12];
+ uint eidr6; /* 0x500d0 - External Interrupt Destination Register 6 */
+ char res60[12];
+ uint eivpr7; /* 0x500e0 - External Interrupt Vector/Priority Register 7 */
+ char res61[12];
+ uint eidr7; /* 0x500f0 - External Interrupt Destination Register 7 */
+ char res62[12];
+ uint eivpr8; /* 0x50100 - External Interrupt Vector/Priority Register 8 */
+ char res63[12];
+ uint eidr8; /* 0x50110 - External Interrupt Destination Register 8 */
+ char res64[12];
+ uint eivpr9; /* 0x50120 - External Interrupt Vector/Priority Register 9 */
+ char res65[12];
+ uint eidr9; /* 0x50130 - External Interrupt Destination Register 9 */
+ char res66[12];
+ uint eivpr10; /* 0x50140 - External Interrupt Vector/Priority Register 10 */
+ char res67[12];
+ uint eidr10; /* 0x50150 - External Interrupt Destination Register 10 */
+ char res68[12];
+ uint eivpr11; /* 0x50160 - External Interrupt Vector/Priority Register 11 */
+ char res69[12];
+ uint eidr11; /* 0x50170 - External Interrupt Destination Register 11 */
+ char res70[140];
+ uint iivpr0; /* 0x50200 - Internal Interrupt Vector/Priority Register 0 */
+ char res71[12];
+ uint iidr0; /* 0x50210 - Internal Interrupt Destination Register 0 */
+ char res72[12];
+ uint iivpr1; /* 0x50220 - Internal Interrupt Vector/Priority Register 1 */
+ char res73[12];
+ uint iidr1; /* 0x50230 - Internal Interrupt Destination Register 1 */
+ char res74[12];
+ uint iivpr2; /* 0x50240 - Internal Interrupt Vector/Priority Register 2 */
+ char res75[12];
+ uint iidr2; /* 0x50250 - Internal Interrupt Destination Register 2 */
+ char res76[12];
+ uint iivpr3; /* 0x50260 - Internal Interrupt Vector/Priority Register 3 */
+ char res77[12];
+ uint iidr3; /* 0x50270 - Internal Interrupt Destination Register 3 */
+ char res78[12];
+ uint iivpr4; /* 0x50280 - Internal Interrupt Vector/Priority Register 4 */
+ char res79[12];
+ uint iidr4; /* 0x50290 - Internal Interrupt Destination Register 4 */
+ char res80[12];
+ uint iivpr5; /* 0x502a0 - Internal Interrupt Vector/Priority Register 5 */
+ char res81[12];
+ uint iidr5; /* 0x502b0 - Internal Interrupt Destination Register 5 */
+ char res82[12];
+ uint iivpr6; /* 0x502c0 - Internal Interrupt Vector/Priority Register 6 */
+ char res83[12];
+ uint iidr6; /* 0x502d0 - Internal Interrupt Destination Register 6 */
+ char res84[12];
+ uint iivpr7; /* 0x502e0 - Internal Interrupt Vector/Priority Register 7 */
+ char res85[12];
+ uint iidr7; /* 0x502f0 - Internal Interrupt Destination Register 7 */
+ char res86[12];
+ uint iivpr8; /* 0x50300 - Internal Interrupt Vector/Priority Register 8 */
+ char res87[12];
+ uint iidr8; /* 0x50310 - Internal Interrupt Destination Register 8 */
+ char res88[12];
+ uint iivpr9; /* 0x50320 - Internal Interrupt Vector/Priority Register 9 */
+ char res89[12];
+ uint iidr9; /* 0x50330 - Internal Interrupt Destination Register 9 */
+ char res90[12];
+ uint iivpr10; /* 0x50340 - Internal Interrupt Vector/Priority Register 10 */
+ char res91[12];
+ uint iidr10; /* 0x50350 - Internal Interrupt Destination Register 10 */
+ char res92[12];
+ uint iivpr11; /* 0x50360 - Internal Interrupt Vector/Priority Register 11 */
+ char res93[12];
+ uint iidr11; /* 0x50370 - Internal Interrupt Destination Register 11 */
+ char res94[12];
+ uint iivpr12; /* 0x50380 - Internal Interrupt Vector/Priority Register 12 */
+ char res95[12];
+ uint iidr12; /* 0x50390 - Internal Interrupt Destination Register 12 */
+ char res96[12];
+ uint iivpr13; /* 0x503a0 - Internal Interrupt Vector/Priority Register 13 */
+ char res97[12];
+ uint iidr13; /* 0x503b0 - Internal Interrupt Destination Register 13 */
+ char res98[12];
+ uint iivpr14; /* 0x503c0 - Internal Interrupt Vector/Priority Register 14 */
+ char res99[12];
+ uint iidr14; /* 0x503d0 - Internal Interrupt Destination Register 14 */
+ char res100[12];
+ uint iivpr15; /* 0x503e0 - Internal Interrupt Vector/Priority Register 15 */
+ char res101[12];
+ uint iidr15; /* 0x503f0 - Internal Interrupt Destination Register 15 */
+ char res102[12];
+ uint iivpr16; /* 0x50400 - Internal Interrupt Vector/Priority Register 16 */
+ char res103[12];
+ uint iidr16; /* 0x50410 - Internal Interrupt Destination Register 16 */
+ char res104[12];
+ uint iivpr17; /* 0x50420 - Internal Interrupt Vector/Priority Register 17 */
+ char res105[12];
+ uint iidr17; /* 0x50430 - Internal Interrupt Destination Register 17 */
+ char res106[12];
+ uint iivpr18; /* 0x50440 - Internal Interrupt Vector/Priority Register 18 */
+ char res107[12];
+ uint iidr18; /* 0x50450 - Internal Interrupt Destination Register 18 */
+ char res108[12];
+ uint iivpr19; /* 0x50460 - Internal Interrupt Vector/Priority Register 19 */
+ char res109[12];
+ uint iidr19; /* 0x50470 - Internal Interrupt Destination Register 19 */
+ char res110[12];
+ uint iivpr20; /* 0x50480 - Internal Interrupt Vector/Priority Register 20 */
+ char res111[12];
+ uint iidr20; /* 0x50490 - Internal Interrupt Destination Register 20 */
+ char res112[12];
+ uint iivpr21; /* 0x504a0 - Internal Interrupt Vector/Priority Register 21 */
+ char res113[12];
+ uint iidr21; /* 0x504b0 - Internal Interrupt Destination Register 21 */
+ char res114[12];
+ uint iivpr22; /* 0x504c0 - Internal Interrupt Vector/Priority Register 22 */
+ char res115[12];
+ uint iidr22; /* 0x504d0 - Internal Interrupt Destination Register 22 */
+ char res116[12];
+ uint iivpr23; /* 0x504e0 - Internal Interrupt Vector/Priority Register 23 */
+ char res117[12];
+ uint iidr23; /* 0x504f0 - Internal Interrupt Destination Register 23 */
+ char res118[12];
+ uint iivpr24; /* 0x50500 - Internal Interrupt Vector/Priority Register 24 */
+ char res119[12];
+ uint iidr24; /* 0x50510 - Internal Interrupt Destination Register 24 */
+ char res120[12];
+ uint iivpr25; /* 0x50520 - Internal Interrupt Vector/Priority Register 25 */
+ char res121[12];
+ uint iidr25; /* 0x50530 - Internal Interrupt Destination Register 25 */
+ char res122[12];
+ uint iivpr26; /* 0x50540 - Internal Interrupt Vector/Priority Register 26 */
+ char res123[12];
+ uint iidr26; /* 0x50550 - Internal Interrupt Destination Register 26 */
+ char res124[12];
+ uint iivpr27; /* 0x50560 - Internal Interrupt Vector/Priority Register 27 */
+ char res125[12];
+ uint iidr27; /* 0x50570 - Internal Interrupt Destination Register 27 */
+ char res126[12];
+ uint iivpr28; /* 0x50580 - Internal Interrupt Vector/Priority Register 28 */
+ char res127[12];
+ uint iidr28; /* 0x50590 - Internal Interrupt Destination Register 28 */
+ char res128[12];
+ uint iivpr29; /* 0x505a0 - Internal Interrupt Vector/Priority Register 29 */
+ char res129[12];
+ uint iidr29; /* 0x505b0 - Internal Interrupt Destination Register 29 */
+ char res130[12];
+ uint iivpr30; /* 0x505c0 - Internal Interrupt Vector/Priority Register 30 */
+ char res131[12];
+ uint iidr30; /* 0x505d0 - Internal Interrupt Destination Register 30 */
+ char res132[12];
+ uint iivpr31; /* 0x505e0 - Internal Interrupt Vector/Priority Register 31 */
+ char res133[12];
+ uint iidr31; /* 0x505f0 - Internal Interrupt Destination Register 31 */
+ char res134[4108];
+ uint mivpr0; /* 0x51600 - Messaging Interrupt Vector/Priority Register 0 */
+ char res135[12];
+ uint midr0; /* 0x51610 - Messaging Interrupt Destination Register 0 */
+ char res136[12];
+ uint mivpr1; /* 0x51620 - Messaging Interrupt Vector/Priority Register 1 */
+ char res137[12];
+ uint midr1; /* 0x51630 - Messaging Interrupt Destination Register 1 */
+ char res138[12];
+ uint mivpr2; /* 0x51640 - Messaging Interrupt Vector/Priority Register 2 */
+ char res139[12];
+ uint midr2; /* 0x51650 - Messaging Interrupt Destination Register 2 */
+ char res140[12];
+ uint mivpr3; /* 0x51660 - Messaging Interrupt Vector/Priority Register 3 */
+ char res141[12];
+ uint midr3; /* 0x51670 - Messaging Interrupt Destination Register 3 */
+ char res142[59852];
+ uint ipi0dr0; /* 0x60040 - Processor 0 Interprocessor Interrupt Dispatch Register 0 */
+ char res143[12];
+ uint ipi0dr1; /* 0x60050 - Processor 0 Interprocessor Interrupt Dispatch Register 1 */
+ char res144[12];
+ uint ipi0dr2; /* 0x60060 - Processor 0 Interprocessor Interrupt Dispatch Register 2 */
+ char res145[12];
+ uint ipi0dr3; /* 0x60070 - Processor 0 Interprocessor Interrupt Dispatch Register 3 */
+ char res146[12];
+ uint ctpr0; /* 0x60080 - Current Task Priority Register for Processor 0 */
+ char res147[12];
+ uint whoami0; /* 0x60090 - Who Am I Register for Processor 0 */
+ char res148[12];
+ uint iack0; /* 0x600a0 - Interrupt Acknowledge Register for Processor 0 */
+ char res149[12];
+ uint eoi0; /* 0x600b0 - End Of Interrupt Register for Processor 0 */
+ char res150[130892];
+} ccsr_pic_t;
+
+/* CPM Block(0x8_0000-0xc_0000) */
+#ifdef CONFIG_MPC8540
+typedef struct ccsr_cpm {
+ char res[262144];
+} ccsr_cpm_t;
+#else
+/* 0x8000-0x8ffff:DPARM */
+
+/* 0x9000-0x90bff: General SIU */
+typedef struct ccsr_cpm_siu {
+ char res1[80];
+ uint smaer;
+ uint smser;
+ uint smevr;
+ char res2[4];
+ uint lmaer;
+ uint lmser;
+ uint lmevr;
+ char res3[2964];
+} ccsr_cpm_siu_t;
+
+/* 0x90c00-0x90cff: Interrupt Controller */
+typedef struct ccsr_cpm_intctl {
+ ushort sicr;
+ char res1[2];
+ uint sivec;
+ uint sipnrh;
+ uint sipnrl;
+ uint siprr;
+ uint scprrh;
+ uint scprrl;
+ uint simrh;
+ uint simrl;
+ uint siexr;
+ char res2[88];
+ uint sccr;
+ char res3[124];
+} ccsr_cpm_intctl_t;
+
+/* 0x90d00-0x90d7f: input/output port */
+typedef struct ccsr_cpm_iop {
+ uint pdira;
+ uint ppara;
+ uint psora;
+ uint podra;
+ uint pdata;
+ char res1[12];
+ uint pdirb;
+ uint pparb;
+ uint psorb;
+ uint podrb;
+ uint pdatb;
+ char res2[12];
+ uint pdirc;
+ uint pparc;
+ uint psorc;
+ uint podrc;
+ uint pdatc;
+ char res3[12];
+ uint pdird;
+ uint ppard;
+ uint psord;
+ uint podrd;
+ uint pdatd;
+ char res4[12];
+} ccsr_cpm_iop_t;
+
+/* 0x90d80-0x91017: CPM timers */
+typedef struct ccsr_cpm_timer {
+ u_char tgcr1;
+ char res1[3];
+ u_char tgcr2;
+ char res2[11];
+ ushort tmr1;
+ ushort tmr2;
+ ushort trr1;
+ ushort trr2;
+ ushort tcr1;
+ ushort tcr2;
+ ushort tcn1;
+ ushort tcn2;
+ ushort tmr3;
+ ushort tmr4;
+ ushort trr3;
+ ushort trr4;
+ ushort tcr3;
+ ushort tcr4;
+ ushort tcn3;
+ ushort tcn4;
+ ushort ter1;
+ ushort ter2;
+ ushort ter3;
+ ushort ter4;
+ char res3[608];
+} ccsr_cpm_timer_t;
+
+/* 0x91018-0x912ff: SDMA */
+typedef struct ccsr_cpm_sdma {
+ uchar sdsr;
+ char res1[3];
+ uchar sdmr;
+ char res2[739];
+} ccsr_cpm_sdma_t;
+
+/* 0x91300-0x9131f: FCC1 */
+typedef struct ccsr_cpm_fcc1 {
+ uint gfmr;
+ uint fpsmr;
+ ushort ftodr;
+ char res1[2];
+ ushort fdsr;
+ char res2[2];
+ ushort fcce;
+ char res3[2];
+ ushort fccm;
+ char res4[2];
+ u_char fccs;
+ char res5[3];
+ u_char ftirr_phy[4];
+} ccsr_cpm_fcc1_t;
+
+/* 0x91320-0x9133f: FCC2 */
+typedef struct ccsr_cpm_fcc2 {
+ uint gfmr;
+ uint fpsmr;
+ ushort ftodr;
+ char res1[2];
+ ushort fdsr;
+ char res2[2];
+ ushort fcce;
+ char res3[2];
+ ushort fccm;
+ char res4[2];
+ u_char fccs;
+ char res5[3];
+ u_char ftirr_phy[4];
+} ccsr_cpm_fcc2_t;
+
+/* 0x91340-0x9137f: FCC3 */
+typedef struct ccsr_cpm_fcc3 {
+ uint gfmr;
+ uint fpsmr;
+ ushort ftodr;
+ char res1[2];
+ ushort fdsr;
+ char res2[2];
+ ushort fcce;
+ char res3[2];
+ ushort fccm;
+ char res4[2];
+ u_char fccs;
+ char res5[3];
+ char res[36];
+} ccsr_cpm_fcc3_t;
+
+/* 0x91380-0x9139f: FCC1 extended */
+typedef struct ccsr_cpm_fcc1_ext {
+ uint firper;
+ uint firer;
+ uint firsr_h;
+ uint firsr_l;
+ u_char gfemr;
+ char res[15];
+
+} ccsr_cpm_fcc1_ext_t;
+
+/* 0x913a0-0x913cf: FCC2 extended */
+typedef struct ccsr_cpm_fcc2_ext {
+ uint firper;
+ uint firer;
+ uint firsr_h;
+ uint firsr_l;
+ u_char gfemr;
+ char res[31];
+} ccsr_cpm_fcc2_ext_t;
+
+/* 0x913d0-0x913ff: FCC3 extended */
+typedef struct ccsr_cpm_fcc3_ext {
+ u_char gfemr;
+ char res[47];
+} ccsr_cpm_fcc3_ext_t;
+
+/* 0x91400-0x915ef: TC layers */
+typedef struct ccsr_cpm_tmp1 {
+ char res[496];
+} ccsr_cpm_tmp1_t;
+
+/* 0x915f0-0x9185f: BRGs:5,6,7,8 */
+typedef struct ccsr_cpm_brg2 {
+ uint brgc5;
+ uint brgc6;
+ uint brgc7;
+ uint brgc8;
+ char res[608];
+} ccsr_cpm_brg2_t;
+
+/* 0x91860-0x919bf: I2C */
+typedef struct ccsr_cpm_i2c {
+ u_char i2mod;
+ char res1[3];
+ u_char i2add;
+ char res2[3];
+ u_char i2brg;
+ char res3[3];
+ u_char i2com;
+ char res4[3];
+ u_char i2cer;
+ char res5[3];
+ u_char i2cmr;
+ char res6[331];
+} ccsr_cpm_i2c_t;
+
+/* 0x919c0-0x919ef: CPM core */
+typedef struct ccsr_cpm_cp {
+ uint cpcr;
+ uint rccr;
+ char res1[14];
+ ushort rter;
+ char res2[2];
+ ushort rtmr;
+ ushort rtscr;
+ char res3[2];
+ uint rtsr;
+ char res4[12];
+} ccsr_cpm_cp_t;
+
+/* 0x919f0-0x919ff: BRGs:1,2,3,4 */
+typedef struct ccsr_cpm_brg1 {
+ uint brgc1;
+ uint brgc2;
+ uint brgc3;
+ uint brgc4;
+} ccsr_cpm_brg1_t;
+
+/* 0x91a00-0x91a9f: SCC1-SCC4 */
+typedef struct ccsr_cpm_scc {
+ uint gsmrl;
+ uint gsmrh;
+ ushort psmr;
+ char res1[2];
+ ushort todr;
+ ushort dsr;
+ ushort scce;
+ char res2[2];
+ ushort sccm;
+ char res3;
+ u_char sccs;
+ char res4[8];
+} ccsr_cpm_scc_t;
+
+/* 0x91a80-0x91a9f */
+typedef struct ccsr_cpm_tmp2 {
+ char res[32];
+} ccsr_cpm_tmp2_t;
+
+/* 0x91aa0-0x91aff: SPI */
+typedef struct ccsr_cpm_spi {
+ ushort spmode;
+ char res1[4];
+ u_char spie;
+ char res2[3];
+ u_char spim;
+ char res3[2];
+ u_char spcom;
+ char res4[82];
+} ccsr_cpm_spi_t;
+
+/* 0x91b00-0x91b1f: CPM MUX */
+typedef struct ccsr_cpm_mux {
+ u_char cmxsi1cr;
+ char res1;
+ u_char cmxsi2cr;
+ char res2;
+ uint cmxfcr;
+ uint cmxscr;
+ char res3[2];
+ ushort cmxuar;
+ char res4[16];
+} ccsr_cpm_mux_t;
+
+/* 0x91b20-0xbffff: SI,MCC,etc */
+typedef struct ccsr_cpm_tmp3 {
+ char res[58592];
+} ccsr_cpm_tmp3_t;
+
+typedef struct ccsr_cpm_iram {
+ unsigned long iram[8192];
+ char res[98304];
+} ccsr_cpm_iram_t;
+
+typedef struct ccsr_cpm {
+ /* Some references are into the unique and known dpram spaces,
+ * others are from the generic base.
+ */
+#define im_dprambase im_dpram1
+ u_char im_dpram1[16*1024];
+ char res1[16*1024];
+ u_char im_dpram2[16*1024];
+ char res2[16*1024];
+
+ ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */
+ ccsr_cpm_intctl_t im_cpm_intctl; /* Interrupt Controller */
+ ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */
+ ccsr_cpm_timer_t im_cpm_timer; /* CPM timers */
+ ccsr_cpm_sdma_t im_cpm_sdma; /* SDMA control/status */
+ ccsr_cpm_fcc1_t im_cpm_fcc1;
+ ccsr_cpm_fcc2_t im_cpm_fcc2;
+ ccsr_cpm_fcc3_t im_cpm_fcc3;
+ ccsr_cpm_fcc1_ext_t im_cpm_fcc1_ext;
+ ccsr_cpm_fcc2_ext_t im_cpm_fcc2_ext;
+ ccsr_cpm_fcc3_ext_t im_cpm_fcc3_ext;
+ ccsr_cpm_tmp1_t im_cpm_tmp1;
+ ccsr_cpm_brg2_t im_cpm_brg2;
+ ccsr_cpm_i2c_t im_cpm_i2c;
+ ccsr_cpm_cp_t im_cpm_cp;
+ ccsr_cpm_brg1_t im_cpm_brg1;
+ ccsr_cpm_scc_t im_cpm_scc[4];
+ ccsr_cpm_tmp2_t im_cpm_tmp2;
+ ccsr_cpm_spi_t im_cpm_spi;
+ ccsr_cpm_mux_t im_cpm_mux;
+ ccsr_cpm_tmp3_t im_cpm_tmp3;
+ ccsr_cpm_iram_t im_cpm_iram;
+} ccsr_cpm_t;
+#endif
+/* RapidIO Registers(0xc_0000-0xe_0000) */
+
+typedef struct ccsr_rio {
+ uint didcar; /* 0xc0000 - Device Identity Capability Register */
+ uint dicar; /* 0xc0004 - Device Information Capability Register */
+ uint aidcar; /* 0xc0008 - Assembly Identity Capability Register */
+ uint aicar; /* 0xc000c - Assembly Information Capability Register */
+ uint pefcar; /* 0xc0010 - Processing Element Features Capability Register */
+ uint spicar; /* 0xc0014 - Switch Port Information Capability Register */
+ uint socar; /* 0xc0018 - Source Operations Capability Register */
+ uint docar; /* 0xc001c - Destination Operations Capability Register */
+ char res1[32];
+ uint msr; /* 0xc0040 - Mailbox Command And Status Register */
+ uint pwdcsr; /* 0xc0044 - Port-Write and Doorbell Command And Status Register */
+ char res2[4];
+ uint pellccsr; /* 0xc004c - Processing Element Logic Layer Control Command and Status Register */
+ char res3[12];
+ uint lcsbacsr; /* 0xc005c - Local Configuration Space Base Address Command and Status Register */
+ uint bdidcsr; /* 0xc0060 - Base Device ID Command and Status Register */
+ char res4[4];
+ uint hbdidlcsr; /* 0xc0068 - Host Base Device ID Lock Command and Status Register */
+ uint ctcsr; /* 0xc006c - Component Tag Command and Status Register */
+ char res5[144];
+ uint pmbh0csr; /* 0xc0100 - 8/16 LP-LVDS Port Maintenance Block Header 0 Command and Status Register */
+ char res6[28];
+ uint pltoccsr; /* 0xc0120 - Port Link Time-out Control Command and Status Register */
+ uint prtoccsr; /* 0xc0124 - Port Response Time-out Control Command and Status Register */
+ char res7[20];
+ uint pgccsr; /* 0xc013c - Port General Command and Status Register */
+ uint plmreqcsr; /* 0xc0140 - Port Link Maintenance Request Command and Status Register */
+ uint plmrespcsr; /* 0xc0144 - Port Link Maintenance Response Command and Status Register */
+ uint plascsr; /* 0xc0148 - Port Local Ackid Status Command and Status Register */
+ char res8[12];
+ uint pescsr; /* 0xc0158 - Port Error and Status Command and Status Register */
+ uint pccsr; /* 0xc015c - Port Control Command and Status Register */
+ char res9[65184];
+ uint cr; /* 0xd0000 - Port Control Command and Status Register */
+ char res10[12];
+ uint pcr; /* 0xd0010 - Port Configuration Register */
+ uint peir; /* 0xd0014 - Port Error Injection Register */
+ char res11[3048];
+ uint rowtar0; /* 0xd0c00 - RapidIO Outbound Window Translation Address Register 0 */
+ char res12[12];
+ uint rowar0; /* 0xd0c10 - RapidIO Outbound Attributes Register 0 */
+ char res13[12];
+ uint rowtar1; /* 0xd0c20 - RapidIO Outbound Window Translation Address Register 1 */
+ char res14[4];
+ uint rowbar1; /* 0xd0c28 - RapidIO Outbound Window Base Address Register 1 */
+ char res15[4];
+ uint rowar1; /* 0xd0c30 - RapidIO Outbound Attributes Register 1 */
+ char res16[12];
+ uint rowtar2; /* 0xd0c40 - RapidIO Outbound Window Translation Address Register 2 */
+ char res17[4];
+ uint rowbar2; /* 0xd0c48 - RapidIO Outbound Window Base Address Register 2 */
+ char res18[4];
+ uint rowar2; /* 0xd0c50 - RapidIO Outbound Attributes Register 2 */
+ char res19[12];
+ uint rowtar3; /* 0xd0c60 - RapidIO Outbound Window Translation Address Register 3 */
+ char res20[4];
+ uint rowbar3; /* 0xd0c68 - RapidIO Outbound Window Base Address Register 3 */
+ char res21[4];
+ uint rowar3; /* 0xd0c70 - RapidIO Outbound Attributes Register 3 */
+ char res22[12];
+ uint rowtar4; /* 0xd0c80 - RapidIO Outbound Window Translation Address Register 4 */
+ char res23[4];
+ uint rowbar4; /* 0xd0c88 - RapidIO Outbound Window Base Address Register 4 */
+ char res24[4];
+ uint rowar4; /* 0xd0c90 - RapidIO Outbound Attributes Register 4 */
+ char res25[12];
+ uint rowtar5; /* 0xd0ca0 - RapidIO Outbound Window Translation Address Register 5 */
+ char res26[4];
+ uint rowbar5; /* 0xd0ca8 - RapidIO Outbound Window Base Address Register 5 */
+ char res27[4];
+ uint rowar5; /* 0xd0cb0 - RapidIO Outbound Attributes Register 5 */
+ char res28[12];
+ uint rowtar6; /* 0xd0cc0 - RapidIO Outbound Window Translation Address Register 6 */
+ char res29[4];
+ uint rowbar6; /* 0xd0cc8 - RapidIO Outbound Window Base Address Register 6 */
+ char res30[4];
+ uint rowar6; /* 0xd0cd0 - RapidIO Outbound Attributes Register 6 */
+ char res31[12];
+ uint rowtar7; /* 0xd0ce0 - RapidIO Outbound Window Translation Address Register 7 */
+ char res32[4];
+ uint rowbar7; /* 0xd0ce8 - RapidIO Outbound Window Base Address Register 7 */
+ char res33[4];
+ uint rowar7; /* 0xd0cf0 - RapidIO Outbound Attributes Register 7 */
+ char res34[12];
+ uint rowtar8; /* 0xd0d00 - RapidIO Outbound Window Translation Address Register 8 */
+ char res35[4];
+ uint rowbar8; /* 0xd0d08 - RapidIO Outbound Window Base Address Register 8 */
+ char res36[4];
+ uint rowar8; /* 0xd0d10 - RapidIO Outbound Attributes Register 8 */
+ char res37[76];
+ uint riwtar4; /* 0xd0d60 - RapidIO Inbound Window Translation Address Register 4 */
+ char res38[4];
+ uint riwbar4; /* 0xd0d68 - RapidIO Inbound Window Base Address Register 4 */
+ char res39[4];
+ uint riwar4; /* 0xd0d70 - RapidIO Inbound Attributes Register 4 */
+ char res40[12];
+ uint riwtar3; /* 0xd0d80 - RapidIO Inbound Window Translation Address Register 3 */
+ char res41[4];
+ uint riwbar3; /* 0xd0d88 - RapidIO Inbound Window Base Address Register 3 */
+ char res42[4];
+ uint riwar3; /* 0xd0d90 - RapidIO Inbound Attributes Register 3 */
+ char res43[12];
+ uint riwtar2; /* 0xd0da0 - RapidIO Inbound Window Translation Address Register 2 */
+ char res44[4];
+ uint riwbar2; /* 0xd0da8 - RapidIO Inbound Window Base Address Register 2 */
+ char res45[4];
+ uint riwar2; /* 0xd0db0 - RapidIO Inbound Attributes Register 2 */
+ char res46[12];
+ uint riwtar1; /* 0xd0dc0 - RapidIO Inbound Window Translation Address Register 1 */
+ char res47[4];
+ uint riwbar1; /* 0xd0dc8 - RapidIO Inbound Window Base Address Register 1 */
+ char res48[4];
+ uint riwar1; /* 0xd0dd0 - RapidIO Inbound Attributes Register 1 */
+ char res49[12];
+ uint riwtar0; /* 0xd0de0 - RapidIO Inbound Window Translation Address Register 0 */
+ char res50[12];
+ uint riwar0; /* 0xd0df0 - RapidIO Inbound Attributes Register 0 */
+ char res51[12];
+ uint pnfedr; /* 0xd0e00 - Port Notification/Fatal Error Detect Register */
+ uint pnfedir; /* 0xd0e04 - Port Notification/Fatal Error Detect Register */
+ uint pnfeier; /* 0xd0e08 - Port Notification/Fatal Error Interrupt Enable Register */
+ uint pecr; /* 0xd0e0c - Port Error Control Register */
+ uint pepcsr0; /* 0xd0e10 - Port Error Packet/Control Symbol Register 0 */
+ uint pepr1; /* 0xd0e14 - Port Error Packet Register 1 */
+ uint pepr2; /* 0xd0e18 - Port Error Packet Register 2 */
+ char res52[4];
+ uint predr; /* 0xd0e20 - Port Recoverable Error Detect Register */
+ char res53[4];
+ uint pertr; /* 0xd0e28 - Port Error Recovery Threshold Register */
+ uint prtr; /* 0xd0e2c - Port Retry Threshold Register */
+ char res54[464];
+ uint omr; /* 0xd1000 - Outbound Mode Register */
+ uint osr; /* 0xd1004 - Outbound Status Register */
+ uint eodqtpar; /* 0xd1008 - Extended Outbound Descriptor Queue Tail Pointer Address Register */
+ uint odqtpar; /* 0xd100c - Outbound Descriptor Queue Tail Pointer Address Register */
+ uint eosar; /* 0xd1010 - Extended Outbound Unit Source Address Register */
+ uint osar; /* 0xd1014 - Outbound Unit Source Address Register */
+ uint odpr; /* 0xd1018 - Outbound Destination Port Register */
+ uint odatr; /* 0xd101c - Outbound Destination Attributes Register */
+ uint odcr; /* 0xd1020 - Outbound Doubleword Count Register */
+ uint eodqhpar; /* 0xd1024 - Extended Outbound Descriptor Queue Head Pointer Address Register */
+ uint odqhpar; /* 0xd1028 - Outbound Descriptor Queue Head Pointer Address Register */
+ char res55[52];
+ uint imr; /* 0xd1060 - Outbound Mode Register */
+ uint isr; /* 0xd1064 - Inbound Status Register */
+ uint eidqtpar; /* 0xd1068 - Extended Inbound Descriptor Queue Tail Pointer Address Register */
+ uint idqtpar; /* 0xd106c - Inbound Descriptor Queue Tail Pointer Address Register */
+ uint eifqhpar; /* 0xd1070 - Extended Inbound Frame Queue Head Pointer Address Register */
+ uint ifqhpar; /* 0xd1074 - Inbound Frame Queue Head Pointer Address Register */
+ char res56[1000];
+ uint dmr; /* 0xd1460 - Doorbell Mode Register */
+ uint dsr; /* 0xd1464 - Doorbell Status Register */
+ uint edqtpar; /* 0xd1468 - Extended Doorbell Queue Tail Pointer Address Register */
+ uint dqtpar; /* 0xd146c - Doorbell Queue Tail Pointer Address Register */
+ uint edqhpar; /* 0xd1470 - Extended Doorbell Queue Head Pointer Address Register */
+ uint dqhpar; /* 0xd1474 - Doorbell Queue Head Pointer Address Register */
+ char res57[104];
+ uint pwmr; /* 0xd14e0 - Port-Write Mode Register */
+ uint pwsr; /* 0xd14e4 - Port-Write Status Register */
+ uint epwqbar; /* 0xd14e8 - Extended Port-Write Queue Base Address Register */
+ uint pwqbar; /* 0xd14ec - Port-Write Queue Base Address Register */
+ char res58[60176];
+} ccsr_rio_t;
+
+/* Global Utilities Register Block(0xe_0000-0xf_ffff) */
+typedef struct ccsr_gur {
+ uint porpllsr; /* 0xe0000 - POR PLL ratio status register */
+ uint porbmsr; /* 0xe0004 - POR boot mode status register */
+ uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */
+ uint pordevsr; /* 0xe000c - POR I/O device status regsiter */
+ uint pordbgmsr; /* 0xe0010 - POR debug mode status register */
+ char res1[12];
+ uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */
+ char res2[12];
+ uint gpiocr; /* 0xe0030 - GPIO control register */
+ char res3[12];
+ uint gpoutdr; /* 0xe0040 - General-purpose output data register */
+ char res4[12];
+ uint gpindr; /* 0xe0050 - General-purpose input data register */
+ char res5[12];
+ uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */
+ char res6[12];
+ uint devdisr; /* 0xe0070 - Device disable control */
+ char res7[12];
+ uint powmgtcsr; /* 0xe0080 - Power management status and control register */
+ char res8[12];
+ uint mcpsumr; /* 0xe0090 - Machine check summary register */
+ char res9[12];
+ uint pvr; /* 0xe00a0 - Processor version register */
+ uint svr; /* 0xe00a4 - System version register */
+ char res10[3416];
+ uint clkocr; /* 0xe0e00 - Clock out select register */
+ char res11[12];
+ uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */
+ char res12[12];
+ uint lbcdllcr; /* 0xe0e20 - LBC DLL control register */
+ char res13[61915];
+} ccsr_gur_t;
+
+typedef struct immap {
+ ccsr_local_ecm_t im_local_ecm;
+ ccsr_ddr_t im_ddr;
+ ccsr_i2c_t im_i2c;
+ ccsr_duart_t im_duart;
+ ccsr_lbc_t im_lbc;
+ ccsr_pcix_t im_pcix;
+ ccsr_l2cache_t im_l2cache;
+ ccsr_dma_t im_dma;
+ ccsr_tsec_t im_tsec1;
+ ccsr_tsec_t im_tsec2;
+ ccsr_pic_t im_pic;
+ ccsr_cpm_t im_cpm;
+ ccsr_rio_t im_rio;
+ ccsr_gur_t im_gur;
+} immap_t;
+
+extern immap_t *immr;
+
+#endif /*__IMMAP_85xx__*/
#define TLB_M 0x00000002 /* Memory is coherent */
#define TLB_G 0x00000001 /* Memory is guarded from prefetch */
+/*
+ * e500 support
+ */
+
+#define MAS0_TLBSEL 0x10000000
+#define MAS0_ESEL 0x000F0000
+#define MAS0_NV 0x00000001
+
+#define MAS1_VALID 0x80000000
+#define MAS1_IPROT 0x40000000
+#define MAS1_TID 0x00FF0000
+#define MAS1_TS 0x00001000
+#define MAS1_TSIZE 0x00000F00
+
+#define MAS2_EPN 0xFFFFF000
+#define MAS2_SHAREN 0x00000200
+#define MAS2_X0 0x00000040
+#define MAS2_X1 0x00000020
+#define MAS2_W 0x00000010
+#define MAS2_I 0x00000008
+#define MAS2_M 0x00000004
+#define MAS2_G 0x00000002
+#define MAS2_E 0x00000001
+
+#define MAS3_RPN 0xFFFFF000
+#define MAS3_U0 0x00000200
+#define MAS3_U1 0x00000100
+#define MAS3_U2 0x00000080
+#define MAS3_U3 0x00000040
+#define MAS3_UX 0x00000020
+#define MAS3_SX 0x00000010
+#define MAS3_UW 0x00000008
+#define MAS3_SW 0x00000004
+#define MAS3_UR 0x00000002
+#define MAS3_SR 0x00000001
+
+#define MAS4_TLBSELD 0x10000000
+#define MAS4_TIDDSEL 0x00030000
+#define MAS4_DSHAREN 0x00001000
+#define MAS4_TSIZED(x) (x << 8)
+#define MAS4_X0D 0x00000040
+#define MAS4_X1D 0x00000020
+#define MAS4_WD 0x00000010
+#define MAS4_ID 0x00000008
+#define MAS4_MD 0x00000004
+#define MAS4_GD 0x00000002
+#define MAS4_ED 0x00000001
+
+#define MAS6_SPID 0x00FF0000
+#define MAS6_SAS 0x00000001
+
+#define BOOKE_PAGESZ_1K 0
+#define BOOKE_PAGESZ_4K 1
+#define BOOKE_PAGESZ_16K 2
+#define BOOKE_PAGESZ_64K 3
+#define BOOKE_PAGESZ_256K 4
+#define BOOKE_PAGESZ_1M 5
+#define BOOKE_PAGESZ_4M 6
+#define BOOKE_PAGESZ_16M 7
+#define BOOKE_PAGESZ_64M 8
+#define BOOKE_PAGESZ_256M 9
+#define BOOKE_PAGESZ_1GB 10
+#define BOOKE_PAGESZ_4GB 11
+
+#define LAWBAR_BASE_ADDR 0x000FFFFF
+#define LAWAR_EN 0x80000000
+#define LAWAR_TRGT_IF 0x00F00000
+#define LAWAR_SIZE 0x0000003F
+
+#define LAWAR_TRGT_IF_PCI 0x00000000
+#define LAWAR_TRGT_IF_PCIX 0x00000000
+#define LAWAR_TRGT_IF_LBC 0x00400000
+#define LAWAR_TRGT_IF_CCSR 0x00800000
+#define LAWAR_TRGT_IF_RIO 0x00c00000
+#define LAWAR_TRGT_IF_DDR 0x00f00000
+
+#define LAWAR_SIZE_BASE 0xa
+#define LAWAR_SIZE_4K (LAWAR_SIZE_BASE+1)
+#define LAWAR_SIZE_8K (LAWAR_SIZE_BASE+2)
+#define LAWAR_SIZE_16K (LAWAR_SIZE_BASE+3)
+#define LAWAR_SIZE_32K (LAWAR_SIZE_BASE+4)
+#define LAWAR_SIZE_64K (LAWAR_SIZE_BASE+5)
+#define LAWAR_SIZE_128K (LAWAR_SIZE_BASE+6)
+#define LAWAR_SIZE_256K (LAWAR_SIZE_BASE+7)
+#define LAWAR_SIZE_512K (LAWAR_SIZE_BASE+8)
+#define LAWAR_SIZE_1M (LAWAR_SIZE_BASE+9)
+#define LAWAR_SIZE_2M (LAWAR_SIZE_BASE+10)
+#define LAWAR_SIZE_4M (LAWAR_SIZE_BASE+11)
+#define LAWAR_SIZE_8M (LAWAR_SIZE_BASE+12)
+#define LAWAR_SIZE_16M (LAWAR_SIZE_BASE+13)
+#define LAWAR_SIZE_32M (LAWAR_SIZE_BASE+14)
+#define LAWAR_SIZE_64M (LAWAR_SIZE_BASE+15)
+#define LAWAR_SIZE_128M (LAWAR_SIZE_BASE+16)
+#define LAWAR_SIZE_256M (LAWAR_SIZE_BASE+17)
+#define LAWAR_SIZE_512M (LAWAR_SIZE_BASE+18)
+#define LAWAR_SIZE_1G (LAWAR_SIZE_BASE+19)
+#define LAWAR_SIZE_2G (LAWAR_SIZE_BASE+20)
+
#endif /* _PPC_MMU_H_ */
#define MSR_SF (1<<63)
#define MSR_ISF (1<<61)
#endif /* CONFIG_PPC64BRIDGE */
-#define MSR_VEC (1<<25) /* Enable AltiVec */
+#define MSR_UCLE (1<<26) /* User-mode cache lock enable (e500) */
+#define MSR_VEC (1<<25) /* Enable AltiVec(74xx) */
+#define MSR_SPE (1<<25) /* Enable SPE(e500) */
#define MSR_POW (1<<18) /* Enable Power Management */
#define MSR_WE (1<<18) /* Wait State Enable */
#define MSR_TGPR (1<<17) /* TLB Update registers in use */
#define MSR_ME (1<<12) /* Machine Check Enable */
#define MSR_FE0 (1<<11) /* Floating Exception mode 0 */
#define MSR_SE (1<<10) /* Single Step */
+#define MSR_DWE (1<<10) /* Debug Wait Enable (4xx) */
+#define MSR_UBLE (1<<10) /* BTB lock enable (e500) */
#define MSR_BE (1<<9) /* Branch Trace */
#define MSR_DE (1<<9) /* Debug Exception Enable */
#define MSR_FE1 (1<<8) /* Floating Exception mode 1 */
#define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */
#define MSR_IR (1<<5) /* Instruction Relocate */
+#define MSR_IS (1<<5) /* Book E Instruction space */
#define MSR_DR (1<<4) /* Data Relocate */
+#define MSR_DS (1<<4) /* Book E Data space */
#define MSR_PE (1<<3) /* Protection Enable */
#define MSR_PX (1<<2) /* Protection Exclusive Mode */
+#define MSR_PMM (1<<2) /* Performance monitor mark bit (e500) */
#define MSR_RI (1<<1) /* Recoverable Exception */
#define MSR_LE (1<<0) /* Little Endian */
#else
#define MSR_ MSR_ME|MSR_RI
#endif
+#ifndef CONFIG_E500
#define MSR_KERNEL MSR_|MSR_IR|MSR_DR
+#else
+#define MSR_KERNEL MSR_ME
+#endif
#define MSR_USER MSR_KERNEL|MSR_PR|MSR_EE
/* Floating Point Status and Control Register (FPSCR) Fields */
#define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */
#define SPRN_CTR 0x009 /* Count Register */
#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */
+#ifndef CONFIG_BOOKE
#define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */
#define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */
+#else
+#define SPRN_DAC1 0x13C /* Book E Data Address Compare 1 */
+#define SPRN_DAC2 0x13D /* Book E Data Address Compare 2 */
+#endif /* CONFIG_BOOKE */
#define SPRN_DAR 0x013 /* Data Address Register */
#define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */
#define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */
#define DBCR_SDA 0x00000004 /* Second DAC Enable */
#define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */
#define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */
-#define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */
+#ifndef CONFIG_BOOKE
+#define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */
+#else
+#define SPRN_DBCR0 0x134 /* Book E Debug Control Register 0 */
+#endif /* CONFIG_BOOKE */
+#ifndef CONFIG_BOOKE
#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */
#define SPRN_DBSR 0x3F0 /* Debug Status Register */
+#else
+#define SPRN_DBCR1 0x135 /* Book E Debug Control Register 1 */
+#define SPRN_DBSR 0x130 /* Book E Debug Status Register */
+#define DBSR_IC 0x08000000 /* Book E Instruction Completion */
+#define DBSR_TIE 0x01000000 /* Book E Trap Instruction Event */
+#endif /* CONFIG_BOOKE */
#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
#define DCCR_NOCACHE 0 /* Noncacheable */
#define DCCR_CACHE 1 /* Cacheable */
#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */
#define DCWR_COPY 0 /* Copy-back */
#define DCWR_WRITE 1 /* Write-through */
+#ifndef CONFIG_BOOKE
#define SPRN_DEAR 0x3D5 /* Data Error Address Register */
+#else
+#define SPRN_DEAR 0x03D /* Book E Data Error Address Register */
+#endif /* CONFIG_BOOKE */
#define SPRN_DEC 0x016 /* Decrement Register */
#define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */
#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */
#define SPRN_EAR 0x11A /* External Address Register */
+#ifndef CONFIG_BOOKE
#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */
+#else
+#define SPRN_ESR 0x03E /* Book E Exception Syndrome Register */
+#endif /* CONFIG_BOOKE */
#define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */
#define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */
#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */
#define HID0_BTCD (1<<1) /* Branch target cache disable */
#define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */
#define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */
+#ifndef CONFIG_BOOKE
#define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */
#define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */
+#else
+#define SPRN_IAC1 0x138 /* Book E Instruction Address Compare 1 */
+#define SPRN_IAC2 0x139 /* Book E Instruction Address Compare 2 */
+#endif /* CONFIG_BOOKE */
#define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */
#define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */
#define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */
#define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */
#define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */
#define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */
+#ifndef CONFIG_BOOKE
#define SPRN_PID 0x3B1 /* Process ID */
#define SPRN_PIR 0x3FF /* Processor Identification Register */
+#else
+#define SPRN_PID 0x030 /* Book E Process ID */
+#define SPRN_PIR 0x11E /* Book E Processor Identification Register */
+#endif /* CONFIG_BOOKE */
#define SPRN_PIT 0x3DB /* Programmable Interval Timer */
#define SPRN_PMC1 0x3B9 /* Performance Counter Register 1 */
#define SPRN_PMC2 0x3BA /* Performance Counter Register 2 */
#define SPRN_TBRU 0x10C /* Time Base Read Upper Register */
#define SPRN_TBWL 0x11D /* Time Base Write Lower Register */
#define SPRN_TBWU 0x11C /* Time Base Write Upper Register */
+#ifndef CONFIG_BOOKE
#define SPRN_TCR 0x3DA /* Timer Control Register */
+#else
+#define SPRN_TCR 0x154 /* Book E Timer Control Register */
+#endif /* CONFIG_BOOKE */
#define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */
#define WP_2_17 0 /* 2^17 clocks */
#define WP_2_21 1 /* 2^21 clocks */
#define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */
#define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */
#define THRM3_E (1<<31)
+#define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */
+#ifndef CONFIG_BOOKE
#define SPRN_TSR 0x3D8 /* Timer Status Register */
+#else
+#define SPRN_TSR 0x150 /* Book E Timer Status Register */
+#endif /* CONFIG_BOOKE */
#define TSR_ENW 0x80000000 /* Enable Next Watchdog */
#define TSR_WIS 0x40000000 /* WDT Interrupt Status */
#define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */
#define SPRN_XER 0x001 /* Fixed Point Exception Register */
#define SPRN_ZPR 0x3B0 /* Zone Protection Register */
+/* Book E definitions */
+#define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */
+#define SPRN_CSRR0 0x03A /* Critical SRR0 */
+#define SPRN_CSRR1 0x03B /* Critical SRR0 */
+#define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */
+#define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */
+#define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */
+#define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */
+#define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */
+#define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */
+#define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */
+#define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */
+#define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */
+#define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */
+#define SPRN_DBCR2 0x136 /* Debug Control Register 2 */
+#define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */
+#define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */
+#define SPRN_DVC1 0x13E /* Data Value Compare Register 1 */
+#define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */
+#define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */
+#define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */
+#define SPRN_IVOR2 0x192 /* Interrupt Vector Offset Register 2 */
+#define SPRN_IVOR3 0x193 /* Interrupt Vector Offset Register 3 */
+#define SPRN_IVOR4 0x194 /* Interrupt Vector Offset Register 4 */
+#define SPRN_IVOR5 0x195 /* Interrupt Vector Offset Register 5 */
+#define SPRN_IVOR6 0x196 /* Interrupt Vector Offset Register 6 */
+#define SPRN_IVOR7 0x197 /* Interrupt Vector Offset Register 7 */
+#define SPRN_IVOR8 0x198 /* Interrupt Vector Offset Register 8 */
+#define SPRN_IVOR9 0x199 /* Interrupt Vector Offset Register 9 */
+#define SPRN_IVOR10 0x19a /* Interrupt Vector Offset Register 10 */
+#define SPRN_IVOR11 0x19b /* Interrupt Vector Offset Register 11 */
+#define SPRN_IVOR12 0x19c /* Interrupt Vector Offset Register 12 */
+#define SPRN_IVOR13 0x19d /* Interrupt Vector Offset Register 13 */
+#define SPRN_IVOR14 0x19e /* Interrupt Vector Offset Register 14 */
+#define SPRN_IVOR15 0x19f /* Interrupt Vector Offset Register 15 */
+
+/* e500 definitions */
+#define SPRN_L1CSR0 0x3f2 /* L1 Cache Control and Status Register 0 */
+#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
+#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
+#define SPRN_L1CSR1 0x3f3 /* L1 Cache Control and Status Register 1 */
+#define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
+#define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
+
+#define SPRN_MMUCSR0 0x3f4 /* MMU control and status register 0 */
+#define SPRN_MAS0 0x270 /* MMU Assist Register 0 */
+#define SPRN_MAS1 0x271 /* MMU Assist Register 1 */
+#define SPRN_MAS2 0x272 /* MMU Assist Register 2 */
+#define SPRN_MAS3 0x273 /* MMU Assist Register 3 */
+#define SPRN_MAS4 0x274 /* MMU Assist Register 4 */
+#define SPRN_MAS5 0x275 /* MMU Assist Register 5 */
+#define SPRN_MAS6 0x276 /* MMU Assist Register 6 */
+
+#define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */
+#define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */
+#define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */
+#define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */
+#define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */
+
+#define SPRN_MCSRR0 0x23a /* Machine Check Save and Restore Register 0 */
+#define SPRN_MCSRR1 0x23b /* Machine Check Save and Restore Register 1 */
+#define SPRN_BUCSR 0x3f5 /* Branch Control and Status Register */
+#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */
+#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */
+#define SPRN_PID1 0x279 /* Process ID Register 1 */
+#define SPRN_PID2 0x27a /* Process ID Register 2 */
+#define SPRN_MCSR 0x23c /* Machine Check Syndrome register */
+#define ESR_ST 0x00800000 /* Store Operation */
+
/* Short-hand versions for a number of the above SPRNs */
#define CTR SPRN_CTR /* Counter Register */
#define DAR SPRN_DAR /* Data Address Register */
#define DABR SPRN_DABR /* Data Address Breakpoint Register */
+#define DAC1 SPRN_DAC1 /* Data Address Register 1 */
+#define DAC2 SPRN_DAC2 /* Data Address Register 2 */
#define DBAT0L SPRN_DBAT0L /* Data BAT 0 Lower Register */
#define DBAT0U SPRN_DBAT0U /* Data BAT 0 Upper Register */
#define DBAT1L SPRN_DBAT1L /* Data BAT 1 Lower Register */
#define DBAT6U SPRN_DBAT6U /* Data BAT 6 Upper Register */
#define DBAT7L SPRN_DBAT7L /* Data BAT 7 Lower Register */
#define DBAT7U SPRN_DBAT7U /* Data BAT 7 Upper Register */
+#define DBCR0 SPRN_DBCR0 /* Debug Control Register 0 */
+#define DBCR1 SPRN_DBCR1 /* Debug Control Register 1 */
+#define DBSR SPRN_DBSR /* Debug Status Register */
#define DCMP SPRN_DCMP /* Data TLB Compare Register */
#define DEC SPRN_DEC /* Decrement Register */
#define DMISS SPRN_DMISS /* Data TLB Miss Register */
#define DSISR SPRN_DSISR /* Data Storage Interrupt Status Register */
#define EAR SPRN_EAR /* External Address Register */
+#define ESR SPRN_ESR /* Exception Syndrome Register */
#define HASH1 SPRN_HASH1 /* Primary Hash Address Register */
#define HASH2 SPRN_HASH2 /* Secondary Hash Address Register */
#define HID0 SPRN_HID0 /* Hardware Implementation Register 0 */
#define HID1 SPRN_HID1 /* Hardware Implementation Register 1 */
#define IABR SPRN_IABR /* Instruction Address Breakpoint Register */
+#define IAC1 SPRN_IAC1 /* Instruction Address Register 1 */
+#define IAC2 SPRN_IAC2 /* Instruction Address Register 2 */
#define IBAT0L SPRN_IBAT0L /* Instruction BAT 0 Lower Register */
#define IBAT0U SPRN_IBAT0U /* Instruction BAT 0 Upper Register */
#define IBAT1L SPRN_IBAT1L /* Instruction BAT 1 Lower Register */
#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */
#define L2CR SPRN_L2CR /* PPC 750 L2 control register */
#define LR SPRN_LR
+#if defined(CONFIG_E500)
+#define PIR SPRN_PIR
+#endif
#define PVR SPRN_PVR /* Processor Version */
#define RPA SPRN_RPA /* Required Physical Address Register */
#define SDR1 SPRN_SDR1 /* MMU hash base register */
#define TBRU SPRN_TBRU /* Time Base Read Upper Register */
#define TBWL SPRN_TBWL /* Time Base Write Lower Register */
#define TBWU SPRN_TBWU /* Time Base Write Upper Register */
+#define TCR SPRN_TCR /* Timer Control Register */
+#define TSR SPRN_TSR /* Timer Status Register */
#define ICTC 1019
#define THRM1 SPRN_THRM1 /* Thermal Management Register 1 */
#define THRM2 SPRN_THRM2 /* Thermal Management Register 2 */
#define THRM3 SPRN_THRM3 /* Thermal Management Register 3 */
#define XER SPRN_XER
+#define DECAR SPRN_DECAR
+#define CSRR0 SPRN_CSRR0
+#define CSRR1 SPRN_CSRR1
+#define IVPR SPRN_IVPR
+#define USPRG0 SPRN_USPRG0
+#define SPRG4R SPRN_SPRG4R
+#define SPRG5R SPRN_SPRG5R
+#define SPRG6R SPRN_SPRG6R
+#define SPRG7R SPRN_SPRG7R
+#define SPRG4W SPRN_SPRG4W
+#define SPRG5W SPRN_SPRG5W
+#define SPRG6W SPRN_SPRG6W
+#define SPRG7W SPRN_SPRG7W
+#define DEAR SPRN_DEAR
+#define DBCR2 SPRN_DBCR2
+#define IAC3 SPRN_IAC3
+#define IAC4 SPRN_IAC4
+#define DVC1 SPRN_DVC1
+#define DVC2 SPRN_DVC2
+#define IVOR0 SPRN_IVOR0
+#define IVOR1 SPRN_IVOR1
+#define IVOR2 SPRN_IVOR2
+#define IVOR3 SPRN_IVOR3
+#define IVOR4 SPRN_IVOR4
+#define IVOR5 SPRN_IVOR5
+#define IVOR6 SPRN_IVOR6
+#define IVOR7 SPRN_IVOR7
+#define IVOR8 SPRN_IVOR8
+#define IVOR9 SPRN_IVOR9
+#define IVOR10 SPRN_IVOR10
+#define IVOR11 SPRN_IVOR11
+#define IVOR12 SPRN_IVOR12
+#define IVOR13 SPRN_IVOR13
+#define IVOR14 SPRN_IVOR14
+#define IVOR15 SPRN_IVOR15
+#define IVOR32 SPRN_IVOR32
+#define IVOR33 SPRN_IVOR33
+#define IVOR34 SPRN_IVOR34
+#define IVOR35 SPRN_IVOR35
+#define MCSRR0 SPRN_MCSRR0
+#define MCSRR1 SPRN_MCSRR1
+#define L1CSR0 SPRN_L1CSR0
+#define L1CSR1 SPRN_L1CSR1
+#define MCSR SPRN_MCSR
+#define MMUCSR0 SPRN_MMUCSR0
+#define BUCSR SPRN_BUCSR
+#define PID0 SPRN_PID
+#define PID1 SPRN_PID1
+#define PID2 SPRN_PID2
+#define MAS0 SPRN_MAS0
+#define MAS1 SPRN_MAS1
+#define MAS2 SPRN_MAS2
+#define MAS3 SPRN_MAS3
+#define MAS4 SPRN_MAS4
+#define MAS5 SPRN_MAS5
+#define MAS6 SPRN_MAS6
/* Device Control Registers */
#define PVR_750 PVR_740
#define PVR_740P 0x10080000
#define PVR_750P PVR_740P
+#define PVR_7400 0x000C0000
+#define PVR_7410 0x800C0000
+#define PVR_7450 0x80000000
+#define PVR_8540 0x80200010
+#define PVR_8560 0x80200010
+
/*
* For the 8xx processors, all of them report the same PVR family for
* the PowerPC core. The various versions of these processors must be
unsigned long bi_flashoffset; /* reserved area for startup monitor */
unsigned long bi_sramstart; /* start of SRAM memory */
unsigned long bi_sramsize; /* size of SRAM memory */
-#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260)
+#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) \
+ || defined(CONFIG_E500)
unsigned long bi_immr_base; /* base of IMMR register */
#endif
#if defined(CONFIG_MPC5XXX)
unsigned short bi_ethspeed; /* Ethernet speed in Mbps */
unsigned long bi_intfreq; /* Internal Freq, in MHz */
unsigned long bi_busfreq; /* Bus Freq, in MHz */
-#if defined(CONFIG_8260)
+#if defined(CONFIG_8260) || defined(CONFIG_MPC8560)
unsigned long bi_cpmfreq; /* CPM_CLK Freq, in MHz */
unsigned long bi_brgfreq; /* BRG_CLK Freq, in MHz */
unsigned long bi_sccfreq; /* SCC_CLK Freq, in MHz */
defined(CONFIG_PN62) || \
defined(CONFIG_PPCHAMELEONEVB) || \
defined(CONFIG_SXNI855T) || \
- defined(CONFIG_SVM_SC8xx)
+ defined(CONFIG_SVM_SC8xx) || \
+ defined(CONFIG_MPC8540ADS) || \
+ defined(CONFIG_MPC8560ADS)
/* second onboard ethernet port */
unsigned char bi_enet1addr[6];
#endif
-#if defined(CFG_GT_6426x) || defined(CONFIG_SVM_SC8xx)
+#if defined(CFG_GT_6426x) || defined(CONFIG_SVM_SC8xx) || \
+ defined(CONFIG_MPC8540ADS) || defined(CONFIG_MPC8560ADS)
/* third onboard ethernet port */
unsigned char bi_enet2addr[6];
#endif
);
-
/*-- High(er) level library functions --*/
#ifndef BZ_NO_STDIO
#elif defined(CONFIG_8260)
#include <asm/immap_8260.h>
#endif
+#ifdef CONFIG_MPC85xx
+#include <mpc85xx.h>
+#include <asm/immap_85xx.h>
+#endif
#ifdef CONFIG_4xx
#include <ppc4xx.h>
#endif
defined(CONFIG_8xx)
uint get_immr (uint);
#endif
+uint get_pir (void);
uint get_pvr (void);
uint rd_ic_cst (void);
void wr_ic_cst (uint);
#endif
ulong get_bus_freq (ulong);
+#if defined(CONFIG_MPC85xx)
+typedef MPC85xx_SYS_INFO sys_info_t;
+void get_sys_info ( sys_info_t * );
+#endif
+
#if defined(CONFIG_4xx) || defined(CONFIG_IOP480)
# if defined(CONFIG_440)
typedef PPC440_SYS_INFO sys_info_t;
#if defined(CONFIG_8xx) || defined(CONFIG_8260)
void cpu_init_f (volatile immap_t *immr);
#endif
-#ifdef CONFIG_4xx
+#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx)
void cpu_init_f (void);
#endif
int cpu_init_r (void);
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-
/* SIU Module Configuration Register */
#define CFG_SIUMCR ( SIUMCR_AEME | SIUMCR_MLRC01 | SIUMCR_DBGC10 )
/* PLPRCR - PLL, Low-Power, and Reset Control Register */
#define CFG_PLPRCR ((( MPC8XX_FACT - 1 ) << PLPRCR_MF_SHIFT ) | \
- PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST )
+ PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST )
/* SCCR - System Clock and reset Control Register */
#define SCCR_MASK SCCR_EBDF11
#endif
/* __CONFIG_H */
-
--- /dev/null
+/*
+ * (C) Copyright 2002,2003 Motorola,Inc.
+ * Xianghua Xiao <X.Xiao@motorola.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* mpc8540ads board configuration file */
+/* please refer to doc/README.mpc85xxads for more info */
+/* make sure you change the MAC address and other network params first,
+ * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE 1 /* BOOKE */
+#define CONFIG_E500 1 /* BOOKE e500 family */
+#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
+#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1 Chip */
+#define CONFIG_MPC8540 1 /* MPC8540 specific */
+#define CONFIG_MPC8540ADS 1 /* MPC8540ADS board specific*/
+
+#undef CONFIG_PCI /* pci ethernet support */
+#define CONFIG_TSEC_ENET /* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
+#undef CONFIG_DDR_ECC /* only for ECC DDR module */
+
+#if defined(CONFIG_MPC85xx_REV1)
+#define CONFIG_DDR_DLL /* possible DLL fix needed */
+#endif
+
+/* Using Localbus SDRAM to emulate flash before we can program the flash,
+ * normally you only need a flash-boot image(u-boot.bin),if unsure undef this.
+ */
+#undef CONFIG_RAM_AS_FLASH
+
+#if !defined(CONFIG_PCI) /* some PCI card is 33Mhz only */
+#define CONFIG_SYS_CLK_FREQ 66000000 /* sysclk for MPC85xx */
+#else
+#define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */
+#endif
+
+#if !defined(CONFIG_SPD_EEPROM) /* manually set up DDR parameters */
+#define CONFIG_DDR_SETTING
+#endif
+
+/* below can be toggled for performance analysis. otherwise use default */
+#define CONFIG_L2_CACHE /* toggle L2 cache */
+#undef CONFIG_BTB /* toggle branch predition */
+#undef CONFIG_ADDR_STREAMING /* toggle addr streaming */
+
+#define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */
+
+#undef CFG_DRAM_TEST /* memory test, takes time */
+#define CFG_MEMTEST_START 0x00200000 /* memtest works on */
+#define CFG_MEMTEST_END 0x00400000
+
+#if defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET)
+#error "You can only use either PCI Ethernet Card or TSEC Ethernet, not both."
+#endif
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
+#define CFG_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */
+#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
+
+#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
+#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
+#define CFG_SDRAM_SIZE 128 /* DDR is now 128MB */
+
+#if defined(CONFIG_RAM_AS_FLASH)
+#define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */
+#else
+#define CFG_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */
+#endif
+#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
+
+#if defined(CONFIG_RAM_AS_FLASH)
+#define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 16M */
+#define CFG_BR0_PRELIM 0xf8001801 /* port size 32bit */
+#else /* Boot from real Flash */
+#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */
+#define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */
+#endif
+
+#define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
+#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
+#define CFG_MAX_FLASH_SECT 64 /* sectors per device */
+#undef CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT 60000 /* Timeout for Flash Erase (in ms)*/
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms)*/
+
+#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#else
+#undef CFG_RAMBOOT
+#endif
+
+#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
+
+#if defined(CONFIG_DDR_SETTING)
+#define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
+#define CFG_DDR_CS0_CONFIG 0x80000002
+#define CFG_DDR_TIMING_1 0x37344321
+#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning*/
+#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR*/
+#define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
+#define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page*/
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+/* local bus definitions */
+#define CFG_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */
+#define CFG_OR2_PRELIM 0xfc006901
+#define CFG_LBC_LCRR 0x00030004 /* local bus freq divider*/
+#define CFG_LBC_LBCR 0x00000000
+#define CFG_LBC_LSRT 0x20000000
+#define CFG_LBC_MRTPR 0x20000000
+#define CFG_LBC_LSDMR_1 0x2861b723
+#define CFG_LBC_LSDMR_2 0x0861b723
+#define CFG_LBC_LSDMR_3 0x0861b723
+#define CFG_LBC_LSDMR_4 0x1861b723
+#define CFG_LBC_LSDMR_5 0x4061b723
+
+#if defined(CONFIG_RAM_AS_FLASH)
+#define CFG_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */
+#else
+#define CFG_BR4_PRELIM 0xfc000801 /* 32KB, 8-bit wide for ADS config reg */
+#endif
+#define CFG_OR4_PRELIM 0xffffe1f1
+#define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000)
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK 1
+#define CFG_INIT_RAM_ADDR 0x40000000 /* Initial RAM address */
+#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX 1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CFG_NS16550
+#define CFG_NS16550_SERIAL
+#define CFG_NS16550_REG_SIZE 1
+#define CFG_NS16550_CLK get_bus_freq(0)
+#define CONFIG_BAUDRATE 115200
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
+#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* I2C */
+#define CONFIG_HARD_I2C /* I2C with hardware support*/
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+
+/* General PCI */
+#define CFG_PCI_MEM_BASE 0xe0000000
+#define CFG_PCI_MEM_PHYS 0xe0000000
+#define CFG_PCI_MEM_SIZE 0x10000000
+#if defined(CONFIG_PCI)
+#define CONFIG_NET_MULTI
+#undef CONFIG_EEPRO100
+#define CONFIG_TULIP
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+ #if !defined(CONFIG_PCI_PNP)
+ #define PCI_ENET0_IOADDR 0xe0000000
+ #define PCI_ENET0_MEMADDR 0xe0000000
+ #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/
+ #endif
+#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
+#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
+#if defined(CONFIG_MPC85xx_REV1) /* Errata PCI 8 */
+ #define CFG_PCI_SUBSYS_DEVICEID 0x0003
+#else
+ #define CFG_PCI_SUBSYS_DEVICEID 0x0008
+#endif
+#elif defined(CONFIG_TSEC_ENET)
+#define CONFIG_NET_MULTI 1
+#define CONFIG_PHY_M88E1011 1 /* GigaBit Ether PHY */
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR 8 /* PHY address */
+#endif
+
+/* Environment */
+#ifndef CFG_RAMBOOT
+ #if defined(CONFIG_RAM_AS_FLASH)
+ #define CFG_ENV_IS_NOWHERE
+ #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x100000)
+ #define CFG_ENV_SIZE 0x2000
+ #else
+ #define CFG_ENV_IS_IN_FLASH 1
+ #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
+ #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
+ #endif
+ #define CFG_ENV_SIZE 0x2000
+#else
+#define CFG_NO_FLASH 1 /* Flash is not usable now */
+#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
+#define CFG_ENV_SIZE 0x2000
+#endif
+
+#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=163.12.64.52:/localhome/r6aads/linuxppc/target ip=10.82.0.105:163.12.64.52:10.82.1.254:255.255.254.0:mpc8540ads-003:eth0:off console=ttyS0,115200"
+/*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/
+#define CONFIG_BOOTCOMMAND "bootm 0xff300000 0xff700000"
+#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
+ #if defined(CONFIG_PCI)
+ #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_PCI | CFG_CMD_I2C ) & \
+ ~(CFG_CMD_ENV | CFG_CMD_LOADS ))
+ #else
+ #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_I2C ) & \
+ ~(CFG_CMD_ENV | \
+ CFG_CMD_LOADS ))
+ #endif
+#else
+ #if defined(CONFIG_PCI)
+ #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_PING | CFG_CMD_I2C )
+ #else
+ #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_I2C )
+ #endif
+#endif
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "MPC8540ADS=> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_LOAD_ADDR 0x1000000 /* default load address */
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE 32768
+#define CFG_CACHELINE_SIZE 32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/* NOTE: change below for your network setting!!! */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_ETHADDR 00:01:af:07:9b:8a
+#define CONFIG_ETH1ADDR 00:01:af:07:9b:8b
+#define CONFIG_ETH2ADDR 00:01:af:07:9b:8c
+#endif
+
+#define CONFIG_SERVERIP 163.12.64.52
+#define CONFIG_IPADDR 10.82.0.105
+#define CONFIG_GATEWAYIP 10.82.1.254
+#define CONFIG_NETMASK 255.255.254.0
+#define CONFIG_HOSTNAME MPC8560ADS_PILOT_003
+#define CONFIG_ROOTPATH /home/r6aads/mpclinux/eldk-2.0.2/ppc_82xx
+#define CONFIG_BOOTFILE pImage
+
+#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * (C) Copyright 2002,2003 Motorola,Inc.
+ * Xianghua Xiao <X.Xiao@motorola.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* mpc8560ads board configuration file */
+/* please refer to doc/README.mpc85xx for more info */
+/* make sure you change the MAC address and other network params first,
+ * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE 1 /* BOOKE */
+#define CONFIG_E500 1 /* BOOKE e500 family */
+#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
+#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */
+#define CONFIG_MPC8560 1 /* MPC8560 specific */
+#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific*/
+
+#undef CONFIG_PCI /* pci ethernet support */
+#define CONFIG_TSEC_ENET /* tsec ethernet support*/
+#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
+#undef CONFIG_DDR_ECC /* only for ECC DDR module */
+
+#if defined(CONFIG_MPC85xx_REV1)
+#define CONFIG_DDR_DLL /* possible DLL fix needed */
+#endif
+
+/* Using Localbus SDRAM to emulate flash before we can program the flash,
+ * normally you need a flash-boot image(u-boot.bin), if so undef this.
+ */
+#undef CONFIG_RAM_AS_FLASH
+
+#if !defined(CONFIG_PCI) /* some PCI card is 33Mhz only */
+#define CONFIG_SYS_CLK_FREQ 66000000/* sysclk for MPC85xx */
+#else
+#define CONFIG_SYS_CLK_FREQ 33000000/* most pci cards are 33Mhz */
+#endif
+
+#if !defined(CONFIG_SPD_EEPROM) /* manually set up DDR parameters */
+#define CONFIG_DDR_SETTING
+#endif
+
+/* below can be toggled for performance analysis. otherwise use default */
+#define CONFIG_L2_CACHE /* toggle L2 cache */
+#undef CONFIG_BTB /* toggle branch predition */
+#undef CONFIG_ADDR_STREAMING /* toggle addr streaming */
+
+#define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */
+
+#undef CFG_DRAM_TEST /* memory test, takes time */
+#define CFG_MEMTEST_START 0x00200000 /* memtest region */
+#define CFG_MEMTEST_END 0x00400000
+
+#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \
+ defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \
+ defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC))
+#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC."
+#endif
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
+#define CFG_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */
+#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
+
+#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
+#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
+#define CFG_SDRAM_SIZE 128 /* DDR is 128MB */
+
+#if defined(CONFIG_RAM_AS_FLASH)
+#define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */
+#else
+#define CFG_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */
+#endif
+#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
+
+#if defined(CONFIG_RAM_AS_FLASH)
+#define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 16M */
+#define CFG_BR0_PRELIM 0xf8001801 /* port size 32bit */
+#else /* Boot from real Flash */
+#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */
+#define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */
+#endif
+
+#define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
+#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
+#define CFG_MAX_FLASH_SECT 64 /* sectors per device */
+#undef CFG_FLASH_CHECKSUM
+#define CFG_FLASH_ERASE_TOUT 60000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#define CFG_RAMBOOT
+#else
+#undef CFG_RAMBOOT
+#endif
+
+#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
+
+#if defined(CONFIG_DDR_SETTING)
+#define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
+#define CFG_DDR_CS0_CONFIG 0x80000002
+#define CFG_DDR_TIMING_1 0x37344321
+#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning*/
+#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR*/
+#define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
+#define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page*/
+#endif
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+/* local bus definitions */
+#define CFG_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */
+#define CFG_OR2_PRELIM 0xfc006901
+#define CFG_LBC_LCRR 0x00030004 /* local bus freq */
+#define CFG_LBC_LBCR 0x00000000
+#define CFG_LBC_LSRT 0x20000000
+#define CFG_LBC_MRTPR 0x20000000
+#define CFG_LBC_LSDMR_1 0x2861b723
+#define CFG_LBC_LSDMR_2 0x0861b723
+#define CFG_LBC_LSDMR_3 0x0861b723
+#define CFG_LBC_LSDMR_4 0x1861b723
+#define CFG_LBC_LSDMR_5 0x4061b723
+
+#if defined(CONFIG_RAM_AS_FLASH)
+#define CFG_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */
+#else
+#define CFG_BR4_PRELIM 0xfc000801 /* 32KB, 8-bit wide for ADS config reg */
+#endif
+#define CFG_OR4_PRELIM 0xffffe1f1
+#define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000)
+
+#define CONFIG_L1_INIT_RAM
+#define CFG_INIT_RAM_LOCK 1
+#define CFG_INIT_RAM_ADDR 0x40000000 /* Initial RAM address */
+#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
+
+#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_ON_SCC /* define if console on SCC */
+#undef CONFIG_CONS_NONE /* define if console on something else */
+#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
+
+#define CONFIG_BAUDRATE 115200
+
+#define CFG_BAUDRATE_TABLE \
+ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+/* Use the HUSH parser */
+#define CFG_HUSH_PARSER
+#ifdef CFG_HUSH_PARSER
+#define CFG_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* I2C */
+#define CONFIG_HARD_I2C /* I2C with hardware support*/
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
+#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+
+#define CFG_PCI_MEM_BASE 0xe0000000
+#define CFG_PCI_MEM_PHYS 0xe0000000
+#define CFG_PCI_MEM_SIZE 0x10000000
+
+#if defined(CONFIG_PCI) /* PCI Ethernet card */
+#define CONFIG_NET_MULTI
+#define CONFIG_EEPRO100
+#undef CONFIG_TULIP
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+ #if !defined(CONFIG_PCI_PNP)
+ #define PCI_ENET0_IOADDR 0xe0000000
+ #define PCI_ENET0_MEMADDR 0xe0000000
+ #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
+ #endif
+#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
+#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
+#if defined(CONFIG_MPC85xx_REV1) /* Errata PCI 7 */
+ #define CFG_PCI_SUBSYS_DEVICEID 0x0003
+#else
+ #define CFG_PCI_SUBSYS_DEVICEID 0x0009
+#endif
+#elif defined(CONFIG_TSEC_ENET) /* TSEC Ethernet port */
+#define CONFIG_NET_MULTI 1
+#define CONFIG_PHY_M88E1011 1 /* GigaBit Ether PHY */
+#define CONFIG_MII 1 /* MII PHY management */
+#define CONFIG_PHY_ADDR 8 /* PHY address */
+#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
+#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
+#undef CONFIG_ETHER_NONE /* define if ether on something else */
+#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
+ #if (CONFIG_ETHER_INDEX == 2)
+ /*
+ * - Rx-CLK is CLK13
+ * - Tx-CLK is CLK14
+ * - Select bus for bd/buffers
+ * - Full duplex
+ */
+ #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+ #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
+ #define CFG_CPMFCR_RAMTYPE 0
+ #define CFG_FCC_PSMR (FCC_PSMR_FDE)
+ #define FETH2_RST 0x01
+ #elif (CONFIG_ETHER_INDEX == 3)
+ /* need more definitions here for FE3 */
+ #define FETH3_RST 0x80
+ #endif /* CONFIG_ETHER_INDEX */
+#define CONFIG_MII /* MII PHY management */
+#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
+/*
+ * GPIO pins used for bit-banged MII communications
+ */
+#define MDIO_PORT 2 /* Port C */
+#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
+#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
+#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
+
+#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
+ else iop->pdat &= ~0x00400000
+
+#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
+ else iop->pdat &= ~0x00200000
+
+#define MIIDELAY udelay(1)
+#endif
+
+/* Environment */
+#ifndef CFG_RAMBOOT
+ #if defined(CONFIG_RAM_AS_FLASH)
+ #define CFG_ENV_IS_NOWHERE
+ #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x100000)
+ #define CFG_ENV_SIZE 0x2000
+ #else
+ #define CFG_ENV_IS_IN_FLASH 1
+ #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
+ #define CFG_ENV_SECT_SIZE 0x40000 /* 128K(one sector) for env */
+ #endif
+ #define CFG_ENV_SIZE 0x2000
+#else
+#define CFG_NO_FLASH 1 /* Flash is not usable now */
+#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
+#define CFG_ENV_SIZE 0x2000
+#endif
+
+#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=163.12.64.52:/localhome/r6aads/linuxppc/target ip=10.82.0.105:163.12.64.52:10.82.1.254:255.255.254.0:mpc8560ads-003:eth0:off console=ttyS0,115200"
+/*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/
+#define CONFIG_BOOTCOMMAND "bootm 0xff400000 0xff700000"
+#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+
+#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
+ #if defined(CONFIG_PCI)
+ #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI | \
+ CFG_CMD_PING | CFG_CMD_I2C) & \
+ ~(CFG_CMD_ENV | \
+ CFG_CMD_LOADS ))
+ #elif defined(CONFIG_TSEC_ENET)
+ #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING | \
+ CFG_CMD_I2C ) & \
+ ~(CFG_CMD_ENV))
+ #elif defined(CONFIG_ETHER_ON_FCC)
+ #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_MII | \
+ CFG_CMD_PING | CFG_CMD_I2C) & \
+ ~(CFG_CMD_ENV))
+ #endif
+#else
+ #if defined(CONFIG_PCI)
+ #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | \
+ CFG_CMD_PING | CFG_CMD_I2C)
+ #elif defined(CONFIG_TSEC_ENET)
+ #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING | \
+ CFG_CMD_I2C)
+ #elif defined(CONFIG_ETHER_ON_FCC)
+ #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MII | \
+ CFG_CMD_PING | CFG_CMD_I2C)
+ #endif
+#endif
+#include <cmd_confdefs.h>
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "MPC8560ADS=> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CFG_LOAD_ADDR 0x1000000 /* default load address */
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/* Cache Configuration */
+#define CFG_DCACHE_SIZE 32768
+#define CFG_CACHELINE_SIZE 32
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
+#endif
+
+/*Note: change below for your network setting!!! */
+#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
+#define CONFIG_ETHADDR 00:01:af:07:9b:8a
+#define CONFIG_ETH1ADDR 00:01:af:07:9b:8b
+#define CONFIG_ETH2ADDR 00:01:af:07:9b:8c
+#endif
+
+#define CONFIG_SERVERIP 163.12.64.52
+#define CONFIG_IPADDR 10.82.0.105
+#define CONFIG_GATEWAYIP 10.82.1.254
+#define CONFIG_NETMASK 255.255.254.0
+#define CONFIG_HOSTNAME MPC8560ADS_PILOT_003
+#define CONFIG_ROOTPATH /home/r6aads/mpclinux/eldk-2.0.2/ppc_82xx
+#define CONFIG_BOOTFILE pImage
+
+#endif /* __CONFIG_H */
#define CFG_BR5_ISP1362 ((CFG_ISP1362_BASE & BR_BA_MSK) | \
BR_PS_16 | BR_MS_GPCM | BR_V )
#endif /* CONFIG_ISP1362_USB */
-
+
/*
* Memory Periodic Timer Prescaler
*
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_PPCHAMELEON_MODULE_BA 0 /* Basic Model */
+#define CONFIG_PPCHAMELEON_MODULE_BA 0 /* Basic Model */
#define CONFIG_PPCHAMELEON_MODULE_ME 1 /* Medium Model */
#define CONFIG_PPCHAMELEON_MODULE_HI 2 /* High-End Model */
#ifndef CONFIG_PPCHAMELEON_MODULE_MODEL
/* The following table includes the supported baudrates */
#define CFG_BAUDRATE_TABLE \
- { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
- 57600, 115200, 230400, 460800, 921600 }
+ { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
+ 57600, 115200, 230400, 460800, 921600 }
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define NAND_DISABLE_CE(nand) do \
{ \
switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
- { \
- case CFG_NAND0_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \
- break; \
- case CFG_NAND1_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CE); \
- break; \
- } \
+ { \
+ case CFG_NAND0_BASE: \
+ out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \
+ break; \
+ case CFG_NAND1_BASE: \
+ out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CE); \
+ break; \
+ } \
} while(0)
#define NAND_ENABLE_CE(nand) do \
{ \
switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
- { \
- case CFG_NAND0_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \
- break; \
- case CFG_NAND1_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CE); \
- break; \
- } \
+ { \
+ case CFG_NAND0_BASE: \
+ out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \
+ break; \
+ case CFG_NAND1_BASE: \
+ out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CE); \
+ break; \
+ } \
} while(0)
-
#define NAND_CTL_CLRALE(nandptr) do \
{ \
switch((unsigned long)nandptr) \
- { \
- case CFG_NAND0_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_ALE); \
- break; \
- case CFG_NAND1_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_ALE); \
- break; \
- } \
+ { \
+ case CFG_NAND0_BASE: \
+ out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_ALE); \
+ break; \
+ case CFG_NAND1_BASE: \
+ out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_ALE); \
+ break; \
+ } \
} while(0)
#define NAND_CTL_SETALE(nandptr) do \
{ \
switch((unsigned long)nandptr) \
- { \
- case CFG_NAND0_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_ALE); \
- break; \
- case CFG_NAND1_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_ALE); \
- break; \
- } \
+ { \
+ case CFG_NAND0_BASE: \
+ out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_ALE); \
+ break; \
+ case CFG_NAND1_BASE: \
+ out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_ALE); \
+ break; \
+ } \
} while(0)
#define NAND_CTL_CLRCLE(nandptr) do \
{ \
switch((unsigned long)nandptr) \
- { \
- case CFG_NAND0_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CLE); \
- break; \
- case CFG_NAND1_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CLE); \
- break; \
- } \
+ { \
+ case CFG_NAND0_BASE: \
+ out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CLE); \
+ break; \
+ case CFG_NAND1_BASE: \
+ out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CLE); \
+ break; \
+ } \
} while(0)
#define NAND_CTL_SETCLE(nandptr) do { \
switch((unsigned long)nandptr) { \
- case CFG_NAND0_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \
- break; \
- case CFG_NAND1_BASE: \
- out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CLE); \
- break; \
- } \
+ case CFG_NAND0_BASE: \
+ out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \
+ break; \
+ case CFG_NAND1_BASE: \
+ out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CLE); \
+ break; \
+ } \
} while(0)
#ifdef NAND_NO_RB
#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
#undef CONFIG_PCI_PNP /* do pci plug-and-play */
- /* resource configuration */
+ /* resource configuration */
#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
#define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
#define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
- /* total size of a CAT24WC16 is 2048 bytes */
+ /* total size of a CAT24WC16 is 2048 bytes */
#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
#define CFG_NVRAM_SIZE 242 /* NVRAM size */
* Cache Configuration
*/
#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
- /* have only 8kB, 16kB is save here */
+ /* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
!-----------------------------------------------------------------------
*/
#define PLLMR0_133_66_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
- PLL_MALDIV_1 | PLL_PCIDIV_4)
+ PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
+ PLL_MALDIV_1 | PLL_PCIDIV_4)
#define PLLMR1_133_66_66_33 (PLL_FBKDIV_4 | \
- PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+ PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
+ PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
#define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
- PLL_MALDIV_1 | PLL_PCIDIV_4)
+ PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
+ PLL_MALDIV_1 | PLL_PCIDIV_4)
#define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
- PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+ PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
+ PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
#define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
- PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
- PLL_MALDIV_1 | PLL_PCIDIV_4)
+ PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
+ PLL_MALDIV_1 | PLL_PCIDIV_4)
#define PLLMR1_266_133_66_33 (PLL_FBKDIV_8 | \
- PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
- PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+ PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
+ PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
#if 0 /* test-only */
#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
* 1 CSR 0 Checkstop reset enable
* 1 LOLRE 0 Loss-of-lock reset enable
* 1 FIOPD 0 Force I/O pull down
- * 5 0 00000
+ * 5 0 00000
*/
#define CFG_PLPRCR (PLPRCR_TEXPS | ((CFG_MF-1)<<20))
* 1 SEME 0 Sync external master enable
* 1 BSC 0 Byte strobe configuration
* 1 GB5E 0 GPL_B5 enable
- * 1 B2DD 0 Bank 2 double drive
- * 1 B3DD 0 Bank 3 double drive
+ * 1 B2DD 0 Bank 2 double drive
+ * 1 B3DD 0 Bank 3 double drive
* 4 0 0000
*/
#define CFG_SIUMCR (SIUMCR_MLRC11)
#define CONFIG_BOOTP_MASK ( CONFIG_BOOTP_DEFAULT | \
CONFIG_BOOTP_BOOTFILESIZE \
)
-
+
/*
* Set default IP stuff just to get bootstrap entries into the
#define CONFIG_SERVERIP 192.168.0.250
#define CONFIG_BOOTCOMMAND "bootm 50040000"
#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
-#define CONFIG_CMDLINE_TAG
+#define CONFIG_CMDLINE_TAG
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CFG_LOAD_ADDR 0x00010000 /* default load address */
#define CFG_HZ 3333333 /* spec says 66.666 MHz, but it appears to be 33 */
- /* valid baudrates */
+ /* valid baudrates */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*
#define WDTIM_CONTROL_ST BIT7
-
/* ---------------------------------------------------------------------------
* Differentiating processor versions for those who care.
* ---------------------------------------------------------------------------
#define CFG_NS16550_SERIAL
#define CFG_NS16550_REG_SIZE (-4)
#define CFG_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */
-#define CFG_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart
+#define CFG_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart
on helen */
/*
#define CFG_LOAD_ADDR 0x10000000 /* default load address */
-/* The 1610 has 6 timers, they can be driven by the RefClk (12Mhz) or by
+/* The 1610 has 6 timers, they can be driven by the RefClk (12Mhz) or by
* DPLL1. This time is further subdivided by a local divisor.
*/
#define CFG_TIMERBASE 0xFFFEC500 /* use timer 1 */
/* Add support for a few extra bootp options like:
* - File size
* - DNS (up to 2 servers)
- * - Send hostname to DHCP server
+ * - Send hostname to DHCP server
*/
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
CONFIG_BOOTP_BOOTFILESIZE | \
CONFIG_BOOTP_DNS | \
- CONFIG_BOOTP_DNS2 | \
- CONFIG_BOOTP_SEND_HOSTNAME)
+ CONFIG_BOOTP_DNS2 | \
+ CONFIG_BOOTP_SEND_HOSTNAME)
/* undef this to save memory */
#define CFG_LONGHELP
*/
#define CONFIG_TIMESTAMP
-/* If this variable is defined, an environment variable named "ver"
+/* If this variable is defined, an environment variable named "ver"
* is created by U-Boot showing the U-Boot version.
*/
#define CONFIG_VERSION_VARIABLE
* Miscellaneous configurable options
*/
#define CFG_BOOTM_HEADER_QUIET 1 /* Suppress the image header dump */
- /* in the bootm command. */
+ /* in the bootm command. */
#define CFG_BOOTM_PROGESS_QUIET 1 /* Suppress the progress displays, */
- /* "## <message>" from the bootm cmd */
+ /* "## <message>" from the bootm cmd */
#define CFG_BOOTP_CHECK_HOSTNAME 1 /* If checkhostname environment is */
- /* defined, then the hostname param */
- /* validated against checkhostname. */
+ /* defined, then the hostname param */
+ /* validated against checkhostname. */
#define CFG_BOOTP_RETRY_COUNT 0x40000000 /* # of timeouts before giving up */
#define CFG_BOOTP_SHORT_RANDOM_DELAY 1 /* Use a short random delay value */
- /* (limited to maximum of 1024 msec) */
+ /* (limited to maximum of 1024 msec) */
#define CFG_CHK_FOR_ABORT_AT_LEAST_ONCE 1
- /* Check for abort key presses */
- /* at least once in dependent of the */
- /* CONFIG_BOOTDELAY value. */
+ /* Check for abort key presses */
+ /* at least once in dependent of the */
+ /* CONFIG_BOOTDELAY value. */
#define CFG_CONSOLE_INFO_QUIET 1 /* Don't print console @ startup */
#define CFG_FAULT_ECHO_LINK_DOWN 1 /* Echo the inverted Ethernet link */
- /* state to the fault LED. */
+ /* state to the fault LED. */
#define CFG_FAULT_MII_ADDR 0x02 /* MII addr of the PHY to check for */
- /* the Ethernet link state. */
+ /* the Ethernet link state. */
#define CFG_STATUS_FLASH_UNTIL_TFTP_OK 1 /* Keeping the status LED flashing */
- /* until the TFTP is successful. */
+ /* until the TFTP is successful. */
#define CFG_STATUS_OFF_AFTER_NETBOOT 1 /* After a successful netboot, */
- /* turn off the STATUS LEDs. */
+ /* turn off the STATUS LEDs. */
#define CFG_TFTP_BLINK_STATUS_ON_DATA_IN 1 /* Blink status LED based on */
- /* incoming data. */
+ /* incoming data. */
#define CFG_TFTP_BLOCKS_PER_HASH 100 /* For every XX blocks, output a '#' */
- /* to signify that tftp is moving. */
+ /* to signify that tftp is moving. */
#define CFG_TFTP_HASHES_PER_FLASH 200 /* For every '#' hashes, */
- /* flash the status LED. */
+ /* flash the status LED. */
#define CFG_TFTP_HASHES_PER_LINE 65 /* Only output XX '#'s per line */
- /* during the tftp file transfer. */
+ /* during the tftp file transfer. */
#define CFG_TFTP_PROGESS_QUIET 1 /* Suppress the progress displays */
- /* '#'s from the tftp command. */
+ /* '#'s from the tftp command. */
#define CFG_TFTP_STATUS_QUIET 1 /* Suppress the status displays */
- /* issued during the tftp command. */
+ /* issued during the tftp command. */
#define CFG_TFTP_TIMEOUT_COUNT 5 /* How many timeouts TFTP will allow */
/* before it gives up. */
SYPCR_LBME |\
SYPCR_SWRI |\
SYPCR_SWP |\
- SYPCR_SWE)
+ SYPCR_SWE)
#else
#define CFG_SYPCR (SYPCR_SWTC |\
SYPCR_BMT |\
/*-----------------------------------------------------------------------
* burn-in test stuff.
- *
+ *
* BURN_IN_CYCLE_DELAY defines the seconds to wait between each burn-in cycle
* Because the burn-in test itself causes also an delay of about 4 seconds,
* this time must be subtracted from the desired overall burn-in cycle time.
--- /dev/null
+/*
+ * Copyright 2003 Motorola,Inc.
+ * Xianghua Xiao(x.xiao@motorola.com)
+ */
+
+#ifndef __E500_H__
+#define __E500_H__
+
+#ifndef __ASSEMBLY__
+
+typedef struct
+{
+ unsigned long freqProcessor;
+ unsigned long freqSystemBus;
+} MPC85xx_SYS_INFO;
+
+#endif /* _ASMLANGUAGE */
+
+/* Motorola E500 core provides 16 TLB1 entries; they can be used for
+ * initial memory mapping like legacy BAT registers do. Usually we
+ * use four MAS registers(MAS0-3) to operate on TLB1 entries.
+ *
+ * We also need LAWs(Local Access Window) to associate a range of
+ * the local 32-bit address space with a particular target interface
+ * such as PCI/PCI-X, RapidIO, Local Bus and DDR SDRAM.
+ *
+ * We put TLB1/LAW code here because memory mapping is board-specific
+ * instead of cpu-specific.
+ */
+
+/* MAS0
+ * tlbsel(TLB Select):0,1
+ * esel(Entry Select): 0,1,2,...,15 for TLB1
+ * nv(Next victim):0,1
+ */
+#define TLB1_MAS0(tlbsel,esel,nv) \
+ ((((tlbsel) << 28) & MAS0_TLBSEL) |\
+ (((esel) << 16) & MAS0_ESEL ) |\
+ (nv) )
+
+
+/* MAS1
+ * v(TLB valid bit):0,1
+ * iprot(invalidate protect):0,1
+ * tid(translation identity):8bit to match process IDs
+ * ts(translation space,comparing with MSR[IS,DS]): 0,1
+ * tsize(translation size):1,2,...,9(4K,16K,64K,256K,1M,4M,16M,64M,256M)
+ */
+#define TLB1_MAS1(v,iprot,tid,ts,tsize) \
+ ((((v) << 31) & MAS1_VALID) |\
+ (((iprot) << 30) & MAS1_IPROT) |\
+ (((tid) << 16) & MAS1_TID) |\
+ (((ts) << 12) & MAS1_TS) |\
+ (((tsize) << 8) & MAS1_TSIZE) )
+
+
+/* MAS2
+ * epn(effective page number):20bits
+ * sharen(Shared cache state):0,1
+ * x0,x1(implementation specific page attribute):0,1
+ * w,i,m,g,e(write-through,cache-inhibited,memory coherency,guarded,
+ * endianness):0,1
+ */
+#define TLB1_MAS2(epn,sharen,x0,x1,w,i,m,g,e) \
+ ((((epn) << 12) & MAS2_EPN) |\
+ (((sharen) << 9) & MAS2_SHAREN) |\
+ (((x0) << 6) & MAS2_X0) |\
+ (((x1) << 5) & MAS2_X1) |\
+ (((w) << 4) & MAS2_W) |\
+ (((i) << 3) & MAS2_I) |\
+ (((m) << 2) & MAS2_M) |\
+ (((g) << 1) & MAS2_G) |\
+ (e) )
+
+
+/* MAS3
+ * rpn(real page number):20bits
+ * u0-u3(user bits, useful for page table management in OS):0,1
+ * ux,sx,uw,sw,ur,sr(permission bits, user and supervisor read,
+ * write,execute permission).
+ */
+#define TLB1_MAS3(rpn,u0,u1,u2,u3,ux,sx,uw,sw,ur,sr) \
+ ((((rpn) << 12) & MAS3_RPN) |\
+ (((u0) << 9) & MAS3_U0) |\
+ (((u1) << 8) & MAS3_U1) |\
+ (((u2) << 7) & MAS3_U2) |\
+ (((u3) << 6) & MAS3_U3) |\
+ (((ux) << 5) & MAS3_UX) |\
+ (((sx) << 4) & MAS3_SX) |\
+ (((uw) << 3) & MAS3_UW) |\
+ (((sw) << 2) & MAS3_SW) |\
+ (((ur) << 1) & MAS3_UR) |\
+ (sr) )
+
+
+#define RESET_VECTOR 0xfffffffc
+#define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for cache
+ line aligned data. */
+
+#endif /* __E500_H__ */
* the internal memory map aligns the above structure on
* a 0x20 byte boundary
*/
+#ifdef CONFIG_MPC8560
+#define ioport_addr(im, idx) (ioport_t *)((uint)&((im)->im_cpm.im_cpm_iop) + ((idx)*0x20))
+#else
#define ioport_addr(im, idx) (ioport_t *)((uint)&(im)->im_ioport + ((idx)*0x20))
+#endif
/*
* this structure provides configuration
--- /dev/null
+/*
+ * Copyright(c) 2003 Motorola Inc.
+ * Xianghua Xiao (x.xiao@motorola.com)
+ */
+
+#ifndef __MPC85xx_H__
+#define __MPC85xx_H__
+
+#define EXC_OFF_SYS_RESET 0x0100 /* System reset */
+
+#if defined(CONFIG_E500)
+#include <e500.h>
+#endif
+
+#if defined(CONFIG_DDR_ECC)
+void dma_init(void);
+uint dma_check(void);
+int dma_xfer(void *dest, uint count, void *src);
+#endif
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control Register 9-8
+ */
+#define SCCR_CLPD 0x00000004 /* CPM Low Power Disable */
+#define SCCR_DFBRG_MSK 0x00000003 /* Division factor of BRGCLK Mask */
+#define SCCR_DFBRG_SHIFT 0
+
+#define SCCR_DFBRG00 0x00000000 /* BRGCLK division by 4 */
+#define SCCR_DFBRG01 0x00000001 /* BRGCLK division by 16 (normal op.)*/
+#define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */
+#define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 256 */
+
+#endif /* __MPC85xx_H__ */
# endif
#endif /* CONFIG_MPC5XXX */
-#if !defined(CONFIG_NET_MULTI) && defined(CONFIG_8260)
+#if !defined(CONFIG_NET_MULTI) && (defined(CONFIG_8260) || defined(CONFIG_MPC8560))
#include <config.h>
#if defined(CONFIG_ETHER_ON_FCC)
#if defined(CONFIG_ETHER_ON_SCC)
#define NIOS_TIMER_STOP (1 << 3) /* Stop timer */
#endif /* __NIOSIO_H__ */
-
#define PCI_DEVICE_ID_MOTOROLA_HAWK 0x4803
#define PCI_DEVICE_ID_MOTOROLA_CPX8216 0x4806
#define PCI_DEVICE_ID_MOTOROLA_MPC190 0x6400
+#define PCI_DEVICE_ID_MOTOROLA_MPC8265A 0x18c0
+#define PCI_DEVICE_ID_MOTOROLA_MPC8540 0x0008
+#define PCI_DEVICE_ID_MOTOROLA_MPC8560 0x0009
#define PCI_VENDOR_ID_PROMISE 0x105a
#define PCI_DEVICE_ID_PROMISE_20265 0x0d30
* fixed bzWrite/bzRead to ignore zero-length requests.
* fixed bzread to correctly handle read requests after EOF.
* wrong parameter order in call to bzDecompressInit in
- bzBuffToBuffDecompress. Fixed.
+ bzBuffToBuffDecompress. Fixed.
--*/
#include "bzlib_private.h"
/*---------------------------------------------------*/
int BZ_API(BZ2_bzCompressInit)
- ( bz_stream* strm,
- int blockSize100k,
- int verbosity,
- int workFactor )
+ ( bz_stream* strm,
+ int blockSize100k,
+ int verbosity,
+ int workFactor )
{
Int32 n;
EState* s;
s->inUse[s->state_in_ch] = True;
switch (s->state_in_len) {
case 1:
- s->block[s->nblock] = (UChar)ch; s->nblock++;
- break;
+ s->block[s->nblock] = (UChar)ch; s->nblock++;
+ break;
case 2:
- s->block[s->nblock] = (UChar)ch; s->nblock++;
- s->block[s->nblock] = (UChar)ch; s->nblock++;
- break;
+ s->block[s->nblock] = (UChar)ch; s->nblock++;
+ s->block[s->nblock] = (UChar)ch; s->nblock++;
+ break;
case 3:
- s->block[s->nblock] = (UChar)ch; s->nblock++;
- s->block[s->nblock] = (UChar)ch; s->nblock++;
- s->block[s->nblock] = (UChar)ch; s->nblock++;
- break;
+ s->block[s->nblock] = (UChar)ch; s->nblock++;
+ s->block[s->nblock] = (UChar)ch; s->nblock++;
+ s->block[s->nblock] = (UChar)ch; s->nblock++;
+ break;
default:
- s->inUse[s->state_in_len-4] = True;
- s->block[s->nblock] = (UChar)ch; s->nblock++;
- s->block[s->nblock] = (UChar)ch; s->nblock++;
- s->block[s->nblock] = (UChar)ch; s->nblock++;
- s->block[s->nblock] = (UChar)ch; s->nblock++;
- s->block[s->nblock] = ((UChar)(s->state_in_len-4));
- s->nblock++;
- break;
+ s->inUse[s->state_in_len-4] = True;
+ s->block[s->nblock] = (UChar)ch; s->nblock++;
+ s->block[s->nblock] = (UChar)ch; s->nblock++;
+ s->block[s->nblock] = (UChar)ch; s->nblock++;
+ s->block[s->nblock] = (UChar)ch; s->nblock++;
+ s->block[s->nblock] = ((UChar)(s->state_in_len-4));
+ s->nblock++;
+ break;
}
}
if (zchh != zs->state_in_ch || \
zs->state_in_len == 255) { \
if (zs->state_in_ch < 256) \
- add_pair_to_block ( zs ); \
+ add_pair_to_block ( zs ); \
zs->state_in_ch = zchh; \
zs->state_in_len = 1; \
} else { \
/*-- fast track the common case --*/
while (True) {
- /*-- block full? --*/
- if (s->nblock >= s->nblockMAX) break;
- /*-- no input? --*/
- if (s->strm->avail_in == 0) break;
- progress_in = True;
- ADD_CHAR_TO_BLOCK ( s, (UInt32)(*((UChar*)(s->strm->next_in))) );
- s->strm->next_in++;
- s->strm->avail_in--;
- s->strm->total_in_lo32++;
- if (s->strm->total_in_lo32 == 0) s->strm->total_in_hi32++;
+ /*-- block full? --*/
+ if (s->nblock >= s->nblockMAX) break;
+ /*-- no input? --*/
+ if (s->strm->avail_in == 0) break;
+ progress_in = True;
+ ADD_CHAR_TO_BLOCK ( s, (UInt32)(*((UChar*)(s->strm->next_in))) );
+ s->strm->next_in++;
+ s->strm->avail_in--;
+ s->strm->total_in_lo32++;
+ if (s->strm->total_in_lo32 == 0) s->strm->total_in_hi32++;
}
} else {
/*-- general, uncommon case --*/
while (True) {
- /*-- block full? --*/
- if (s->nblock >= s->nblockMAX) break;
- /*-- no input? --*/
- if (s->strm->avail_in == 0) break;
- /*-- flush/finish end? --*/
- if (s->avail_in_expect == 0) break;
- progress_in = True;
- ADD_CHAR_TO_BLOCK ( s, (UInt32)(*((UChar*)(s->strm->next_in))) );
- s->strm->next_in++;
- s->strm->avail_in--;
- s->strm->total_in_lo32++;
- if (s->strm->total_in_lo32 == 0) s->strm->total_in_hi32++;
- s->avail_in_expect--;
+ /*-- block full? --*/
+ if (s->nblock >= s->nblockMAX) break;
+ /*-- no input? --*/
+ if (s->strm->avail_in == 0) break;
+ /*-- flush/finish end? --*/
+ if (s->avail_in_expect == 0) break;
+ progress_in = True;
+ ADD_CHAR_TO_BLOCK ( s, (UInt32)(*((UChar*)(s->strm->next_in))) );
+ s->strm->next_in++;
+ s->strm->avail_in--;
+ s->strm->total_in_lo32++;
+ if (s->strm->total_in_lo32 == 0) s->strm->total_in_hi32++;
+ s->avail_in_expect--;
}
}
return progress_in;
while (True) {
if (s->state == BZ_S_OUTPUT) {
- progress_out |= copy_output_until_stop ( s );
- if (s->state_out_pos < s->numZ) break;
- if (s->mode == BZ_M_FINISHING &&
- s->avail_in_expect == 0 &&
- isempty_RL(s)) break;
- prepare_new_block ( s );
- s->state = BZ_S_INPUT;
- if (s->mode == BZ_M_FLUSHING &&
- s->avail_in_expect == 0 &&
- isempty_RL(s)) break;
+ progress_out |= copy_output_until_stop ( s );
+ if (s->state_out_pos < s->numZ) break;
+ if (s->mode == BZ_M_FINISHING &&
+ s->avail_in_expect == 0 &&
+ isempty_RL(s)) break;
+ prepare_new_block ( s );
+ s->state = BZ_S_INPUT;
+ if (s->mode == BZ_M_FLUSHING &&
+ s->avail_in_expect == 0 &&
+ isempty_RL(s)) break;
}
if (s->state == BZ_S_INPUT) {
- progress_in |= copy_input_until_stop ( s );
- if (s->mode != BZ_M_RUNNING && s->avail_in_expect == 0) {
- flush_RL ( s );
- BZ2_compressBlock ( s, (Bool)(s->mode == BZ_M_FINISHING) );
- s->state = BZ_S_OUTPUT;
- }
- else
- if (s->nblock >= s->nblockMAX) {
- BZ2_compressBlock ( s, False );
- s->state = BZ_S_OUTPUT;
- }
- else
- if (s->strm->avail_in == 0) {
- break;
- }
+ progress_in |= copy_input_until_stop ( s );
+ if (s->mode != BZ_M_RUNNING && s->avail_in_expect == 0) {
+ flush_RL ( s );
+ BZ2_compressBlock ( s, (Bool)(s->mode == BZ_M_FINISHING) );
+ s->state = BZ_S_OUTPUT;
+ }
+ else
+ if (s->nblock >= s->nblockMAX) {
+ BZ2_compressBlock ( s, False );
+ s->state = BZ_S_OUTPUT;
+ }
+ else
+ if (s->strm->avail_in == 0) {
+ break;
+ }
}
}
switch (s->mode) {
case BZ_M_IDLE:
- return BZ_SEQUENCE_ERROR;
+ return BZ_SEQUENCE_ERROR;
case BZ_M_RUNNING:
- if (action == BZ_RUN) {
- progress = handle_compress ( strm );
- return progress ? BZ_RUN_OK : BZ_PARAM_ERROR;
- }
- else
+ if (action == BZ_RUN) {
+ progress = handle_compress ( strm );
+ return progress ? BZ_RUN_OK : BZ_PARAM_ERROR;
+ }
+ else
if (action == BZ_FLUSH) {
- s->avail_in_expect = strm->avail_in;
- s->mode = BZ_M_FLUSHING;
- goto preswitch;
- }
- else
- if (action == BZ_FINISH) {
- s->avail_in_expect = strm->avail_in;
- s->mode = BZ_M_FINISHING;
- goto preswitch;
- }
- else
- return BZ_PARAM_ERROR;
+ s->avail_in_expect = strm->avail_in;
+ s->mode = BZ_M_FLUSHING;
+ goto preswitch;
+ }
+ else
+ if (action == BZ_FINISH) {
+ s->avail_in_expect = strm->avail_in;
+ s->mode = BZ_M_FINISHING;
+ goto preswitch;
+ }
+ else
+ return BZ_PARAM_ERROR;
case BZ_M_FLUSHING:
- if (action != BZ_FLUSH) return BZ_SEQUENCE_ERROR;
- if (s->avail_in_expect != s->strm->avail_in)
- return BZ_SEQUENCE_ERROR;
- progress = handle_compress ( strm );
- if (s->avail_in_expect > 0 || !isempty_RL(s) ||
- s->state_out_pos < s->numZ) return BZ_FLUSH_OK;
- s->mode = BZ_M_RUNNING;
- return BZ_RUN_OK;
+ if (action != BZ_FLUSH) return BZ_SEQUENCE_ERROR;
+ if (s->avail_in_expect != s->strm->avail_in)
+ return BZ_SEQUENCE_ERROR;
+ progress = handle_compress ( strm );
+ if (s->avail_in_expect > 0 || !isempty_RL(s) ||
+ s->state_out_pos < s->numZ) return BZ_FLUSH_OK;
+ s->mode = BZ_M_RUNNING;
+ return BZ_RUN_OK;
case BZ_M_FINISHING:
- if (action != BZ_FINISH) return BZ_SEQUENCE_ERROR;
- if (s->avail_in_expect != s->strm->avail_in)
- return BZ_SEQUENCE_ERROR;
- progress = handle_compress ( strm );
- if (!progress) return BZ_SEQUENCE_ERROR;
- if (s->avail_in_expect > 0 || !isempty_RL(s) ||
- s->state_out_pos < s->numZ) return BZ_FINISH_OK;
- s->mode = BZ_M_IDLE;
- return BZ_STREAM_END;
+ if (action != BZ_FINISH) return BZ_SEQUENCE_ERROR;
+ if (s->avail_in_expect != s->strm->avail_in)
+ return BZ_SEQUENCE_ERROR;
+ progress = handle_compress ( strm );
+ if (!progress) return BZ_SEQUENCE_ERROR;
+ if (s->avail_in_expect > 0 || !isempty_RL(s) ||
+ s->state_out_pos < s->numZ) return BZ_FINISH_OK;
+ s->mode = BZ_M_IDLE;
+ return BZ_STREAM_END;
}
return BZ_OK; /*--not reached--*/
}
/*---------------------------------------------------*/
int BZ_API(BZ2_bzDecompressInit)
- ( bz_stream* strm,
- int verbosity,
- int small )
+ ( bz_stream* strm,
+ int verbosity,
+ int small )
{
DState* s;
if (s->blockRandomised) {
while (True) {
- /* try to finish existing run */
- while (True) {
- if (s->strm->avail_out == 0) return;
- if (s->state_out_len == 0) break;
- *( (UChar*)(s->strm->next_out) ) = s->state_out_ch;
- BZ_UPDATE_CRC ( s->calculatedBlockCRC, s->state_out_ch );
- s->state_out_len--;
- s->strm->next_out++;
- s->strm->avail_out--;
- s->strm->total_out_lo32++;
- if (s->strm->total_out_lo32 == 0) s->strm->total_out_hi32++;
- }
-
- /* can a new run be started? */
- if (s->nblock_used == s->save_nblock+1) return;
-
-
- s->state_out_len = 1;
- s->state_out_ch = s->k0;
- BZ_GET_FAST(k1); BZ_RAND_UPD_MASK;
- k1 ^= BZ_RAND_MASK; s->nblock_used++;
- if (s->nblock_used == s->save_nblock+1) continue;
- if (k1 != s->k0) { s->k0 = k1; continue; };
-
- s->state_out_len = 2;
- BZ_GET_FAST(k1); BZ_RAND_UPD_MASK;
- k1 ^= BZ_RAND_MASK; s->nblock_used++;
- if (s->nblock_used == s->save_nblock+1) continue;
- if (k1 != s->k0) { s->k0 = k1; continue; };
-
- s->state_out_len = 3;
- BZ_GET_FAST(k1); BZ_RAND_UPD_MASK;
- k1 ^= BZ_RAND_MASK; s->nblock_used++;
- if (s->nblock_used == s->save_nblock+1) continue;
- if (k1 != s->k0) { s->k0 = k1; continue; };
-
- BZ_GET_FAST(k1); BZ_RAND_UPD_MASK;
- k1 ^= BZ_RAND_MASK; s->nblock_used++;
- s->state_out_len = ((Int32)k1) + 4;
- BZ_GET_FAST(s->k0); BZ_RAND_UPD_MASK;
- s->k0 ^= BZ_RAND_MASK; s->nblock_used++;
+ /* try to finish existing run */
+ while (True) {
+ if (s->strm->avail_out == 0) return;
+ if (s->state_out_len == 0) break;
+ *( (UChar*)(s->strm->next_out) ) = s->state_out_ch;
+ BZ_UPDATE_CRC ( s->calculatedBlockCRC, s->state_out_ch );
+ s->state_out_len--;
+ s->strm->next_out++;
+ s->strm->avail_out--;
+ s->strm->total_out_lo32++;
+ if (s->strm->total_out_lo32 == 0) s->strm->total_out_hi32++;
+ }
+
+ /* can a new run be started? */
+ if (s->nblock_used == s->save_nblock+1) return;
+
+
+ s->state_out_len = 1;
+ s->state_out_ch = s->k0;
+ BZ_GET_FAST(k1); BZ_RAND_UPD_MASK;
+ k1 ^= BZ_RAND_MASK; s->nblock_used++;
+ if (s->nblock_used == s->save_nblock+1) continue;
+ if (k1 != s->k0) { s->k0 = k1; continue; };
+
+ s->state_out_len = 2;
+ BZ_GET_FAST(k1); BZ_RAND_UPD_MASK;
+ k1 ^= BZ_RAND_MASK; s->nblock_used++;
+ if (s->nblock_used == s->save_nblock+1) continue;
+ if (k1 != s->k0) { s->k0 = k1; continue; };
+
+ s->state_out_len = 3;
+ BZ_GET_FAST(k1); BZ_RAND_UPD_MASK;
+ k1 ^= BZ_RAND_MASK; s->nblock_used++;
+ if (s->nblock_used == s->save_nblock+1) continue;
+ if (k1 != s->k0) { s->k0 = k1; continue; };
+
+ BZ_GET_FAST(k1); BZ_RAND_UPD_MASK;
+ k1 ^= BZ_RAND_MASK; s->nblock_used++;
+ s->state_out_len = ((Int32)k1) + 4;
+ BZ_GET_FAST(s->k0); BZ_RAND_UPD_MASK;
+ s->k0 ^= BZ_RAND_MASK; s->nblock_used++;
}
} else {
while (True) {
- /* try to finish existing run */
- if (c_state_out_len > 0) {
- while (True) {
- if (cs_avail_out == 0) goto return_notr;
- if (c_state_out_len == 1) break;
- *( (UChar*)(cs_next_out) ) = c_state_out_ch;
- BZ_UPDATE_CRC ( c_calculatedBlockCRC, c_state_out_ch );
- c_state_out_len--;
- cs_next_out++;
- cs_avail_out--;
- }
- s_state_out_len_eq_one:
- {
- if (cs_avail_out == 0) {
- c_state_out_len = 1; goto return_notr;
- };
- *( (UChar*)(cs_next_out) ) = c_state_out_ch;
- BZ_UPDATE_CRC ( c_calculatedBlockCRC, c_state_out_ch );
- cs_next_out++;
- cs_avail_out--;
- }
- }
- /* can a new run be started? */
- if (c_nblock_used == s_save_nblockPP) {
- c_state_out_len = 0; goto return_notr;
- };
- c_state_out_ch = c_k0;
- BZ_GET_FAST_C(k1); c_nblock_used++;
- if (k1 != c_k0) {
- c_k0 = k1; goto s_state_out_len_eq_one;
- };
- if (c_nblock_used == s_save_nblockPP)
- goto s_state_out_len_eq_one;
-
- c_state_out_len = 2;
- BZ_GET_FAST_C(k1); c_nblock_used++;
- if (c_nblock_used == s_save_nblockPP) continue;
- if (k1 != c_k0) { c_k0 = k1; continue; };
-
- c_state_out_len = 3;
- BZ_GET_FAST_C(k1); c_nblock_used++;
- if (c_nblock_used == s_save_nblockPP) continue;
- if (k1 != c_k0) { c_k0 = k1; continue; };
-
- BZ_GET_FAST_C(k1); c_nblock_used++;
- c_state_out_len = ((Int32)k1) + 4;
- BZ_GET_FAST_C(c_k0); c_nblock_used++;
+ /* try to finish existing run */
+ if (c_state_out_len > 0) {
+ while (True) {
+ if (cs_avail_out == 0) goto return_notr;
+ if (c_state_out_len == 1) break;
+ *( (UChar*)(cs_next_out) ) = c_state_out_ch;
+ BZ_UPDATE_CRC ( c_calculatedBlockCRC, c_state_out_ch );
+ c_state_out_len--;
+ cs_next_out++;
+ cs_avail_out--;
+ }
+ s_state_out_len_eq_one:
+ {
+ if (cs_avail_out == 0) {
+ c_state_out_len = 1; goto return_notr;
+ };
+ *( (UChar*)(cs_next_out) ) = c_state_out_ch;
+ BZ_UPDATE_CRC ( c_calculatedBlockCRC, c_state_out_ch );
+ cs_next_out++;
+ cs_avail_out--;
+ }
+ }
+ /* can a new run be started? */
+ if (c_nblock_used == s_save_nblockPP) {
+ c_state_out_len = 0; goto return_notr;
+ };
+ c_state_out_ch = c_k0;
+ BZ_GET_FAST_C(k1); c_nblock_used++;
+ if (k1 != c_k0) {
+ c_k0 = k1; goto s_state_out_len_eq_one;
+ };
+ if (c_nblock_used == s_save_nblockPP)
+ goto s_state_out_len_eq_one;
+
+ c_state_out_len = 2;
+ BZ_GET_FAST_C(k1); c_nblock_used++;
+ if (c_nblock_used == s_save_nblockPP) continue;
+ if (k1 != c_k0) { c_k0 = k1; continue; };
+
+ c_state_out_len = 3;
+ BZ_GET_FAST_C(k1); c_nblock_used++;
+ if (c_nblock_used == s_save_nblockPP) continue;
+ if (k1 != c_k0) { c_k0 = k1; continue; };
+
+ BZ_GET_FAST_C(k1); c_nblock_used++;
+ c_state_out_len = ((Int32)k1) + 4;
+ BZ_GET_FAST_C(c_k0); c_nblock_used++;
}
return_notr:
total_out_lo32_old = s->strm->total_out_lo32;
s->strm->total_out_lo32 += (avail_out_INIT - cs_avail_out);
if (s->strm->total_out_lo32 < total_out_lo32_old)
- s->strm->total_out_hi32++;
+ s->strm->total_out_hi32++;
/* save */
s->calculatedBlockCRC = c_calculatedBlockCRC;
}
-
/*---------------------------------------------------*/
__inline__ Int32 BZ2_indexIntoF ( Int32 indx, Int32 *cftab )
{
if (s->blockRandomised) {
while (True) {
- /* try to finish existing run */
- while (True) {
- if (s->strm->avail_out == 0) return;
- if (s->state_out_len == 0) break;
- *( (UChar*)(s->strm->next_out) ) = s->state_out_ch;
- BZ_UPDATE_CRC ( s->calculatedBlockCRC, s->state_out_ch );
- s->state_out_len--;
- s->strm->next_out++;
- s->strm->avail_out--;
- s->strm->total_out_lo32++;
- if (s->strm->total_out_lo32 == 0) s->strm->total_out_hi32++;
- }
-
- /* can a new run be started? */
- if (s->nblock_used == s->save_nblock+1) return;
-
-
- s->state_out_len = 1;
- s->state_out_ch = s->k0;
- BZ_GET_SMALL(k1); BZ_RAND_UPD_MASK;
- k1 ^= BZ_RAND_MASK; s->nblock_used++;
- if (s->nblock_used == s->save_nblock+1) continue;
- if (k1 != s->k0) { s->k0 = k1; continue; };
-
- s->state_out_len = 2;
- BZ_GET_SMALL(k1); BZ_RAND_UPD_MASK;
- k1 ^= BZ_RAND_MASK; s->nblock_used++;
- if (s->nblock_used == s->save_nblock+1) continue;
- if (k1 != s->k0) { s->k0 = k1; continue; };
-
- s->state_out_len = 3;
- BZ_GET_SMALL(k1); BZ_RAND_UPD_MASK;
- k1 ^= BZ_RAND_MASK; s->nblock_used++;
- if (s->nblock_used == s->save_nblock+1) continue;
- if (k1 != s->k0) { s->k0 = k1; continue; };
-
- BZ_GET_SMALL(k1); BZ_RAND_UPD_MASK;
- k1 ^= BZ_RAND_MASK; s->nblock_used++;
- s->state_out_len = ((Int32)k1) + 4;
- BZ_GET_SMALL(s->k0); BZ_RAND_UPD_MASK;
- s->k0 ^= BZ_RAND_MASK; s->nblock_used++;
+ /* try to finish existing run */
+ while (True) {
+ if (s->strm->avail_out == 0) return;
+ if (s->state_out_len == 0) break;
+ *( (UChar*)(s->strm->next_out) ) = s->state_out_ch;
+ BZ_UPDATE_CRC ( s->calculatedBlockCRC, s->state_out_ch );
+ s->state_out_len--;
+ s->strm->next_out++;
+ s->strm->avail_out--;
+ s->strm->total_out_lo32++;
+ if (s->strm->total_out_lo32 == 0) s->strm->total_out_hi32++;
+ }
+
+ /* can a new run be started? */
+ if (s->nblock_used == s->save_nblock+1) return;
+
+
+ s->state_out_len = 1;
+ s->state_out_ch = s->k0;
+ BZ_GET_SMALL(k1); BZ_RAND_UPD_MASK;
+ k1 ^= BZ_RAND_MASK; s->nblock_used++;
+ if (s->nblock_used == s->save_nblock+1) continue;
+ if (k1 != s->k0) { s->k0 = k1; continue; };
+
+ s->state_out_len = 2;
+ BZ_GET_SMALL(k1); BZ_RAND_UPD_MASK;
+ k1 ^= BZ_RAND_MASK; s->nblock_used++;
+ if (s->nblock_used == s->save_nblock+1) continue;
+ if (k1 != s->k0) { s->k0 = k1; continue; };
+
+ s->state_out_len = 3;
+ BZ_GET_SMALL(k1); BZ_RAND_UPD_MASK;
+ k1 ^= BZ_RAND_MASK; s->nblock_used++;
+ if (s->nblock_used == s->save_nblock+1) continue;
+ if (k1 != s->k0) { s->k0 = k1; continue; };
+
+ BZ_GET_SMALL(k1); BZ_RAND_UPD_MASK;
+ k1 ^= BZ_RAND_MASK; s->nblock_used++;
+ s->state_out_len = ((Int32)k1) + 4;
+ BZ_GET_SMALL(s->k0); BZ_RAND_UPD_MASK;
+ s->k0 ^= BZ_RAND_MASK; s->nblock_used++;
}
} else {
while (True) {
- /* try to finish existing run */
- while (True) {
- if (s->strm->avail_out == 0) return;
- if (s->state_out_len == 0) break;
- *( (UChar*)(s->strm->next_out) ) = s->state_out_ch;
- BZ_UPDATE_CRC ( s->calculatedBlockCRC, s->state_out_ch );
- s->state_out_len--;
- s->strm->next_out++;
- s->strm->avail_out--;
- s->strm->total_out_lo32++;
- if (s->strm->total_out_lo32 == 0) s->strm->total_out_hi32++;
- }
-
- /* can a new run be started? */
- if (s->nblock_used == s->save_nblock+1) return;
-
- s->state_out_len = 1;
- s->state_out_ch = s->k0;
- BZ_GET_SMALL(k1); s->nblock_used++;
- if (s->nblock_used == s->save_nblock+1) continue;
- if (k1 != s->k0) { s->k0 = k1; continue; };
-
- s->state_out_len = 2;
- BZ_GET_SMALL(k1); s->nblock_used++;
- if (s->nblock_used == s->save_nblock+1) continue;
- if (k1 != s->k0) { s->k0 = k1; continue; };
-
- s->state_out_len = 3;
- BZ_GET_SMALL(k1); s->nblock_used++;
- if (s->nblock_used == s->save_nblock+1) continue;
- if (k1 != s->k0) { s->k0 = k1; continue; };
-
- BZ_GET_SMALL(k1); s->nblock_used++;
- s->state_out_len = ((Int32)k1) + 4;
- BZ_GET_SMALL(s->k0); s->nblock_used++;
+ /* try to finish existing run */
+ while (True) {
+ if (s->strm->avail_out == 0) return;
+ if (s->state_out_len == 0) break;
+ *( (UChar*)(s->strm->next_out) ) = s->state_out_ch;
+ BZ_UPDATE_CRC ( s->calculatedBlockCRC, s->state_out_ch );
+ s->state_out_len--;
+ s->strm->next_out++;
+ s->strm->avail_out--;
+ s->strm->total_out_lo32++;
+ if (s->strm->total_out_lo32 == 0) s->strm->total_out_hi32++;
+ }
+
+ /* can a new run be started? */
+ if (s->nblock_used == s->save_nblock+1) return;
+
+ s->state_out_len = 1;
+ s->state_out_ch = s->k0;
+ BZ_GET_SMALL(k1); s->nblock_used++;
+ if (s->nblock_used == s->save_nblock+1) continue;
+ if (k1 != s->k0) { s->k0 = k1; continue; };
+
+ s->state_out_len = 2;
+ BZ_GET_SMALL(k1); s->nblock_used++;
+ if (s->nblock_used == s->save_nblock+1) continue;
+ if (k1 != s->k0) { s->k0 = k1; continue; };
+
+ s->state_out_len = 3;
+ BZ_GET_SMALL(k1); s->nblock_used++;
+ if (s->nblock_used == s->save_nblock+1) continue;
+ if (k1 != s->k0) { s->k0 = k1; continue; };
+
+ BZ_GET_SMALL(k1); s->nblock_used++;
+ s->state_out_len = ((Int32)k1) + 4;
+ BZ_GET_SMALL(s->k0); s->nblock_used++;
}
}
while (True) {
if (s->state == BZ_X_IDLE) return BZ_SEQUENCE_ERROR;
if (s->state == BZ_X_OUTPUT) {
- if (s->smallDecompress)
- unRLE_obuf_to_output_SMALL ( s ); else
- unRLE_obuf_to_output_FAST ( s );
- if (s->nblock_used == s->save_nblock+1 && s->state_out_len == 0) {
- BZ_FINALISE_CRC ( s->calculatedBlockCRC );
- if (s->verbosity >= 3)
- VPrintf2 ( " {0x%x, 0x%x}", s->storedBlockCRC,
- s->calculatedBlockCRC );
- if (s->verbosity >= 2) VPrintf0 ( "]" );
- if (s->calculatedBlockCRC != s->storedBlockCRC)
- return BZ_DATA_ERROR;
- s->calculatedCombinedCRC
- = (s->calculatedCombinedCRC << 1) |
- (s->calculatedCombinedCRC >> 31);
- s->calculatedCombinedCRC ^= s->calculatedBlockCRC;
- s->state = BZ_X_BLKHDR_1;
- } else {
- return BZ_OK;
- }
+ if (s->smallDecompress)
+ unRLE_obuf_to_output_SMALL ( s ); else
+ unRLE_obuf_to_output_FAST ( s );
+ if (s->nblock_used == s->save_nblock+1 && s->state_out_len == 0) {
+ BZ_FINALISE_CRC ( s->calculatedBlockCRC );
+ if (s->verbosity >= 3)
+ VPrintf2 ( " {0x%x, 0x%x}", s->storedBlockCRC,
+ s->calculatedBlockCRC );
+ if (s->verbosity >= 2) VPrintf0 ( "]" );
+ if (s->calculatedBlockCRC != s->storedBlockCRC)
+ return BZ_DATA_ERROR;
+ s->calculatedCombinedCRC
+ = (s->calculatedCombinedCRC << 1) |
+ (s->calculatedCombinedCRC >> 31);
+ s->calculatedCombinedCRC ^= s->calculatedBlockCRC;
+ s->state = BZ_X_BLKHDR_1;
+ } else {
+ return BZ_OK;
+ }
}
if (s->state >= BZ_X_MAGIC_1) {
- Int32 r = BZ2_decompress ( s );
- if (r == BZ_STREAM_END) {
- if (s->verbosity >= 3)
- VPrintf2 ( "\n combined CRCs: stored = 0x%x, computed = 0x%x",
- s->storedCombinedCRC, s->calculatedCombinedCRC );
- if (s->calculatedCombinedCRC != s->storedCombinedCRC)
- return BZ_DATA_ERROR;
- return r;
- }
- if (s->state != BZ_X_OUTPUT) return r;
+ Int32 r = BZ2_decompress ( s );
+ if (r == BZ_STREAM_END) {
+ if (s->verbosity >= 3)
+ VPrintf2 ( "\n combined CRCs: stored = 0x%x, computed = 0x%x",
+ s->storedCombinedCRC, s->calculatedCombinedCRC );
+ if (s->calculatedCombinedCRC != s->storedCombinedCRC)
+ return BZ_DATA_ERROR;
+ return r;
+ }
+ if (s->state != BZ_X_OUTPUT) return r;
}
}
/*---------------------------------------------------*/
BZFILE* BZ_API(BZ2_bzWriteOpen)
- ( int* bzerror,
- FILE* f,
- int blockSize100k,
- int verbosity,
- int workFactor )
+ ( int* bzerror,
+ FILE* f,
+ int blockSize100k,
+ int verbosity,
+ int workFactor )
{
Int32 ret;
bzFile* bzf = NULL;
if (workFactor == 0) workFactor = 30;
ret = BZ2_bzCompressInit ( &(bzf->strm), blockSize100k,
- verbosity, workFactor );
+ verbosity, workFactor );
if (ret != BZ_OK)
{ BZ_SETERR(ret); free(bzf); return NULL; };
}
-
/*---------------------------------------------------*/
void BZ_API(BZ2_bzWrite)
- ( int* bzerror,
- BZFILE* b,
- void* buf,
- int len )
+ ( int* bzerror,
+ BZFILE* b,
+ void* buf,
+ int len )
{
Int32 n, n2, ret;
bzFile* bzf = (bzFile*)b;
bzf->strm.next_out = bzf->buf;
ret = BZ2_bzCompress ( &(bzf->strm), BZ_RUN );
if (ret != BZ_RUN_OK)
- { BZ_SETERR(ret); return; };
+ { BZ_SETERR(ret); return; };
if (bzf->strm.avail_out < BZ_MAX_UNUSED) {
- n = BZ_MAX_UNUSED - bzf->strm.avail_out;
- n2 = fwrite ( (void*)(bzf->buf), sizeof(UChar),
- n, bzf->handle );
- if (n != n2 || ferror(bzf->handle))
- { BZ_SETERR(BZ_IO_ERROR); return; };
+ n = BZ_MAX_UNUSED - bzf->strm.avail_out;
+ n2 = fwrite ( (void*)(bzf->buf), sizeof(UChar),
+ n, bzf->handle );
+ if (n != n2 || ferror(bzf->handle))
+ { BZ_SETERR(BZ_IO_ERROR); return; };
}
if (bzf->strm.avail_in == 0)
- { BZ_SETERR(BZ_OK); return; };
+ { BZ_SETERR(BZ_OK); return; };
}
}
/*---------------------------------------------------*/
void BZ_API(BZ2_bzWriteClose)
- ( int* bzerror,
- BZFILE* b,
- int abandon,
- unsigned int* nbytes_in,
- unsigned int* nbytes_out )
+ ( int* bzerror,
+ BZFILE* b,
+ int abandon,
+ unsigned int* nbytes_in,
+ unsigned int* nbytes_out )
{
BZ2_bzWriteClose64 ( bzerror, b, abandon,
- nbytes_in, NULL, nbytes_out, NULL );
+ nbytes_in, NULL, nbytes_out, NULL );
}
void BZ_API(BZ2_bzWriteClose64)
- ( int* bzerror,
- BZFILE* b,
- int abandon,
- unsigned int* nbytes_in_lo32,
- unsigned int* nbytes_in_hi32,
- unsigned int* nbytes_out_lo32,
- unsigned int* nbytes_out_hi32 )
+ ( int* bzerror,
+ BZFILE* b,
+ int abandon,
+ unsigned int* nbytes_in_lo32,
+ unsigned int* nbytes_in_hi32,
+ unsigned int* nbytes_out_lo32,
+ unsigned int* nbytes_out_hi32 )
{
Int32 n, n2, ret;
bzFile* bzf = (bzFile*)b;
if ((!abandon) && bzf->lastErr == BZ_OK) {
while (True) {
- bzf->strm.avail_out = BZ_MAX_UNUSED;
- bzf->strm.next_out = bzf->buf;
- ret = BZ2_bzCompress ( &(bzf->strm), BZ_FINISH );
- if (ret != BZ_FINISH_OK && ret != BZ_STREAM_END)
- { BZ_SETERR(ret); return; };
-
- if (bzf->strm.avail_out < BZ_MAX_UNUSED) {
- n = BZ_MAX_UNUSED - bzf->strm.avail_out;
- n2 = fwrite ( (void*)(bzf->buf), sizeof(UChar),
- n, bzf->handle );
- if (n != n2 || ferror(bzf->handle))
- { BZ_SETERR(BZ_IO_ERROR); return; };
- }
-
- if (ret == BZ_STREAM_END) break;
+ bzf->strm.avail_out = BZ_MAX_UNUSED;
+ bzf->strm.next_out = bzf->buf;
+ ret = BZ2_bzCompress ( &(bzf->strm), BZ_FINISH );
+ if (ret != BZ_FINISH_OK && ret != BZ_STREAM_END)
+ { BZ_SETERR(ret); return; };
+
+ if (bzf->strm.avail_out < BZ_MAX_UNUSED) {
+ n = BZ_MAX_UNUSED - bzf->strm.avail_out;
+ n2 = fwrite ( (void*)(bzf->buf), sizeof(UChar),
+ n, bzf->handle );
+ if (n != n2 || ferror(bzf->handle))
+ { BZ_SETERR(BZ_IO_ERROR); return; };
+ }
+
+ if (ret == BZ_STREAM_END) break;
}
}
if ( !abandon && !ferror ( bzf->handle ) ) {
fflush ( bzf->handle );
if (ferror(bzf->handle))
- { BZ_SETERR(BZ_IO_ERROR); return; };
+ { BZ_SETERR(BZ_IO_ERROR); return; };
}
if (nbytes_in_lo32 != NULL)
/*---------------------------------------------------*/
BZFILE* BZ_API(BZ2_bzReadOpen)
- ( int* bzerror,
- FILE* f,
- int verbosity,
- int small,
- void* unused,
- int nUnused )
+ ( int* bzerror,
+ FILE* f,
+ int verbosity,
+ int small,
+ void* unused,
+ int nUnused )
{
bzFile* bzf = NULL;
int ret;
/*---------------------------------------------------*/
int BZ_API(BZ2_bzRead)
- ( int* bzerror,
- BZFILE* b,
- void* buf,
- int len )
+ ( int* bzerror,
+ BZFILE* b,
+ void* buf,
+ int len )
{
Int32 n, ret;
bzFile* bzf = (bzFile*)b;
while (True) {
if (ferror(bzf->handle))
- { BZ_SETERR(BZ_IO_ERROR); return 0; };
+ { BZ_SETERR(BZ_IO_ERROR); return 0; };
if (bzf->strm.avail_in == 0 && !myfeof(bzf->handle)) {
- n = fread ( bzf->buf, sizeof(UChar),
- BZ_MAX_UNUSED, bzf->handle );
- if (ferror(bzf->handle))
- { BZ_SETERR(BZ_IO_ERROR); return 0; };
- bzf->bufN = n;
- bzf->strm.avail_in = bzf->bufN;
- bzf->strm.next_in = bzf->buf;
+ n = fread ( bzf->buf, sizeof(UChar),
+ BZ_MAX_UNUSED, bzf->handle );
+ if (ferror(bzf->handle))
+ { BZ_SETERR(BZ_IO_ERROR); return 0; };
+ bzf->bufN = n;
+ bzf->strm.avail_in = bzf->bufN;
+ bzf->strm.next_in = bzf->buf;
}
ret = BZ2_bzDecompress ( &(bzf->strm) );
if (ret != BZ_OK && ret != BZ_STREAM_END)
- { BZ_SETERR(ret); return 0; };
+ { BZ_SETERR(ret); return 0; };
if (ret == BZ_OK && myfeof(bzf->handle) &&
- bzf->strm.avail_in == 0 && bzf->strm.avail_out > 0)
- { BZ_SETERR(BZ_UNEXPECTED_EOF); return 0; };
+ bzf->strm.avail_in == 0 && bzf->strm.avail_out > 0)
+ { BZ_SETERR(BZ_UNEXPECTED_EOF); return 0; };
if (ret == BZ_STREAM_END)
- { BZ_SETERR(BZ_STREAM_END);
- return len - bzf->strm.avail_out; };
+ { BZ_SETERR(BZ_STREAM_END);
+ return len - bzf->strm.avail_out; };
if (bzf->strm.avail_out == 0)
- { BZ_SETERR(BZ_OK); return len; };
+ { BZ_SETERR(BZ_OK); return len; };
}
/*---------------------------------------------------*/
void BZ_API(BZ2_bzReadGetUnused)
- ( int* bzerror,
- BZFILE* b,
- void** unused,
- int* nUnused )
+ ( int* bzerror,
+ BZFILE* b,
+ void** unused,
+ int* nUnused )
{
bzFile* bzf = (bzFile*)b;
if (bzf == NULL)
#ifndef BZ_NO_COMPRESS
/*---------------------------------------------------*/
int BZ_API(BZ2_bzBuffToBuffCompress)
- ( char* dest,
- unsigned int* destLen,
- char* source,
- unsigned int sourceLen,
- int blockSize100k,
- int verbosity,
- int workFactor )
+ ( char* dest,
+ unsigned int* destLen,
+ char* source,
+ unsigned int sourceLen,
+ int blockSize100k,
+ int verbosity,
+ int workFactor )
{
bz_stream strm;
int ret;
strm.bzfree = NULL;
strm.opaque = NULL;
ret = BZ2_bzCompressInit ( &strm, blockSize100k,
- verbosity, workFactor );
+ verbosity, workFactor );
if (ret != BZ_OK) return ret;
strm.next_in = source;
/*---------------------------------------------------*/
int BZ_API(BZ2_bzBuffToBuffDecompress)
- ( char* dest,
- unsigned int* destLen,
- char* source,
- unsigned int sourceLen,
- int small,
- int verbosity )
+ ( char* dest,
+ unsigned int* destLen,
+ char* source,
+ unsigned int sourceLen,
+ int small,
+ int verbosity )
{
bz_stream strm;
int ret;
if (destLen == NULL || source == NULL)
- return BZ_PARAM_ERROR;
+ return BZ_PARAM_ERROR;
strm.bzalloc = NULL;
strm.bzfree = NULL;
#endif
static
BZFILE * bzopen_or_bzdopen
- ( const char *path, /* no use when bzdopen */
- int fd, /* no use when bzdopen */
- const char *mode,
- int open_mode) /* bzopen: 0, bzdopen:1 */
+ ( const char *path, /* no use when bzdopen */
+ int fd, /* no use when bzdopen */
+ const char *mode,
+ int open_mode) /* bzopen: 0, bzdopen:1 */
{
int bzerr;
char unused[BZ_MAX_UNUSED];
while (*mode) {
switch (*mode) {
case 'r':
- writing = 0; break;
+ writing = 0; break;
case 'w':
- writing = 1; break;
+ writing = 1; break;
case 's':
- smallMode = 1; break;
+ smallMode = 1; break;
default:
- if (isdigit((int)(*mode))) {
- blockSize100k = *mode-BZ_HDR_0;
- }
+ if (isdigit((int)(*mode))) {
+ blockSize100k = *mode-BZ_HDR_0;
+ }
}
mode++;
}
if (open_mode==0) {
if (path==NULL || strcmp(path,"")==0) {
- fp = (writing ? stdout : stdin);
- SET_BINARY_MODE(fp);
+ fp = (writing ? stdout : stdin);
+ SET_BINARY_MODE(fp);
} else {
- fp = fopen(path,mode2);
+ fp = fopen(path,mode2);
}
} else {
#ifdef BZ_STRICT_ANSI
if (blockSize100k < 1) blockSize100k = 1;
if (blockSize100k > 9) blockSize100k = 9;
bzfp = BZ2_bzWriteOpen(&bzerr,fp,blockSize100k,
- verbosity,workFactor);
+ verbosity,workFactor);
} else {
bzfp = BZ2_bzReadOpen(&bzerr,fp,verbosity,smallMode,
- unused,nUnused);
+ unused,nUnused);
}
if (bzfp == NULL) {
if (fp != stdin && fp != stdout) fclose(fp);
case path="" or NULL => use stdin or stdout.
--*/
BZFILE * BZ_API(BZ2_bzopen)
- ( const char *path,
- const char *mode )
+ ( const char *path,
+ const char *mode )
{
return bzopen_or_bzdopen(path,-1,mode,/*bzopen*/0);
}
/*---------------------------------------------------*/
BZFILE * BZ_API(BZ2_bzdopen)
- ( int fd,
- const char *mode )
+ ( int fd,
+ const char *mode )
{
return bzopen_or_bzdopen(NULL,fd,mode,/*bzdopen*/1);
}
if(((bzFile*)b)->writing){
BZ2_bzWriteClose(&bzerr,b,0,NULL,NULL);
if(bzerr != BZ_OK){
- BZ2_bzWriteClose(NULL,b,1,NULL,NULL);
+ BZ2_bzWriteClose(NULL,b,1,NULL,NULL);
}
}else{
BZ2_bzReadClose(&bzerr,b);
s->nInUse = 0;
for (i = 0; i < 256; i++)
if (s->inUse[i]) {
- s->seqToUnseq[s->nInUse] = i;
- s->nInUse++;
+ s->seqToUnseq[s->nInUse] = i;
+ s->nInUse++;
}
}
case lll: s->state = lll; \
while (True) { \
if (s->bsLive >= nnn) { \
- UInt32 v; \
- v = (s->bsBuff >> \
- (s->bsLive-nnn)) & ((1 << nnn)-1); \
- s->bsLive -= nnn; \
- vvv = v; \
- break; \
+ UInt32 v; \
+ v = (s->bsBuff >> \
+ (s->bsLive-nnn)) & ((1 << nnn)-1); \
+ s->bsLive -= nnn; \
+ vvv = v; \
+ break; \
} \
if (s->strm->avail_in == 0) RETURN(BZ_OK); \
s->bsBuff \
- = (s->bsBuff << 8) | \
- ((UInt32) \
- (*((UChar*)(s->strm->next_in)))); \
+ = (s->bsBuff << 8) | \
+ ((UInt32) \
+ (*((UChar*)(s->strm->next_in)))); \
s->bsLive += 8; \
s->strm->next_in++; \
s->strm->avail_in--; \
s->strm->total_in_lo32++; \
if (s->strm->total_in_lo32 == 0) \
- s->strm->total_in_hi32++; \
+ s->strm->total_in_hi32++; \
}
#define GET_UCHAR(lll,uuu) \
if (groupPos == 0) { \
groupNo++; \
if (groupNo >= nSelectors) \
- RETURN(BZ_DATA_ERROR); \
+ RETURN(BZ_DATA_ERROR); \
groupPos = BZ_G_SIZE; \
gSel = s->selector[groupNo]; \
gMinlen = s->minLens[gSel]; \
GET_BITS(label1, zvec, zn); \
while (1) { \
if (zn > 20 /* the longest code */) \
- RETURN(BZ_DATA_ERROR); \
+ RETURN(BZ_DATA_ERROR); \
if (zvec <= gLimit[zn]) break; \
zn++; \
GET_BIT(label2, zj); \
GET_BITS(BZ_X_MAGIC_4, s->blockSize100k, 8)
if (s->blockSize100k < (BZ_HDR_0 + 1) ||
- s->blockSize100k > (BZ_HDR_0 + 9)) RETURN(BZ_DATA_ERROR_MAGIC);
+ s->blockSize100k > (BZ_HDR_0 + 9)) RETURN(BZ_DATA_ERROR_MAGIC);
s->blockSize100k -= BZ_HDR_0;
if (s->smallDecompress) {
- s->ll16 = BZALLOC( s->blockSize100k * 100000 * sizeof(UInt16) );
- s->ll4 = BZALLOC(
- ((1 + s->blockSize100k * 100000) >> 1) * sizeof(UChar)
- );
- if (s->ll16 == NULL || s->ll4 == NULL) RETURN(BZ_MEM_ERROR);
+ s->ll16 = BZALLOC( s->blockSize100k * 100000 * sizeof(UInt16) );
+ s->ll4 = BZALLOC(
+ ((1 + s->blockSize100k * 100000) >> 1) * sizeof(UChar)
+ );
+ if (s->ll16 == NULL || s->ll4 == NULL) RETURN(BZ_MEM_ERROR);
} else {
- s->tt = BZALLOC( s->blockSize100k * 100000 * sizeof(Int32) );
- if (s->tt == NULL) RETURN(BZ_MEM_ERROR);
+ s->tt = BZALLOC( s->blockSize100k * 100000 * sizeof(Int32) );
+ if (s->tt == NULL) RETURN(BZ_MEM_ERROR);
}
GET_UCHAR(BZ_X_BLKHDR_1, uc);
s->currBlockNo++;
if (s->verbosity >= 2)
- VPrintf1 ( "\n [%d: huff+mtf ", s->currBlockNo );
+ VPrintf1 ( "\n [%d: huff+mtf ", s->currBlockNo );
s->storedBlockCRC = 0;
GET_UCHAR(BZ_X_BCRC_1, uc);
s->origPtr = (s->origPtr << 8) | ((Int32)uc);
if (s->origPtr < 0)
- RETURN(BZ_DATA_ERROR);
+ RETURN(BZ_DATA_ERROR);
if (s->origPtr > 10 + 100000*s->blockSize100k)
- RETURN(BZ_DATA_ERROR);
+ RETURN(BZ_DATA_ERROR);
/*--- Receive the mapping table ---*/
for (i = 0; i < 16; i++) {
- GET_BIT(BZ_X_MAPPING_1, uc);
- if (uc == 1)
- s->inUse16[i] = True; else
- s->inUse16[i] = False;
+ GET_BIT(BZ_X_MAPPING_1, uc);
+ if (uc == 1)
+ s->inUse16[i] = True; else
+ s->inUse16[i] = False;
}
for (i = 0; i < 256; i++) s->inUse[i] = False;
for (i = 0; i < 16; i++)
- if (s->inUse16[i])
- for (j = 0; j < 16; j++) {
- GET_BIT(BZ_X_MAPPING_2, uc);
- if (uc == 1) s->inUse[i * 16 + j] = True;
- }
+ if (s->inUse16[i])
+ for (j = 0; j < 16; j++) {
+ GET_BIT(BZ_X_MAPPING_2, uc);
+ if (uc == 1) s->inUse[i * 16 + j] = True;
+ }
makeMaps_d ( s );
if (s->nInUse == 0) RETURN(BZ_DATA_ERROR);
alphaSize = s->nInUse+2;
GET_BITS(BZ_X_SELECTOR_2, nSelectors, 15);
if (nSelectors < 1) RETURN(BZ_DATA_ERROR);
for (i = 0; i < nSelectors; i++) {
- j = 0;
- while (True) {
- GET_BIT(BZ_X_SELECTOR_3, uc);
- if (uc == 0) break;
- j++;
- if (j >= nGroups) RETURN(BZ_DATA_ERROR);
- }
- s->selectorMtf[i] = j;
+ j = 0;
+ while (True) {
+ GET_BIT(BZ_X_SELECTOR_3, uc);
+ if (uc == 0) break;
+ j++;
+ if (j >= nGroups) RETURN(BZ_DATA_ERROR);
+ }
+ s->selectorMtf[i] = j;
}
/*--- Undo the MTF values for the selectors. ---*/
{
- UChar pos[BZ_N_GROUPS], tmp, v;
- for (v = 0; v < nGroups; v++) pos[v] = v;
-
- for (i = 0; i < nSelectors; i++) {
- v = s->selectorMtf[i];
- tmp = pos[v];
- while (v > 0) { pos[v] = pos[v-1]; v--; }
- pos[0] = tmp;
- s->selector[i] = tmp;
- }
+ UChar pos[BZ_N_GROUPS], tmp, v;
+ for (v = 0; v < nGroups; v++) pos[v] = v;
+
+ for (i = 0; i < nSelectors; i++) {
+ v = s->selectorMtf[i];
+ tmp = pos[v];
+ while (v > 0) { pos[v] = pos[v-1]; v--; }
+ pos[0] = tmp;
+ s->selector[i] = tmp;
+ }
}
/*--- Now the coding tables ---*/
for (t = 0; t < nGroups; t++) {
- GET_BITS(BZ_X_CODING_1, curr, 5);
- for (i = 0; i < alphaSize; i++) {
- while (True) {
- if (curr < 1 || curr > 20) RETURN(BZ_DATA_ERROR);
- GET_BIT(BZ_X_CODING_2, uc);
- if (uc == 0) break;
- GET_BIT(BZ_X_CODING_3, uc);
- if (uc == 0) curr++; else curr--;
- }
- s->len[t][i] = curr;
- }
+ GET_BITS(BZ_X_CODING_1, curr, 5);
+ for (i = 0; i < alphaSize; i++) {
+ while (True) {
+ if (curr < 1 || curr > 20) RETURN(BZ_DATA_ERROR);
+ GET_BIT(BZ_X_CODING_2, uc);
+ if (uc == 0) break;
+ GET_BIT(BZ_X_CODING_3, uc);
+ if (uc == 0) curr++; else curr--;
+ }
+ s->len[t][i] = curr;
+ }
}
/*--- Create the Huffman decoding tables ---*/
for (t = 0; t < nGroups; t++) {
- minLen = 32;
- maxLen = 0;
- for (i = 0; i < alphaSize; i++) {
- if (s->len[t][i] > maxLen) maxLen = s->len[t][i];
- if (s->len[t][i] < minLen) minLen = s->len[t][i];
- }
- BZ2_hbCreateDecodeTables (
- &(s->limit[t][0]),
- &(s->base[t][0]),
- &(s->perm[t][0]),
- &(s->len[t][0]),
- minLen, maxLen, alphaSize
- );
- s->minLens[t] = minLen;
+ minLen = 32;
+ maxLen = 0;
+ for (i = 0; i < alphaSize; i++) {
+ if (s->len[t][i] > maxLen) maxLen = s->len[t][i];
+ if (s->len[t][i] < minLen) minLen = s->len[t][i];
+ }
+ BZ2_hbCreateDecodeTables (
+ &(s->limit[t][0]),
+ &(s->base[t][0]),
+ &(s->perm[t][0]),
+ &(s->len[t][0]),
+ minLen, maxLen, alphaSize
+ );
+ s->minLens[t] = minLen;
}
/*--- Now the MTF values ---*/
/*-- MTF init --*/
{
- Int32 ii, jj, kk;
- kk = MTFA_SIZE-1;
- for (ii = 256 / MTFL_SIZE - 1; ii >= 0; ii--) {
- for (jj = MTFL_SIZE-1; jj >= 0; jj--) {
- s->mtfa[kk] = (UChar)(ii * MTFL_SIZE + jj);
- kk--;
- }
- s->mtfbase[ii] = kk + 1;
- }
+ Int32 ii, jj, kk;
+ kk = MTFA_SIZE-1;
+ for (ii = 256 / MTFL_SIZE - 1; ii >= 0; ii--) {
+ for (jj = MTFL_SIZE-1; jj >= 0; jj--) {
+ s->mtfa[kk] = (UChar)(ii * MTFL_SIZE + jj);
+ kk--;
+ }
+ s->mtfbase[ii] = kk + 1;
+ }
}
/*-- end MTF init --*/
while (True) {
- if (nextSym == EOB) break;
-
- if (nextSym == BZ_RUNA || nextSym == BZ_RUNB) {
-
- es = -1;
- N = 1;
- do {
- if (nextSym == BZ_RUNA) es = es + (0+1) * N; else
- if (nextSym == BZ_RUNB) es = es + (1+1) * N;
- N = N * 2;
- GET_MTF_VAL(BZ_X_MTF_3, BZ_X_MTF_4, nextSym);
- }
- while (nextSym == BZ_RUNA || nextSym == BZ_RUNB);
-
- es++;
- uc = s->seqToUnseq[ s->mtfa[s->mtfbase[0]] ];
- s->unzftab[uc] += es;
-
- if (s->smallDecompress)
- while (es > 0) {
- if (nblock >= nblockMAX) RETURN(BZ_DATA_ERROR);
- s->ll16[nblock] = (UInt16)uc;
- nblock++;
- es--;
- }
- else
- while (es > 0) {
- if (nblock >= nblockMAX) RETURN(BZ_DATA_ERROR);
- s->tt[nblock] = (UInt32)uc;
- nblock++;
- es--;
- };
-
- continue;
-
- } else {
-
- if (nblock >= nblockMAX) RETURN(BZ_DATA_ERROR);
-
- /*-- uc = MTF ( nextSym-1 ) --*/
- {
- Int32 ii, jj, kk, pp, lno, off;
- UInt32 nn;
- nn = (UInt32)(nextSym - 1);
-
- if (nn < MTFL_SIZE) {
- /* avoid general-case expense */
- pp = s->mtfbase[0];
- uc = s->mtfa[pp+nn];
- while (nn > 3) {
- Int32 z = pp+nn;
- s->mtfa[(z) ] = s->mtfa[(z)-1];
- s->mtfa[(z)-1] = s->mtfa[(z)-2];
- s->mtfa[(z)-2] = s->mtfa[(z)-3];
- s->mtfa[(z)-3] = s->mtfa[(z)-4];
- nn -= 4;
- }
- while (nn > 0) {
- s->mtfa[(pp+nn)] = s->mtfa[(pp+nn)-1]; nn--;
- };
- s->mtfa[pp] = uc;
- } else {
- /* general case */
- lno = nn / MTFL_SIZE;
- off = nn % MTFL_SIZE;
- pp = s->mtfbase[lno] + off;
- uc = s->mtfa[pp];
- while (pp > s->mtfbase[lno]) {
- s->mtfa[pp] = s->mtfa[pp-1]; pp--;
- };
- s->mtfbase[lno]++;
- while (lno > 0) {
- s->mtfbase[lno]--;
- s->mtfa[s->mtfbase[lno]]
- = s->mtfa[s->mtfbase[lno-1] + MTFL_SIZE - 1];
- lno--;
- }
- s->mtfbase[0]--;
- s->mtfa[s->mtfbase[0]] = uc;
- if (s->mtfbase[0] == 0) {
- kk = MTFA_SIZE-1;
- for (ii = 256 / MTFL_SIZE-1; ii >= 0; ii--) {
- for (jj = MTFL_SIZE-1; jj >= 0; jj--) {
- s->mtfa[kk] = s->mtfa[s->mtfbase[ii] + jj];
- kk--;
- }
- s->mtfbase[ii] = kk + 1;
- }
- }
- }
- }
- /*-- end uc = MTF ( nextSym-1 ) --*/
-
- s->unzftab[s->seqToUnseq[uc]]++;
- if (s->smallDecompress)
- s->ll16[nblock] = (UInt16)(s->seqToUnseq[uc]); else
- s->tt[nblock] = (UInt32)(s->seqToUnseq[uc]);
- nblock++;
-
- GET_MTF_VAL(BZ_X_MTF_5, BZ_X_MTF_6, nextSym);
- continue;
- }
+ if (nextSym == EOB) break;
+
+ if (nextSym == BZ_RUNA || nextSym == BZ_RUNB) {
+
+ es = -1;
+ N = 1;
+ do {
+ if (nextSym == BZ_RUNA) es = es + (0+1) * N; else
+ if (nextSym == BZ_RUNB) es = es + (1+1) * N;
+ N = N * 2;
+ GET_MTF_VAL(BZ_X_MTF_3, BZ_X_MTF_4, nextSym);
+ }
+ while (nextSym == BZ_RUNA || nextSym == BZ_RUNB);
+
+ es++;
+ uc = s->seqToUnseq[ s->mtfa[s->mtfbase[0]] ];
+ s->unzftab[uc] += es;
+
+ if (s->smallDecompress)
+ while (es > 0) {
+ if (nblock >= nblockMAX) RETURN(BZ_DATA_ERROR);
+ s->ll16[nblock] = (UInt16)uc;
+ nblock++;
+ es--;
+ }
+ else
+ while (es > 0) {
+ if (nblock >= nblockMAX) RETURN(BZ_DATA_ERROR);
+ s->tt[nblock] = (UInt32)uc;
+ nblock++;
+ es--;
+ };
+
+ continue;
+
+ } else {
+
+ if (nblock >= nblockMAX) RETURN(BZ_DATA_ERROR);
+
+ /*-- uc = MTF ( nextSym-1 ) --*/
+ {
+ Int32 ii, jj, kk, pp, lno, off;
+ UInt32 nn;
+ nn = (UInt32)(nextSym - 1);
+
+ if (nn < MTFL_SIZE) {
+ /* avoid general-case expense */
+ pp = s->mtfbase[0];
+ uc = s->mtfa[pp+nn];
+ while (nn > 3) {
+ Int32 z = pp+nn;
+ s->mtfa[(z) ] = s->mtfa[(z)-1];
+ s->mtfa[(z)-1] = s->mtfa[(z)-2];
+ s->mtfa[(z)-2] = s->mtfa[(z)-3];
+ s->mtfa[(z)-3] = s->mtfa[(z)-4];
+ nn -= 4;
+ }
+ while (nn > 0) {
+ s->mtfa[(pp+nn)] = s->mtfa[(pp+nn)-1]; nn--;
+ };
+ s->mtfa[pp] = uc;
+ } else {
+ /* general case */
+ lno = nn / MTFL_SIZE;
+ off = nn % MTFL_SIZE;
+ pp = s->mtfbase[lno] + off;
+ uc = s->mtfa[pp];
+ while (pp > s->mtfbase[lno]) {
+ s->mtfa[pp] = s->mtfa[pp-1]; pp--;
+ };
+ s->mtfbase[lno]++;
+ while (lno > 0) {
+ s->mtfbase[lno]--;
+ s->mtfa[s->mtfbase[lno]]
+ = s->mtfa[s->mtfbase[lno-1] + MTFL_SIZE - 1];
+ lno--;
+ }
+ s->mtfbase[0]--;
+ s->mtfa[s->mtfbase[0]] = uc;
+ if (s->mtfbase[0] == 0) {
+ kk = MTFA_SIZE-1;
+ for (ii = 256 / MTFL_SIZE-1; ii >= 0; ii--) {
+ for (jj = MTFL_SIZE-1; jj >= 0; jj--) {
+ s->mtfa[kk] = s->mtfa[s->mtfbase[ii] + jj];
+ kk--;
+ }
+ s->mtfbase[ii] = kk + 1;
+ }
+ }
+ }
+ }
+ /*-- end uc = MTF ( nextSym-1 ) --*/
+
+ s->unzftab[s->seqToUnseq[uc]]++;
+ if (s->smallDecompress)
+ s->ll16[nblock] = (UInt16)(s->seqToUnseq[uc]); else
+ s->tt[nblock] = (UInt32)(s->seqToUnseq[uc]);
+ nblock++;
+
+ GET_MTF_VAL(BZ_X_MTF_5, BZ_X_MTF_6, nextSym);
+ continue;
+ }
}
/* Now we know what nblock is, we can do a better sanity
- check on s->origPtr.
+ check on s->origPtr.
*/
if (s->origPtr < 0 || s->origPtr >= nblock)
- RETURN(BZ_DATA_ERROR);
+ RETURN(BZ_DATA_ERROR);
s->state_out_len = 0;
s->state_out_ch = 0;
if (s->smallDecompress) {
- /*-- Make a copy of cftab, used in generation of T --*/
- for (i = 0; i <= 256; i++) s->cftabCopy[i] = s->cftab[i];
-
- /*-- compute the T vector --*/
- for (i = 0; i < nblock; i++) {
- uc = (UChar)(s->ll16[i]);
- SET_LL(i, s->cftabCopy[uc]);
- s->cftabCopy[uc]++;
- }
-
- /*-- Compute T^(-1) by pointer reversal on T --*/
- i = s->origPtr;
- j = GET_LL(i);
- do {
- Int32 tmp = GET_LL(j);
- SET_LL(j, i);
- i = j;
- j = tmp;
- }
- while (i != s->origPtr);
-
- s->tPos = s->origPtr;
- s->nblock_used = 0;
- if (s->blockRandomised) {
- BZ_RAND_INIT_MASK;
- BZ_GET_SMALL(s->k0); s->nblock_used++;
- BZ_RAND_UPD_MASK; s->k0 ^= BZ_RAND_MASK;
- } else {
- BZ_GET_SMALL(s->k0); s->nblock_used++;
- }
+ /*-- Make a copy of cftab, used in generation of T --*/
+ for (i = 0; i <= 256; i++) s->cftabCopy[i] = s->cftab[i];
+
+ /*-- compute the T vector --*/
+ for (i = 0; i < nblock; i++) {
+ uc = (UChar)(s->ll16[i]);
+ SET_LL(i, s->cftabCopy[uc]);
+ s->cftabCopy[uc]++;
+ }
+
+ /*-- Compute T^(-1) by pointer reversal on T --*/
+ i = s->origPtr;
+ j = GET_LL(i);
+ do {
+ Int32 tmp = GET_LL(j);
+ SET_LL(j, i);
+ i = j;
+ j = tmp;
+ }
+ while (i != s->origPtr);
+
+ s->tPos = s->origPtr;
+ s->nblock_used = 0;
+ if (s->blockRandomised) {
+ BZ_RAND_INIT_MASK;
+ BZ_GET_SMALL(s->k0); s->nblock_used++;
+ BZ_RAND_UPD_MASK; s->k0 ^= BZ_RAND_MASK;
+ } else {
+ BZ_GET_SMALL(s->k0); s->nblock_used++;
+ }
} else {
- /*-- compute the T^(-1) vector --*/
- for (i = 0; i < nblock; i++) {
- uc = (UChar)(s->tt[i] & 0xff);
- s->tt[s->cftab[uc]] |= (i << 8);
- s->cftab[uc]++;
- }
-
- s->tPos = s->tt[s->origPtr] >> 8;
- s->nblock_used = 0;
- if (s->blockRandomised) {
- BZ_RAND_INIT_MASK;
- BZ_GET_FAST(s->k0); s->nblock_used++;
- BZ_RAND_UPD_MASK; s->k0 ^= BZ_RAND_MASK;
- } else {
- BZ_GET_FAST(s->k0); s->nblock_used++;
- }
+ /*-- compute the T^(-1) vector --*/
+ for (i = 0; i < nblock; i++) {
+ uc = (UChar)(s->tt[i] & 0xff);
+ s->tt[s->cftab[uc]] |= (i << 8);
+ s->cftab[uc]++;
+ }
+
+ s->tPos = s->tt[s->origPtr] >> 8;
+ s->nblock_used = 0;
+ if (s->blockRandomised) {
+ BZ_RAND_INIT_MASK;
+ BZ_GET_FAST(s->k0); s->nblock_used++;
+ BZ_RAND_UPD_MASK; s->k0 ^= BZ_RAND_MASK;
+ } else {
+ BZ_GET_FAST(s->k0); s->nblock_used++;
+ }
}
RETURN(BZ_OK);
-
endhdr_2:
GET_UCHAR(BZ_X_ENDHDR_2, uc);
yy = zz << 1; \
if (yy > nHeap) break; \
if (yy < nHeap && \
- weight[heap[yy+1]] < weight[heap[yy]]) \
- yy++; \
+ weight[heap[yy+1]] < weight[heap[yy]]) \
+ yy++; \
if (weight[tmp] < weight[heap[yy]]) break; \
heap[zz] = heap[yy]; \
zz = yy; \
/*---------------------------------------------------*/
void BZ2_hbMakeCodeLengths ( UChar *len,
- Int32 *freq,
- Int32 alphaSize,
- Int32 maxLen )
+ Int32 *freq,
+ Int32 alphaSize,
+ Int32 maxLen )
{
/*--
Nodes and heap entries run from 1. Entry 0
parent[0] = -2;
for (i = 1; i <= alphaSize; i++) {
- parent[i] = -1;
- nHeap++;
- heap[nHeap] = i;
- UPHEAP(nHeap);
+ parent[i] = -1;
+ nHeap++;
+ heap[nHeap] = i;
+ UPHEAP(nHeap);
}
AssertH( nHeap < (BZ_MAX_ALPHA_SIZE+2), 2001 );
while (nHeap > 1) {
- n1 = heap[1]; heap[1] = heap[nHeap]; nHeap--; DOWNHEAP(1);
- n2 = heap[1]; heap[1] = heap[nHeap]; nHeap--; DOWNHEAP(1);
- nNodes++;
- parent[n1] = parent[n2] = nNodes;
- weight[nNodes] = ADDWEIGHTS(weight[n1], weight[n2]);
- parent[nNodes] = -1;
- nHeap++;
- heap[nHeap] = nNodes;
- UPHEAP(nHeap);
+ n1 = heap[1]; heap[1] = heap[nHeap]; nHeap--; DOWNHEAP(1);
+ n2 = heap[1]; heap[1] = heap[nHeap]; nHeap--; DOWNHEAP(1);
+ nNodes++;
+ parent[n1] = parent[n2] = nNodes;
+ weight[nNodes] = ADDWEIGHTS(weight[n1], weight[n2]);
+ parent[nNodes] = -1;
+ nHeap++;
+ heap[nHeap] = nNodes;
+ UPHEAP(nHeap);
}
AssertH( nNodes < (BZ_MAX_ALPHA_SIZE * 2), 2002 );
tooLong = False;
for (i = 1; i <= alphaSize; i++) {
- j = 0;
- k = i;
- while (parent[k] >= 0) { k = parent[k]; j++; }
- len[i-1] = j;
- if (j > maxLen) tooLong = True;
+ j = 0;
+ k = i;
+ while (parent[k] >= 0) { k = parent[k]; j++; }
+ len[i-1] = j;
+ if (j > maxLen) tooLong = True;
}
if (! tooLong) break;
for (i = 1; i < alphaSize; i++) {
- j = weight[i] >> 8;
- j = 1 + (j / 2);
- weight[i] = j << 8;
+ j = weight[i] >> 8;
+ j = 1 + (j / 2);
+ weight[i] = j << 8;
}
}
}
/*---------------------------------------------------*/
void BZ2_hbAssignCodes ( Int32 *code,
- UChar *length,
- Int32 minLen,
- Int32 maxLen,
- Int32 alphaSize )
+ UChar *length,
+ Int32 minLen,
+ Int32 maxLen,
+ Int32 alphaSize )
{
Int32 n, vec, i;
vec = 0;
for (n = minLen; n <= maxLen; n++) {
for (i = 0; i < alphaSize; i++)
- if (length[i] == n) { code[i] = vec; vec++; };
+ if (length[i] == n) { code[i] = vec; vec++; };
vec <<= 1;
}
}
/*---------------------------------------------------*/
void BZ2_hbCreateDecodeTables ( Int32 *limit,
- Int32 *base,
- Int32 *perm,
- UChar *length,
- Int32 minLen,
- Int32 maxLen,
- Int32 alphaSize )
+ Int32 *base,
+ Int32 *perm,
+ UChar *length,
+ Int32 minLen,
+ Int32 maxLen,
+ Int32 alphaSize )
{
Int32 pp, i, j, vec;
pp = 0;
for (i = minLen; i <= maxLen; i++)
for (j = 0; j < alphaSize; j++)
- if (length[j] == i) { perm[pp] = j; pp++; };
+ if (length[j] == i) { perm[pp] = j; pp++; };
for (i = 0; i < BZ_MAX_CODE_LEN; i++) base[i] = 0;
for (i = 0; i < alphaSize; i++) base[length[i]+1]++;
#endif
-
/*-- General stuff. --*/
#define BZ_VERSION "1.0.2, 30-Dec-2001"
#define AssertD(cond,msg) \
{ if (!(cond)) { \
fprintf ( stderr, \
- "\n\nlibbzip2(debug build): internal error\n\t%s\n", msg );\
+ "\n\nlibbzip2(debug build): internal error\n\t%s\n", msg );\
exit(1); \
}}
#else
#define BZ_MAX_SELECTORS (2 + (900000 / BZ_G_SIZE))
-
/*-- Stuff for randomising repetitive blocks. --*/
extern Int32 BZ2_rNums[512];
s->rNToGo--;
-
/*-- Stuff for doing CRCs. --*/
extern UInt32 BZ2_crc32Table[256];
#define BZ_UPDATE_CRC(crcVar,cha) \
{ \
crcVar = (crcVar << 8) ^ \
- BZ2_crc32Table[(crcVar >> 24) ^ \
- ((UChar)cha)]; \
+ BZ2_crc32Table[(crcVar >> 24) ^ \
+ ((UChar)cha)]; \
}
-
/*-- States and modes for compression. --*/
#define BZ_M_IDLE 1
#define BZ_N_OVERSHOOT (BZ_N_RADIX + BZ_N_QSORT + BZ_N_SHELL + 2)
-
-
/*-- Structure holding all the compression-side stuff. --*/
typedef
EState;
-
/*-- externs for compression. --*/
extern void
BZ2_hbMakeCodeLengths ( UChar*, Int32*, Int32, Int32 );
-
/*-- states for decompression. --*/
#define BZ_X_IDLE 1
#define BZ_X_CCRC_4 50
-
/*-- Constants for the fast MTF decoder. --*/
#define MTFA_SIZE 4096
#define MTFL_SIZE 16
-
/*-- Structure holding all the decompression-side stuff. --*/
typedef
DState;
-
/*-- Macros for decompression. --*/
#define BZ_GET_FAST(cccc) \
#define SET_LL4(i,n) \
{ if (((i) & 0x1) == 0) \
- s->ll4[(i) >> 1] = (s->ll4[(i) >> 1] & 0xf0) | (n); else \
- s->ll4[(i) >> 1] = (s->ll4[(i) >> 1] & 0x0f) | ((n) << 4); \
+ s->ll4[(i) >> 1] = (s->ll4[(i) >> 1] & 0xf0) | (n); else \
+ s->ll4[(i) >> 1] = (s->ll4[(i) >> 1] & 0x0f) | ((n) << 4); \
}
#define GET_LL4(i) \
extern void
BZ2_hbCreateDecodeTables ( Int32*, Int32*, Int32*, UChar*,
- Int32, Int32, Int32 );
+ Int32, Int32, Int32 );
#endif
#endif
#include <net.h>
#ifdef CFG_ALLOC_DPRAM
-#if !defined(CONFIG_8260)
+#if !(defined(CONFIG_8260)||defined(CONFIG_MPC8560))
#include <commproc.h>
#endif
#endif
#if defined(CONFIG_LOGBUFFER)
#include <logbuff.h>
#endif
+#if defined(CFG_INIT_RAM_LOCK) && defined(CONFIG_E500)
+#include <asm/cache.h>
+#endif
#if (CONFIG_COMMANDS & CFG_CMD_DOC)
void doc_init (void);
get_clocks, /* get CPU and bus clocks (etc.) */
init_timebase,
#ifdef CFG_ALLOC_DPRAM
-#if !defined(CONFIG_8260)
+#if !(defined(CONFIG_8260) || defined(CONFIG_MPC8560))
dpram_init,
#endif
#endif
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
-#ifndef CONFIG_8260
+#if !(defined(CONFIG_8260) || defined(CONFIG_MPC8560))
/* Clear initial global data */
memset ((void *) gd, 0, sizeof (gd_t));
#endif
bd->bi_sramsize = 0; /* FIXME */ /* size of SRAM memory */
#endif
-#if defined(CONFIG_8xx) || defined(CONFIG_8260) || defined(CONFIG_5xx)
+#if defined(CONFIG_8xx) || defined(CONFIG_8260) || defined(CONFIG_5xx) || \
+ defined(CONFIG_E500)
bd->bi_immr_base = CFG_IMMR; /* base of IMMR register */
#endif
#if defined(CONFIG_MPC5XXX)
WATCHDOG_RESET ();
bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */
bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
-#if defined(CONFIG_8260)
+#if defined(CONFIG_8260) || defined(CONFIG_MPC8560)
bd->bi_cpmfreq = gd->cpm_clk;
bd->bi_brgfreq = gd->brg_clk;
bd->bi_sccfreq = gd->scc_clk;
icache_enable (); /* it's time to enable the instruction cache */
#endif
+#if defined(CFG_INIT_RAM_LOCK) && defined(CONFIG_E500)
+ unlock_ram_in_cache(); /* it's time to unlock D-cache in e500 */
+#endif
+
#if defined(CONFIG_BAB7xx) || defined(CONFIG_CPC45)
/*
* Do PCI configuration on BAB7xx and CPC45 _before_ the flash
load_sernum_ethaddr ();
#endif
-#if defined(CFG_GT_6426x) || defined(CONFIG_PN62) || defined(CONFIG_PPCHAMELEONEVB)
+#if defined(CFG_GT_6426x) || defined(CONFIG_PN62) || defined(CONFIG_PPCHAMELEONEVB) || \
+ defined(CONFIG_MPC8540ADS) || defined(CONFIG_MPC8560ADS)
/* handle the 2nd ethernet address */
s = getenv ("eth1addr");
s = (*e) ? e + 1 : e;
}
#endif
-#if defined(CFG_GT_6426x)
+#if defined(CFG_GT_6426x) || defined(CONFIG_MPC8540ADS) || defined(CONFIG_MPC8560ADS)
/* handle the 3rd ethernet address */
s = getenv ("eth2addr");
defined(CONFIG_LWMON) || \
defined(CONFIG_MPC8260ADS) || \
defined(CONFIG_MPC8266ADS) || \
+ defined(CONFIG_MPC8560ADS) || \
defined(CONFIG_PCU_E) || \
defined(CONFIG_RPXSUPER) || \
defined(CONFIG_SPD823TS) )
extern int plb2800_eth_initialize(bd_t*);
extern int mpc5xxx_fec_initialize(bd_t*);
extern int skge_initialize(bd_t*);
+extern int tsec_initialize(bd_t*);
extern int au1x00_enet_initialize(bd_t*);
static struct eth_device *eth_devices, *eth_current;
#if defined(CONFIG_SK98)
skge_initialize(bis);
#endif
+#ifdef CONFIG_TSEC_ENET
+ tsec_initialize(bis);
+#endif
#if defined(CONFIG_AU1X00)
au1x00_enet_initialize(bis);
#endif
#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
#if defined(CFG_FAULT_ECHO_LINK_DOWN) && defined(CONFIG_STATUS_LED) && defined(STATUS_LED_RED)
/*
- * Echo the inverted link state to the fault LED.
+ * Echo the inverted link state to the fault LED.
*/
if(miiphy_link(CFG_FAULT_MII_ADDR)) {
status_led_set (STATUS_LED_RED, STATUS_LED_OFF);
#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
#if defined(CFG_FAULT_ECHO_LINK_DOWN) && defined(CONFIG_STATUS_LED) && defined(STATUS_LED_RED)
/*
- * Echo the inverted link state to the fault LED.
+ * Echo the inverted link state to the fault LED.
*/
if(miiphy_link(CFG_FAULT_MII_ADDR)) {
status_led_set (STATUS_LED_RED, STATUS_LED_OFF);
DECLARE_GLOBAL_DATA_PTR;
int bootmode = post_bootmode_get (0);
int newword;
-
+
if (post_hotkeys_pressed() && !(bootmode & POST_POWERTEST)) {
newword = BOOTMODE_MAGIC | POST_SLOWTEST;
} else if (bootmode == 0) {
projects / u-boot / commitdiff