imx: mx6: ddr add more register entry for mmdc_p_regs

Add more register entry for MMDC structure.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>

diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
index 7bfbdc3cf9206f986857ff835db624a075800fd8..f3194dadb601ae34e907297fe81a3cc3f63de75d 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
+++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
@@ -40,30 +40,77 @@ struct mmdc_p_regs {
        u32 res1[2];
        u32 mdrwd;
        u32 mdor;
-       u32 res2[3];
+       u32 mdmrr;
+       u32 mdcfg3lp;
+       u32 mdmr4;
        u32 mdasp;
-       u32 res3[240];
+       u32 res2[239];
+       u32 maarcr;
        u32 mapsr;
-       u32 res4[254];
+       u32 maexidr0;
+       u32 maexidr1;
+       u32 madpcr0;
+       u32 madpcr1;
+       u32 madpsr0;
+       u32 madpsr1;
+       u32 madpsr2;
+       u32 madpsr3;
+       u32 madpsr4;
+       u32 madpsr5;
+       u32 masbs0;
+       u32 masbs1;
+       u32 res3[2];
+       u32 magenp;
+       u32 res4[239];
        u32 mpzqhwctrl;
-       u32 res5[2];
+       u32 mpzqswctrl;
+       u32 mpwlgcr;
        u32 mpwldectrl0;
        u32 mpwldectrl1;
-       u32 res6;
+       u32 mpwldlst;
        u32 mpodtctrl;
        u32 mprddqby0dl;
        u32 mprddqby1dl;
        u32 mprddqby2dl;
        u32 mprddqby3dl;
-       u32 res7[4];
+       u32 mpwrdqby0dl;
+       u32 mpwrdqby1dl;
+       u32 mpwrdqby2dl;
+       u32 mpwrdqby3dl;
        u32 mpdgctrl0;
        u32 mpdgctrl1;
-       u32 res8;
+       u32 mpdgdlst0;
        u32 mprddlctl;
-       u32 res9;
+       u32 mprddlst;
        u32 mpwrdlctl;
-       u32 res10[25];
+       u32 mpwrdlst;
+       u32 mpsdctrl;
+       u32 mpzqlp2ctl;
+       u32 mprddlhwctl;
+       u32 mpwrdlhwctl;
+       u32 mprddlhwst0;
+       u32 mprddlhwst1;
+       u32 mpwrdlhwst0;
+       u32 mpwrdlhwst1;
+       u32 mpwlhwerr;
+       u32 mpdghwst0;
+       u32 mpdghwst1;
+       u32 mpdghwst2;
+       u32 mpdghwst3;
+       u32 mppdcmpr1;
+       u32 mppdcmpr2;
+       u32 mpswdar0;
+       u32 mpswdrdr0;
+       u32 mpswdrdr1;
+       u32 mpswdrdr2;
+       u32 mpswdrdr3;
+       u32 mpswdrdr4;
+       u32 mpswdrdr5;
+       u32 mpswdrdr6;
+       u32 mpswdrdr7;
        u32 mpmur0;
+       u32 mpwrcadl;
+       u32 mpdccr;
 };
 
 #define MX6UL_IOM_DDR_BASE     0x020e0200