#include <asm/fec.h>
#endif
-/*
- * Breath some life into the CPU...
- *
- * Set up the memory map,
- * initialize a bunch of registers,
- * initialize the UPM's
- */
-void cpu_init_f(void)
+void init_fbcs(void)
{
- scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
- gpio_t *gpio = (gpio_t *) MMAP_GPIO;
fbcs_t *fbcs __maybe_unused = (fbcs_t *) MMAP_FBCS;
- out_be32(&scm1->mpr, 0x77777777);
- out_be32(&scm1->pacra, 0);
- out_be32(&scm1->pacrb, 0);
- out_be32(&scm1->pacrc, 0);
- out_be32(&scm1->pacrd, 0);
- out_be32(&scm1->pacre, 0);
- out_be32(&scm1->pacrf, 0);
- out_be32(&scm1->pacrg, 0);
-
- /* FlexBus */
- out_8(&gpio->par_be,
- GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 |
- GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0);
- out_8(&gpio->par_fbctl,
- GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA |
- GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS);
-
-#if !defined(CONFIG_CF_SBF)
+#if !defined(CONFIG_SERIAL_BOOT)
#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
#endif
+}
+
+/*
+ * Breath some life into the CPU...
+ *
+ * Set up the memory map,
+ * initialize a bunch of registers,
+ * initialize the UPM's
+ */
+void cpu_init_f(void)
+{
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+#ifdef CONFIG_MCF5441x
+ scm_t *scm = (scm_t *) MMAP_SCM;
+ pm_t *pm = (pm_t *) MMAP_PM;
+
+ /* Disable Switch */
+ *(unsigned long *)(MMAP_L2_SW0 + 0x00000024) = 0;
+
+ /* Disable core watchdog */
+ out_be16(&scm->cwcr, 0);
+ out_8(&gpio->par_fbctl,
+ GPIO_PAR_FBCTL_ALE_FB_ALE | GPIO_PAR_FBCTL_OE_FB_OE |
+ GPIO_PAR_FBCTL_FBCLK | GPIO_PAR_FBCTL_RW |
+ GPIO_PAR_FBCTL_TA_TA);
+ out_8(&gpio->par_be,
+ GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 |
+ GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0);
+
+ /* eDMA */
+ out_8(&pm->pmcr0, 17);
+
+ /* INTR0 - INTR2 */
+ out_8(&pm->pmcr0, 18);
+ out_8(&pm->pmcr0, 19);
+ out_8(&pm->pmcr0, 20);
+
+ /* I2C */
+ out_8(&pm->pmcr0, 22);
+ out_8(&pm->pmcr1, 4);
+ out_8(&pm->pmcr1, 7);
+
+ /* DTMR0 - DTMR3*/
+ out_8(&pm->pmcr0, 28);
+ out_8(&pm->pmcr0, 29);
+ out_8(&pm->pmcr0, 30);
+ out_8(&pm->pmcr0, 31);
+
+ /* PIT0 - PIT3 */
+ out_8(&pm->pmcr0, 32);
+ out_8(&pm->pmcr0, 33);
+ out_8(&pm->pmcr0, 34);
+ out_8(&pm->pmcr0, 35);
+
+ /* Edge Port */
+ out_8(&pm->pmcr0, 36);
+ out_8(&pm->pmcr0, 37);
+
+ /* USB OTG */
+ out_8(&pm->pmcr0, 44);
+ /* USB Host */
+ out_8(&pm->pmcr0, 45);
+
+ /* ESDHC */
+ out_8(&pm->pmcr0, 51);
+
+ /* ENET0 - ENET1 */
+ out_8(&pm->pmcr0, 53);
+ out_8(&pm->pmcr0, 54);
+
+ /* NAND */
+ out_8(&pm->pmcr0, 63);
+
+#ifdef CONFIG_SYS_I2C_0
+ out_8(&gpio->par_cani2c, 0xF0);
+ /* I2C0 pull up */
+ out_be16(&gpio->pcr_b, 0x003C);
+ /* I2C0 max speed */
+ out_8(&gpio->srcr_cani2c, 0x03);
+#endif
+#ifdef CONFIG_SYS_I2C_2
+ /* I2C2 */
+ out_8(&gpio->par_ssi0h, 0xA0);
+ /* I2C2, UART7 */
+ out_8(&gpio->par_ssi0h, 0xA8);
+ /* UART7 */
+ out_8(&gpio->par_ssi0l, 0x2);
+ /* UART8, UART9 */
+ out_8(&gpio->par_cani2c, 0xAA);
+ /* UART4, UART0 */
+ out_8(&gpio->par_uart0, 0xAF);
+ /* UART5, UART1 */
+ out_8(&gpio->par_uart1, 0xAF);
+ /* UART6, UART2 */
+ out_8(&gpio->par_uart2, 0xAF);
+ /* I2C2 pull up */
+ out_be16(&gpio->pcr_h, 0xF000);
+#endif
+#ifdef CONFIG_SYS_I2C_5
+ /* I2C5 */
+ out_8(&gpio->par_uart1, 0x0A);
+ /* I2C5 pull up */
+ out_be16(&gpio->pcr_e, 0x0003);
+ out_be16(&gpio->pcr_f, 0xC000);
+#endif
+
+ /* Lowest slew rate for UART0,1,2 */
+ out_8(&gpio->srcr_uart, 0x00);
+#endif /* CONFIG_MCF5441x */
+
+#ifdef CONFIG_MCF5445x
+ scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+
+ out_be32(&scm1->mpr, 0x77777777);
+ out_be32(&scm1->pacra, 0);
+ out_be32(&scm1->pacrb, 0);
+ out_be32(&scm1->pacrc, 0);
+ out_be32(&scm1->pacrd, 0);
+ out_be32(&scm1->pacre, 0);
+ out_be32(&scm1->pacrf, 0);
+ out_be32(&scm1->pacrg, 0);
+
+ /* FlexBus */
+ out_8(&gpio->par_be,
+ GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 |
+ GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0);
+ out_8(&gpio->par_fbctl,
+ GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA |
+ GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS);
+
+#ifdef CONFIG_FSL_I2C
+ out_be16(&gpio->par_feci2c,
+ GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);
+#endif
+#endif /* CONFIG_MCF5445x */
+
+ /* FlexBus Chipselect */
+ init_fbcs();
/*
* now the flash base address is no longer at 0 (Newer ColdFire family
if (CONFIG_SYS_CS0_BASE != 0)
setvbr(CONFIG_SYS_CS0_BASE);
-#ifdef CONFIG_FSL_I2C
- out_be16(&gpio->par_feci2c,
- GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);
-#endif
-
icache_enable();
}
void uart_port_conf(int port)
{
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+#ifdef CONFIG_MCF5441x
+ pm_t *pm = (pm_t *) MMAP_PM;
+#endif
/* Setup Ports: */
switch (port) {
+#ifdef CONFIG_MCF5441x
+ case 0:
+ /* UART0 */
+ out_8(&pm->pmcr0, 24);
+ clrbits_8(&gpio->par_uart0,
+ ~(GPIO_PAR_UART0_U0RXD_MASK | GPIO_PAR_UART0_U0TXD_MASK));
+ setbits_8(&gpio->par_uart0,
+ GPIO_PAR_UART0_U0RXD_U0RXD | GPIO_PAR_UART0_U0TXD_U0TXD);
+ break;
+ case 1:
+ /* UART1 */
+ out_8(&pm->pmcr0, 25);
+ clrbits_8(&gpio->par_uart1,
+ ~(GPIO_PAR_UART1_U1RXD_MASK | GPIO_PAR_UART1_U1TXD_MASK));
+ setbits_8(&gpio->par_uart1,
+ GPIO_PAR_UART1_U1RXD_U1RXD | GPIO_PAR_UART1_U1TXD_U1TXD);
+ break;
+ case 2:
+ /* UART2 */
+ out_8(&pm->pmcr0, 26);
+ clrbits_8(&gpio->par_uart2,
+ ~(GPIO_PAR_UART2_U2RXD_MASK | GPIO_PAR_UART2_U2TXD_MASK));
+ setbits_8(&gpio->par_uart2,
+ GPIO_PAR_UART2_U2RXD_U2RXD | GPIO_PAR_UART2_U2TXD_U2TXD);
+ break;
+ case 3:
+ /* UART3 */
+ out_8(&pm->pmcr0, 27);
+ clrbits_8(&gpio->par_dspi0,
+ ~(GPIO_PAR_DSPI0_SIN_MASK | GPIO_PAR_DSPI0_SOUT_MASK));
+ setbits_8(&gpio->par_dspi0,
+ GPIO_PAR_DSPI0_SIN_U3RXD | GPIO_PAR_DSPI0_SOUT_U3TXD);
+ break;
+ case 4:
+ /* UART4 */
+ out_8(&pm->pmcr1, 24);
+ clrbits_8(&gpio->par_uart0,
+ ~(GPIO_PAR_UART0_U0CTS_MASK | GPIO_PAR_UART0_U0RTS_MASK));
+ setbits_8(&gpio->par_uart0,
+ GPIO_PAR_UART0_U0CTS_U4TXD | GPIO_PAR_UART0_U0RTS_U4RXD);
+ break;
+ case 5:
+ /* UART5 */
+ out_8(&pm->pmcr1, 25);
+ clrbits_8(&gpio->par_uart1,
+ ~(GPIO_PAR_UART1_U1CTS_MASK | GPIO_PAR_UART1_U1RTS_MASK));
+ setbits_8(&gpio->par_uart1,
+ GPIO_PAR_UART1_U1CTS_U5TXD | GPIO_PAR_UART1_U1RTS_U5RXD);
+ break;
+ case 6:
+ /* UART6 */
+ out_8(&pm->pmcr1, 26);
+ clrbits_8(&gpio->par_uart2,
+ ~(GPIO_PAR_UART2_U2CTS_MASK | GPIO_PAR_UART2_U2RTS_MASK));
+ setbits_8(&gpio->par_uart2,
+ GPIO_PAR_UART2_U2CTS_U6TXD | GPIO_PAR_UART2_U2RTS_U6RXD);
+ break;
+ case 7:
+ /* UART7 */
+ out_8(&pm->pmcr1, 27);
+ clrbits_8(&gpio->par_ssi0h, ~GPIO_PAR_SSI0H_RXD_MASK);
+ clrbits_8(&gpio->par_ssi0l, ~GPIO_PAR_SSI0L_BCLK_MASK);
+ setbits_8(&gpio->par_ssi0h, GPIO_PAR_SSI0H_FS_U7TXD);
+ setbits_8(&gpio->par_ssi0l, GPIO_PAR_SSI0L_BCLK_U7RXD);
+ break;
+ case 8:
+ /* UART8 */
+ out_8(&pm->pmcr0, 28);
+ clrbits_8(&gpio->par_cani2c,
+ ~(GPIO_PAR_CANI2C_I2C0SCL_MASK | GPIO_PAR_CANI2C_I2C0SDA_MASK));
+ setbits_8(&gpio->par_cani2c,
+ GPIO_PAR_CANI2C_I2C0SCL_U8TXD | GPIO_PAR_CANI2C_I2C0SDA_U8RXD);
+ break;
+ case 9:
+ /* UART9 */
+ out_8(&pm->pmcr1, 29);
+ clrbits_8(&gpio->par_cani2c,
+ ~(GPIO_PAR_CANI2C_CAN1TX_MASK | GPIO_PAR_CANI2C_CAN1RX_MASK));
+ setbits_8(&gpio->par_cani2c,
+ GPIO_PAR_CANI2C_CAN1TX_U9TXD | GPIO_PAR_CANI2C_CAN1RX_U9RXD);
+ break;
+#endif
+#ifdef CONFIG_MCF5445x
case 0:
clrbits_8(&gpio->par_uart,
GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
GPIO_PAR_FECI2C_SCL_U2TXD | GPIO_PAR_FECI2C_SDA_U2RXD);
#endif
break;
+#endif /* CONFIG_MCF5445x */
}
}
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
struct fec_info_s *info = (struct fec_info_s *)dev->priv;
+#ifdef CONFIG_MCF5445x
if (setclear) {
#ifdef CONFIG_SYS_FEC_NO_SHARED_PHY
if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
#endif
}
}
+#endif /* CONFIG_MCF5445x */
+
+#ifdef CONFIG_MCF5441x
+ if (setclear) {
+ out_8(&gpio->par_fec, 0x03);
+ out_8(&gpio->srcr_fec, 0x0F);
+ clrsetbits_8(&gpio->par_simp0h, ~GPIO_PAR_SIMP0H_DAT_MASK,
+ GPIO_PAR_SIMP0H_DAT_GPIO);
+ clrsetbits_8(&gpio->pddr_g, ~GPIO_PDDR_G4_MASK,
+ GPIO_PDDR_G4_OUTPUT);
+ clrbits_8(&gpio->podr_g, ~GPIO_PODR_G4_MASK);
+
+ } else
+ clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC_MASK);
+#endif
return 0;
}
#endif
{
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+#ifdef CONFIG_MCF5445x
out_8(&gpio->par_dspi,
GPIO_PAR_DSPI_SIN_SIN |
GPIO_PAR_DSPI_SOUT_SOUT |
GPIO_PAR_DSPI_SCK_SCK);
+#endif
+
+#ifdef CONFIG_MCF5441x
+ pm_t *pm = (pm_t *) MMAP_PM;
+
+ out_8(&gpio->par_dspi0,
+ GPIO_PAR_DSPI0_SIN_DSPI0SIN | GPIO_PAR_DSPI0_SOUT_DSPI0SOUT |
+ GPIO_PAR_DSPI0_SCK_DSPI0SCK);
+ out_8(&gpio->srcr_dspiow, 3);
+
+ /* DSPI0 */
+ out_8(&pm->pmcr0, 23);
+#endif
}
int cfspi_claim_bus(uint bus, uint cs)
/* Clear FIFO and resume transfer */
clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
+#ifdef CONFIG_MCF5445x
switch (cs) {
case 0:
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
break;
}
+#endif
+
+#ifdef CONFIG_MCF5441x
+ switch (cs) {
+ case 0:
+ clrbits_8(&gpio->par_dspi0, ~GPIO_PAR_DSPI0_PCS0_MASK);
+ setbits_8(&gpio->par_dspi0, GPIO_PAR_DSPI0_PCS0_DSPI0PCS0);
+ break;
+ case 1:
+ clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
+ setbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
+ break;
+ }
+#endif
return 0;
}
/* Clear FIFO */
clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
+#ifdef CONFIG_MCF5445x
switch (cs) {
case 0:
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
break;
}
+#endif
+
+#ifdef CONFIG_MCF5441x
+ if (cs == 1)
+ clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
+#endif
}
#endif
* Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
* Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
*
+ * Copyright 2010-2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
* MA 02111-1307 USA
*/
+#include <common.h>
#include <asm-offsets.h>
#include <config.h>
+#include <timestamp.h>
#include "version.h"
#include <asm/cache.h>
addl #60,%sp; /* space for 15 regs */ \
rte;
-#if defined(CONFIG_CF_SBF)
+#if defined(CONFIG_SERIAL_BOOT)
#define ASM_DRAMINIT (asm_dram_init - CONFIG_SYS_TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
+#define ASM_DRAMINIT_N (asm_dram_init - TEXT_BASE)
#define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - CONFIG_SYS_TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
#endif
* These vectors are to catch any un-intended traps.
*/
_vectors:
-#if defined(CONFIG_CF_SBF)
+#if defined(CONFIG_SERIAL_BOOT)
INITSP: .long 0 /* Initial SP */
+#ifdef CONFIG_CF_SBF
INITPC: .long ASM_DRAMINIT /* Initial PC */
+#endif
+#ifdef CONFIG_SYS_NAND_BOOT
+INITPC: .long ASM_DRAMINIT_N /* Initial PC */
+#endif
#else
vector1E: .long _FAULT /* Autovector Level 6 */
vector1F: .long _FAULT /* Autovector Level 7 */
-#if !defined(CONFIG_CF_SBF)
+#if !defined(CONFIG_SERIAL_BOOT)
/* TRAP #0 - #15 */
vector20_2F:
.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
#endif
-#if defined(CONFIG_CF_SBF)
+#if defined(CONFIG_SERIAL_BOOT)
/* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */
asm_sbf_img_hdr:
.long 0x00000000 /* checksum, not yet implemented */
- .long 0x00030000 /* image length */
+ .long 0x00040000 /* image length */
.long CONFIG_SYS_TEXT_BASE /* image to be relocated at */
asm_dram_init:
move.w #0x2700,%sr /* Mask off Interrupt */
+#ifdef CONFIG_SYS_NAND_BOOT
+ /* for assembly stack */
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+ movec %d0, %RAMBAR1
+
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
+ clr.l %sp@-
+#endif
+
+#ifdef CONFIG_CF_SBF
move.l #CONFIG_SYS_INIT_RAM_ADDR, %d0
movec %d0, %VBR
move.l #(CONFIG_SYS_CS0_CTRL), (%a1)
move.l #0xFC008004, %a1
move.l #(CONFIG_SYS_CS0_MASK), (%a1)
+#endif /* CONFIG_CF_SBF */
+
+#ifdef CONFIG_MCF5441x
+ /* TC: enable all peripherals,
+ in the future only enable certain peripherals */
+ move.l #0xFC04002D, %a1
+#if defined(CONFIG_CF_SBF)
+ move.b #23, (%a1) /* dspi */
+#endif
+ move.b #46, (%a1) /* DDR */
+
+ /* slew settings */
+ move.l #0xEC094060, %a1
+ move.b #0, (%a1)
+
+ /* use vco instead of cpu*2 clock for ddr clock */
+ move.l #0xEC09001A, %a1
+ move.w #0xE01D, (%a1)
+
+ /* DDR settings */
+ move.l #0xFC0B8180, %a1
+ move.l #0x00000000, (%a1)
+ move.l #0x40000000, (%a1)
+
+ move.l #0xFC0B81AC, %a1
+ move.l #0x01030203, (%a1)
+
+ move.l #0xFC0B8000, %a1
+ move.l #0x01010101, (%a1)+ /* 0x00 */
+ move.l #0x00000101, (%a1)+ /* 0x04 */
+ move.l #0x01010100, (%a1)+ /* 0x08 */
+ move.l #0x01010000, (%a1)+ /* 0x0C */
+ move.l #0x00010101, (%a1)+ /* 0x10 */
+ move.l #0xFC0B8018, %a1
+ move.l #0x00010100, (%a1)+ /* 0x18 */
+ move.l #0x00000001, (%a1)+ /* 0x1C */
+ move.l #0x01000001, (%a1)+ /* 0x20 */
+ move.l #0x00000100, (%a1)+ /* 0x24 */
+ move.l #0x00010001, (%a1)+ /* 0x28 */
+ move.l #0x00000200, (%a1)+ /* 0x2C */
+ move.l #0x01000002, (%a1)+ /* 0x30 */
+ move.l #0x00000000, (%a1)+ /* 0x34 */
+ move.l #0x00000100, (%a1)+ /* 0x38 */
+ move.l #0x02000100, (%a1)+ /* 0x3C */
+ move.l #0x02000407, (%a1)+ /* 0x40 */
+ move.l #0x02030007, (%a1)+ /* 0x44 */
+ move.l #0x02000100, (%a1)+ /* 0x48 */
+ move.l #0x0A030203, (%a1)+ /* 0x4C */
+ move.l #0x00020708, (%a1)+ /* 0x50 */
+ move.l #0x00050008, (%a1)+ /* 0x54 */
+ move.l #0x04030002, (%a1)+ /* 0x58 */
+ move.l #0x00000004, (%a1)+ /* 0x5C */
+ move.l #0x020A0000, (%a1)+ /* 0x60 */
+ move.l #0x0C00000E, (%a1)+ /* 0x64 */
+ move.l #0x00002004, (%a1)+ /* 0x68 */
+ move.l #0x00000000, (%a1)+ /* 0x6C */
+ move.l #0x00100010, (%a1)+ /* 0x70 */
+ move.l #0x00100010, (%a1)+ /* 0x74 */
+ move.l #0x00000000, (%a1)+ /* 0x78 */
+ move.l #0x07990000, (%a1)+ /* 0x7C */
+ move.l #0xFC0B80A0, %a1
+ move.l #0x00000000, (%a1)+ /* 0xA0 */
+ move.l #0x00C80064, (%a1)+ /* 0xA4 */
+ move.l #0x44520002, (%a1)+ /* 0xA8 */
+ move.l #0x00C80023, (%a1)+ /* 0xAC */
+ move.l #0xFC0B80B4, %a1
+ move.l #0x0000C350, (%a1) /* 0xB4 */
+ move.l #0xFC0B80E0, %a1
+ move.l #0x04000000, (%a1)+ /* 0xE0 */
+ move.l #0x03000304, (%a1)+ /* 0xE4 */
+ move.l #0x40040000, (%a1)+ /* 0xE8 */
+ move.l #0xC0004004, (%a1)+ /* 0xEC */
+ move.l #0x0642C000, (%a1)+ /* 0xF0 */
+ move.l #0x00000642, (%a1)+ /* 0xF4 */
+ move.l #0xFC0B8024, %a1
+ tpf
+ move.l #0x01000100, (%a1) /* 0x24 */
+
+ move.l #0x2000, %d1
+ jsr asm_delay
+#endif /* CONFIG_MCF5441x */
+
+#ifdef CONFIG_MCF5445x
/* Dram Initialization a1, a2, and d0 */
/* mscr sdram */
move.l #0xFC0A4074, %a1
add.l #1, %d1
cmp.l #1, %d2
bne dramsz_loop
-
+#ifdef CONFIG_SYS_NAND_BOOT
+ beq asm_nand_chk_status
+#endif
/* SDRAM Chip 0 and 1 */
move.l #(CONFIG_SYS_SDRAM_BASE), (%a1)
or.l %d1, (%a1)
move.l #2000, %d1
jsr asm_delay
+#endif /* CONFIG_MCF5445x */
+#ifdef CONFIG_CF_SBF
/*
* DSPI Initialization
* a0 - general, sram - 0x80008000 - 32, see M54455EVB.h
*/
/* Enable pins for DSPI mode - chip-selects are enabled later */
asm_dspi_init:
+#ifdef CONFIG_MCF5441x
+ move.l #0xEC09404E, %a1
+ move.l #0xEC09404F, %a2
+ move.b #0xFF, (%a1)
+ move.b #0x80, (%a2)
+#endif
+
+#ifdef CONFIG_MCF5445x
move.l #0xFC0A4063, %a0
move.b #0x7F, (%a0)
-
+#endif
/* Configure DSPI module */
move.l #0xFC05C000, %a0
move.l #0x80FF0C00, (%a0) /* Master, clear TX/RX FIFO */
move.l #0xFC05C00C, %a0
+#ifdef CONFIG_MCF5441x
+ move.l #0x3E000016, (%a0)
+#endif
+#ifdef CONFIG_MCF5445x
move.l #0x3E000011, (%a0)
+#endif
move.l #0xFC05C034, %a2 /* dtfr */
move.l #0xFC05C03B, %a3 /* drfr */
move.b (%a3), %d1
rts
+#endif /* CONFIG_CF_SBF */
+
+#ifdef CONFIG_SYS_NAND_BOOT
+ /* copy 4 boot pages to dram as soon as possible */
+ /* each page is 996 bytes (1056 total with 60 ECC bytes */
+ move.l #0x00000000, %a1 /* src */
+ move.l #TEXT_BASE, %a2 /* dst */
+ move.l #0x3E0, %d0 /* sz in long */
+
+asm_boot_nand_copy:
+ move.l (%a1)+, (%a2)+
+ subq.l #1, %d0
+ bne asm_boot_nand_copy
+
+ /* jump to memory and execute */
+ move.l #(asm_nand_init), %a0
+ jmp (%a0)
+
+asm_nand_init:
+ /* exit nand boot-mode */
+ move.l #0xFC0FFF30, %a1
+ or.l #0x00000040, %d1
+ move.l %d1, (%a1)
+
+ /* initialize general use internal ram */
+ move.l #0, %d0
+ move.l #(CACR_STATUS), %a1 /* CACR */
+ move.l #(ICACHE_STATUS), %a2 /* icache */
+ move.l #(DCACHE_STATUS), %a3 /* dcache */
+ move.l %d0, (%a1)
+ move.l %d0, (%a2)
+ move.l %d0, (%a3)
+
+ /* invalidate and disable cache */
+ move.l #0x01004100, %d0 /* Invalidate cache cmd */
+ movec %d0, %CACR /* Invalidate cache */
+ move.l #0, %d0
+ movec %d0, %ACR0
+ movec %d0, %ACR1
+ movec %d0, %ACR2
+ movec %d0, %ACR3
+
+ /* Must disable global address */
+ move.l #0xFC008000, %a1
+ move.l #(CONFIG_SYS_CS0_BASE), (%a1)
+ move.l #0xFC008008, %a1
+ move.l #(CONFIG_SYS_CS0_CTRL), (%a1)
+ move.l #0xFC008004, %a1
+ move.l #(CONFIG_SYS_CS0_MASK), (%a1)
+
+ /* NAND port configuration */
+ move.l #0xEC094048, %a1
+ move.b #0xFD, (%a1)+
+ move.b #0x5F, (%a1)+
+ move.b #0x04, (%a1)+
+
+ /* reset nand */
+ move.l #0xFC0FFF38, %a1 /* isr */
+ move.l #0x000e0000, (%a1)
+ move.l #0xFC0FFF08, %a2
+ move.l #0x00000000, (%a2)+ /* car */
+ move.l #0x11000000, (%a2)+ /* rar */
+ move.l #0x00000000, (%a2)+ /* rpt */
+ move.l #0x00000000, (%a2)+ /* rai */
+ move.l #0xFC0FFF2c, %a2 /* cfg */
+ move.l #0x00000000, (%a2)+ /* secsz */
+ move.l #0x000e0681, (%a2)+
+ move.l #0xFC0FFF04, %a2 /* cmd2 */
+ move.l #0xFF404001, (%a2)
+ move.l #0x000e0000, (%a1)
+
+ move.l #0x2000, %d1
+ jsr asm_delay
+
+ /* setup nand */
+ move.l #0xFC0FFF00, %a1
+ move.l #0x30700000, (%a1)+ /* cmd1 */
+ move.l #0x007EF000, (%a1)+ /* cmd2 */
+
+ move.l #0xFC0FFF2C, %a1
+ move.l #0x00000841, (%a1)+ /* secsz */
+ move.l #0x000e0681, (%a1)+ /* cfg */
+
+ move.l #100, %d4 /* 100 pages ~200KB */
+ move.l #4, %d2 /* start at 4 */
+ move.l #0xFC0FFF04, %a0 /* cmd2 */
+ move.l #0xFC0FFF0C, %a1 /* rar */
+ move.l #(TEXT_BASE + 0xF80), %a2 /* dst */
+
+asm_nand_read:
+ move.l #0x11000000, %d0 /* rar */
+ or.l %d2, %d0
+ move.l %d0, (%a1)
+ add.l #1, %d2
+
+ move.l (%a0), %d0 /* cmd2 */
+ or.l #1, %d0
+ move.l %d0, (%a0)
+
+ move.l #0x200, %d1
+ jsr asm_delay
+
+asm_nand_chk_status:
+ move.l #0xFC0FFF38, %a4 /* isr */
+ move.l (%a4), %d0
+ and.l #0x40000000, %d0
+ tst.l %d0
+ beq asm_nand_chk_status
+
+ move.l #0xFC0FFF38, %a4 /* isr */
+ move.l (%a4), %d0
+ or.l #0x000E0000, %d0
+ move.l %d0, (%a4)
+
+ move.l #0x200, %d3
+ move.l #0xFC0FC000, %a3 /* buf 1 */
+asm_nand_copy:
+ move.l (%a3)+, (%a2)+
+ subq.l #1, %d3
+ bgt asm_nand_copy
+
+ subq.l #1, %d4
+ bgt asm_nand_read
+
+ /* jump to memory and execute */
+ move.l #(TEXT_BASE + 0x400), %a0
+ jmp (%a0)
+
+#endif /* CONFIG_SYS_NAND_BOOT */
asm_delay:
nop
subq.l #1, %d1
bne asm_delay
rts
-#endif /* CONFIG_CF_SBF */
+#endif /* CONFIG_CF_SBF || CONFIG_NAND_U_BOOT */
.text
. = 0x400
.globl _start
_start:
-#if !defined(CONFIG_CF_SBF)
+#if !defined(CONFIG_SERIAL_BOOT)
nop
nop
move.w #0x2700,%sr /* Mask off Interrupt */
movec %d0, %ACR1
movec %d0, %ACR2
movec %d0, %ACR3
+#else
+ move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+ movec %d0, %RAMBAR1
+#endif
/* set stackpointer to end of internal ram to get some stackspace for
the first c-code */
move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
clr.l %sp@-
-#endif
move.l #__got_start, %a5 /* put relocation table address to a5 */
--- /dev/null
+/*
+ * MCF5441x Internal Memory Map
+ *
+ * Copyright 2010-2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IMMAP_5441X__
+#define __IMMAP_5441X__
+
+/* Module Base Addresses */
+#define MMAP_XBS 0xFC004000
+#define MMAP_FBCS 0xFC008000
+#define MMAP_CAN0 0xFC020000
+#define MMAP_CAN1 0xFC024000
+#define MMAP_I2C1 0xFC038000
+#define MMAP_DSPI1 0xFC03C000
+#define MMAP_SCM 0xFC040000
+#define MMAP_PM 0xFC04002C
+#define MMAP_EDMA 0xFC044000
+#define MMAP_INTC0 0xFC048000
+#define MMAP_INTC1 0xFC04C000
+#define MMAP_INTC2 0xFC050000
+#define MMAP_IACK 0xFC054000
+#define MMAP_I2C0 0xFC058000
+#define MMAP_DSPI0 0xFC05C000
+#define MMAP_UART0 0xFC060000
+#define MMAP_UART1 0xFC064000
+#define MMAP_UART2 0xFC068000
+#define MMAP_UART3 0xFC06C000
+#define MMAP_DTMR0 0xFC070000
+#define MMAP_DTMR1 0xFC074000
+#define MMAP_DTMR2 0xFC078000
+#define MMAP_DTMR3 0xFC07C000
+#define MMAP_PIT0 0xFC080000
+#define MMAP_PIT1 0xFC084000
+#define MMAP_PIT2 0xFC088000
+#define MMAP_PIT3 0xFC08C000
+#define MMAP_EPORT0 0xFC090000
+#define MMAP_ADC 0xFC094000
+#define MMAP_DAC0 0xFC098000
+#define MMAP_DAC1 0xFC09C000
+#define MMAP_RRTC 0xFC0A8000
+#define MMAP_SIM 0xFC0AC000
+#define MMAP_USBOTG 0xFC0B0000
+#define MMAP_USBEHCI 0xFC0B4000
+#define MMAP_SDRAM 0xFC0B8000
+#define MMAP_SSI0 0xFC0BC000
+#define MMAP_PLL 0xFC0C0000
+#define MMAP_RNG 0xFC0C4000
+#define MMAP_SSI1 0xFC0C8000
+#define MMAP_ESDHC 0xFC0CC000
+#define MMAP_FEC0 0xFC0D4000
+#define MMAP_FEC1 0xFC0D8000
+#define MMAP_L2_SW0 0xFC0DC000
+#define MMAP_L2_SW1 0xFC0E0000
+
+#define MMAP_NFC_RAM 0xFC0FC000
+#define MMAP_NFC 0xFC0FF000
+
+#define MMAP_1WIRE 0xEC008000
+#define MMAP_I2C2 0xEC010000
+#define MMAP_I2C3 0xEC014000
+#define MMAP_I2C4 0xEC018000
+#define MMAP_I2C5 0xEC01C000
+#define MMAP_DSPI2 0xEC038000
+#define MMAP_DSPI3 0xEC03C000
+#define MMAP_UART4 0xEC060000
+#define MMAP_UART5 0xEC064000
+#define MMAP_UART6 0xEC068000
+#define MMAP_UART7 0xEC06C000
+#define MMAP_UART8 0xEC070000
+#define MMAP_UART9 0xEC074000
+#define MMAP_RCM 0xEC090000
+#define MMAP_CCM 0xEC090000
+#define MMAP_GPIO 0xEC094000
+
+#include <asm/coldfire/crossbar.h>
+#include <asm/coldfire/dspi.h>
+#include <asm/coldfire/edma.h>
+#include <asm/coldfire/eport.h>
+#include <asm/coldfire/flexbus.h>
+#include <asm/coldfire/flexcan.h>
+#include <asm/coldfire/intctrl.h>
+#include <asm/coldfire/ssi.h>
+
+/* Serial Boot Facility (SBF) */
+typedef struct sbf {
+ u8 resv0[0x18];
+ u16 sbfsr; /* Serial Boot Facility Status */
+ u8 resv1[0x6];
+ u16 sbfcr; /* Serial Boot Facility Control */
+} sbf_t;
+
+/* Reset Controller Module (RCM) */
+typedef struct rcm {
+ u8 rcr;
+ u8 rsr;
+} rcm_t;
+
+/* Chip Configuration Module (CCM) */
+typedef struct ccm {
+ u8 ccm_resv0[0x4]; /* 0x00 */
+ u16 ccr; /* 0x04 Chip Configuration */
+ u8 resv1[0x2]; /* 0x06 */
+ u16 rcon; /* 0x08 Reset Configuration */
+ u16 cir; /* 0x0A Chip Identification */
+ u8 resv2[0x2]; /* 0x0C */
+ u16 misccr; /* 0x0E Miscellaneous Control */
+ u16 cdrh; /* 0x10 Clock Divider */
+ u16 cdrl; /* 0x12 Clock Divider */
+ u16 uocsr; /* 0x14 USB On-the-Go Controller Status */
+ u16 uhcsr; /* 0x16 */
+ u16 misccr3; /* 0x18 */
+ u16 misccr2; /* 0x1A */
+ u16 adctsr; /* 0x1C */
+ u16 dactsr; /* 0x1E */
+ u16 sbfsr; /* 0x20 */
+ u16 sbfcr; /* 0x22 */
+ u32 fnacr; /* 0x24 */
+} ccm_t;
+
+/* General Purpose I/O Module (GPIO) */
+typedef struct gpio {
+ u8 podr_a; /* 0x00 */
+ u8 podr_b; /* 0x01 */
+ u8 podr_c; /* 0x02 */
+ u8 podr_d; /* 0x03 */
+ u8 podr_e; /* 0x04 */
+ u8 podr_f; /* 0x05 */
+ u8 podr_g; /* 0x06 */
+ u8 podr_h; /* 0x07 */
+ u8 podr_i; /* 0x08 */
+ u8 podr_j; /* 0x09 */
+ u8 podr_k; /* 0x0A */
+ u8 rsvd0; /* 0x0B */
+
+ u8 pddr_a; /* 0x0C */
+ u8 pddr_b; /* 0x0D */
+ u8 pddr_c; /* 0x0E */
+ u8 pddr_d; /* 0x0F */
+ u8 pddr_e; /* 0x10 */
+ u8 pddr_f; /* 0x11 */
+ u8 pddr_g; /* 0x12 */
+ u8 pddr_h; /* 0x13 */
+ u8 pddr_i; /* 0x14 */
+ u8 pddr_j; /* 0x15 */
+ u8 pddr_k; /* 0x16 */
+ u8 rsvd1; /* 0x17 */
+
+ u8 ppdsdr_a; /* 0x18 */
+ u8 ppdsdr_b; /* 0x19 */
+ u8 ppdsdr_c; /* 0x1A */
+ u8 ppdsdr_d; /* 0x1B */
+ u8 ppdsdr_e; /* 0x1C */
+ u8 ppdsdr_f; /* 0x1D */
+ u8 ppdsdr_g; /* 0x1E */
+ u8 ppdsdr_h; /* 0x1F */
+ u8 ppdsdr_i; /* 0x20 */
+ u8 ppdsdr_j; /* 0x21 */
+ u8 ppdsdr_k; /* 0x22 */
+ u8 rsvd2; /* 0x23 */
+
+ u8 pclrr_a; /* 0x24 */
+ u8 pclrr_b; /* 0x25 */
+ u8 pclrr_c; /* 0x26 */
+ u8 pclrr_d; /* 0x27 */
+ u8 pclrr_e; /* 0x28 */
+ u8 pclrr_f; /* 0x29 */
+ u8 pclrr_g; /* 0x2A */
+ u8 pclrr_h; /* 0x2B */
+ u8 pclrr_i; /* 0x2C */
+ u8 pclrr_j; /* 0x2D */
+ u8 pclrr_k; /* 0x2E */
+ u8 rsvd3; /* 0x2F */
+
+ u16 pcr_a; /* 0x30 */
+ u16 pcr_b; /* 0x32 */
+ u16 pcr_c; /* 0x34 */
+ u16 pcr_d; /* 0x36 */
+ u16 pcr_e; /* 0x38 */
+ u16 pcr_f; /* 0x3A */
+ u16 pcr_g; /* 0x3C */
+ u16 pcr_h; /* 0x3E */
+ u16 pcr_i; /* 0x40 */
+ u16 pcr_j; /* 0x42 */
+ u16 pcr_k; /* 0x44 */
+ u16 rsvd4; /* 0x46 */
+
+ u8 par_fbctl; /* 0x48 */
+ u8 par_be; /* 0x49 */
+ u8 par_cs; /* 0x4A */
+ u8 par_cani2c; /* 0x4B */
+ u8 par_irqh; /* 0x4C */
+ u8 par_irql; /* 0x4D */
+ u8 par_dspi0; /* 0x4E */
+ u8 par_dspiow; /* 0x4F */
+ u8 par_timer; /* 0x50 */
+ u8 par_uart2; /* 0x51 */
+ u8 par_uart1; /* 0x52 */
+ u8 par_uart0; /* 0x53 */
+ u8 par_sdhch; /* 0x54 */
+ u8 par_sdhcl; /* 0x55 */
+ u8 par_simp0h; /* 0x56 */
+ u8 par_simp1h; /* 0x57 */
+ u8 par_ssi0h; /* 0x58 */
+ u8 par_ssi0l; /* 0x59 */
+ u8 par_dbg1h; /* 0x5A */
+ u8 par_dbg0h; /* 0x5B */
+ u8 par_dbgl; /* 0x5C */
+ u8 rsvd5; /* 0x5D */
+ u8 par_fec; /* 0x5E */
+ u8 rsvd6; /* 0x5F */
+
+ u8 mscr_sdram; /* 0x60 */
+ u8 rsvd7[3]; /* 0x61-0x63 */
+
+ u8 srcr_fb1; /* 0x64 */
+ u8 srcr_fb2; /* 0x65 */
+ u8 srcr_fb3; /* 0x66 */
+ u8 srcr_fb4; /* 0x67 */
+ u8 srcr_dspiow; /* 0x68 */
+ u8 srcr_cani2c; /* 0x69 */
+ u8 srcr_irq; /* 0x6A */
+ u8 srcr_timer; /* 0x6B */
+ u8 srcr_uart; /* 0x6C */
+ u8 srcr_fec; /* 0x6D */
+ u8 srcr_sdhc; /* 0x6E */
+ u8 srcr_simp0; /* 0x6F */
+ u8 srcr_ssi0; /* 0x70 */
+ u8 rsvd8[3]; /* 0x71-0x73 */
+
+ u16 urts_pol; /* 0x74 */
+ u16 ucts_pol; /* 0x76 */
+ u16 utxd_wom; /* 0x78 */
+ u32 urxd_wom; /* 0x7c */
+
+ u32 hcr1; /* 0x80 */
+ u32 hcr0; /* 0x84 */
+} gpio_t;
+
+/* SDRAM Controller (SDRAMC) */
+typedef struct sdramc {
+ u32 cr00; /* 0x00 */
+ u32 cr01; /* 0x04 */
+ u32 cr02; /* 0x08 */
+ u32 cr03; /* 0x0C */
+ u32 cr04; /* 0x10 */
+ u32 cr05; /* 0x14 */
+ u32 cr06; /* 0x18 */
+ u32 cr07; /* 0x1C */
+
+ u32 cr08; /* 0x20 */
+ u32 cr09; /* 0x24 */
+ u32 cr10; /* 0x28 */
+ u32 cr11; /* 0x2C */
+ u32 cr12; /* 0x30 */
+ u32 cr13; /* 0x34 */
+ u32 cr14; /* 0x38 */
+ u32 cr15; /* 0x3C */
+
+ u32 cr16; /* 0x40 */
+ u32 cr17; /* 0x44 */
+ u32 cr18; /* 0x48 */
+ u32 cr19; /* 0x4C */
+ u32 cr20; /* 0x50 */
+ u32 cr21; /* 0x54 */
+ u32 cr22; /* 0x58 */
+ u32 cr23; /* 0x5C */
+
+ u32 cr24; /* 0x60 */
+ u32 cr25; /* 0x64 */
+ u32 cr26; /* 0x68 */
+ u32 cr27; /* 0x6C */
+ u32 cr28; /* 0x70 */
+ u32 cr29; /* 0x74 */
+ u32 cr30; /* 0x78 */
+ u32 cr31; /* 0x7C */
+
+ u32 cr32; /* 0x80 */
+ u32 cr33; /* 0x84 */
+ u32 cr34; /* 0x88 */
+ u32 cr35; /* 0x8C */
+ u32 cr36; /* 0x90 */
+ u32 cr37; /* 0x94 */
+ u32 cr38; /* 0x98 */
+ u32 cr39; /* 0x9C */
+
+ u32 cr40; /* 0xA0 */
+ u32 cr41; /* 0xA4 */
+ u32 cr42; /* 0xA8 */
+ u32 cr43; /* 0xAC */
+ u32 cr44; /* 0xB0 */
+ u32 cr45; /* 0xB4 */
+ u32 cr46; /* 0xB8 */
+ u32 cr47; /* 0xBC */
+ u32 cr48; /* 0xC0 */
+ u32 cr49; /* 0xC4 */
+ u32 cr50; /* 0xC8 */
+ u32 cr51; /* 0xCC */
+ u32 cr52; /* 0xD0 */
+ u32 cr53; /* 0xD4 */
+ u32 cr54; /* 0xD8 */
+ u32 cr55; /* 0xDC */
+ u32 cr56; /* 0xE0 */
+ u32 cr57; /* 0xE4 */
+ u32 cr58; /* 0xE8 */
+ u32 cr59; /* 0xEC */
+ u32 cr60; /* 0xF0 */
+ u32 cr61; /* 0xF4 */
+ u32 cr62; /* 0xF8 */
+ u32 cr63; /* 0xFC */
+
+ u32 rsvd3[32]; /* 0xF4-0x1A8 */
+
+ u32 rcrcr; /* 0x180 */
+ u32 swrcr; /* 0x184 */
+ u32 rcr; /* 0x188 */
+ u32 msovr; /* 0x18C */
+ u32 rcrdbg; /* 0x190 */
+ u32 sl0adj; /* 0x194 */
+ u32 sl1adj; /* 0x198 */
+ u32 sl2adj; /* 0x19C */
+ u32 sl3adj; /* 0x1A0 */
+ u32 sl4adj; /* 0x1A4 */
+ u32 flight_tm; /* 0x1A8 */
+ u32 padcr; /* 0x1AC */
+} sdramc_t;
+
+/* Phase Locked Loop (PLL) */
+typedef struct pll {
+ u32 pcr; /* Control */
+ u32 pdr; /* Divider */
+ u32 psr; /* Status */
+} pll_t;
+
+typedef struct scm {
+ u8 rsvd1[19]; /* 0x00 - 0x12 */
+ u8 wcr; /* 0x13 */
+ u16 rsvd2; /* 0x14 - 0x15 */
+ u16 cwcr; /* 0x16 */
+ u8 rsvd3[3]; /* 0x18 - 0x1A */
+ u8 cwsr; /* 0x1B */
+ u8 rsvd4[3]; /* 0x1C - 0x1E */
+ u8 scmisr; /* 0x1F */
+ u32 rsvd5; /* 0x20 - 0x23 */
+ u32 bcr; /* 0x24 */
+ u8 rsvd6[72]; /* 0x28 - 0x6F */
+ u32 cfadr; /* 0x70 */
+ u8 rsvd7; /* 0x74 */
+ u8 cfier; /* 0x75 */
+ u8 cfloc; /* 0x76 */
+ u8 cfatr; /* 0x77 */
+ u32 rsvd8; /* 0x78 - 0x7B */
+ u32 cfdtr; /* 0x7C */
+} scm_t;
+
+typedef struct pm {
+ u8 pmsr0; /* */
+ u8 pmcr0;
+ u8 pmsr1;
+ u8 pmcr1;
+ u32 pmhr0;
+ u32 pmlr0;
+ u32 pmhr1;
+ u32 pmlr1;
+} pm_t;
+
+#endif /* __IMMAP_5441X__ */
--- /dev/null
+/*
+ * MCF5441X Internal Memory Map
+ *
+ * Copyright 2010-2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MCF5441X__
+#define __MCF5441X__
+
+/* Interrupt Controller (INTC) */
+#define INT0_LO_RSVD0 (0)
+#define INT0_LO_EPORT1 (1)
+#define INT0_LO_EPORT2 (2)
+#define INT0_LO_EPORT3 (3)
+#define INT0_LO_EPORT4 (4)
+#define INT0_LO_EPORT5 (5)
+#define INT0_LO_EPORT6 (6)
+#define INT0_LO_EPORT7 (7)
+#define INT0_LO_EDMA_00 (8)
+#define INT0_LO_EDMA_01 (9)
+#define INT0_LO_EDMA_02 (10)
+#define INT0_LO_EDMA_03 (11)
+#define INT0_LO_EDMA_04 (12)
+#define INT0_LO_EDMA_05 (13)
+#define INT0_LO_EDMA_06 (14)
+#define INT0_LO_EDMA_07 (15)
+#define INT0_LO_EDMA_08 (16)
+#define INT0_LO_EDMA_09 (17)
+#define INT0_LO_EDMA_10 (18)
+#define INT0_LO_EDMA_11 (19)
+#define INT0_LO_EDMA_12 (20)
+#define INT0_LO_EDMA_13 (21)
+#define INT0_LO_EDMA_14 (22)
+#define INT0_LO_EDMA_15 (23)
+#define INT0_LO_EDMA_ERR (24)
+#define INT0_LO_SCM (25)
+#define INT0_LO_UART0 (26)
+#define INT0_LO_UART1 (27)
+#define INT0_LO_UART2 (28)
+#define INT0_LO_UART3 (29)
+#define INT0_LO_I2C0 (30)
+#define INT0_LO_DSPI0 (31)
+#define INT0_HI_DTMR0 (32)
+#define INT0_HI_DTMR1 (33)
+#define INT0_HI_DTMR2 (34)
+#define INT0_HI_DTMR3 (35)
+#define INT0_HI_MACNET0_TXF (36)
+#define INT0_HI_MACNET0_TXB (37)
+#define INT0_HI_MACNET0_UN (38)
+#define INT0_HI_MACNET0_RL (39)
+#define INT0_HI_MACNET0_RXF (40)
+#define INT0_HI_MACNET0_RXB (41)
+#define INT0_HI_MACNET0_MII (42)
+#define INT0_HI_MACNET0_LC (43)
+/* not used 44 */
+#define INT0_HI_MACNET0_GRA (45)
+#define INT0_HI_MACNET0_EBERR (46)
+#define INT0_HI_MACNET0_BABT (47)
+#define INT0_HI_MACNET0_BABR (48)
+#define INT0_HI_MACNET1_TXF (49)
+#define INT0_HI_MACNET1_TXB (50)
+#define INT0_HI_MACNET1_UN (51)
+#define INT0_HI_MACNET1_RL (52)
+#define INT0_HI_MACNET1_RXF (53)
+#define INT0_HI_MACNET1_RXB (54)
+#define INT0_HI_MACNET1_MII (55)
+#define INT0_HI_MACNET1_LC (56)
+/* not used 57 */
+#define INT0_HI_MACNET1_GRA (58)
+#define INT0_HI_MACNET1_EBERR (59)
+#define INT0_HI_MACNET1_BABT (60)
+#define INT0_HI_MACNET1_BABR (61)
+#define INT0_HI_SCMIR (62)
+#define INT0_HI_OW (63)
+
+#define INT1_LO_CAN0_IFG (0)
+#define INT1_LO_CAN0_BOFF (1)
+/* not used 2 */
+#define INT1_LO_CAN0_TXRXWRN (3)
+#define INT1_LO_CAN1_IFG (4)
+#define INT1_LO_CAN1_BOFF (5)
+/* not used 6 */
+#define INT1_LO_CAN1_TXRXWRN (7)
+#define INT1_LO_EDMA_16 (8)
+#define INT1_LO_EDMA_17 (9)
+#define INT1_LO_EDMA_18 (10)
+#define INT1_LO_EDMA_19 (11)
+#define INT1_LO_EDMA_20 (12)
+#define INT1_LO_EDMA_21 (13)
+#define INT1_LO_EDMA_22 (14)
+#define INT1_LO_EDMA_23 (15)
+#define INT1_LO_EDMA_24 (16)
+#define INT1_LO_EDMA_25 (17)
+#define INT1_LO_EDMA_26 (18)
+#define INT1_LO_EDMA_27 (19)
+#define INT1_LO_EDMA_28 (20)
+#define INT1_LO_EDMA_29 (21)
+#define INT1_LO_EDMA_30 (22)
+#define INT1_LO_EDMA_31 (23)
+#define INT1_LO_EDMA_32 (24)
+#define INT1_LO_EDMA_33 (25)
+#define INT1_LO_EDMA_34 (26)
+#define INT1_LO_EDMA_35 (27)
+#define INT1_LO_EDMA_36 (28)
+#define INT1_LO_EDMA_37 (29)
+#define INT1_LO_EDMA_38 (30)
+#define INT1_LO_EDMA_39 (31)
+#define INT1_LO_EDMA_40 (32)
+#define INT1_HI_EDMA_41 (33)
+#define INT1_HI_EDMA_42 (34)
+#define INT1_HI_EDMA_43 (35)
+#define INT1_HI_EDMA_44 (36)
+#define INT1_HI_EDMA_45 (37)
+#define INT1_HI_EDMA_46 (38)
+#define INT1_HI_EDMA_47 (39)
+#define INT1_HI_EDMA_48 (40)
+#define INT1_HI_EDMA_49 (41)
+#define INT1_HI_EDMA_50 (42)
+#define INT1_HI_EDMA_51 (43)
+#define INT1_HI_EDMA_52 (44)
+#define INT1_HI_EDMA_53 (45)
+#define INT1_HI_EDMA_54 (46)
+#define INT1_HI_EDMA_55 (47)
+#define INT1_HI_UART4 (48)
+#define INT1_HI_UART5 (49)
+#define INT1_HI_UART6 (50)
+#define INT1_HI_UART7 (51)
+#define INT1_HI_UART8 (52)
+#define INT1_HI_UART9 (53)
+#define INT1_HI_DSPI1 (54)
+#define INT1_HI_DSPI2 (55)
+#define INT1_HI_DSPI3 (56)
+#define INT1_HI_I2C1 (57)
+#define INT1_HI_I2C2 (58)
+#define INT1_HI_I2C3 (59)
+#define INT1_HI_I2C4 (60)
+#define INT1_HI_I2C5 (61)
+
+#define INT2_LO_EDMA56_63 (0)
+#define INT2_LO_PWM_SM0SR_CF (1)
+#define INT2_LO_PWM_SM1SR_CF (2)
+#define INT2_LO_PWM_SM2SR_CF (3)
+#define INT2_LO_PWM_SM3SR_CF (4)
+#define INT2_LO_PWM_SM0SR_RF (5)
+#define INT2_LO_PWM_SM1SR_RF (6)
+#define INT2_LO_PWM_SM2SR_RF (7)
+#define INT2_LO_PWM_SM3SR_RF (8)
+#define INT2_LO_PWM_FSR (9)
+#define INT2_LO_PWM_SMSR_REF (10)
+#define INT2_LO_PLL_SR_LOCF (11)
+#define INT2_LO_PLL_SR_LOLF (12)
+#define INT2_LO_PIT0_PIF (13)
+#define INT2_LO_PIT1_PIF (14)
+#define INT2_LO_PIT2_PIF (15)
+#define INT2_LO_PIT3_PIF (16)
+#define INT2_LO_USBOTG_USBSTS (17)
+#define INT2_LO_USBH_USBSTS (18)
+/* not used 19-20 */
+#define INT2_LO_SSI0 (21)
+#define INT2_LO_SSI1 (22)
+#define INT2_LO_NFC (23)
+/* not used 24-25 */
+#define INT2_LO_RTC (26)
+#define INT2_LO_CCM_UOCSR (27)
+#define INT2_LO_RNG_EI (28)
+#define INT2_LO_SIM1_DATA (29)
+#define INT2_LO_SIM1 (30)
+#define INT2_LO_SDHC (31)
+/* not used 32-37 */
+#define INT2_HI_L2SW_BERR (38)
+#define INT2_HI_L2SW_RXB (39)
+#define INT2_HI_L2SW_RXF (40)
+#define INT2_HI_L2SW_TXB (41)
+#define INT2_HI_L2SW_TXF (42)
+#define INT2_HI_L2SW_QM (43)
+#define INT2_HI_L2SW_OD0 (44)
+#define INT2_HI_L2SW_OD1 (45)
+#define INT2_HI_L2SW_OD2 (46)
+#define INT2_HI_L2SW_LRN (47)
+#define INT2_HI_MACNET0_TS (48)
+#define INT2_HI_MACNET0_WAKE (49)
+#define INT2_HI_MACNET0_PLR (50)
+/* not used 51-54 */
+#define INT2_HI_MACNET1_TS (51)
+#define INT2_HI_MACNET1_WAKE (52)
+#define INT2_HI_MACNET1_PLR (53)
+
+/* Serial Boot Facility (SBF) */
+#define SBF_SBFCR_BLDIV(x) (((x)&0x000F))
+#define SBF_SBFCR_FR (0x0010)
+
+/* Reset Controller Module (RCM) */
+#define RCM_RCR_SOFTRST (0x80)
+#define RCM_RCR_FRCRSTOUT (0x40)
+
+#define RCM_RSR_SOFT (0x20)
+#define RCM_RSR_LOC (0x10)
+#define RCM_RSR_POR (0x08)
+#define RCM_RSR_EXT (0x04)
+#define RCM_RSR_WDR_CORE (0x02)
+#define RCM_RSR_LOL (0x01)
+
+/* Chip Configuration Module (CCM) */
+#define CCM_CCR_BOOTMOD (0xC000)
+#define CCM_CCR_PLLMULT (0x0FC0)
+#define CCM_CCR_BOOTPS (0x0030)
+#define CCM_CCR_BOOTPS_32 (0x0000)
+#define CCM_CCR_BOOTPS_16 (0x0020)
+#define CCM_CCR_BOOTPS_8 (0x0010)
+#define CCM_CCR_BOOTPS_ (0x0000)
+#define CCM_CCR_ALESEL (0x0008)
+#define CCM_CCR_OSCMOD (0x0004)
+#define CCM_CCR_PLLMOD (0x0002)
+#define CCM_CCR_BOOTMEM (0x0001)
+
+#define CCM_CIR_PIN_MASK (0xFFC0)
+#define CCM_CIR_PRN_MASK (0x003F)
+#define CCM_CIR_PIN_MCF54410 (0x9F<<6)
+#define CCM_CIR_PIN_MCF54415 (0xA0<<6)
+#define CCM_CIR_PIN_MCF54416 (0xA1<<6)
+#define CCM_CIR_PIN_MCF54417 (0xA2<<6)
+#define CCM_CIR_PIN_MCF54418 (0xA3<<6)
+
+#define CCM_MISCCR_PWM_EXTCLK(x) (((x)&(0x0003)<<14)
+#define CCM_MISCCR_PWM_EXTCLK_MASK (0x3FFF)
+#define CCM_MISCCR_PWM_EXTCLK_TMR0 (0x0000)
+#define CCM_MISCCR_PWM_EXTCLK_TMR1 (0x4000)
+#define CCM_MISCCR_PWM_EXTCLK_TMR2 (0x8000)
+#define CCM_MISCCR_PWM_EXTCLK_TMR3 (0xC000)
+#define CCM_MISCCR_LIMP (0x1000)
+#define CCM_MISCCR_BME (0x0800)
+#define CCM_MISCCR_BMT(x) (((x)&0x0007)<<8)
+#define CCM_MISCCR_BMT_65536 (0)
+#define CCM_MISCCR_BMT_32768 (1)
+#define CCM_MISCCR_BMT_16384 (2)
+#define CCM_MISCCR_BMT_8192 (3)
+#define CCM_MISCCR_BMT_4096 (4)
+#define CCM_MISCCR_BMT_2048 (5)
+#define CCM_MISCCR_BMT_1024 (6)
+#define CCM_MISCCR_BMT_512 (7)
+#define CCM_MISCCR_SDHCSRC (0x0040)
+#define CCM_MISCCR_SSI1SRC (0x0020)
+#define CCM_MISCCR_SSI0SRC (0x0010)
+#define CCM_MISCCR_USBHOC (0x0008)
+#define CCM_MISCCR_USBOOC (0x0004)
+#define CCM_MISCCR_USBPUE (0x0002)
+#define CCM_MISCCR_USBSRC (0x0001)
+
+#define CCM_CDRH_SSI0DIV(x) (((x)&0x00FF)<<8)
+#define CCM_CDRH_SSI0DIV_MASK (0x00FF)
+#define CCM_CDRH_SSI1DIV(x) (((x)&0x00FF))
+#define CCM_CDRH_SSI1DIV_MASK (0xFF00)
+#define CCM_CDRL_LPDIV(x) (((x)&0x000F)<<8)
+#define CCM_CDRL_LPDIV_MASK (0xFF0F)
+#define CCM_CDR_LPDIV(x) CCM_CDRL_LPDIV(x)
+
+#define CCM_UOCSR_DPPD (0x2000)
+#define CCM_UOCSR_DMPD (0x1000)
+#define CCM_UOCSR_DRV_VBUS (0x0800)
+#define CCM_UOCSR_CRG_VBUS (0x0400)
+#define CCM_UOCSR_DCR_VBUS (0x0200)
+#define CCM_UOCSR_DPPU (0x0100)
+#define CCM_UOCSR_AVLD (0x0080)
+#define CCM_UOCSR_BVLD (0x0040)
+#define CCM_UOCSR_VVLD (0x0020)
+#define CCM_UOCSR_SEND (0x0010)
+#define CCM_UOCSR_PWRFLT (0x0008)
+#define CCM_UOCSR_WKUP (0x0004)
+#define CCM_UOCSR_UOMIE (0x0002)
+#define CCM_UOCSR_XPDE (0x0001)
+
+#define CCM_UHCSR_DRV_VBUS (0x0010)
+#define CCM_UHCSR_PWRFLT (0x0008)
+#define CCM_UHCSR_WKUP (0x0004)
+#define CCM_UHCSR_UOMIE (0x0002)
+#define CCM_UHCSR_XPDE (0x0001)
+
+#define CCM_MISCCR3_TMR_ENET (0x1000)
+#define CCM_MISCCR3_ENETCLK(x) (((x)&7)<<8)
+#define CCM_MISCCR3_ENETCLK_MASK (0xF8FF)
+#define CCM_MISCCR3_ENETCLK_MII (0x0700)
+#define CCM_MISCCR3_ENETCLK_OSC (0x0600)
+#define CCM_MISCCR3_ENETCLK_USB (0x0500)
+#define CCM_MISCCR3_ENETCLK_TMR3 (0x0400)
+#define CCM_MISCCR3_ENETCLK_TMR2 (0x0300)
+#define CCM_MISCCR3_ENETCLK_TMR1 (0x0200)
+#define CCM_MISCCR3_ENETCLK_TMR0 (0x0100)
+#define CCM_MISCCR3_ENETCLK_INTBUS (0x0000)
+
+#define CCM_MISCCR2_EXTCLKBYP (0x8000)
+#define CCM_MISCCR2_DDR2CLK (0x4000)
+#define CCM_MISCCR2_RGPIO_HALF (0x2000)
+#define CCM_MISCCR2_SWTSCR (0x1000)
+#define CCM_MISCCR2_PLLMODE(x) (((x)&7)<<8)
+#define CCM_MISCCR2_PLLMODE_MASK (0xF8FF)
+#define CCM_MISCCR2_DCCBYP (0x0080)
+#define CCM_MISCCR2_DAC1SEL (0x0040)
+#define CCM_MISCCR2_DAC0SEL (0x0020)
+#define CCM_MISCCR2_ADCEN (0x0010)
+#define CCM_MISCCR2_ADC7SEL (0x0008)
+#define CCM_MISCCR2_ADC3SEL (0x0004)
+#define CCM_MISCCR2_FBHALF (0x0002)
+#define CCM_MISCCR2_ULPI (0x0001)
+
+#define CCM_FNACR_PCR(x) (((x)&0x0F)<<24)
+#define CCM_FNACR_PCR_MASK (0xF0FFFFFF)
+#define CCM_FNACR_MCC(x) ((x)&0xFFFF)
+#define CCM_FNACR_MCC_MASK (0xFFFF0000)
+
+/* General Purpose I/O Module (GPIO) */
+#define GPIO_PAR_FBCTL_ALE(x) (((x)&3)<<6)
+#define GPIO_PAR_FBCTL_ALE_MASK (0x3F)
+#define GPIO_PAR_FBCTL_ALE_FB_ALE (0xC0)
+#define GPIO_PAR_FBCTL_ALE_FB_TS (0x80)
+#define GPIO_PAR_FBCTL_ALE_GPIO (0x00)
+#define GPIO_PAR_FBCTL_OE(x) (((x)&3)<<4)
+#define GPIO_PAR_FBCTL_OE_MASK (0xCF)
+#define GPIO_PAR_FBCTL_OE_FB_OE (0x30)
+#define GPIO_PAR_FBCTL_OE_FB_TBST (0x20)
+#define GPIO_PAR_FBCTL_OE_NFC_RE (0x20)
+#define GPIO_PAR_FBCTL_OE_GPIO (0x00)
+#define GPIO_PAR_FBCTL_FBCLK (0x08)
+#define GPIO_PAR_FBCTL_RW (0x04)
+#define GPIO_PAR_FBCTL_TA(x) ((x)&3)
+#define GPIO_PAR_FBCTL_TA_MASK (0xFC)
+#define GPIO_PAR_FBCTL_TA_TA (0x03)
+#define GPIO_PAR_FBCTL_TA_NFC_RB (0x01)
+#define GPIO_PAR_FBCTL_TA_GPIO (0x00)
+
+#define GPIO_PAR_BE_BS3(x) (((x)&0x03)<<6)
+#define GPIO_PAR_BE_BE3_MASK (0x3F)
+#define GPIO_PAR_BE_BE3_BE3 (0xC0)
+#define GPIO_PAR_BE_BE3_CS3 (0x80)
+#define GPIO_PAR_BE_BE3_FB_A1 (0x40)
+#define GPIO_PAR_BE_BE3_NFC_ALE (0x40)
+#define GPIO_PAR_BE_BE3_GPIO (0x00)
+#define GPIO_PAR_BE_BS2(x) (((x)&0x03)<<4)
+#define GPIO_PAR_BE_BE2_MASK (0xCF)
+#define GPIO_PAR_BE_BE2_BE2 (0x30)
+#define GPIO_PAR_BE_BE2_CS2 (0x20)
+#define GPIO_PAR_BE_BE2_FB_A0 (0x10)
+#define GPIO_PAR_BE_BE2_NFC_CLE (0x10)
+#define GPIO_PAR_BE_BE2_GPIO (0x00)
+#define GPIO_PAR_BE_BS1(x) (((x)&0x03)<<2)
+#define GPIO_PAR_BE_BE1_MASK (0xF3)
+#define GPIO_PAR_BE_BE1_BE1 (0x0C)
+#define GPIO_PAR_BE_BE1_FB_TSZ1 (0x08)
+#define GPIO_PAR_BE_BE1_GPIO (0x00)
+#define GPIO_PAR_BE_BS0(x) ((x)&0x03)
+#define GPIO_PAR_BE_BE0_MASK (0xFC)
+#define GPIO_PAR_BE_BE0_BE0 (0x03)
+#define GPIO_PAR_BE_BE0_FB_TSZ0 (0x02)
+#define GPIO_PAR_BE_BE0_GPIO (0x00)
+
+#define GPIO_PAR_CS_CS5(x) (((x)&0x03)<<6)
+#define GPIO_PAR_CS_CS5_MASK (0x3F)
+#define GPIO_PAR_CS_CS5_CS5 (0xC0)
+#define GPIO_PAR_CS_CS5_DACK1 (0x80)
+#define GPIO_PAR_CS_CS5_GPIO (0x00)
+#define GPIO_PAR_CS_CS4(x) (((x)&0x03)<<4)
+#define GPIO_PAR_CS_CS4_MASK (0xCF)
+#define GPIO_PAR_CS_CS4_CS4 (0x30)
+#define GPIO_PAR_CS_CS4_DREQ1 (0x20)
+#define GPIO_PAR_CS_CS4_GPIO (0x00)
+#define GPIO_PAR_CS_CS1(x) (((x)&0x03)<<2)
+#define GPIO_PAR_CS_CS1_MASK (0xF3)
+#define GPIO_PAR_CS_CS1_CS1 (0x0C)
+#define GPIO_PAR_CS_CS1_NFC_CE (0x04)
+#define GPIO_PAR_CS_CS1_GPIO (0x00)
+#define GPIO_PAR_CS_CS0_CS0 (0x01)
+
+#define GPIO_PAR_CANI2C_I2C0SCL(x) (((x)&0x03)<<6)
+#define GPIO_PAR_CANI2C_I2C0SCL_MASK (0x3F)
+#define GPIO_PAR_CANI2C_I2C0SCL_I2C0SCL (0xC0)
+#define GPIO_PAR_CANI2C_I2C0SCL_U8TXD (0x80)
+#define GPIO_PAR_CANI2C_I2C0SCL_CAN0TX (0x40)
+#define GPIO_PAR_CANI2C_I2C0SCL_GPIO (0x00)
+#define GPIO_PAR_CANI2C_I2C0SDA(x) (((x)&0x03)<<4)
+#define GPIO_PAR_CANI2C_I2C0SDA_MASK (0xCF)
+#define GPIO_PAR_CANI2C_I2C0SDA_I2C0SDA (0x30)
+#define GPIO_PAR_CANI2C_I2C0SDA_U8RXD (0x20)
+#define GPIO_PAR_CANI2C_I2C0SDA_CAN0RX (0x10)
+#define GPIO_PAR_CANI2C_I2C0SDA_GPIO (0x00)
+#define GPIO_PAR_CANI2C_CAN1TX(x) (((x)&0x03)<<2)
+#define GPIO_PAR_CANI2C_CAN1TX_MASK (0xF3)
+#define GPIO_PAR_CANI2C_CAN1TX_CAN1TX (0x0C)
+#define GPIO_PAR_CANI2C_CAN1TX_U9TXD (0x08)
+#define GPIO_PAR_CANI2C_CAN1TX_I2C1SCL (0x04)
+#define GPIO_PAR_CANI2C_CAN1TX_GPIO (0x00)
+#define GPIO_PAR_CANI2C_CAN1RX(x) ((x)&0x03)
+#define GPIO_PAR_CANI2C_CAN1RX_MASK (0xFC)
+#define GPIO_PAR_CANI2C_CAN1RX_CAN1RX (0x03)
+#define GPIO_PAR_CANI2C_CAN1RX_U9RXD (0x02)
+#define GPIO_PAR_CANI2C_CAN1RX_I2C1SDA (0x01)
+#define GPIO_PAR_CANI2C_CAN1RX_GPIO (0x00)
+
+#define GPIO_PAR_IRQH_IRQ7 (0x10)
+#define GPIO_PAR_IRQH_IRQ4(x) (((x)&0x03)<<2)
+#define GPIO_PAR_IRQH_IRQ4_MASK (0xF3)
+#define GPIO_PAR_IRQH_IRQ4_IRQ4 (0x0C)
+#define GPIO_PAR_IRQH_IRQ4_DREQ0 (0x08)
+#define GPIO_PAR_IRQH_IRQ4_GPIO (0x00)
+#define GPIO_PAR_IRQH_IRQ1 (0x03)
+
+#define GPIO_PAR_IRQL_IRQ6(x) (((x)&0x03)<<6)
+#define GPIO_PAR_IRQL_IRQ6_MASK (0x3F)
+#define GPIO_PAR_IRQL_IRQ6_IRQ6 (0xC0)
+#define GPIO_PAR_IRQL_IRQ6_USBCLKIN (0x40)
+#define GPIO_PAR_IRQL_IRQ6_GPIO (0x00)
+#define GPIO_PAR_IRQL_IRQ3(x) (((x)&0x03)<<4)
+#define GPIO_PAR_IRQL_IRQ3_MASK (0xCF)
+#define GPIO_PAR_IRQL_IRQ3_IRQ3 (0x30)
+#define GPIO_PAR_IRQL_IRQ3_DSPI0_PCS3 (0x20)
+#define GPIO_PAR_IRQL_IRQ3_USB1_VBUS_EN (0x10)
+#define GPIO_PAR_IRQL_IRQ3_GPIO (0x00)
+#define GPIO_PAR_IRQL_IRQ2(x) (((x)&0x03)<<2)
+#define GPIO_PAR_IRQL_IRQ2_MASK (0xF3)
+#define GPIO_PAR_IRQL_IRQ2_IRQ2 (0x0C)
+#define GPIO_PAR_IRQL_IRQ2_DSPI0_PCS2 (0x08)
+#define GPIO_PAR_IRQL_IRQ2_USB1_VBUS_OC (0x04)
+#define GPIO_PAR_IRQL_IRQ2_GPIO (0x00)
+
+#define GPIO_PAR_DSPI0_SIN(x) (((x)&0x03)<<6)
+#define GPIO_PAR_DSPI0_SIN_MASK (0x3F)
+#define GPIO_PAR_DSPI0_SIN_DSPI0SIN (0xC0)
+#define GPIO_PAR_DSPI0_SIN_SBF_DI (0xC0)
+#define GPIO_PAR_DSPI0_SIN_U3RXD (0x80)
+#define GPIO_PAR_DSPI0_SIN_SDHC_CMD (0x40)
+#define GPIO_PAR_DSPI0_SIN_GPIO (0x00)
+#define GPIO_PAR_DSPI0_SOUT(x) (((x)&0x03)<<4)
+#define GPIO_PAR_DSPI0_SOUT_MASK (0xCF)
+#define GPIO_PAR_DSPI0_SOUT_DSPI0SOUT (0x30)
+#define GPIO_PAR_DSPI0_SOUT_SBF_DO (0x30)
+#define GPIO_PAR_DSPI0_SOUT_U3TXD (0x20)
+#define GPIO_PAR_DSPI0_SOUT_SDHC_DAT0 (0x10)
+#define GPIO_PAR_DSPI0_SOUT_GPIO (0x00)
+#define GPIO_PAR_DSPI0_SCK(x) (((x)&0x03)<<2)
+#define GPIO_PAR_DSPI0_SCK_MASK (0xF3)
+#define GPIO_PAR_DSPI0_SCK_DSPI0SCK (0x0C)
+#define GPIO_PAR_DSPI0_SCK_SBF_CK (0x0C)
+#define GPIO_PAR_DSPI0_SCK_I2C3SCL (0x08)
+#define GPIO_PAR_DSPI0_SCK_SDHC_CLK (0x04)
+#define GPIO_PAR_DSPI0_SCK_GPIO (0x00)
+#define GPIO_PAR_DSPI0_PCS0(x) ((x)&0x03)
+#define GPIO_PAR_DSPI0_PCS0_MASK (0xFC)
+#define GPIO_PAR_DSPI0_PCS0_DSPI0PCS0 (0x03)
+#define GPIO_PAR_DSPI0_PCS0_SS (0x03)
+#define GPIO_PAR_DSPI0_PCS0_I2C3SDA (0x02)
+#define GPIO_PAR_DSPI0_PCS0_SDHC_DAT3 (0x01)
+#define GPIO_PAR_DSPI0_PCS0_GPIO (0x00)
+
+#define GPIO_PAR_DSPIOW_DSPI0PSC1 (0x80)
+#define GPIO_PAR_DSPIOW_SBF_CS (0x80)
+#define GPIO_PAR_DSPIOW_OWDAT (((x)&0x03)<<4)
+#define GPIO_PAR_DSPIOW_OWDAT_MASK (0xCF)
+#define GPIO_PAR_DSPIOW_OWDAT_OWDAT (0x30)
+#define GPIO_PAR_DSPIOW_OWDAT_DACK0 (0x20)
+#define GPIO_PAR_DSPIOW_OWDAT_GPIO (0x00)
+
+#define GPIO_PAR_TIMER_T3IN(x) (((x)&0x03)<<6)
+#define GPIO_PAR_TIMER_T3IN_MASK (0x3F)
+#define GPIO_PAR_TIMER_T3IN_T3IN (0xC0)
+#define GPIO_PAR_TIMER_T3IN_EXTA3 (0xC0)
+#define GPIO_PAR_TIMER_T3IN_T3OUT (0x80)
+#define GPIO_PAR_TIMER_T3IN_USB0_VBUSEN (0x40)
+#define GPIO_PAR_TIMER_T3IN_ULIPI_DIR (0x40)
+#define GPIO_PAR_TIMER_T3IN_GPIO (0x00)
+#define GPIO_PAR_TIMER_T2IN(x) (((x)&0x03)<<4)
+#define GPIO_PAR_TIMER_T2IN_MASK (0xCF)
+#define GPIO_PAR_TIMER_T2IN_T2IN (0x30)
+#define GPIO_PAR_TIMER_T2IN_EXTA2 (0x30)
+#define GPIO_PAR_TIMER_T2IN_T2OUT (0x20)
+#define GPIO_PAR_TIMER_T2IN_SDHC_DAT2 (0x10)
+#define GPIO_PAR_TIMER_T2IN_GPIO (0x00)
+#define GPIO_PAR_TIMER_T1IN(x) (((x)&0x03)<<2)
+#define GPIO_PAR_TIMER_T1IN_MASK (0xF3)
+#define GPIO_PAR_TIMER_T1IN_T1IN (0x0C)
+#define GPIO_PAR_TIMER_T1IN_EXTA1 (0x0C)
+#define GPIO_PAR_TIMER_T1IN_T1OUT (0x08)
+#define GPIO_PAR_TIMER_T1IN_SDHC_DAT1 (0x04)
+#define GPIO_PAR_TIMER_T1IN_GPIO (0x00)
+#define GPIO_PAR_TIMER_T0IN(x) ((x)&0x03)
+#define GPIO_PAR_TIMER_T0IN_MASK (0xFC)
+#define GPIO_PAR_TIMER_T0IN_T0IN (0x03)
+#define GPIO_PAR_TIMER_T0IN_EXTA0 (0x03)
+#define GPIO_PAR_TIMER_T0IN_T0OUT (0x02)
+#define GPIO_PAR_TIMER_T0IN_USBO_VBUSOC (0x01)
+#define GPIO_PAR_TIMER_T0IN_ULPI_NXT (0x01)
+#define GPIO_PAR_TIMER_T0IN_GPIO (0x00)
+
+#define GPIO_PAR_UART2_U2CTS(x) (((x)&0x03)<<6)
+#define GPIO_PAR_UART2_U2CTS_MASK (0x3F)
+#define GPIO_PAR_UART2_U2CTS_U2CTS (0xC0)
+#define GPIO_PAR_UART2_U2CTS_U6TXD (0x80)
+#define GPIO_PAR_UART2_U2CTS_SSI1_BCLK (0x40)
+#define GPIO_PAR_UART2_U2CTS_GPIO (0x00)
+#define GPIO_PAR_UART2_U2RTS(x) (((x)&0x03)<<4)
+#define GPIO_PAR_UART2_U2RTS_MASK (0xCF)
+#define GPIO_PAR_UART2_U2RTS_U2RTS (0x30)
+#define GPIO_PAR_UART2_U2RTS_U6RXD (0x20)
+#define GPIO_PAR_UART2_U2RTS_SSI1_FS (0x10)
+#define GPIO_PAR_UART2_U2RTS_GPIO (0x00)
+#define GPIO_PAR_UART2_U2RXD(x) (((x)&0x03)<<2)
+#define GPIO_PAR_UART2_U2RXD_MASK (0xF3)
+#define GPIO_PAR_UART2_U2RXD_U2RXD (0x0C)
+#define GPIO_PAR_UART2_U2RXD_PWM_A3 (0x08)
+#define GPIO_PAR_UART2_U2RXD_SSI1_RXD (0x04)
+#define GPIO_PAR_UART2_U2RXD_GPIO (0x00)
+#define GPIO_PAR_UART2_U2TXD(x) ((x)&0x03)
+#define GPIO_PAR_UART2_U2TXD_MASK (0xFC)
+#define GPIO_PAR_UART2_U2TXD_U2TXD (0x03)
+#define GPIO_PAR_UART2_U2TXD_PWM_B3 (0x02)
+#define GPIO_PAR_UART2_U2TXD_SSI1_TXD (0x01)
+#define GPIO_PAR_UART2_U2TXD_GPIO (0x00)
+
+#define GPIO_PAR_UART1_U1CTS(x) (((x)&0x03)<<6)
+#define GPIO_PAR_UART1_U1CTS_MASK (0x3F)
+#define GPIO_PAR_UART1_U1CTS_U1CTS (0xC0)
+#define GPIO_PAR_UART1_U1CTS_U5TXD (0x80)
+#define GPIO_PAR_UART1_U1CTS_DSPI3_SCK (0x40)
+#define GPIO_PAR_UART1_U1CTS_GPIO (0x00)
+#define GPIO_PAR_UART1_U1RTS(x) (((x)&0x03)<<4)
+#define GPIO_PAR_UART1_U1RTS_MASK (0xCF)
+#define GPIO_PAR_UART1_U1RTS_U1RTS (0x30)
+#define GPIO_PAR_UART1_U1RTS_U5RXD (0x20)
+#define GPIO_PAR_UART1_U1RTS_DSPI3_PCS0 (0x10)
+#define GPIO_PAR_UART1_U1RTS_GPIO (0x00)
+#define GPIO_PAR_UART1_U1RXD(x) (((x)&0x03)<<2)
+#define GPIO_PAR_UART1_U1RXD_MASK (0xF3)
+#define GPIO_PAR_UART1_U1RXD_U1RXD (0x0C)
+#define GPIO_PAR_UART1_U1RXD_I2C5SDA (0x08)
+#define GPIO_PAR_UART1_U1RXD_DSPI3_SIN (0x04)
+#define GPIO_PAR_UART1_U1RXD_GPIO (0x00)
+#define GPIO_PAR_UART1_U1TXD(x) ((x)&0x03)
+#define GPIO_PAR_UART1_U1TXD_MASK (0xFC)
+#define GPIO_PAR_UART1_U1TXD_U1TXD (0x03)
+#define GPIO_PAR_UART1_U1TXD_I2C5SCL (0x02)
+#define GPIO_PAR_UART1_U1TXD_DSPI3_SOUT (0x01)
+#define GPIO_PAR_UART1_U1TXD_GPIO (0x00)
+
+#define GPIO_PAR_UART0_U0CTS(x) (((x)&0x03)<<6)
+#define GPIO_PAR_UART0_U0CTS_MASK (0x3F)
+#define GPIO_PAR_UART0_U0CTS_U0CTS (0xC0)
+#define GPIO_PAR_UART0_U0CTS_U4TXD (0x80)
+#define GPIO_PAR_UART0_U0CTS_DSPI2_SCK (0x40)
+#define GPIO_PAR_UART0_U0CTS_GPIO (0x00)
+#define GPIO_PAR_UART0_U0RTS(x) (((x)&0x03)<<4)
+#define GPIO_PAR_UART0_U0RTS_MASK (0xCF)
+#define GPIO_PAR_UART0_U0RTS_U0RTS (0x30)
+#define GPIO_PAR_UART0_U0RTS_U4RXD (0x20)
+#define GPIO_PAR_UART0_U0RTS_DSPI2_PCS0 (0x10)
+#define GPIO_PAR_UART0_U0RTS_GPIO (0x00)
+#define GPIO_PAR_UART0_U0RXD(x) (((x)&0x03)<<2)
+#define GPIO_PAR_UART0_U0RXD_MASK (0xF3)
+#define GPIO_PAR_UART0_U0RXD_U0RXD (0x0C)
+#define GPIO_PAR_UART0_U0RXD_I2C4SDA (0x08)
+#define GPIO_PAR_UART0_U0RXD_DSPI2_SIN (0x04)
+#define GPIO_PAR_UART0_U0RXD_GPIO (0x00)
+#define GPIO_PAR_UART0_U0TXD(x) ((x)&0x03)
+#define GPIO_PAR_UART0_U0TXD_MASK (0xFC)
+#define GPIO_PAR_UART0_U0TXD_U0TXD (0x03)
+#define GPIO_PAR_UART0_U0TXD_I2C4SCL (0x02)
+#define GPIO_PAR_UART0_U0TXD_DSPI2_SOUT (0x01)
+#define GPIO_PAR_UART0_U0TXD_GPIO (0x00)
+
+#define GPIO_PAR_SDHCH_DAT3(x) (((x)&0x03)<<6)
+#define GPIO_PAR_SDHCH_DAT3_MASK (0x3F)
+#define GPIO_PAR_SDHCH_DAT3_DAT3 (0xC0)
+#define GPIO_PAR_SDHCH_DAT3_PWM_A1 (0x80)
+#define GPIO_PAR_SDHCH_DAT3_DSPI1_PCS0 (0x40)
+#define GPIO_PAR_SDHCH_DAT3_GPIO (0x00)
+#define GPIO_PAR_SDHCH_DAT2(x) (((x)&0x03)<<4)
+#define GPIO_PAR_SDHCH_DAT2_MASK (0xCF)
+#define GPIO_PAR_SDHCH_DAT2_DAT2 (0x30)
+#define GPIO_PAR_SDHCH_DAT2_PWM_B1 (0x20)
+#define GPIO_PAR_SDHCH_DAT2_DSPI1_PCS2 (0x10)
+#define GPIO_PAR_SDHCH_DAT2_GPIO (0x00)
+#define GPIO_PAR_SDHCH_DAT1(x) (((x)&0x03)<<2)
+#define GPIO_PAR_SDHCH_DAT1_MASK (0xF3)
+#define GPIO_PAR_SDHCH_DAT1_DAT1 (0x0C)
+#define GPIO_PAR_SDHCH_DAT1_PWM_A2 (0x08)
+#define GPIO_PAR_SDHCH_DAT1_DSPI1_PCS1 (0x04)
+#define GPIO_PAR_SDHCH_DAT1_GPIO (0x00)
+#define GPIO_PAR_SDHCH_DAT0(x) ((x)&0x03)
+#define GPIO_PAR_SDHCH_DAT0_MASK (0xFC)
+#define GPIO_PAR_SDHCH_DAT0_DAT0 (0x03)
+#define GPIO_PAR_SDHCH_DAT0_PWM_B2 (0x02)
+#define GPIO_PAR_SDHCH_DAT0_DSPI1_SOUT (0x01)
+#define GPIO_PAR_SDHCH_DAT0_GPIO (0x00)
+
+#define GPIO_PAR_SDHCL_CMD(x) (((x)&0x03)<<2)
+#define GPIO_PAR_SDHCL_CMD_MASK (0xF3)
+#define GPIO_PAR_SDHCL_CMD_CMD (0x0C)
+#define GPIO_PAR_SDHCL_CMD_PWM_A0 (0x08)
+#define GPIO_PAR_SDHCL_CMD_DSPI1_SIN (0x04)
+#define GPIO_PAR_SDHCL_CMD_GPIO (0x00)
+#define GPIO_PAR_SDHCL_CLK(x) ((x)&0x03)
+#define GPIO_PAR_SDHCL_CLK_MASK (0xFC)
+#define GPIO_PAR_SDHCL_CLK_CLK (0x03)
+#define GPIO_PAR_SDHCL_CLK_PWM_B0 (0x02)
+#define GPIO_PAR_SDHCL_CLK_DSPI1_SCK (0x01)
+#define GPIO_PAR_SDHCL_CLK_GPIO (0x00)
+
+#define GPIO_PAR_SIMP0H_DAT(x) (((x)&0x03)<<6)
+#define GPIO_PAR_SIMP0H_DAT_MASK (0x3F)
+#define GPIO_PAR_SIMP0H_DAT_DAT (0xC0)
+#define GPIO_PAR_SIMP0H_DAT_PWM_FAULT2 (0x80)
+#define GPIO_PAR_SIMP0H_DAT_SDHC_DAT7 (0x40)
+#define GPIO_PAR_SIMP0H_DAT_GPIO (0x00)
+#define GPIO_PAR_SIMP0H_VEN(x) (((x)&0x03)<<4)
+#define GPIO_PAR_SIMP0H_VEN_MASK (0xCF)
+#define GPIO_PAR_SIMP0H_VEN_VEN (0x30)
+#define GPIO_PAR_SIMP0H_VEN_PWM_FAULT0 (0x20)
+#define GPIO_PAR_SIMP0H_VEN_GPIO (0x00)
+#define GPIO_PAR_SIMP0H_RST(x) (((x)&0x03)<<2)
+#define GPIO_PAR_SIMP0H_RST_MASK (0xF3)
+#define GPIO_PAR_SIMP0H_RST_RST (0x0C)
+#define GPIO_PAR_SIMP0H_RST_PWM_FORCE (0x08)
+#define GPIO_PAR_SIMP0H_RST_SDHC_DAT6 (0x04)
+#define GPIO_PAR_SIMP0H_RST_GPIO (0x00)
+#define GPIO_PAR_SIMP0H_PD(x) ((x)&0x03)
+#define GPIO_PAR_SIMP0H_PD_MASK (0xFC)
+#define GPIO_PAR_SIMP0H_PD_PD (0x03)
+#define GPIO_PAR_SIMP0H_PD_PWM_SYNC (0x02)
+#define GPIO_PAR_SIMP0H_PD_SDHC_DAT5 (0x01)
+#define GPIO_PAR_SIMP0H_PD_GPIO (0x00)
+
+#define GPIO_PAR_SIMP0L_CLK(x) ((x)&0x03)
+#define GPIO_PAR_SIMP0L_CLK_MASK (0xFC)
+#define GPIO_PAR_SIMP0L_CLK_CLK (0x03)
+#define GPIO_PAR_SIMP0L_CLK_PWM_FAULT1 (0x02)
+#define GPIO_PAR_SIMP0L_CLK_SDHC_DAT4 (0x01)
+#define GPIO_PAR_SIMP0L_CLK_GPIO (0x00)
+
+#define GPIO_PAR_SSI0H_RXD(x) (((x)&0x03)<<6)
+#define GPIO_PAR_SSI0H_RXD_MASK (0x3F)
+#define GPIO_PAR_SSI0H_RXD_RXD (0xC0)
+#define GPIO_PAR_SSI0H_RXD_I2C2SDA (0x80)
+#define GPIO_PAR_SSI0H_RXD_SIM1_VEN (0x40)
+#define GPIO_PAR_SSI0H_RXD_GPIO (0x00)
+#define GPIO_PAR_SSI0H_TXD(x) (((x)&0x03)<<4)
+#define GPIO_PAR_SSI0H_TXD_MASK (0xCF)
+#define GPIO_PAR_SSI0H_TXD_TXD (0x30)
+#define GPIO_PAR_SSI0H_TXD_I2C2SCL (0x20)
+#define GPIO_PAR_SSI0H_TXD_SIM1_DAT (0x10)
+#define GPIO_PAR_SSI0H_TXD_GPIO (0x00)
+#define GPIO_PAR_SSI0H_FS(x) (((x)&0x03)<<2)
+#define GPIO_PAR_SSI0H_FS_MASK (0xF3)
+#define GPIO_PAR_SSI0H_FS_FS (0x0C)
+#define GPIO_PAR_SSI0H_FS_U7TXD (0x08)
+#define GPIO_PAR_SSI0H_FS_SIM1_RST (0x04)
+#define GPIO_PAR_SSI0H_FS_GPIO (0x00)
+#define GPIO_PAR_SSI0H_MCLK(x) ((x)&0x03)
+#define GPIO_PAR_SSI0H_MCLK_MASK (0xFC)
+#define GPIO_PAR_SSI0H_MCLK_MCLK (0x03)
+#define GPIO_PAR_SSI0H_MCLK_SSI_CLKIN (0x02)
+#define GPIO_PAR_SSI0H_MCLK_SIM1_CLK (0x01)
+#define GPIO_PAR_SSI0H_MCLK_GPIO (0x00)
+
+#define GPIO_PAR_SSI0L_BCLK(x) ((x)&0x03)
+#define GPIO_PAR_SSI0L_BCLK_MASK (0xFC)
+#define GPIO_PAR_SSI0L_BCLK_BCLK (0x03)
+#define GPIO_PAR_SSI0L_BCLK_U7RXD (0x02)
+#define GPIO_PAR_SSI0L_BCLK_SIM1_PD (0x01)
+#define GPIO_PAR_SSI0L_BCLK_GPIO (0x00)
+
+#define GPIO_PAR_DEBUGH1_DAT3 (0x40)
+#define GPIO_PAR_DEBUGH1_DAT2 (0x10)
+#define GPIO_PAR_DEBUGH1_DAT1 (0x04)
+#define GPIO_PAR_DEBUGH1_DAT0 (0x01)
+
+#define GPIO_PAR_DEBUGH0_PST3 (0x40)
+#define GPIO_PAR_DEBUGH0_PST2 (0x10)
+#define GPIO_PAR_DEBUGH0_PST1 (0x04)
+#define GPIO_PAR_DEBUGH0_PST0 (0x01)
+
+#define GPIO_PODR_G4_VAL (0x01 << 4)
+#define GPIO_PODR_G4_MASK (0xff & ~GPIO_PODR_G4_VAL)
+#define GPIO_PDDR_G4_OUTPUT (0x01 << 4)
+#define GPIO_PDDR_G4_MASK (0xff & ~GPIO_PDDR_G4_OUTPUT)
+
+#define GPIO_PAR_DEBUGL_ALLPST (0x01)
+
+#define GPIO_PAR_FEC_FEC(x) ((x)&0x0F)
+#define GPIO_PAR_FEC_FEC_MASK (0xF0)
+#define GPIO_PAR_FEC_FEC_GPIO (0x0D)
+#define GPIO_PAR_FEC_FEC_RMII1 (0x0C)
+#define GPIO_PAR_FEC_FEC_RMII1FUL (0x0B)
+#define GPIO_PAR_FEC_FEC_RMII_ULPI (0x0A)
+#define GPIO_PAR_FEC_FEC_RMII0 (0x09)
+#define GPIO_PAR_FEC_FEC_RMII0FUL_ULPI (0x08)
+#define GPIO_PAR_FEC_FEC_RMII0FUL (0x07)
+#define GPIO_PAR_FEC_FEC_RMII0_1FUL (0x06)
+#define GPIO_PAR_FEC_FEC_RMII0FUL_1 (0x05) /* 0:Full 1: */
+/* Both 0&1: MDC, MDIO, COL & TXER - GPIO */
+#define GPIO_PAR_FEC_FEC_RMII0_1 (0x04)
+#define GPIO_PAR_FEC_FEC_RMII0FUL_1FUL (0x03)
+#define GPIO_PAR_FEC_FEC_MII (0x01) /* MDC & MDIO - GPIO */
+#define GPIO_PAR_FEC_FEC_MIIFUL (0x00)
+
+
+/* TC: Need to edit here.... */
+
+/* Mode Select Control */
+#define GPIO_MSCR_SDRAM_MSC(x) ((x)&0x03)
+#define GPIO_MSCR_SDRAM_MSC_MASK (0xFC)
+
+/* Slew Rate Control */
+
+#define GPIO_SRCR_FB3_FB3(x) ((x)&0x03)
+#define GPIO_SRCR_FB3_FB3_MASK (0xFC)
+
+#define GPIO_SRCR_FB2_FB2(x) ((x)&0x03)
+#define GPIO_SRCR_FB2_FB2_MASK (0xFC)
+
+#define GPIO_SRCR_FB1_FB1(x) ((x)&0x03)
+#define GPIO_SRCR_FB1_FB1_MASK (0xFC)
+
+#define GPIO_SRCR_FB4_FB5(x) (((x)&0x03)<<2)
+#define GPIO_SRCR_FB4_FB5_MASK (0xF3)
+#define GPIO_SRCR_FB4_FB4(x) ((x)&0x03)
+#define GPIO_SRCR_FB4_FB4_MASK (0xFC)
+
+#define GPIO_SRCR_DSPIOW_OWDAT(x) (((x)&0x03)<<4)
+#define GPIO_SRCR_DSPIOW_OWDAT_MASK (0xCF)
+#define GPIO_SRCR_DSPIOW_DSPI0(x) ((x)&0x03)
+#define GPIO_SRCR_DSPIOW_DSPI0_MASK (0xFC)
+
+#define GPIO_SRCR_CANI2C_CAN1(x) (((x)&0x03)<<2)
+#define GPIO_SRCR_CANI2C_CAN1_MASK (0xF3)
+#define GPIO_SRCR_CANI2C_I2C0(x) ((x)&0x03)
+#define GPIO_SRCR_CANI2C_I2C0_MASK (0xFC)
+
+#define GPIO_SRCR_IRQ0_IRQ0(x) ((x)&0x03)
+#define GPIO_SRCR_IRQ0_IRQ0_MASK (0xFC)
+
+#define GPIO_SRCR_TIMER_TMR3(x) (((x)&0x03)<<6)
+#define GPIO_SRCR_TIMER_TMR3_MASK (0x3F)
+#define GPIO_SRCR_TIMER_TMR2(x) (((x)&0x03)<<4)
+#define GPIO_SRCR_TIMER_TMR2_MASK (0xCF)
+#define GPIO_SRCR_TIMER_TMR1(x) (((x)&0x03)<<2)
+#define GPIO_SRCR_TIMER_TMR1_MASK (0xF3)
+#define GPIO_SRCR_TIMER_TMR0(x) ((x)&0x03)
+#define GPIO_SRCR_TIMER_TMR0_MASK (0xFC)
+
+#define GPIO_SRCR_UART_U2(x) (((x)&0x03)<<4)
+#define GPIO_SRCR_UART_U2_MASK (0xCF)
+#define GPIO_SRCR_UART_U1(x) (((x)&0x03)<<2)
+#define GPIO_SRCR_UART_U1_MASK (0xF3)
+#define GPIO_SRCR_UART_U0(x) ((x)&0x03)
+#define GPIO_SRCR_UART_U0_MASK (0xFC)
+
+#define GPIO_SRCR_FEC_RMII0(x) (((x)&0x03)<<2)
+#define GPIO_SRCR_FEC_RMII0_MASK (0xF3)
+#define GPIO_SRCR_FEC_RMII1(x) ((x)&0x03)
+#define GPIO_SRCR_FEC_RMII1_MASK (0xFC)
+
+#define GPIO_SRCR_SDHC_SDHC(x) ((x)&0x03)
+#define GPIO_SRCR_SDHC_SDHC_MASK (0xFC)
+
+#define GPIO_SRCR_SIM0_SIMP0(x) ((x)&0x03)
+#define GPIO_SRCR_SIM0_SIMP0_MASK (0xFC)
+
+#define GPIO_SRCR_SSI0_SSI0(x) ((x)&0x03)
+#define GPIO_SRCR_SSI0_SSI0_MASK (0xFC)
+
+#define GPIO_PCR_URTS_U2 (0x0004)
+#define GPIO_PCR_URTS_U1 (0x0002)
+#define GPIO_PCR_URTS_U0 (0x0001)
+
+#define GPIO_PCR_UCTS_U2 (0x0004)
+#define GPIO_PCR_UCTS_U1 (0x0002)
+#define GPIO_PCR_UCTS_U0 (0x0001)
+
+#define GPIO_UTXD_WOM_U9 (0x0200)
+#define GPIO_UTXD_WOM_U8 (0x0100)
+#define GPIO_UTXD_WOM_U7 (0x0080)
+#define GPIO_UTXD_WOM_U6 (0x0040)
+#define GPIO_UTXD_WOM_U5 (0x0020)
+#define GPIO_UTXD_WOM_U4 (0x0010)
+#define GPIO_UTXD_WOM_U3 (0x0008)
+#define GPIO_UTXD_WOM_U2 (0x0004)
+#define GPIO_UTXD_WOM_U1 (0x0002)
+#define GPIO_UTXD_WOM_U0 (0x0001)
+
+#define GPIO_URXD_WOM_U9(x) (((x)&3)<<18)
+#define GPIO_URXD_WOM_U9_MASK (0xFFF3FFFF)
+#define GPIO_URXD_WOM_U8(x) (((x)&3)<<16)
+#define GPIO_URXD_WOM_U8_MASK (0xFFFCFFFF)
+#define GPIO_URXD_WOM_U7(x) (((x)&3)<<14)
+#define GPIO_URXD_WOM_U7_MASK (0xFFFF3FFF)
+#define GPIO_URXD_WOM_U6(x) (((x)&3)<<12)
+#define GPIO_URXD_WOM_U6_MASK (0xFFFFCFFF)
+#define GPIO_URXD_WOM_U5(x) (((x)&3)<<10)
+#define GPIO_URXD_WOM_U5_MASK (0xFFFFF3FF)
+#define GPIO_URXD_WOM_U4(x) (((x)&3)<<8)
+#define GPIO_URXD_WOM_U4_MASK (0xFFFFFCFF)
+#define GPIO_URXD_WOM_U3(x) (((x)&3)<<6)
+#define GPIO_URXD_WOM_U3_MASK (0xFFFFFF3F)
+#define GPIO_URXD_WOM_U2(x) (((x)&3)<<4)
+#define GPIO_URXD_WOM_U2_MASK (0xFFFFFFCF)
+#define GPIO_URXD_WOM_U1(x) (((x)&3)<<2)
+#define GPIO_URXD_WOM_U1_MASK (0xFFFFFFF3)
+#define GPIO_URXD_WOM_U0(x) ((x)&3)
+#define GPIO_URXD_WOM_U0_MASK (0xFFFFFFFC)
+
+#define GPIO_HCR1_PG4_0(x) (((x)&0x1F)<<27)
+#define GPIO_HCR1_PG4_0_MASK (0x07FFFFFF)
+#define GPIO_HCR1_PF7_3(x) (((x)&0x1F)<<22)
+#define GPIO_HCR1_PF7_3_MASK (0xF83FFFFF)
+#define GPIO_HCR1_PE6_0(x) (((x)&0x7F)<<15)
+#define GPIO_HCR1_PE6_0_MASK (0xFFC07FFF)
+#define GPIO_HCR1_PD7_3(x) (((x)&0x1F)<<10)
+#define GPIO_HCR1_PD7_3_MASK (0xFFFF83FF)
+#define GPIO_HCR1_PC7_1(x) (((x)&0x7F)<<3)
+#define GPIO_HCR1_PC7_1_MASK (0xFFFFFC07)
+#define GPIO_HCR1_PB2_0(x) ((x)&7)
+#define GPIO_HCR1_PB2_0_MASK (0xFFFFFFF8)
+
+#define GPIO_HCR0_PK3 (0x00000400)
+#define GPIO_HCR0_PK0 (0x00000200)
+#define GPIO_HCR0_PD2_0(x) (((x)&7)<<6)
+#define GPIO_HCR0_PD2_0_MASK (0xFFFFFE3F)
+#define GPIO_HCR0_PE7 (0x00000020)
+#define GPIO_HCR0_PH7_3(x) ((x)&0x1F)
+#define GPIO_HCR0_PH7_3_MASK(x) (0xFFFFFFE0)
+
+/* SDRAM Controller (SDRAMC) */
+
+/* Phase Locked Loop (PLL) */
+#define PLL_CR_LOCIRQ (0x00040000)
+#define PLL_CR_LOCRE (0x00020000)
+#define PLL_CR_LOCEN (0x00010000)
+#define PLL_CR_LOLIRQ (0x00004000)
+#define PLL_CR_LOLRE (0x00002000)
+#define PLL_CR_LOLEN (0x00001000)
+#define PLL_CR_REFDIV(x) (((x)&7)<<8)
+#define PLL_CR_REFDIV_MASK (0xFFFFF8FF)
+#define PLL_CR_FBKDIV(x) ((x)&0x3F)
+#define PLL_CR_FBKDIV_MASK (0xFFFFFFC0)
+#define PLL_CR_FBKDIV_BITS (0x3F)
+
+#define PLL_DR_OUTDIV5(x) (((x)&0x1F)<<21)
+#define PLL_DR_OUTDIV5_MASK (0xFC1FFFFF)
+#define PLL_DR_OUTDIV5_BITS (0x03E00000)
+#define PLL_DR_OUTDIV4(x) (((x)&0x1F)<<16)
+#define PLL_DR_OUTDIV4_MASK (0xFFE0FFFF)
+#define PLL_DR_OUTDIV4_BITS (0x001F0000)
+#define PLL_DR_OUTDIV3(x) (((x)&0x1F)<<10)
+#define PLL_DR_OUTDIV3_MASK (0xFFFF83FF)
+#define PLL_DR_OUTDIV3_BITS (0x00007C00)
+#define PLL_DR_OUTDIV2(x) (((x)&0x1F)<<5)
+#define PLL_DR_OUTDIV2_MASK (0xFFFFFC1F)
+#define PLL_DR_OUTDIV2_BITS (0x000003E0)
+#define PLL_DR_OUTDIV1(x) ((x)&0x1F)
+#define PLL_DR_OUTDIV1_MASK (0xFFFFFFE0)
+#define PLL_DR_OUTDIV1_BITS (0x0000001F)
+
+#define PLL_SR_LOCF (0x00000200)
+#define PLL_SR_LOC (0x00000100)
+#define PLL_SR_LOLF (0x00000040)
+#define PLL_SR_LOCKS (0x00000020)
+#define PLL_SR_LOCK (0x00000010)
+#define PLL_PSR_LOCK PLL_SR_LOCK /* compatible with 5x */
+#define PLL_SR_MODE(x) ((x)&7)
+#define PLL_SR_MODE_MASK (0xFFFFFFF8)
+
+#endif /* __MCF5441X__ */
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