]> git.sur5r.net Git - u-boot/commitdiff
odroid-c2: enable I2C
authorBeniamino Galvani <b.galvani@gmail.com>
Sun, 29 Oct 2017 09:09:01 +0000 (10:09 +0100)
committerHeiko Schocher <hs@denx.de>
Mon, 20 Nov 2017 09:11:44 +0000 (10:11 +0100)
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
arch/arm/include/asm/arch-meson/gxbb.h
board/amlogic/odroid-c2/odroid-c2.c
configs/odroid-c2_defconfig

index 74d5290340632b8a8e1c6907398de6fae45b53a4..95a6fe6998e249b2baed5e743bc3eecc82543e61 100644 (file)
@@ -47,6 +47,7 @@
 #define GXBB_GCLK_MPEG_OTHER   GXBB_HIU_ADDR(0x53)
 #define GXBB_GCLK_MPEG_AO      GXBB_HIU_ADDR(0x54)
 
+#define GXBB_GCLK_MPEG_0_I2C   BIT(9)
 #define GXBB_GCLK_MPEG_1_ETH   BIT(3)
 
 #endif /* __GXBB_H__ */
index eac04d8178d2806cd28dacae40bf5f0bb68f1db4..a5ea8dc5af2ff40fe22c7fac5289d771890264ee 100644 (file)
@@ -35,6 +35,7 @@ int misc_init_r(void)
                                     GXBB_ETH_REG_0_CLK_EN);
 
        /* Enable power and clock gate */
+       setbits_le32(GXBB_GCLK_MPEG_0, GXBB_GCLK_MPEG_0_I2C);
        setbits_le32(GXBB_GCLK_MPEG_1, GXBB_GCLK_MPEG_1_ETH);
        clrbits_le32(GXBB_MEM_PD_REG_0, GXBB_MEM_PD_REG_0_ETH_MASK);
 
index f7f8016644077665e810e78f75759b55a8ce76dc..1afd2fc1113302dbc674e50b7ac48c4cbdf3ba83 100644 (file)
@@ -11,12 +11,15 @@ CONFIG_DEBUG_UART=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
 # CONFIG_CMD_LOADS is not set
 CONFIG_CMD_MMC=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_OF_CONTROL=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_MESON_GX=y
 CONFIG_DM_ETH=y