return 0;
}
-phys_size_t initdram (int board_type)
-{
- unsigned long val;
-
- mtdcr(memcfga, mem_mb0cf);
- val = mfdcr(memcfgd);
-
- return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-}
-
#ifdef CONFIG_IDE_RESET
void ide_set_reset(int on)
{
common/cmd_mem.o (.text)
common/cmd_nvedit.o (.text)
common/console.o (.text)
- common/lists.o (.text)
common/main.o (.text)
/*
return 0;
}
-
-/* ------------------------------------------------------------------------- */
-
-int misc_init_f (void)
-{
- return 0; /* dummy implementation */
-}
-
-
int misc_init_r (void)
{
volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
return 0;
}
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- unsigned long val;
-
- mtdcr(memcfga, mem_mb0cf);
- val = mfdcr(memcfgd);
-
- return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-}
-
-/* ------------------------------------------------------------------------- */
-
void reset_phy(void)
{
#ifdef CONFIG_LXT971_NO_SLEEP
common/cmd_mem.o (.text)
common/cmd_nvedit.o (.text)
common/console.o (.text)
- common/lists.o (.text)
common/main.o (.text)
net/net.o (.text)
return 0;
}
-
-/* ------------------------------------------------------------------------- */
-
-int misc_init_f (void)
-{
- return 0; /* dummy implementation */
-}
-
-
int misc_init_r (void)
{
/* adjust flash start and offset */
/* ------------------------------------------------------------------------- */
-phys_size_t initdram (int board_type)
-{
- unsigned long val;
-
- mtdcr(memcfga, mem_mb0cf);
- val = mfdcr(memcfgd);
-
- return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-}
-
-/* ------------------------------------------------------------------------- */
-
#if defined(CFG_EEPROM_WREN)
/* Input: <dev_addr> I2C address of EEPROM device to enable.
* <state> -1: deliver current state
return 0;
}
-
-int misc_init_f (void)
-{
- return 0; /* dummy implementation */
-}
-
-
int misc_init_r (void)
{
unsigned long cntrl0Reg;
return 0;
}
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- unsigned long val;
-
- mtdcr(memcfga, mem_mb0cf);
- val = mfdcr(memcfgd);
-
- return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-}
-
-/* ------------------------------------------------------------------------- */
-
#if defined(CFG_EEPROM_WREN)
/* Input: <dev_addr> I2C address of EEPROM device to enable.
* <state> -1: deliver current state
}
}
-int misc_init_f (void)
-{
- return 0; /* dummy implementation */
-}
-
int misc_init_r (void)
{
unsigned long cntrl0Reg;
return 0;
}
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- unsigned long val;
-
- mtdcr(memcfga, mem_mb0cf);
- val = mfdcr(memcfgd);
-
- return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-}
-
void reset_phy(void)
{
#ifdef CONFIG_LXT971_NO_SLEEP
#endif
}
-/* ------------------------------------------------------------------------- */
-
#ifdef CONFIG_CPCI405_VER2
#ifdef CONFIG_IDE_RESET
return 0;
}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- return (16 * 1024 * 1024);
-}
-
-/* ------------------------------------------------------------------------- */
-
-int testdram (void)
-{
- /* TODO: XXX XXX XXX */
- printf ("test: 16 MB - ok\n");
-
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
return 0;
}
-
-/* ------------------------------------------------------------------------- */
-
phys_size_t initdram (int board_type)
{
return (16 * 1024 * 1024);
}
-
-/* ------------------------------------------------------------------------- */
-
-int testdram (void)
-{
- /* TODO: XXX XXX XXX */
- printf ("test: 16 MB - ok\n");
-
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
common/cmd_mem.o (.text)
common/cmd_nvedit.o (.text)
common/console.o (.text)
- common/lists.o (.text)
common/main.o (.text)
board/esd/dasa_sim/flash.o (.text)
return 0;
}
-
-/* ------------------------------------------------------------------------- */
-
-int misc_init_f (void)
-{
- return 0; /* dummy implementation */
-}
-
-
int misc_init_r (void)
{
/* adjust flash start and offset */
return 0;
}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- unsigned long val;
-
- mtdcr(memcfga, mem_mb0cf);
- val = mfdcr(memcfgd);
-
-#if 0
- printf("\nmb0cf=%x\n", val); /* test-only */
- printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
- return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-}
-
-/* ------------------------------------------------------------------------- */
-
-int testdram (void)
-{
- /* TODO: XXX XXX XXX */
- printf ("test: 16 MB - ok\n");
-
- return (0);
-}
return 0;
}
-
-
-phys_size_t initdram (int board_type)
-{
- return (16 * 1024 * 1024);
-}
-
-
-int testdram (void)
-{
- /* TODO: XXX XXX XXX */
- printf ("test: 16 MB - ok\n");
-
- return (0);
-}
return 0;
}
-
-phys_size_t initdram (int board_type)
-{
- unsigned long val;
-
- mtdcr(memcfga, mem_mb0cf);
- val = mfdcr(memcfgd);
-
-#if 0
- printf("\nmb0cf=%x\n", val); /* test-only */
- printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
- return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-}
-
-
#ifdef CONFIG_IDE_RESET
void ide_set_reset(int on)
{
return 0;
}
-
-int misc_init_f (void)
-{
- return 0; /* dummy implementation */
-}
-
-
int misc_init_r (void)
{
volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
return 0;
}
-
-
-phys_size_t initdram (int board_type)
-{
- unsigned long val;
-
- mtdcr(memcfga, mem_mb0cf);
- val = mfdcr(memcfgd);
-
- return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-}
return 0;
}
-
-int misc_init_f (void)
-{
- return 0; /* dummy implementation */
-}
-
-
/*
* Check Board Identity:
*/
return (0);
}
-
-
-phys_size_t initdram (int board_type)
-{
- unsigned long val;
-
- mtdcr (memcfga, mem_mb0cf);
- val = mfdcr (memcfgd);
-
-#if 0
- printf ("\nmb0cf=%x\n", val); /* test-only */
- printf ("strap=%x\n", mfdcr (strap)); /* test-only */
-#endif
-
- return (4 * 1024 * 1024 << ((val & 0x000e0000) >> 17));
-}
-
-
-int testdram (void)
-{
- /* TODO: XXX XXX XXX */
- printf ("test: 16 MB - ok\n");
-
- return (0);
-}
# esd PLU405 boards
#
-TEXT_BASE = 0xFFFC0000
-#TEXT_BASE = 0x00FC0000
+TEXT_BASE = 0xFFFA0000
int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
-
/* Prototypes */
int gunzip(void *, int, unsigned char *, unsigned long *);
-
int board_early_init_f (void)
{
/*
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */
mtdcr(uictr, 0x10000000); /* set int trigger levels */
- mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
+ mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest prio */
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
/*
- * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
+ * EBC Configuration Register: set ready timeout to
+ * 512 ebc-clks -> ca. 15 us
*/
mtebc (epcr, 0xa8400000); /* ebc always driven */
return 0;
}
-
-int misc_init_f (void)
-{
- return 0; /* dummy implementation */
-}
-
-
int misc_init_r (void)
{
unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
printf("\nFPGA: Booting failed ");
switch (status) {
case ERROR_FPGA_PRG_INIT_LOW:
- printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
+ printf("(Timeout: INIT not low "
+ "after asserting PROGRAM*)\n");
break;
case ERROR_FPGA_PRG_INIT_HIGH:
- printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
+ printf("(Timeout: INIT not high "
+ "after deasserting PROGRAM*)\n");
break;
case ERROR_FPGA_PRG_DONE:
- printf("(Timeout: DONE not high after programming FPGA)\n ");
+ printf("(Timeout: DONE not high "
+ "after programming FPGA)\n");
break;
}
/*
* Reset external DUARTs
*/
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
- udelay(10); /* wait 10us */
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
- udelay(1000); /* wait 1ms */
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_DUART_RST);
+ udelay(10);
+ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_DUART_RST);
+ udelay(1000);
/*
* Set NAND-FLASH GPIO signals to default
*/
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
+ out_be32((void*)GPIO0_OR,
+ in_be32((void*)GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_NAND_CE);
/*
return (0);
}
-
/*
* Check Board Identity:
*/
return 0;
}
-
-phys_size_t initdram (int board_type)
-{
- unsigned long val;
-
- mtdcr(memcfga, mem_mb0cf);
- val = mfdcr(memcfgd);
-
- return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-}
-
-
#ifdef CONFIG_IDE_RESET
void ide_set_reset(int on)
{
}
#endif /* CONFIG_IDE_RESET */
-
void reset_phy(void)
{
#ifdef CONFIG_LXT971_NO_SLEEP
#endif
}
-
#if defined(CFG_EEPROM_WREN)
/* Input: <dev_addr> I2C address of EEPROM device to enable.
* <state> -1: deliver current state
switch (state) {
case 1:
/* Enable write access, clear bit GPIO0. */
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_EEPROM_WP);
+ out_be32((void*)GPIO0_OR,
+ in_be32((void*)GPIO0_OR) & ~CFG_EEPROM_WP);
state = 0;
break;
case 0:
/* Disable write access, set bit GPIO0. */
- out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP);
+ out_be32((void*)GPIO0_OR,
+ in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP);
state = 0;
break;
default:
/* Read current status back. */
- state = (0 == (in_be32((void*)GPIO0_OR) & CFG_EEPROM_WP));
+ state = (0 == (in_be32((void*)GPIO0_OR) &
+ CFG_EEPROM_WP));
break;
}
}
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/4xx_uart.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
- cpu/ppc4xx/4xx_enet.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
-
-/* . = env_offset;*/
-/* common/environment.o(.text)*/
*(.text)
*(.fixup)
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
-
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
return 0;
}
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- unsigned long val;
-
- mtdcr(memcfga, mem_mb0cf);
- val = mfdcr(memcfgd);
-
-#if 0
- printf("\nmb0cf=%x\n", val); /* test-only */
- printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
- return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-}
-
-
/* ------------------------------------------------------------------------- */
void reset_phy(void)
{
return 0;
}
-
-int misc_init_f (void)
-{
- return 0; /* dummy implementation */
-}
-
-
int misc_init_r (void)
{
unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
return 0;
}
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- unsigned long val;
-
- mtdcr(memcfga, mem_mb0cf);
- val = mfdcr(memcfgd);
-
-#if 0
- printf("\nmb0cf=%x\n", val); /* test-only */
- printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
- return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-}
-
-/* ------------------------------------------------------------------------- */
-
-int testdram (void)
-{
- /* TODO: XXX XXX XXX */
- printf ("test: 16 MB - ok\n");
-
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
#ifdef CONFIG_IDE_RESET
void ide_set_reset(int on)
{
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/4xx_uart.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
-
-/* . = env_offset;*/
-/* common/environment.o(.text)*/
*(.text)
*(.fixup)
};
int filesize = sizeof(fpgadata);
-
int board_early_init_f (void)
{
/*
return 0;
}
-
-/* ------------------------------------------------------------------------- */
-
int misc_init_r (void)
{
/* adjust flash start and offset */
return (0);
}
-
/*
* Check Board Identity:
*/
-
int checkboard (void)
{
char str[64];
return 0;
}
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- unsigned long val;
-
- mtdcr(memcfga, mem_mb0cf);
- val = mfdcr(memcfgd);
-
-#if 0
- printf("\nmb0cf=%x\n", val); /* test-only */
- printf("strap=%x\n", mfdcr(strap)); /* test-only */
-#endif
-
- return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-}
-
-/* ------------------------------------------------------------------------- */
-
void reset_phy(void)
{
#ifdef CONFIG_LXT971_NO_SLEEP
return 0;
}
-
-/* ------------------------------------------------------------------------- */
-
-int misc_init_f (void)
-{
- return 0; /* dummy implementation */
-}
-
-
int misc_init_r (void)
{
volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
return 0;
}
-
-/* ------------------------------------------------------------------------- */
-
-phys_size_t initdram (int board_type)
-{
- unsigned long val;
-
- mtdcr(memcfga, mem_mb0cf);
- val = mfdcr(memcfgd);
-
- return (4*1024*1024 << ((val & 0x000e0000) >> 17));
-}
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
-#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
+#define CONFIG_RESET_PHY_R 1 /* use reset_phy() */
#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_USB
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
-/*-----------------------------------------------------------------------
+/*
* NAND-FLASH stuff
- *-----------------------------------------------------------------------
*/
-#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
+#define CFG_NAND_BASE_LIST {CFG_NAND_BASE}
#define NAND_MAX_CHIPS 1
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define NAND_BIG_DELAY_US 25
#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
#define CFG_NAND_QUIET 1
-/*-----------------------------------------------------------------------
+/*
* PCI stuff
- *-----------------------------------------------------------------------
*/
#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
#define PCI_HOST_FORCE 1 /* configure as pci host */
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
+#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
/* resource configuration */
#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
-#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
+#define CFG_PCI_PTM2PCI 0x08000000 /* Host: use this pci address */
-/*-----------------------------------------------------------------------
+/*
* IDE/ATA stuff
- *-----------------------------------------------------------------------
*/
#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
#undef CONFIG_IDE_LED /* no led for ide supported */
#define CONFIG_IDE_RESET 1 /* reset for ide supported */
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
-#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
+/* max. 1 drives per IDE bus */
+#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1)
#define CFG_ATA_BASE_ADDR 0xF0100000
#define CFG_ATA_IDE0_OFFSET 0x0000
-#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
-#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
-#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
+#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
+#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register access */
+#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*
* FLASH organization
*/
-#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
+#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
-#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
-#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
-#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
-#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
+#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
+#define CFG_FLASH_ADDR0 0x5555 /* 1st addr for flash config cycles */
+#define CFG_FLASH_ADDR1 0x2AAA /* 2nd addr for flash config cycles */
/*
* The following defines are added for buggy IOP480 byte interface.
* All other boards should use the standard values (CPCI405 etc.)
*/
-#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
-#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
-#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
+#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
+#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
+#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
-#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */
-/*-----------------------------------------------------------------------
+/*
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
-#define CFG_FLASH_BASE 0xFFFC0000
+#define CFG_FLASH_BASE 0xFFFA0000
#define CFG_MONITOR_BASE TEXT_BASE
-#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
-#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
+#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384kB for Monitor */
+#define CFG_MALLOC_LEN (384 * 1024) /* Reserve 384kB for malloc() */
-#if (CFG_MONITOR_BASE < FLASH_BASE0_PRELIM)
-# define CFG_RAMBOOT 1
-#else
-# undef CFG_RAMBOOT
-#endif
-
-/*-----------------------------------------------------------------------
+/*
* Environment Variable setup
*/
#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
- /* total size of a CAT24WC16 is 2048 bytes */
+#define CFG_ENV_OFFSET 0x100 /* reseve 0x100 bytes for strapping */
+#define CFG_ENV_SIZE 0x700
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC16) for environment
+/*
+ * I2C EEPROM (24WC16) for environment
*/
#define CONFIG_HARD_I2C /* I2c with hardware support */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
-#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */
+#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM 24WC16 */
#define CFG_EEPROM_WREN 1
-/* CAT24WC08/16... */
+/* 24WC16 */
#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
+/* mask of address bits that overflow into the "EEPROM chip address" */
#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
-#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
- /* 16 byte page write mode using*/
- /* last 4 bits of the address */
+#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The 24WC16 has */
+ /* 16 byte page write mode using */
+ /* last 4 bits of the address */
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
-/*-----------------------------------------------------------------------
+/*
* External Bus Controller (EBC) Setup
*/
-
-#define CAN_BA 0xF0000000 /* CAN Base Address */
-#define DUART0_BA 0xF0000400 /* DUART Base Address */
-#define DUART1_BA 0xF0000408 /* DUART Base Address */
-#define RTC_BA 0xF0000500 /* RTC Base Address */
-#define VGA_BA 0xF1000000 /* Epson VGA Base Address */
-#define CFG_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */
-
-/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
+#define CAN_BA 0xF0000000 /* CAN Base Address */
+#define DUART0_BA 0xF0000400 /* DUART Base Address */
+#define DUART1_BA 0xF0000408 /* DUART Base Address */
+#define RTC_BA 0xF0000500 /* RTC Base Address */
+#define VGA_BA 0xF1000000 /* Epson VGA Base Address */
+#define CFG_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */
+
+/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
+/* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
#define CFG_EBC_PB0AP 0x92015480
-/*#define CFG_EBC_PB0AP 0x08055880 /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
-#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+/* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+#define CFG_EBC_PB0CR 0xFFC5A000
-/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
+/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
#define CFG_EBC_PB1AP 0x92015480
-#define CFG_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
+/* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
+#define CFG_EBC_PB1CR 0xF4018000
-/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
-#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
+/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
+/* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB2AP 0x010053C0
+/* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
+#define CFG_EBC_PB2CR 0xF0018000
-/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */
-#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */
+/* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB3AP 0x010053C0
+/* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+#define CFG_EBC_PB3CR 0xF011A000
-/*-----------------------------------------------------------------------
+/*
* FPGA stuff
*/
-
-#define CFG_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */
+#define CFG_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */
/* FPGA internal regs */
#define CFG_FPGA_CTRL 0x000
#define CFG_FPGA_CTRL_WDI 0x0002
#define CFG_FPGA_CTRL_PS2_RESET 0x0020
-#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
+#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
#define CFG_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
/* FPGA program pin configuration */
#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
-#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
-#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
-#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
-#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
+#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
+#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
+#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
+#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
-/*-----------------------------------------------------------------------
+/*
* Definitions for initial stack pointer and data area (in data cache)
*/
/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
/* On Chip Memory location */
#define CFG_OCM_DATA_ADDR 0xF8000000
#define CFG_OCM_DATA_SIZE 0x1000
-#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
-#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
+#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
+#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
-#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-/*-----------------------------------------------------------------------
+/*
* Definitions for GPIO setup (PPC405EP specific)
*
* GPIO0[0] - External Bus Controller BLAST output
*
* Boot Flags
*/
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
/*
- * Default speed selection (cpu_plb_opb_ebc) in mhz.
+ * Default speed selection (cpu_plb_opb_ebc) in MHz.
* This value will be set if iic boot eprom is disabled.
*/
-#if 0
+#if 1
#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
#endif
#define PLLMR0_DEFAULT PLLMR0_200_100_50_33
#define PLLMR1_DEFAULT PLLMR1_200_100_50_33
#endif
-#if 1
+#if 0
#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
#endif
+/*
+ * PCI OHCI controller
+ */
+#define CONFIG_USB_OHCI_NEW 1
+#define CONFIG_PCI_OHCI 1
+#define CFG_OHCI_SWAP_REG_ACCESS 1
+#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
+#define CFG_USB_OHCI_SLOT_NAME "ohci_pci"
+#define CONFIG_USB_STORAGE 1
+
#endif /* __CONFIG_H */
/*
* board/config.h - configuration options, board specific
*/
-
#ifndef __CONFIG_H
#define __CONFIG_H
* High Level Configuration Options
* (easy to change)
*/
-
#define CONFIG_405EP 1 /* This is a PPC405 CPU */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_VOM405 1 /* ...on a VOM405 board */
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
-
/*
* Command line configuration.
*/
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_BSP
-#define CONFIG_CMD_PCI
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_ELF
#define CONFIG_CMD_I2C
#define CONFIG_CMD_PING
#define CONFIG_CMD_EEPROM
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
-#undef CONFIG_PCI_PNP /* do pci plug-and-play */
- /* resource configuration */
-
-#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
-
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
-#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
-#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
-#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
-#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
-
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
+/*
* FLASH organization
*/
#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-#if 0 /* test-only */
-#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
-#endif
-
-/*-----------------------------------------------------------------------
+/*
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CFG_SDRAM_BASE _must_ start at 0
# undef CFG_RAMBOOT
#endif
-/*-----------------------------------------------------------------------
+/*
* Environment Variable setup
*/
#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
#define CFG_NVRAM_SIZE 242 /* NVRAM size */
-/*-----------------------------------------------------------------------
+/*
* I2C EEPROM (CAT24WC16) for environment
*/
#define CONFIG_HARD_I2C /* I2c with hardware support */
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
-/*-----------------------------------------------------------------------
+/*
* External Bus Controller (EBC) Setup
*/
-
#define CAN_BA 0xF0000000 /* CAN Base Address */
/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
-/*-----------------------------------------------------------------------
+/*
* FPGA stuff
*/
#define CFG_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */
#define CFG_FPGA_INIT 0x00010000 /* unused (ppc input) */
#define CFG_FPGA_DONE 0x00008000 /* JTAG TDI->TDO pin (ppc input) */
-/*-----------------------------------------------------------------------
+/*
* Definitions for initial stack pointer and data area (in data cache)
*/
/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-/*-----------------------------------------------------------------------
+/*
* Definitions for GPIO setup (PPC405EP specific)
*
* GPIO0[0] - External Bus Controller BLAST output
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