.rx_flow = 22,
};
+#ifndef CONFIG_SOC_K2G
static void keystone2_net_serdes_setup(void);
+#endif
int keystone2_eth_read_mac_addr(struct eth_device *dev)
{
(status & SGMII_REG_STATUS_LINK);
}
+#ifdef CONFIG_SOC_K2G
+int keystone_rgmii_config(struct phy_device *phy_dev)
+{
+ unsigned int i, status;
+
+ i = 0;
+ do {
+ if (i > SGMII_ANEG_TIMEOUT) {
+ puts(" TIMEOUT !\n");
+ phy_dev->link = 0;
+ return 0;
+ }
+
+ if (ctrlc()) {
+ puts("user interrupt!\n");
+ phy_dev->link = 0;
+ return -EINTR;
+ }
+
+ if ((i++ % 500) == 0)
+ printf(".");
+
+ udelay(1000); /* 1 ms */
+ status = readl(RGMII_STATUS_REG);
+ } while (!(status & RGMII_REG_STATUS_LINK));
+
+ puts(" done\n");
+
+ return 0;
+}
+#else
int keystone_sgmii_config(struct phy_device *phy_dev, int port, int interface)
{
unsigned int i, status, mask;
return 0;
}
+#endif
int mac_sl_reset(u32 port)
{
writel(cfg->max_rx_len, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN);
writel(cfg->ctl, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL);
-#if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
+#ifndef CONFIG_SOC_K2HK
/* Map RX packet flow priority to 0 */
writel(0, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RX_PRI_MAP);
#endif
if (sys_has_mdio)
keystone2_mdio_reset(mdio_bus);
+#ifdef CONFIG_SOC_K2G
+ keystone_rgmii_config(phy_dev);
+#else
keystone_sgmii_config(phy_dev, eth_priv->slave_port - 1,
eth_priv->sgmii_link_type);
+#endif
udelay(10000);
return res;
}
+#ifndef CONFIG_SOC_K2G
keystone2_net_serdes_setup();
+#endif
/* Create phy device and bind it with driver */
#ifdef CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE
.loopback = 0,
};
+#ifndef CONFIG_SOC_K2G
static void keystone2_net_serdes_setup(void)
{
ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE,
/* wait till setup */
udelay(5000);
}
+#endif