ARM: mxs: Configure 2 Gbit DDR2 RAM for BG0900

The BG0900 module has 2Gbit DRAM module on it, adjust the DataBahn
DRAM controller registers so the DRAM module will be correctly
recognised.

Signed-off-by: Christoph G. Baumann <c.baumann@ppc-ag.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>

diff --git a/board/ppcag/bg0900/spl_boot.c b/board/ppcag/bg0900/spl_boot.c
index 2616e1fadafd89553ce742e597946f6e7ba60f9b..a04c9553e40ddf185e8d5a6dffca33705e918343 100644 (file)
--- a/board/ppcag/bg0900/spl_boot.c
+++ b/board/ppcag/bg0900/spl_boot.c
@@ -118,6 +118,19 @@ const iomux_cfg_t iomux_setup[] = {
 
 void mxs_adjust_memory_params(uint32_t *dram_vals)
 {
+       /*
+        * DDR Controller Registers
+        * Manufacturer:        Winbond
+        * Device Part Number:  W972GG6JB-25I
+        * Clock Freq.:         200MHz
+        * Density:             2Gb
+        * Chip Selects:        1
+        * Number of Banks:     8
+        * Row address:         14
+        * Column address:      10
+        */
+
+       dram_vals[0x74 / 4] = 0x0102010A;
        dram_vals[0x98 / 4] = 0x04005003;
        dram_vals[0x9c / 4] = 0x090000c8;