nds32: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment

Add ARCH_DMA_MINALIGN definition to asm/cache.h

Signed-off-by: Macpaul Lin <macpaul@andestech.com>

diff --git a/arch/nds32/include/asm/cache.h b/arch/nds32/include/asm/cache.h
index d7691962131ef8223bf10981831ef0afe4407622..fc22c7bc0526d090fa591aac0bdb5702c539165a 100644 (file)
--- a/arch/nds32/include/asm/cache.h
+++ b/arch/nds32/include/asm/cache.h
@@ -51,4 +51,15 @@ DEFINE_GET_SYS_REG(DCM_CFG);
 #define DCM_CFG_OFF_DSZ        6       /* D-cache line size */
 #define DCM_CFG_MSK_DSZ        (0x7UL << DCM_CFG_OFF_DSZ)
 
+/*
+ * The current upper bound for NDS32 L1 data cache line sizes is 32 bytes.
+ * We use that value for aligning DMA buffers unless the board config has
+ * specified an alternate cache line size.
+ */
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+#define ARCH_DMA_MINALIGN      CONFIG_SYS_CACHELINE_SIZE
+#else
+#define ARCH_DMA_MINALIGN      32
+#endif
+
 #endif /* _ASM_CACHE_H */