]> git.sur5r.net Git - u-boot/commitdiff
usb: dwc2-otg: adjust fifo size via platform data
authorXu Ziyuan <xzy.xu@rock-chips.com>
Thu, 14 Jul 2016 06:52:33 +0000 (14:52 +0800)
committerSimon Glass <sjg@chromium.org>
Tue, 26 Jul 2016 02:44:19 +0000 (20:44 -0600)
The total FIFO size of some SoCs may be different from the existen, this
patch supports fifo size setting from platform data.

Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
drivers/usb/gadget/dwc2_udc_otg.c
drivers/usb/gadget/dwc2_udc_otg_regs.h
include/usb/dwc2_udc.h

index a23278d957a6a184e4d04b184c860afa0a401c66..029927f8ac15bf07c6c9183132f69b9e0ebb80bc 100644 (file)
@@ -403,6 +403,7 @@ static void reconfig_usbd(struct dwc2_udc *dev)
        int i;
        unsigned int uTemp = writel(CORE_SOFT_RESET, &reg->grstctl);
        uint32_t dflt_gusbcfg;
+       uint32_t rx_fifo_sz, tx_fifo_sz, np_tx_fifo_sz;
 
        debug("Reseting OTG controller\n");
 
@@ -467,18 +468,27 @@ static void reconfig_usbd(struct dwc2_udc *dev)
        /* 10. Unmask device IN EP common interrupts*/
        writel(DIEPMSK_INIT, &reg->diepmsk);
 
+       rx_fifo_sz = RX_FIFO_SIZE;
+       np_tx_fifo_sz = NPTX_FIFO_SIZE;
+       tx_fifo_sz = PTX_FIFO_SIZE;
+
+       if (dev->pdata->rx_fifo_sz)
+               rx_fifo_sz = dev->pdata->rx_fifo_sz;
+       if (dev->pdata->np_tx_fifo_sz)
+               np_tx_fifo_sz = dev->pdata->np_tx_fifo_sz;
+       if (dev->pdata->tx_fifo_sz)
+               tx_fifo_sz = dev->pdata->tx_fifo_sz;
+
        /* 11. Set Rx FIFO Size (in 32-bit words) */
-       writel(RX_FIFO_SIZE >> 2, &reg->grxfsiz);
+       writel(rx_fifo_sz, &reg->grxfsiz);
 
        /* 12. Set Non Periodic Tx FIFO Size */
-       writel((NPTX_FIFO_SIZE >> 2) << 16 | ((RX_FIFO_SIZE >> 2)) << 0,
+       writel((np_tx_fifo_sz << 16) | rx_fifo_sz,
               &reg->gnptxfsiz);
 
        for (i = 1; i < DWC2_MAX_HW_ENDPOINTS; i++)
-               writel((PTX_FIFO_SIZE >> 2) << 16 |
-                      ((RX_FIFO_SIZE + NPTX_FIFO_SIZE +
-                        PTX_FIFO_SIZE*(i-1)) >> 2) << 0,
-                      &reg->dieptxf[i-1]);
+               writel((rx_fifo_sz + np_tx_fifo_sz + tx_fifo_sz*(i-1)) |
+                       tx_fifo_sz << 16, &reg->dieptxf[i-1]);
 
        /* Flush the RX FIFO */
        writel(RX_FIFO_FLUSH, &reg->grstctl);
index 78ec90ea9f4387632cfa9796be0cd14d61c17871..c94396afc02648828fe9b81ef11fe7e647d49a51 100644 (file)
@@ -130,9 +130,9 @@ struct dwc2_usbotg_reg {
 #define HIGH_SPEED_CONTROL_PKT_SIZE    64
 #define HIGH_SPEED_BULK_PKT_SIZE       512
 
-#define RX_FIFO_SIZE                   (1024*4)
-#define NPTX_FIFO_SIZE                 (1024*4)
-#define PTX_FIFO_SIZE                  (1536*1)
+#define RX_FIFO_SIZE                   (1024)
+#define NPTX_FIFO_SIZE                 (1024)
+#define PTX_FIFO_SIZE                  (384)
 
 #define DEPCTL_TXFNUM_0                (0x0<<22)
 #define DEPCTL_TXFNUM_1                (0x1<<22)
index 3ce43f8c011be3c8dd685838beb5a515fc470e4e..7324d8a62db49b5f0f62bbcec3be4bcbe1564d03 100644 (file)
@@ -20,6 +20,9 @@ struct dwc2_plat_otg_data {
        unsigned int    usb_phy_ctrl;
        unsigned int    usb_flags;
        unsigned int    usb_gusbcfg;
+       unsigned int    rx_fifo_sz;
+       unsigned int    np_tx_fifo_sz;
+       unsigned int    tx_fifo_sz;
 };
 
 int dwc2_udc_probe(struct dwc2_plat_otg_data *pdata);