OMAP3: fix DRAM size for IGEP-based boards.

The total RAM size of the IGEP-based boards is 512MiB not 1GiB, the
LPDDR memory consist on two dies of 256MiB.

Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com>
Tested-by: Javier Martinez Canillas <javier@dowhile0.org>

diff --git a/board/isee/igep0020/igep0020.c b/board/isee/igep0020/igep0020.c
index a4d099a5db6d8cb4bf8ca62817e8feea2ba71a60..a8257a3005fab8d93d0b373afd15e64954d23ccb 100644 (file)
--- a/board/isee/igep0020/igep0020.c
+++ b/board/isee/igep0020/igep0020.c
@@ -77,19 +77,19 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
 {
        *mr = MICRON_V_MR_165;
 #ifdef CONFIG_BOOT_NAND
-       *mcfg = MICRON_V_MCFG_200(512 << 20);
+       *mcfg = MICRON_V_MCFG_200(256 << 20);
        *ctrla = MICRON_V_ACTIMA_200;
        *ctrlb = MICRON_V_ACTIMB_200;
        *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
 #else
        if (get_cpu_family() == CPU_OMAP34XX) {
-               *mcfg = NUMONYX_V_MCFG_165(512 << 20);
+               *mcfg = NUMONYX_V_MCFG_165(256 << 20);
                *ctrla = NUMONYX_V_ACTIMA_165;
                *ctrlb = NUMONYX_V_ACTIMB_165;
                *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
 
        } else {
-               *mcfg = NUMONYX_V_MCFG_200(512 << 20);
+               *mcfg = NUMONYX_V_MCFG_200(256 << 20);
                *ctrla = NUMONYX_V_ACTIMA_200;
                *ctrlb = NUMONYX_V_ACTIMB_200;
                *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;

diff --git a/board/isee/igep0030/igep0030.c b/board/isee/igep0030/igep0030.c
index 4f8b6452df4f9ff209e278a817dd710cb88a1ac6..107cb7f8e0581d0f8c7c5487773e6873eec70cfe 100644 (file)
--- a/board/isee/igep0030/igep0030.c
+++ b/board/isee/igep0030/igep0030.c
@@ -64,19 +64,19 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
 {
        *mr = MICRON_V_MR_165;
 #ifdef CONFIG_BOOT_NAND
-       *mcfg = MICRON_V_MCFG_200(512 << 20);
+       *mcfg = MICRON_V_MCFG_200(256 << 20);
        *ctrla = MICRON_V_ACTIMA_200;
        *ctrlb = MICRON_V_ACTIMB_200;
        *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
 #else
        if (get_cpu_family() == CPU_OMAP34XX) {
-               *mcfg = NUMONYX_V_MCFG_165(512 << 20);
+               *mcfg = NUMONYX_V_MCFG_165(256 << 20);
                *ctrla = NUMONYX_V_ACTIMA_165;
                *ctrlb = NUMONYX_V_ACTIMB_165;
                *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
 
        } else {
-               *mcfg = NUMONYX_V_MCFG_200(512 << 20);
+               *mcfg = NUMONYX_V_MCFG_200(256 << 20);
                *ctrla = NUMONYX_V_ACTIMA_200;
                *ctrlb = NUMONYX_V_ACTIMB_200;
                *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;