]> git.sur5r.net Git - u-boot/commitdiff
Add UART base addresses for additional UARTs
authorLandheer-Cieslak, Ronald <ronaldlandheercieslak@eaton.com>
Wed, 25 Oct 2017 13:46:53 +0000 (13:46 +0000)
committerTom Rini <trini@konsulko.com>
Fri, 17 Nov 2017 15:53:45 +0000 (10:53 -0500)
UARTs 1 through 5 were missing in the code - added.
Also pick the default according to the configuration setting for the
console index.

Signed-off-by: Ronald Landheer-Cieslak <ronaldlandheercieslak@eaton.com>
arch/arm/include/asm/arch-am33xx/hardware.h
arch/arm/include/asm/arch-am33xx/hardware_am33xx.h

index 3437e6116da5ff74a74e45bc1de1f65a648cca8e..c2cc849f322a1ed250517a534a2b86a5e2d99773 100644 (file)
 #define DDR_CONTROL_BASE_ADDR          0x44E11404
 
 /* UART */
-#define DEFAULT_UART_BASE              UART0_BASE
+#if CONFIG_CONS_INDEX == 1
+#      define DEFAULT_UART_BASE UART0_BASE
+#elif CONFIG_CONS_INDEX == 2
+#      define DEFAULT_UART_BASE UART1_BASE
+#elif CONFIG_CONS_INDEX == 3
+#      define DEFAULT_UART_BASE UART2_BASE
+#elif CONFIG_CONS_INDEX == 4
+#      define DEFAULT_UART_BASE UART3_BASE
+#elif CONFIG_CONS_INDEX == 5
+#      define DEFAULT_UART_BASE UART4_BASE
+#elif CONFIG_CONS_INDEX == 6
+#      define DEFAULT_UART_BASE UART5_BASE
+#endif
 
 /* GPMC Base address */
 #define GPMC_BASE                      0x50000000
index fa9b84f95b4deca64b56e24654e976ab536d7765..3e462834554557761f0a25649455b367868638bd 100644 (file)
 
 /* UART Base Address */
 #define UART0_BASE                     0x44E09000
+#define UART1_BASE                     0x48022000
+#define UART2_BASE                     0x48024000
+#define UART3_BASE                     0x481A6000
+#define UART4_BASE                     0x481A8000
+#define UART5_BASE                     0x481AA000
 
 /* GPIO Base address */
 #define GPIO2_BASE                     0x481AC000