u32 dram_timing4; /* 0x10 */
u32 lowpwr_timing;
u32 dram_odt;
- u32 __padding0[4];
+ u32 extratime1;
+ u32 __padding0[3];
u32 dram_addrw; /* 0x2c */
u32 dram_if_width; /* 0x30 */
u32 dram_dev_width;
u32 dram_timing4;
u32 lowpwr_timing;
u32 dram_odt;
+ u32 extratime1;
u32 dram_addrw;
u32 dram_if_width;
u32 dram_dev_width;
/* Field instance: sdr::ctrlgrp::dramsts */
#define SDR_CTRLGRP_DRAMSTS_DBEERR_MASK 0x00000008
#define SDR_CTRLGRP_DRAMSTS_SBEERR_MASK 0x00000004
+/* Register template: sdr::ctrlgrp::extratime1 */
+#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB 20
+#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB 24
+#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB 28
/* SDRAM width macro for configuration with ECC */
#define SDRAM_WIDTH_32BIT_WITH_ECC 40
# Filter out only the macros which are actually used by the code
#
grep_sdram_config() {
- egrep "#define (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN|CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA|CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP|CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP|CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP|CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP|CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR|CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN|CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC|CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46|CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4|CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64|RW_MGR_ACTIVATE_0_AND_1|RW_MGR_ACTIVATE_0_AND_1_WAIT1|RW_MGR_ACTIVATE_0_AND_1_WAIT2|RW_MGR_ACTIVATE_1|RW_MGR_CLEAR_DQS_ENABLE|RW_MGR_GUARANTEED_READ|RW_MGR_GUARANTEED_READ_CONT|RW_MGR_GUARANTEED_WRITE|RW_MGR_GUARANTEED_WRITE_WAIT0|RW_MGR_GUARANTEED_WRITE_WAIT1|RW_MGR_GUARANTEED_WRITE_WAIT2|RW_MGR_GUARANTEED_WRITE_WAIT3|RW_MGR_IDLE|RW_MGR_IDLE_LOOP1|RW_MGR_IDLE_LOOP2|RW_MGR_INIT_RESET_0_CKE_0|RW_MGR_INIT_RESET_1_CKE_0|RW_MGR_LFSR_WR_RD_BANK_0|RW_MGR_LFSR_WR_RD_BANK_0_DATA|RW_MGR_LFSR_WR_RD_BANK_0_DQS|RW_MGR_LFSR_WR_RD_BANK_0_NOP|RW_MGR_LFSR_WR_RD_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_BANK_0_WL_1|RW_MGR_LFSR_WR_RD_DM_BANK_0|RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA|RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS|RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP|RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1|RW_MGR_MRS0_DLL_RESET|RW_MGR_MRS0_DLL_RESET_MIRR|RW_MGR_MRS0_USER|RW_MGR_MRS0_USER_MIRR|RW_MGR_MRS1|RW_MGR_MRS1_MIRR|RW_MGR_MRS2|RW_MGR_MRS2_MIRR|RW_MGR_MRS3|RW_MGR_MRS3_MIRR|RW_MGR_PRECHARGE_ALL|RW_MGR_READ_B2B|RW_MGR_READ_B2B_WAIT1|RW_MGR_READ_B2B_WAIT2|RW_MGR_REFRESH_ALL|RW_MGR_RETURN|RW_MGR_SGLE_READ|RW_MGR_ZQCL|RW_MGR_TRUE_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_ADDRESS_MIRRORING|RW_MGR_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_DATA_WIDTH|RW_MGR_MEM_DQ_PER_READ_DQS|RW_MGR_MEM_DQ_PER_WRITE_DQS|RW_MGR_MEM_IF_READ_DQS_WIDTH|RW_MGR_MEM_IF_WRITE_DQS_WIDTH|RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM|RW_MGR_MEM_NUMBER_OF_RANKS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS|IO_DELAY_PER_DCHAIN_TAP|IO_DELAY_PER_DQS_EN_DCHAIN_TAP|IO_DELAY_PER_OPA_TAP|IO_DLL_CHAIN_LENGTH|IO_DQDQS_OUT_PHASE_MAX|IO_DQS_EN_DELAY_MAX|IO_DQS_EN_DELAY_OFFSET|IO_DQS_EN_PHASE_MAX|IO_DQS_IN_DELAY_MAX|IO_DQS_IN_RESERVE|IO_DQS_OUT_RESERVE|IO_IO_IN_DELAY_MAX|IO_IO_OUT1_DELAY_MAX|IO_IO_OUT2_DELAY_MAX|IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS|AFI_RATE_RATIO|CALIB_LFIFO_OFFSET|CALIB_VFIFO_OFFSET|ENABLE_SUPER_QUICK_CALIBRATION|MAX_LATENCY_COUNT_WIDTH|READ_VALID_FIFO_SIZE|REG_FILE_INIT_SEQ_SIGNATURE|TINIT_CNTR0_VAL|TINIT_CNTR1_VAL|TINIT_CNTR2_VAL|TRESET_CNTR0_VAL|TRESET_CNTR1_VAL|TRESET_CNTR2_VAL)[[:space:]]"
+ egrep "#define (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN|CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA|CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP|CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP|CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP|CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP|CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR|CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN|CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC|CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46|CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4|CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64|RW_MGR_ACTIVATE_0_AND_1|RW_MGR_ACTIVATE_0_AND_1_WAIT1|RW_MGR_ACTIVATE_0_AND_1_WAIT2|RW_MGR_ACTIVATE_1|RW_MGR_CLEAR_DQS_ENABLE|RW_MGR_GUARANTEED_READ|RW_MGR_GUARANTEED_READ_CONT|RW_MGR_GUARANTEED_WRITE|RW_MGR_GUARANTEED_WRITE_WAIT0|RW_MGR_GUARANTEED_WRITE_WAIT1|RW_MGR_GUARANTEED_WRITE_WAIT2|RW_MGR_GUARANTEED_WRITE_WAIT3|RW_MGR_IDLE|RW_MGR_IDLE_LOOP1|RW_MGR_IDLE_LOOP2|RW_MGR_INIT_RESET_0_CKE_0|RW_MGR_INIT_RESET_1_CKE_0|RW_MGR_LFSR_WR_RD_BANK_0|RW_MGR_LFSR_WR_RD_BANK_0_DATA|RW_MGR_LFSR_WR_RD_BANK_0_DQS|RW_MGR_LFSR_WR_RD_BANK_0_NOP|RW_MGR_LFSR_WR_RD_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_BANK_0_WL_1|RW_MGR_LFSR_WR_RD_DM_BANK_0|RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA|RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS|RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP|RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1|RW_MGR_MRS0_DLL_RESET|RW_MGR_MRS0_DLL_RESET_MIRR|RW_MGR_MRS0_USER|RW_MGR_MRS0_USER_MIRR|RW_MGR_MRS1|RW_MGR_MRS1_MIRR|RW_MGR_MRS2|RW_MGR_MRS2_MIRR|RW_MGR_MRS3|RW_MGR_MRS3_MIRR|RW_MGR_PRECHARGE_ALL|RW_MGR_READ_B2B|RW_MGR_READ_B2B_WAIT1|RW_MGR_READ_B2B_WAIT2|RW_MGR_REFRESH_ALL|RW_MGR_RETURN|RW_MGR_SGLE_READ|RW_MGR_ZQCL|RW_MGR_TRUE_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_ADDRESS_MIRRORING|RW_MGR_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_DATA_WIDTH|RW_MGR_MEM_DQ_PER_READ_DQS|RW_MGR_MEM_DQ_PER_WRITE_DQS|RW_MGR_MEM_IF_READ_DQS_WIDTH|RW_MGR_MEM_IF_WRITE_DQS_WIDTH|RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM|RW_MGR_MEM_NUMBER_OF_RANKS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS|IO_DELAY_PER_DCHAIN_TAP|IO_DELAY_PER_DQS_EN_DCHAIN_TAP|IO_DELAY_PER_OPA_TAP|IO_DLL_CHAIN_LENGTH|IO_DQDQS_OUT_PHASE_MAX|IO_DQS_EN_DELAY_MAX|IO_DQS_EN_DELAY_OFFSET|IO_DQS_EN_PHASE_MAX|IO_DQS_IN_DELAY_MAX|IO_DQS_IN_RESERVE|IO_DQS_OUT_RESERVE|IO_IO_IN_DELAY_MAX|IO_IO_OUT1_DELAY_MAX|IO_IO_OUT2_DELAY_MAX|IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS|AFI_RATE_RATIO|CALIB_LFIFO_OFFSET|CALIB_VFIFO_OFFSET|ENABLE_SUPER_QUICK_CALIBRATION|MAX_LATENCY_COUNT_WIDTH|READ_VALID_FIFO_SIZE|REG_FILE_INIT_SEQ_SIGNATURE|TINIT_CNTR0_VAL|TINIT_CNTR1_VAL|TINIT_CNTR2_VAL|TRESET_CNTR0_VAL|TRESET_CNTR1_VAL|TRESET_CNTR2_VAL|CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR|CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC|CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP)[[:space:]]"
}
#
SDR_CTRLGRP_DRAMODT_READ_LSB) |
(CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
SDR_CTRLGRP_DRAMODT_WRITE_LSB),
+ .extratime1 =
+ (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR <<
+ SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC <<
+ SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB) |
+(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP <<
+ SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB),
.dram_addrw =
(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB) |
config CMD_DDRPHY_DUMP
bool "Enable dump command of DDR PHY parameters"
- depends on ARCH_UNIPHIER_LD4 || ARCH_UNIPHIER_PRO4 || ARCH_UNIPHIER_SLD8
+ depends on ARCH_UNIPHIER_LD4 || ARCH_UNIPHIER_PRO4 || \
+ ARCH_UNIPHIER_SLD8 || ARCH_UNIPHIER_LD11
default y
help
The command "ddrphy" shows the resulting parameters of DDR PHY
/*
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2014 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
+ * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#endif
}
-#define VENDOR_PREFIX "socionext,"
-#define DTB_FILE_PREFIX "uniphier-"
-
static int uniphier_set_fdt_file(void)
{
DECLARE_GLOBAL_DATA_PTR;
const char *compat;
char dtb_name[256];
- int buf_len = 256;
+ int buf_len = sizeof(dtb_name);
if (getenv("fdt_file"))
return 0; /* do nothing if it is already set */
if (!compat)
return -EINVAL;
- if (strncmp(compat, VENDOR_PREFIX, strlen(VENDOR_PREFIX)))
+ /* rip off the vendor prefix "socionext," */
+ compat = strchr(compat, ',');
+ if (!compat)
return -EINVAL;
+ compat++;
- compat += strlen(VENDOR_PREFIX);
-
- strncat(dtb_name, DTB_FILE_PREFIX, buf_len);
- buf_len -= strlen(DTB_FILE_PREFIX);
-
- strncat(dtb_name, compat, buf_len);
+ strncpy(dtb_name, compat, buf_len);
buf_len -= strlen(compat);
strncat(dtb_name, ".dtb", buf_len);
*/
#include <common.h>
+#include <spl.h>
#include <linux/bitops.h>
#include <linux/io.h>
+#include "../boot-mode/boot-device.h"
#include "../init.h"
+#include "../sc64-regs.h"
#include "../sg-regs.h"
void uniphier_ld11_clk_init(void)
{
- if (readl(SG_PINMON0) & BIT(27)) {
- /* if booted without stand-by MPU */
-
+ /* if booted from a device other than USB, without stand-by MPU */
+ if ((readl(SG_PINMON0) & BIT(27)) &&
+ spl_boot_device_raw() != BOOT_DEVICE_USB) {
writel(1, SG_ETPHYPSHUT);
writel(1, SG_ETPHYCNT);
writel(3, SG_ETPHYPSHUT);
writel(7, SG_ETPHYCNT);
}
+
+#ifdef CONFIG_USB_EHCI
+ {
+ /* FIXME: the current clk driver can not handle parents */
+ u32 tmp;
+ tmp = readl(SC_CLKCTRL4);
+ tmp |= SC_CLKCTRL4_MIO | SC_CLKCTRL4_STDMAC;
+ writel(tmp, SC_CLKCTRL4);
+ }
+#endif
}
int uniphier_ld20_dpll_init(const struct uniphier_board_data *bd)
{
- unsigned int dpll_ssc_rate = UNIPHIER_BD_DPLL_SSC_GET_RATE(bd->flags);
- unsigned int dram_freq = bd->dram_freq;
-
- uniphier_ld20_sscpll_init(SC_DPLL0CTRL, dram_freq, dpll_ssc_rate, 2);
- uniphier_ld20_sscpll_init(SC_DPLL1CTRL, dram_freq, dpll_ssc_rate, 2);
- uniphier_ld20_sscpll_init(SC_DPLL2CTRL, dram_freq, dpll_ssc_rate, 2);
+ uniphier_ld20_sscpll_init(SC_DPLL0CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
+ uniphier_ld20_sscpll_init(SC_DPLL1CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
+ uniphier_ld20_sscpll_init(SC_DPLL2CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2);
return 0;
}
if (!base)
return -ENOMEM;
- mdelay(1);
-
tmp = readl(base); /* SSCPLLCTRL */
tmp |= SC_PLLCTRL_SSC_EN;
writel(tmp, base);
int uniphier_ld20_pll_init(const struct uniphier_board_data *bd)
{
- unsigned int dpll_ssc_rate = UNIPHIER_BD_DPLL_SSC_GET_RATE(bd->flags);
-
uniphier_ld20_sscpll_init(SC_CPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
/* do nothing for SPLL */
uniphier_ld20_sscpll_init(SC_SPLL2CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4);
mdelay(1);
- if (dpll_ssc_rate > 0) {
- uniphier_ld20_sscpll_ssc_en(SC_DPLL0CTRL);
- uniphier_ld20_sscpll_ssc_en(SC_DPLL1CTRL);
- uniphier_ld20_sscpll_ssc_en(SC_DPLL2CTRL);
- }
+ uniphier_ld20_sscpll_ssc_en(SC_CPLLCTRL);
+ uniphier_ld20_sscpll_ssc_en(SC_SPLL2CTRL);
+ uniphier_ld20_sscpll_ssc_en(SC_MPLLCTRL);
+ uniphier_ld20_sscpll_ssc_en(SC_VPPLLCTRL);
+ uniphier_ld20_sscpll_ssc_en(SC_GPPLLCTRL);
+ uniphier_ld20_sscpll_ssc_en(SC_DPLL0CTRL);
+ uniphier_ld20_sscpll_ssc_en(SC_DPLL1CTRL);
+ uniphier_ld20_sscpll_ssc_en(SC_DPLL2CTRL);
uniphier_ld20_vpll27_init(SC_VPLL27FCTRL);
uniphier_ld20_vpll27_init(SC_VPLL27ACTRL);
/* field separator */
#define FS " "
-static unsigned long uniphier_ld4_base[] = {
- 0x5bc01000,
- 0x5be01000,
- 0 /* sentinel */
+#define ptr_to_uint(p) ((unsigned int)(unsigned long)(p))
+
+struct phy_param {
+ resource_size_t base;
+ unsigned int nr_dx;
+};
+
+static const struct phy_param uniphier_ld4_phy_param[] = {
+ { .base = 0x5bc01000, .nr_dx = 2, },
+ { .base = 0x5be01000, .nr_dx = 2, },
+ { /* sentinel */ }
+};
+
+static const struct phy_param uniphier_pro4_phy_param[] = {
+ { .base = 0x5bc01000, .nr_dx = 2, },
+ { .base = 0x5bc02000, .nr_dx = 2, },
+ { .base = 0x5be01000, .nr_dx = 2, },
+ { .base = 0x5be02000, .nr_dx = 2, },
+ { /* sentinel */ }
};
-static unsigned long uniphier_pro4_base[] = {
- 0x5bc01000,
- 0x5be01000,
- 0 /* sentinel */
+static const struct phy_param uniphier_sld8_phy_param[] = {
+ { .base = 0x5bc01000, .nr_dx = 2, },
+ { .base = 0x5be01000, .nr_dx = 2, },
+ { /* sentinel */ }
};
-static unsigned long uniphier_sld8_base[] = {
- 0x5bc01000,
- 0x5be01000,
- 0 /* sentinel */
+static const struct phy_param uniphier_ld11_phy_param[] = {
+ { .base = 0x5bc01000, .nr_dx = 4, },
+ { /* sentinel */ }
};
-static u32 read_bdl(struct ddrphy_datx8 __iomem *dx, int index)
+static void print_bdl(void __iomem *reg, int n)
{
- return (readl(&dx->bdlr[index / 5]) >> (index % 5 * 6)) & 0x3f;
+ u32 val = readl(reg);
+ int i;
+
+ for (i = 0; i < n; i++)
+ printf(FS PRINTF_FORMAT, (val >> i * 6) & 0x3f);
}
-static void dump_loop(unsigned long *base,
- void (*callback)(struct ddrphy_datx8 __iomem *))
+static void dump_loop(const struct phy_param *phy_param,
+ void (*callback)(void __iomem *))
{
- struct ddrphy __iomem *phy;
+ void __iomem *phy_base, *dx_base;
int p, dx;
- for (p = 0; *base; base++, p++) {
- phy = ioremap(*base, SZ_4K);
+ for (p = 0; phy_param->base; phy_param++, p++) {
+ phy_base = ioremap(phy_param->base, SZ_4K);
+ dx_base = phy_base + PHY_DX_BASE;
- for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) {
+ for (dx = 0; dx < phy_param->nr_dx; dx++) {
printf("PHY%dDX%d:", p, dx);
- (*callback)(&phy->dx[dx]);
+ (*callback)(dx_base);
+ dx_base += PHY_DX_STRIDE;
printf("\n");
}
- iounmap(phy);
+ iounmap(phy_base);
}
}
-static void __wbdl_dump(struct ddrphy_datx8 __iomem *dx)
+static void __wbdl_dump(void __iomem *dx_base)
{
- int i;
+ print_bdl(dx_base + PHY_DX_BDLR0, 5);
+ print_bdl(dx_base + PHY_DX_BDLR1, 5);
- for (i = 0; i < 10; i++)
- printf(FS PRINTF_FORMAT, read_bdl(dx, i));
-
- printf(FS "(+" PRINTF_FORMAT ")", readl(&dx->lcdlr[1]) & 0xff);
+ printf(FS "(+" PRINTF_FORMAT ")",
+ readl(dx_base + PHY_DX_LCDLR1) & 0xff);
}
-static void wbdl_dump(unsigned long *base)
+static void wbdl_dump(const struct phy_param *phy_param)
{
printf("\n--- Write Bit Delay Line ---\n");
printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS (WDQD)\n");
- dump_loop(base, &__wbdl_dump);
+ dump_loop(phy_param, &__wbdl_dump);
}
-static void __rbdl_dump(struct ddrphy_datx8 __iomem *dx)
+static void __rbdl_dump(void __iomem *dx_base)
{
- int i;
+ print_bdl(dx_base + PHY_DX_BDLR3, 5);
+ print_bdl(dx_base + PHY_DX_BDLR4, 4);
- for (i = 15; i < 24; i++)
- printf(FS PRINTF_FORMAT, read_bdl(dx, i));
-
- printf(FS "(+" PRINTF_FORMAT ")", (readl(&dx->lcdlr[1]) >> 8) & 0xff);
+ printf(FS "(+" PRINTF_FORMAT ")",
+ (readl(dx_base + PHY_DX_LCDLR1) >> 8) & 0xff);
}
-static void rbdl_dump(unsigned long *base)
+static void rbdl_dump(const struct phy_param *phy_param)
{
printf("\n--- Read Bit Delay Line ---\n");
printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM (RDQSD)\n");
- dump_loop(base, &__rbdl_dump);
+ dump_loop(phy_param, &__rbdl_dump);
}
-static void __wld_dump(struct ddrphy_datx8 __iomem *dx)
+static void __wld_dump(void __iomem *dx_base)
{
int rank;
- u32 lcdlr0 = readl(&dx->lcdlr[0]);
- u32 gtr = readl(&dx->gtr);
+ u32 lcdlr0 = readl(dx_base + PHY_DX_LCDLR0);
+ u32 gtr = readl(dx_base + PHY_DX_GTR);
for (rank = 0; rank < 4; rank++) {
u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */
}
}
-static void wld_dump(unsigned long *base)
+static void wld_dump(const struct phy_param *phy_param)
{
printf("\n--- Write Leveling Delay ---\n");
printf(" Rank0 Rank1 Rank2 Rank3\n");
- dump_loop(base, &__wld_dump);
+ dump_loop(phy_param, &__wld_dump);
}
-static void __dqsgd_dump(struct ddrphy_datx8 __iomem *dx)
+static void __dqsgd_dump(void __iomem *dx_base)
{
int rank;
- u32 lcdlr2 = readl(&dx->lcdlr[2]);
- u32 gtr = readl(&dx->gtr);
+ u32 lcdlr2 = readl(dx_base + PHY_DX_LCDLR2);
+ u32 gtr = readl(dx_base + PHY_DX_GTR);
for (rank = 0; rank < 4; rank++) {
u32 dqsgd = (lcdlr2 >> (8 * rank)) & 0xff; /* Delay */
}
}
-static void dqsgd_dump(unsigned long *base)
+static void dqsgd_dump(const struct phy_param *phy_param)
{
printf("\n--- DQS Gating Delay ---\n");
printf(" Rank0 Rank1 Rank2 Rank3\n");
- dump_loop(base, &__dqsgd_dump);
+ dump_loop(phy_param, &__dqsgd_dump);
}
-static void __mdl_dump(struct ddrphy_datx8 __iomem *dx)
+static void __mdl_dump(void __iomem *dx_base)
{
int i;
- u32 mdl = readl(&dx->mdlr);
+ u32 mdl = readl(dx_base + PHY_DX_MDLR);
for (i = 0; i < 3; i++)
printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff);
}
-static void mdl_dump(unsigned long *base)
+static void mdl_dump(const struct phy_param *phy_param)
{
printf("\n--- Master Delay Line ---\n");
printf(" IPRD TPRD MDLD\n");
- dump_loop(base, &__mdl_dump);
+ dump_loop(phy_param, &__mdl_dump);
}
-#define REG_DUMP(x) \
- { u32 __iomem *p = &phy->x; printf("%3d: %-10s: %p : %08x\n", \
- p - (u32 *)phy, #x, p, readl(p)); }
-
-static void reg_dump(unsigned long *base)
+#define REG_DUMP(x) \
+ { int ofst = PHY_ ## x; void __iomem *reg = phy_base + ofst; \
+ printf("%3d: %-10s: %08x : %08x\n", \
+ ofst >> PHY_REG_SHIFT, #x, \
+ ptr_to_uint(reg), readl(reg)); }
+
+#define DX_REG_DUMP(dx, x) \
+ { int ofst = PHY_DX_BASE + PHY_DX_STRIDE * (dx) + \
+ PHY_DX_## x; \
+ void __iomem *reg = phy_base + ofst; \
+ printf("%3d: DX%d%-7s: %08x : %08x\n", \
+ ofst >> PHY_REG_SHIFT, (dx), #x, \
+ ptr_to_uint(reg), readl(reg)); }
+
+static void reg_dump(const struct phy_param *phy_param)
{
- struct ddrphy __iomem *phy;
- int p;
+ void __iomem *phy_base;
+ int p, dx;
printf("\n--- DDR PHY registers ---\n");
- for (p = 0; *base; base++, p++) {
- phy = ioremap(*base, SZ_4K);
+ for (p = 0; phy_param->base; phy_param++, p++) {
+ phy_base = ioremap(phy_param->base, SZ_4K);
- printf("== PHY%d (base: %p) ==\n", p, phy);
+ printf("== PHY%d (base: %08x) ==\n", p, ptr_to_uint(phy_base));
printf(" No: Name : Address : Data\n");
- REG_DUMP(ridr);
- REG_DUMP(pir);
- REG_DUMP(pgcr[0]);
- REG_DUMP(pgcr[1]);
- REG_DUMP(pgsr[0]);
- REG_DUMP(pgsr[1]);
- REG_DUMP(pllcr);
- REG_DUMP(ptr[0]);
- REG_DUMP(ptr[1]);
- REG_DUMP(ptr[2]);
- REG_DUMP(ptr[3]);
- REG_DUMP(ptr[4]);
- REG_DUMP(acmdlr);
- REG_DUMP(acbdlr);
- REG_DUMP(dxccr);
- REG_DUMP(dsgcr);
- REG_DUMP(dcr);
- REG_DUMP(dtpr[0]);
- REG_DUMP(dtpr[1]);
- REG_DUMP(dtpr[2]);
- REG_DUMP(mr0);
- REG_DUMP(mr1);
- REG_DUMP(mr2);
- REG_DUMP(mr3);
- REG_DUMP(dx[0].gcr);
- REG_DUMP(dx[0].gtr);
- REG_DUMP(dx[1].gcr);
- REG_DUMP(dx[1].gtr);
-
- iounmap(phy);
+ REG_DUMP(RIDR);
+ REG_DUMP(PIR);
+ REG_DUMP(PGCR0);
+ REG_DUMP(PGCR1);
+ REG_DUMP(PGSR0);
+ REG_DUMP(PGSR1);
+ REG_DUMP(PLLCR);
+ REG_DUMP(PTR0);
+ REG_DUMP(PTR1);
+ REG_DUMP(PTR2);
+ REG_DUMP(PTR3);
+ REG_DUMP(PTR4);
+ REG_DUMP(ACMDLR);
+ REG_DUMP(ACBDLR);
+ REG_DUMP(DXCCR);
+ REG_DUMP(DSGCR);
+ REG_DUMP(DCR);
+ REG_DUMP(DTPR0);
+ REG_DUMP(DTPR1);
+ REG_DUMP(DTPR2);
+ REG_DUMP(MR0);
+ REG_DUMP(MR1);
+ REG_DUMP(MR2);
+ REG_DUMP(MR3);
+
+ for (dx = 0; dx < phy_param->nr_dx; dx++) {
+ DX_REG_DUMP(dx, GCR);
+ DX_REG_DUMP(dx, GTR);
+ }
+
+ iounmap(phy_base);
}
}
static int do_ddr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
char *cmd = argv[1];
- unsigned long *base;
+ const struct phy_param *phy_param;
switch (uniphier_get_soc_type()) {
case SOC_UNIPHIER_LD4:
- base = uniphier_ld4_base;
+ phy_param = uniphier_ld4_phy_param;
break;
case SOC_UNIPHIER_PRO4:
- base = uniphier_pro4_base;
+ phy_param = uniphier_pro4_phy_param;
break;
case SOC_UNIPHIER_SLD8:
- base = uniphier_sld8_base;
+ phy_param = uniphier_sld8_phy_param;
+ break;
+ case SOC_UNIPHIER_LD11:
+ phy_param = uniphier_ld11_phy_param;
break;
default:
printf("unsupported SoC\n");
cmd = "all";
if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all"))
- wbdl_dump(base);
+ wbdl_dump(phy_param);
if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all"))
- rbdl_dump(base);
+ rbdl_dump(phy_param);
if (!strcmp(cmd, "wld") || !strcmp(cmd, "all"))
- wld_dump(base);
+ wld_dump(phy_param);
if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all"))
- dqsgd_dump(base);
+ dqsgd_dump(phy_param);
if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all"))
- mdl_dump(base);
+ mdl_dump(phy_param);
if (!strcmp(cmd, "reg") || !strcmp(cmd, "all"))
- reg_dump(base);
+ reg_dump(phy_param);
return CMD_RET_SUCCESS;
}
--- /dev/null
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef ARCH_DDRPHY_INIT_H
+#define ARCH_DDRPHY_INTT_H
+
+#include <linux/compiler.h>
+#include <linux/types.h>
+
+int uniphier_ld4_ddrphy_init(void __iomem *phy_base, int freq, bool ddr3plus);
+void ddrphy_prepare_training(void __iomem *phy_base, int rank);
+int ddrphy_training(void __iomem *phy_base);
+
+#endif /* ARCH_DDRPHY_INT_H */
+++ /dev/null
-/*
- * Copyright (C) 2016 Socionext Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _DDRPHY_LD20_REGS_H
-#define _DDRPHY_LD20_REGS_H
-
-#include <linux/bitops.h>
-
-#define PHY_REG_SHIFT 2
-#define PHY_SLV_DLY_WIDTH 6
-#define PHY_BITLVL_DLY_WIDTH 6
-#define PHY_MAS_DLY_WIDTH 8
-
-#define PHY_SCL_START (0x40 << (PHY_REG_SHIFT))
-#define PHY_SCL_DATA_0 (0x41 << (PHY_REG_SHIFT))
-#define PHY_SCL_DATA_1 (0x42 << (PHY_REG_SHIFT))
-#define PHY_SCL_LATENCY (0x43 << (PHY_REG_SHIFT))
-#define PHY_SCL_CONFIG_1 (0x46 << (PHY_REG_SHIFT))
-#define PHY_SCL_CONFIG_2 (0x47 << (PHY_REG_SHIFT))
-#define PHY_PAD_CTRL (0x48 << (PHY_REG_SHIFT))
-#define PHY_DLL_RECALIB (0x49 << (PHY_REG_SHIFT))
-#define PHY_DLL_RECALIB_TRIM_MASK GENMASK(PHY_SLV_DLY_WIDTH - 1, 0)
-#define PHY_DLL_RECALIB_INCR BIT(27)
-#define PHY_DLL_ADRCTRL (0x4A << (PHY_REG_SHIFT))
-#define PHY_DLL_ADRCTRL_TRIM_MASK GENMASK(PHY_SLV_DLY_WIDTH - 1, 0)
-#define PHY_DLL_ADRCTRL_INCR BIT(9)
-#define PHY_DLL_ADRCTRL_MDL_SHIFT 24
-#define PHY_DLL_ADRCTRL_MDL_MASK (GENMASK(PHY_MAS_DLY_WIDTH - 1, 0) << \
- PHY_DLL_ADRCTRL_MDL_SHIFT)
-#define PHY_LANE_SEL (0x4B << (PHY_REG_SHIFT))
-#define PHY_LANE_SEL_LANE_SHIFT 0
-#define PHY_LANE_SEL_LANE_WIDTH 8
-#define PHY_LANE_SEL_BIT_SHIFT 8
-#define PHY_LANE_SEL_BIT_WIDTH 4
-#define PHY_DLL_TRIM_1 (0x4C << (PHY_REG_SHIFT))
-#define PHY_DLL_TRIM_2 (0x4D << (PHY_REG_SHIFT))
-#define PHY_DLL_TRIM_3 (0x4E << (PHY_REG_SHIFT))
-#define PHY_SCL_MAIN_CLK_DELTA (0x50 << (PHY_REG_SHIFT))
-#define PHY_WRLVL_AUTOINC_TRIM (0x53 << (PHY_REG_SHIFT))
-#define PHY_WRLVL_DYN_ODT (0x54 << (PHY_REG_SHIFT))
-#define PHY_WRLVL_ON_OFF (0x55 << (PHY_REG_SHIFT))
-#define PHY_UNQ_ANALOG_DLL_1 (0x57 << (PHY_REG_SHIFT))
-#define PHY_UNQ_ANALOG_DLL_2 (0x58 << (PHY_REG_SHIFT))
-#define PHY_DLL_INCR_TRIM_1 (0x59 << (PHY_REG_SHIFT))
-#define PHY_DLL_INCR_TRIM_3 (0x5A << (PHY_REG_SHIFT))
-#define PHY_SCL_CONFIG_3 (0x5B << (PHY_REG_SHIFT))
-#define PHY_UNIQUIFY_TSMC_IO_1 (0x5C << (PHY_REG_SHIFT))
-#define PHY_SCL_START_ADDR (0x62 << (PHY_REG_SHIFT))
-#define PHY_IP_DQ_DQS_BITWISE_TRIM (0x65 << (PHY_REG_SHIFT))
-#define PHY_IP_DQ_DQS_BITWISE_TRIM_MASK \
- GENMASK(PHY_BITLVL_DLY_WIDTH - 1, 0)
-#define PHY_IP_DQ_DQS_BITWISE_TRIM_INC \
- BIT(PHY_BITLVL_DLY_WIDTH)
-#define PHY_IP_DQ_DQS_BITWISE_TRIM_OVERRIDE \
- BIT(PHY_BITLVL_DLY_WIDTH + 1)
-#define PHY_DSCL_CNT (0x67 << (PHY_REG_SHIFT))
-#define PHY_OP_DQ_DM_DQS_BITWISE_TRIM (0x68 << (PHY_REG_SHIFT))
-#define PHY_OP_DQ_DM_DQS_BITWISE_TRIM_MASK \
- GENMASK(PHY_BITLVL_DLY_WIDTH - 1, 0)
-#define PHY_OP_DQ_DM_DQS_BITWISE_TRIM_INC \
- BIT(PHY_BITLVL_DLY_WIDTH)
-#define PHY_OP_DQ_DM_DQS_BITWISE_TRIM_OVERRIDE \
- BIT(PHY_BITLVL_DLY_WIDTH + 1)
-#define PHY_DLL_TRIM_CLK (0x69 << (PHY_REG_SHIFT))
-#define PHY_DLL_TRIM_CLK_MASK GENMASK(PHY_SLV_DLY_WIDTH, 0)
-#define PHY_DLL_TRIM_CLK_INCR BIT(PHY_SLV_DLY_WIDTH + 1)
-#define PHY_DYNAMIC_BIT_LVL (0x6B << (PHY_REG_SHIFT))
-#define PHY_SCL_WINDOW_TRIM (0x6D << (PHY_REG_SHIFT))
-#define PHY_DISABLE_GATING_FOR_SCL (0x6E << (PHY_REG_SHIFT))
-#define PHY_SCL_CONFIG_4 (0x6F << (PHY_REG_SHIFT))
-#define PHY_DYNAMIC_WRITE_BIT_LVL (0x70 << (PHY_REG_SHIFT))
-#define PHY_VREF_TRAINING (0x72 << (PHY_REG_SHIFT))
-#define PHY_SCL_GATE_TIMING (0x78 << (PHY_REG_SHIFT))
-
-#endif /* _DDRPHY_LD20_REGS_H */
/*
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2014 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/err.h>
-#include <linux/types.h>
#include <linux/io.h>
+#include "ddrphy-init.h"
#include "ddrphy-regs.h"
enum dram_freq {
static u32 ddrphy_mr0[DRAM_FREQ_NR] = {0x00000b51, 0x00000d71};
static u32 ddrphy_mr2[DRAM_FREQ_NR] = {0x00000290, 0x00000298};
-int uniphier_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq,
- bool ddr3plus)
+int uniphier_ld4_ddrphy_init(void __iomem *phy_base, int freq, bool ddr3plus)
{
enum dram_freq freq_e;
u32 tmp;
return -EINVAL;
}
- writel(0x0300c473, &phy->pgcr[1]);
- writel(ddrphy_ptr0[freq_e], &phy->ptr[0]);
- writel(ddrphy_ptr1[freq_e], &phy->ptr[1]);
- writel(0x00083DEF, &phy->ptr[2]);
- writel(ddrphy_ptr3[freq_e], &phy->ptr[3]);
- writel(ddrphy_ptr4[freq_e], &phy->ptr[4]);
- writel(0xF004001A, &phy->dsgcr);
+ writel(0x0300c473, phy_base + PHY_PGCR1);
+ writel(ddrphy_ptr0[freq_e], phy_base + PHY_PTR0);
+ writel(ddrphy_ptr1[freq_e], phy_base + PHY_PTR1);
+ writel(0x00083DEF, phy_base + PHY_PTR2);
+ writel(ddrphy_ptr3[freq_e], phy_base + PHY_PTR3);
+ writel(ddrphy_ptr4[freq_e], phy_base + PHY_PTR4);
+ writel(0xF004001A, phy_base + PHY_DSGCR);
/* change the value of the on-die pull-up/pull-down registors */
- tmp = readl(&phy->dxccr);
+ tmp = readl(phy_base + PHY_DXCCR);
tmp &= ~0x0ee0;
- tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM;
- writel(tmp, &phy->dxccr);
+ tmp |= PHY_DXCCR_DQSNRES_688_OHM | PHY_DXCCR_DQSRES_688_OHM;
+ writel(tmp, phy_base + PHY_DXCCR);
- writel(0x0000040B, &phy->dcr);
- writel(ddrphy_dtpr0[freq_e], &phy->dtpr[0]);
- writel(ddrphy_dtpr1[freq_e], &phy->dtpr[1]);
- writel(ddrphy_dtpr2[freq_e], &phy->dtpr[2]);
- writel(ddrphy_mr0[freq_e], &phy->mr0);
- writel(0x00000006, &phy->mr1);
- writel(ddrphy_mr2[freq_e], &phy->mr2);
- writel(ddr3plus ? 0x00000800 : 0x00000000, &phy->mr3);
+ writel(0x0000040B, phy_base + PHY_DCR);
+ writel(ddrphy_dtpr0[freq_e], phy_base + PHY_DTPR0);
+ writel(ddrphy_dtpr1[freq_e], phy_base + PHY_DTPR1);
+ writel(ddrphy_dtpr2[freq_e], phy_base + PHY_DTPR2);
+ writel(ddrphy_mr0[freq_e], phy_base + PHY_MR0);
+ writel(0x00000006, phy_base + PHY_MR1);
+ writel(ddrphy_mr2[freq_e], phy_base + PHY_MR2);
+ writel(ddr3plus ? 0x00000800 : 0x00000000, phy_base + PHY_MR3);
- while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))
+ while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE))
;
- writel(0x0300C473, &phy->pgcr[1]);
- writel(0x0000005D, &phy->zq[0].cr[1]);
+ writel(0x0300C473, phy_base + PHY_PGCR1);
+ writel(0x0000005D, phy_base + PHY_ZQ_BASE + PHY_ZQ_CR1);
return 0;
}
/*
* UniPhier DDR PHY registers
*
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2014 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef ARCH_DDRPHY_REGS_H
#define ARCH_DDRPHY_REGS_H
-#include <linux/bitops.h>
-#include <linux/compiler.h>
-#include <linux/types.h>
+#define PHY_REG_SHIFT 2
-#ifndef __ASSEMBLY__
-
-struct ddrphy {
- u32 ridr; /* Revision Identification Register */
- u32 pir; /* PHY Initialixation Register */
- u32 pgcr[2]; /* PHY General Configuration Register */
- u32 pgsr[2]; /* PHY General Status Register */
- u32 pllcr; /* PLL Control Register */
- u32 ptr[5]; /* PHY Timing Register */
- u32 acmdlr; /* AC Master Delay Line Register */
- u32 acbdlr; /* AC Bit Delay Line Register */
- u32 aciocr; /* AC I/O Configuration Register */
- u32 dxccr; /* DATX8 Common Configuration Register */
- u32 dsgcr; /* DDR System General Configuration Register */
- u32 dcr; /* DRAM Configuration Register */
- u32 dtpr[3]; /* DRAM Timing Parameters Register */
- u32 mr0; /* Mode Register 0 */
- u32 mr1; /* Mode Register 1 */
- u32 mr2; /* Mode Register 2 */
- u32 mr3; /* Mode Register 3 */
- u32 odtcr; /* ODT Configuration Register */
- u32 dtcr; /* Data Training Configuration Register */
- u32 dtar[4]; /* Data Training Address Register */
- u32 dtdr[2]; /* Data Training Data Register */
- u32 dtedr[2]; /* Data Training Eye Data Register */
- u32 pgcr2; /* PHY General Configuration Register 2 */
- u32 rsv0[8]; /* Reserved */
- u32 rdimmgcr[2]; /* RDIMM General Configuration Register */
- u32 rdimmcr0[2]; /* RDIMM Control Register */
- u32 dcuar; /* DCU Address Register */
- u32 dcudr; /* DCU Data Register */
- u32 dcurr; /* DCU Run Register */
- u32 dculr; /* DCU Loop Register */
- u32 dcugcr; /* DCU General Configuration Register */
- u32 dcutpr; /* DCU Timing Parameters Register */
- u32 dcusr[2]; /* DCU Status Register */
- u32 rsv1[8]; /* Reserved */
- u32 bistrr; /* BIST Run Register */
- u32 bistwcr; /* BIST Word Count Register */
- u32 bistmskr[3]; /* BIST Mask Register */
- u32 bistlsr; /* BIST LFSR Sed Register */
- u32 bistar[3]; /* BIST Address Register */
- u32 bistudpr; /* BIST User Data Pattern Register */
- u32 bistgsr; /* BIST General Status Register */
- u32 bistwer; /* BIST Word Error Register */
- u32 bistber[4]; /* BIST Bit Error Register */
- u32 bistwcsr; /* BIST Word Count Status Register */
- u32 bistfwr[3]; /* BIST Fail Word Register */
- u32 rsv2[10]; /* Reserved */
- u32 gpr[2]; /* General Purpose Register */
- struct ddrphy_zq { /* ZQ */
- u32 cr[2]; /* Impedance Control Register */
- u32 sr[2]; /* Impedance Status Register */
- } zq[4];
- struct ddrphy_datx8 { /* DATX8 */
- u32 gcr; /* General Configuration Register */
- u32 gsr[2]; /* General Status Register */
- u32 bdlr[5]; /* Bit Delay Line Register */
- u32 lcdlr[3]; /* Local Calibrated Delay Line Register */
- u32 mdlr; /* Master Delay Line Register */
- u32 gtr; /* General Timing Register */
- u32 gsr2; /* General Status Register 2 */
- u32 rsv[2]; /* Reserved */
- } dx[9];
-};
-
-#endif /* __ASSEMBLY__ */
-
-#define PIR_INIT BIT(0) /* Initialization Trigger */
-#define PIR_ZCAL BIT(1) /* Impedance Calibration */
-#define PIR_PLLINIT BIT(4) /* PLL Initialization */
-#define PIR_DCAL BIT(5) /* DDL Calibration */
-#define PIR_PHYRST BIT(6) /* PHY Reset */
-#define PIR_DRAMRST BIT(7) /* DRAM Reset */
-#define PIR_DRAMINIT BIT(8) /* DRAM Initialization */
-#define PIR_WL BIT(9) /* Write Leveling */
-#define PIR_QSGATE BIT(10) /* Read DQS Gate Training */
-#define PIR_WLADJ BIT(11) /* Write Leveling Adjust */
-#define PIR_RDDSKW BIT(12) /* Read Data Bit Deskew */
-#define PIR_WRDSKW BIT(13) /* Write Data Bit Deskew */
-#define PIR_RDEYE BIT(14) /* Read Data Eye Training */
-#define PIR_WREYE BIT(15) /* Write Data Eye Training */
-#define PIR_LOCKBYP BIT(28) /* PLL Lock Bypass */
-#define PIR_DCALBYP BIT(29) /* DDL Calibration Bypass */
-#define PIR_ZCALBYP BIT(30) /* Impedance Calib Bypass */
-#define PIR_INITBYP BIT(31) /* Initialization Bypass */
-
-#define PGSR0_IDONE BIT(0) /* Initialization Done */
-#define PGSR0_PLDONE BIT(1) /* PLL Lock Done */
-#define PGSR0_DCDONE BIT(2) /* DDL Calibration Done */
-#define PGSR0_ZCDONE BIT(3) /* Impedance Calibration Done */
-#define PGSR0_DIDONE BIT(4) /* DRAM Initialization Done */
-#define PGSR0_WLDONE BIT(5) /* Write Leveling Done */
-#define PGSR0_QSGDONE BIT(6) /* DQS Gate Training Done */
-#define PGSR0_WLADONE BIT(7) /* Write Leveling Adjust Done */
-#define PGSR0_RDDONE BIT(8) /* Read Bit Deskew Done */
-#define PGSR0_WDDONE BIT(9) /* Write Bit Deskew Done */
-#define PGSR0_REDONE BIT(10) /* Read Eye Training Done */
-#define PGSR0_WEDONE BIT(11) /* Write Eye Training Done */
-#define PGSR0_IERR BIT(16) /* Initialization Error */
-#define PGSR0_PLERR BIT(17) /* PLL Lock Error */
-#define PGSR0_DCERR BIT(18) /* DDL Calibration Error */
-#define PGSR0_ZCERR BIT(19) /* Impedance Calib Error */
-#define PGSR0_DIERR BIT(20) /* DRAM Initialization Error */
-#define PGSR0_WLERR BIT(21) /* Write Leveling Error */
-#define PGSR0_QSGERR BIT(22) /* DQS Gate Training Error */
-#define PGSR0_WLAERR BIT(23) /* Write Leveling Adj Error */
-#define PGSR0_RDERR BIT(24) /* Read Bit Deskew Error */
-#define PGSR0_WDERR BIT(25) /* Write Bit Deskew Error */
-#define PGSR0_REERR BIT(26) /* Read Eye Training Error */
-#define PGSR0_WEERR BIT(27) /* Write Eye Training Error */
-#define PGSR0_DTERR_SHIFT 28 /* Data Training Error Status*/
-#define PGSR0_DTERR (7 << (PGSR0_DTERR_SHIFT))
-#define PGSR0_APLOCK BIT(31) /* AC PLL Lock */
-
-#define DXCCR_DQSRES_OPEN (0 << 5)
-#define DXCCR_DQSRES_688_OHM (1 << 5)
-#define DXCCR_DQSRES_611_OHM (2 << 5)
-#define DXCCR_DQSRES_550_OHM (3 << 5)
-#define DXCCR_DQSRES_500_OHM (4 << 5)
-#define DXCCR_DQSRES_458_OHM (5 << 5)
-#define DXCCR_DQSRES_393_OHM (6 << 5)
-#define DXCCR_DQSRES_344_OHM (7 << 5)
-
-#define DXCCR_DQSNRES_OPEN (0 << 9)
-#define DXCCR_DQSNRES_688_OHM (1 << 9)
-#define DXCCR_DQSNRES_611_OHM (2 << 9)
-#define DXCCR_DQSNRES_550_OHM (3 << 9)
-#define DXCCR_DQSNRES_500_OHM (4 << 9)
-#define DXCCR_DQSNRES_458_OHM (5 << 9)
-#define DXCCR_DQSNRES_393_OHM (6 << 9)
-#define DXCCR_DQSNRES_344_OHM (7 << 9)
-
-#define DTCR_DTRANK_SHIFT 4 /* Data Training Rank */
-#define DTCR_DTRANK_MASK (0x3 << (DTCR_DTRANK_SHIFT))
-#define DTCR_DTMPR BIT(6) /* Data Training using MPR */
-#define DTCR_RANKEN_SHIFT 24 /* Rank Enable */
-#define DTCR_RANKEN_MASK (0xf << (DTCR_RANKEN_SHIFT))
-
-#define DXGCR_WLRKEN_SHIFT 26 /* Write Level Rank Enable */
-#define DXGCR_WLRKEN_MASK (0xf << (DXGCR_WLRKEN_SHIFT))
-
-/* SoC-specific parameters */
-#define NR_DATX8_PER_DDRPHY 2
-
-#ifndef __ASSEMBLY__
-int uniphier_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq,
- bool ddr3plus);
-void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank);
-int ddrphy_training(struct ddrphy __iomem *phy);
-#endif
+#define PHY_RIDR (0x000 << PHY_REG_SHIFT)
+#define PHY_PIR (0x001 << PHY_REG_SHIFT)
+#define PHY_PIR_INIT BIT(0) /* Initialization Trigger */
+#define PHY_PIR_ZCAL BIT(1) /* Impedance Calibration */
+#define PHY_PIR_PLLINIT BIT(4) /* PLL Initialization */
+#define PHY_PIR_DCAL BIT(5) /* DDL Calibration */
+#define PHY_PIR_PHYRST BIT(6) /* PHY Reset */
+#define PHY_PIR_DRAMRST BIT(7) /* DRAM Reset */
+#define PHY_PIR_DRAMINIT BIT(8) /* DRAM Initialization */
+#define PHY_PIR_WL BIT(9) /* Write Leveling */
+#define PHY_PIR_QSGATE BIT(10) /* Read DQS Gate Training */
+#define PHY_PIR_WLADJ BIT(11) /* Write Leveling Adjust */
+#define PHY_PIR_RDDSKW BIT(12) /* Read Data Bit Deskew */
+#define PHY_PIR_WRDSKW BIT(13) /* Write Data Bit Deskew */
+#define PHY_PIR_RDEYE BIT(14) /* Read Data Eye Training */
+#define PHY_PIR_WREYE BIT(15) /* Write Data Eye Training */
+#define PHY_PIR_LOCKBYP BIT(28) /* PLL Lock Bypass */
+#define PHY_PIR_DCALBYP BIT(29) /* DDL Calibration Bypass */
+#define PHY_PIR_ZCALBYP BIT(30) /* Impedance Calib Bypass */
+#define PHY_PIR_INITBYP BIT(31) /* Initialization Bypass */
+#define PHY_PGCR0 (0x002 << PHY_REG_SHIFT)
+#define PHY_PGCR1 (0x003 << PHY_REG_SHIFT)
+#define PHY_PGCR1_INHVT BIT(26) /* VT Calculation Inhibit */
+#define PHY_PGSR0 (0x004 << PHY_REG_SHIFT)
+#define PHY_PGSR0_IDONE BIT(0) /* Initialization Done */
+#define PHY_PGSR0_PLDONE BIT(1) /* PLL Lock Done */
+#define PHY_PGSR0_DCDONE BIT(2) /* DDL Calibration Done */
+#define PHY_PGSR0_ZCDONE BIT(3) /* Impedance Calibration Done */
+#define PHY_PGSR0_DIDONE BIT(4) /* DRAM Initialization Done */
+#define PHY_PGSR0_WLDONE BIT(5) /* Write Leveling Done */
+#define PHY_PGSR0_QSGDONE BIT(6) /* DQS Gate Training Done */
+#define PHY_PGSR0_WLADONE BIT(7) /* Write Leveling Adjust Done */
+#define PHY_PGSR0_RDDONE BIT(8) /* Read Bit Deskew Done */
+#define PHY_PGSR0_WDDONE BIT(9) /* Write Bit Deskew Done */
+#define PHY_PGSR0_REDONE BIT(10) /* Read Eye Training Done */
+#define PHY_PGSR0_WEDONE BIT(11) /* Write Eye Training Done */
+#define PHY_PGSR0_DIERR BIT(20) /* DRAM Initialization Error */
+#define PHY_PGSR0_WLERR BIT(21) /* Write Leveling Error */
+#define PHY_PGSR0_QSGERR BIT(22) /* DQS Gate Training Error */
+#define PHY_PGSR0_WLAERR BIT(23) /* Write Leveling Adj Error */
+#define PHY_PGSR0_RDERR BIT(24) /* Read Bit Deskew Error */
+#define PHY_PGSR0_WDERR BIT(25) /* Write Bit Deskew Error */
+#define PHY_PGSR0_REERR BIT(26) /* Read Eye Training Error */
+#define PHY_PGSR0_WEERR BIT(27) /* Write Eye Training Error */
+#define PHY_PGSR0_DTERR_SHIFT 28 /* Data Training Error Status*/
+#define PHY_PGSR0_DTERR (7 << (PHY_PGSR0_DTERR_SHIFT))
+#define PHY_PGSR1 (0x005 << PHY_REG_SHIFT)
+#define PHY_PGSR1_VTSTOP BIT(30) /* VT Stop (v3-) */
+#define PHY_PLLCR (0x006 << PHY_REG_SHIFT)
+#define PHY_PTR0 (0x007 << PHY_REG_SHIFT)
+#define PHY_PTR1 (0x008 << PHY_REG_SHIFT)
+#define PHY_PTR2 (0x009 << PHY_REG_SHIFT)
+#define PHY_PTR3 (0x00A << PHY_REG_SHIFT)
+#define PHY_PTR4 (0x00B << PHY_REG_SHIFT)
+#define PHY_ACMDLR (0x00C << PHY_REG_SHIFT)
+#define PHY_ACBDLR (0x00D << PHY_REG_SHIFT)
+#define PHY_ACIOCR (0x00E << PHY_REG_SHIFT)
+#define PHY_DXCCR (0x00F << PHY_REG_SHIFT)
+#define PHY_DXCCR_DQSRES_OPEN (0 << 5)
+#define PHY_DXCCR_DQSRES_688_OHM (1 << 5)
+#define PHY_DXCCR_DQSRES_611_OHM (2 << 5)
+#define PHY_DXCCR_DQSRES_550_OHM (3 << 5)
+#define PHY_DXCCR_DQSRES_500_OHM (4 << 5)
+#define PHY_DXCCR_DQSRES_458_OHM (5 << 5)
+#define PHY_DXCCR_DQSRES_393_OHM (6 << 5)
+#define PHY_DXCCR_DQSRES_344_OHM (7 << 5)
+#define PHY_DXCCR_DQSNRES_OPEN (0 << 9)
+#define PHY_DXCCR_DQSNRES_688_OHM (1 << 9)
+#define PHY_DXCCR_DQSNRES_611_OHM (2 << 9)
+#define PHY_DXCCR_DQSNRES_550_OHM (3 << 9)
+#define PHY_DXCCR_DQSNRES_500_OHM (4 << 9)
+#define PHY_DXCCR_DQSNRES_458_OHM (5 << 9)
+#define PHY_DXCCR_DQSNRES_393_OHM (6 << 9)
+#define PHY_DXCCR_DQSNRES_344_OHM (7 << 9)
+#define PHY_DSGCR (0x010 << PHY_REG_SHIFT)
+#define PHY_DCR (0x011 << PHY_REG_SHIFT)
+#define PHY_DTPR0 (0x012 << PHY_REG_SHIFT)
+#define PHY_DTPR1 (0x013 << PHY_REG_SHIFT)
+#define PHY_DTPR2 (0x014 << PHY_REG_SHIFT)
+#define PHY_MR0 (0x015 << PHY_REG_SHIFT)
+#define PHY_MR1 (0x016 << PHY_REG_SHIFT)
+#define PHY_MR2 (0x017 << PHY_REG_SHIFT)
+#define PHY_MR3 (0x018 << PHY_REG_SHIFT)
+#define PHY_ODTCR (0x019 << PHY_REG_SHIFT)
+#define PHY_DTCR (0x01A << PHY_REG_SHIFT)
+#define PHY_DTCR_DTRANK_SHIFT 4 /* Data Training Rank */
+#define PHY_DTCR_DTRANK_MASK (0x3 << (PHY_DTCR_DTRANK_SHIFT))
+#define PHY_DTCR_DTMPR BIT(6) /* Data Training using MPR */
+#define PHY_DTCR_RANKEN_SHIFT 24 /* Rank Enable */
+#define PHY_DTCR_RANKEN_MASK (0xf << (PHY_DTCR_RANKEN_SHIFT))
+#define PHY_DTAR0 (0x01B << PHY_REG_SHIFT)
+#define PHY_DTAR1 (0x01C << PHY_REG_SHIFT)
+#define PHY_DTAR2 (0x01D << PHY_REG_SHIFT)
+#define PHY_DTAR3 (0x01E << PHY_REG_SHIFT)
+#define PHY_DTDR0 (0x01F << PHY_REG_SHIFT)
+#define PHY_DTDR1 (0x020 << PHY_REG_SHIFT)
+#define PHY_DTEDR0 (0x021 << PHY_REG_SHIFT)
+#define PHY_DTEDR1 (0x022 << PHY_REG_SHIFT)
+#define PHY_PGCR2 (0x023 << PHY_REG_SHIFT)
+#define PHY_GPR0 (0x05E << PHY_REG_SHIFT)
+#define PHY_GPR1 (0x05F << PHY_REG_SHIFT)
+/* ZQ */
+#define PHY_ZQ_BASE (0x060 << PHY_REG_SHIFT)
+#define PHY_ZQ_STRIDE (0x004 << PHY_REG_SHIFT)
+#define PHY_ZQ_CR0 (0x000 << PHY_REG_SHIFT)
+#define PHY_ZQ_CR1 (0x001 << PHY_REG_SHIFT)
+#define PHY_ZQ_SR0 (0x002 << PHY_REG_SHIFT)
+#define PHY_ZQ_SR1 (0x003 << PHY_REG_SHIFT)
+/* DATX8 */
+#define PHY_DX_BASE (0x070 << PHY_REG_SHIFT)
+#define PHY_DX_STRIDE (0x010 << PHY_REG_SHIFT)
+#define PHY_DX_GCR (0x000 << PHY_REG_SHIFT)
+#define PHY_DX_GCR_WLRKEN_SHIFT 26 /* Write Level Rank Enable */
+#define PHY_DX_GCR_WLRKEN_MASK (0xf << (PHY_DX_GCR_WLRKEN_SHIFT))
+#define PHY_DX_GSR0 (0x001 << PHY_REG_SHIFT)
+#define PHY_DX_GSR1 (0x002 << PHY_REG_SHIFT)
+#define PHY_DX_BDLR0 (0x003 << PHY_REG_SHIFT)
+#define PHY_DX_BDLR1 (0x004 << PHY_REG_SHIFT)
+#define PHY_DX_BDLR2 (0x005 << PHY_REG_SHIFT)
+#define PHY_DX_BDLR3 (0x006 << PHY_REG_SHIFT)
+#define PHY_DX_BDLR4 (0x007 << PHY_REG_SHIFT)
+#define PHY_DX_LCDLR0 (0x008 << PHY_REG_SHIFT)
+#define PHY_DX_LCDLR1 (0x009 << PHY_REG_SHIFT)
+#define PHY_DX_LCDLR2 (0x00A << PHY_REG_SHIFT)
+#define PHY_DX_MDLR (0x00B << PHY_REG_SHIFT)
+#define PHY_DX_GTR (0x00C << PHY_REG_SHIFT)
+#define PHY_DX_GSR2 (0x00D << PHY_REG_SHIFT)
#endif /* ARCH_DDRPHY_REGS_H */
/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2011-2014 Panasonic Corporation
+ * Copyright (C) 2015-2016 Socionext Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <linux/err.h>
#include <linux/io.h>
+#include "ddrphy-init.h"
#include "ddrphy-regs.h"
-void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank)
+/* for LD4, Pro4, sLD8 */
+#define NR_DATX8_PER_DDRPHY 2
+
+void ddrphy_prepare_training(void __iomem *phy_base, int rank)
{
+ void __iomem *dx_base = phy_base + PHY_DX_BASE;
int dx;
- u32 __iomem tmp, *p;
+ u32 tmp;
for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) {
- p = &phy->dx[dx].gcr;
-
- tmp = readl(p);
+ tmp = readl(dx_base + PHY_DX_GCR);
/* Specify the rank that should be write leveled */
- tmp &= ~DXGCR_WLRKEN_MASK;
- tmp |= (1 << (DXGCR_WLRKEN_SHIFT + rank)) & DXGCR_WLRKEN_MASK;
- writel(tmp, p);
+ tmp &= ~PHY_DX_GCR_WLRKEN_MASK;
+ tmp |= (1 << (PHY_DX_GCR_WLRKEN_SHIFT + rank)) &
+ PHY_DX_GCR_WLRKEN_MASK;
+ writel(tmp, dx_base + PHY_DX_GCR);
+ dx_base += PHY_DX_STRIDE;
}
- p = &phy->dtcr;
-
- tmp = readl(p);
+ tmp = readl(phy_base + PHY_DTCR);
/* Specify the rank used during data bit deskew and eye centering */
- tmp &= ~DTCR_DTRANK_MASK;
- tmp |= (rank << DTCR_DTRANK_SHIFT) & DTCR_DTRANK_MASK;
+ tmp &= ~PHY_DTCR_DTRANK_MASK;
+ tmp |= (rank << PHY_DTCR_DTRANK_SHIFT) & PHY_DTCR_DTRANK_MASK;
/* Use Multi-Purpose Register for DQS gate training */
- tmp |= DTCR_DTMPR;
+ tmp |= PHY_DTCR_DTMPR;
/* Specify the rank enabled for data-training */
- tmp &= ~DTCR_RANKEN_MASK;
- tmp |= (1 << (DTCR_RANKEN_SHIFT + rank)) & DTCR_RANKEN_MASK;
- writel(tmp, p);
+ tmp &= ~PHY_DTCR_RANKEN_MASK;
+ tmp |= (1 << (PHY_DTCR_RANKEN_SHIFT + rank)) & PHY_DTCR_RANKEN_MASK;
+ writel(tmp, phy_base + PHY_DTCR);
}
struct ddrphy_init_sequence {
static const struct ddrphy_init_sequence init_sequence[] = {
{
"DRAM Initialization",
- PIR_DRAMRST | PIR_DRAMINIT,
- PGSR0_DIDONE,
- PGSR0_DIERR
+ PHY_PIR_DRAMRST | PHY_PIR_DRAMINIT,
+ PHY_PGSR0_DIDONE,
+ PHY_PGSR0_DIERR
},
{
"Write Leveling",
- PIR_WL,
- PGSR0_WLDONE,
- PGSR0_WLERR
+ PHY_PIR_WL,
+ PHY_PGSR0_WLDONE,
+ PHY_PGSR0_WLERR
},
{
"Read DQS Gate Training",
- PIR_QSGATE,
- PGSR0_QSGDONE,
- PGSR0_QSGERR
+ PHY_PIR_QSGATE,
+ PHY_PGSR0_QSGDONE,
+ PHY_PGSR0_QSGERR
},
{
"Write Leveling Adjustment",
- PIR_WLADJ,
- PGSR0_WLADONE,
- PGSR0_WLAERR
+ PHY_PIR_WLADJ,
+ PHY_PGSR0_WLADONE,
+ PHY_PGSR0_WLAERR
},
{
"Read Bit Deskew",
- PIR_RDDSKW,
- PGSR0_RDDONE,
- PGSR0_RDERR
+ PHY_PIR_RDDSKW,
+ PHY_PGSR0_RDDONE,
+ PHY_PGSR0_RDERR
},
{
"Write Bit Deskew",
- PIR_WRDSKW,
- PGSR0_WDDONE,
- PGSR0_WDERR
+ PHY_PIR_WRDSKW,
+ PHY_PGSR0_WDDONE,
+ PHY_PGSR0_WDERR
},
{
"Read Eye Training",
- PIR_RDEYE,
- PGSR0_REDONE,
- PGSR0_REERR
+ PHY_PIR_RDEYE,
+ PHY_PGSR0_REDONE,
+ PHY_PGSR0_REERR
},
{
"Write Eye Training",
- PIR_WREYE,
- PGSR0_WEDONE,
- PGSR0_WEERR
+ PHY_PIR_WREYE,
+ PHY_PGSR0_WEDONE,
+ PHY_PGSR0_WEERR
}
};
-int ddrphy_training(struct ddrphy __iomem *phy)
+int ddrphy_training(void __iomem *phy_base)
{
int i;
u32 pgsr0;
- u32 init_flag = PIR_INIT;
- u32 done_flag = PGSR0_IDONE;
+ u32 init_flag = PHY_PIR_INIT;
+ u32 done_flag = PHY_PGSR0_IDONE;
int timeout = 50000; /* 50 msec is long enough */
#ifdef DISPLAY_ELAPSED_TIME
ulong start = get_timer(0);
done_flag |= init_sequence[i].done_flag;
}
- writel(init_flag, &phy->pir);
+ writel(init_flag, phy_base + PHY_PIR);
do {
if (--timeout < 0) {
return -ETIMEDOUT;
}
udelay(1);
- pgsr0 = readl(&phy->pgsr[0]);
+ pgsr0 = readl(phy_base + PHY_PGSR0);
} while ((pgsr0 & done_flag) != done_flag);
for (i = 0; i < ARRAY_SIZE(init_sequence); i++) {
--- /dev/null
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _DDRUQPHY_REGS_H
+#define _DDRUQPHY_REGS_H
+
+#include <linux/bitops.h>
+
+#define PHY_REG_SHIFT 2
+#define PHY_SLV_DLY_WIDTH 6
+#define PHY_BITLVL_DLY_WIDTH 6
+#define PHY_MAS_DLY_WIDTH 8
+
+#define PHY_SCL_START (0x40 << (PHY_REG_SHIFT))
+#define PHY_SCL_START_GO_DONE BIT(28)
+#define PHY_SCL_DATA_0 (0x41 << (PHY_REG_SHIFT))
+#define PHY_SCL_DATA_1 (0x42 << (PHY_REG_SHIFT))
+#define PHY_SCL_LATENCY (0x43 << (PHY_REG_SHIFT))
+#define PHY_SCL_CONFIG_1 (0x46 << (PHY_REG_SHIFT))
+#define PHY_SCL_CONFIG_2 (0x47 << (PHY_REG_SHIFT))
+#define PHY_PAD_CTRL (0x48 << (PHY_REG_SHIFT))
+#define PHY_DLL_RECALIB (0x49 << (PHY_REG_SHIFT))
+#define PHY_DLL_RECALIB_TRIM_MASK GENMASK(PHY_SLV_DLY_WIDTH - 1, 0)
+#define PHY_DLL_RECALIB_INCR BIT(27)
+#define PHY_DLL_ADRCTRL (0x4A << (PHY_REG_SHIFT))
+#define PHY_DLL_ADRCTRL_TRIM_MASK GENMASK(PHY_SLV_DLY_WIDTH - 1, 0)
+#define PHY_DLL_ADRCTRL_INCR BIT(9)
+#define PHY_DLL_ADRCTRL_MDL_SHIFT 24
+#define PHY_DLL_ADRCTRL_MDL_MASK (GENMASK(PHY_MAS_DLY_WIDTH - 1, 0) << \
+ PHY_DLL_ADRCTRL_MDL_SHIFT)
+#define PHY_LANE_SEL (0x4B << (PHY_REG_SHIFT))
+#define PHY_LANE_SEL_LANE_SHIFT 0
+#define PHY_LANE_SEL_LANE_WIDTH 8
+#define PHY_LANE_SEL_BIT_SHIFT 8
+#define PHY_LANE_SEL_BIT_WIDTH 4
+#define PHY_DLL_TRIM_1 (0x4C << (PHY_REG_SHIFT))
+#define PHY_DLL_TRIM_2 (0x4D << (PHY_REG_SHIFT))
+#define PHY_DLL_TRIM_3 (0x4E << (PHY_REG_SHIFT))
+#define PHY_SCL_MAIN_CLK_DELTA (0x50 << (PHY_REG_SHIFT))
+#define PHY_WRLVL_AUTOINC_TRIM (0x53 << (PHY_REG_SHIFT))
+#define PHY_WRLVL_DYN_ODT (0x54 << (PHY_REG_SHIFT))
+#define PHY_WRLVL_ON_OFF (0x55 << (PHY_REG_SHIFT))
+#define PHY_UNQ_ANALOG_DLL_1 (0x57 << (PHY_REG_SHIFT))
+#define PHY_UNQ_ANALOG_DLL_2 (0x58 << (PHY_REG_SHIFT))
+#define PHY_DLL_INCR_TRIM_1 (0x59 << (PHY_REG_SHIFT))
+#define PHY_DLL_INCR_TRIM_3 (0x5A << (PHY_REG_SHIFT))
+#define PHY_SCL_CONFIG_3 (0x5B << (PHY_REG_SHIFT))
+#define PHY_UNIQUIFY_TSMC_IO_1 (0x5C << (PHY_REG_SHIFT))
+#define PHY_SCL_START_ADDR (0x62 << (PHY_REG_SHIFT))
+#define PHY_IP_DQ_DQS_BITWISE_TRIM (0x65 << (PHY_REG_SHIFT))
+#define PHY_IP_DQ_DQS_BITWISE_TRIM_MASK \
+ GENMASK(PHY_BITLVL_DLY_WIDTH - 1, 0)
+#define PHY_IP_DQ_DQS_BITWISE_TRIM_INC \
+ BIT(PHY_BITLVL_DLY_WIDTH)
+#define PHY_IP_DQ_DQS_BITWISE_TRIM_OVERRIDE \
+ BIT(PHY_BITLVL_DLY_WIDTH + 1)
+#define PHY_DSCL_CNT (0x67 << (PHY_REG_SHIFT))
+#define PHY_OP_DQ_DM_DQS_BITWISE_TRIM (0x68 << (PHY_REG_SHIFT))
+#define PHY_OP_DQ_DM_DQS_BITWISE_TRIM_MASK \
+ GENMASK(PHY_BITLVL_DLY_WIDTH - 1, 0)
+#define PHY_OP_DQ_DM_DQS_BITWISE_TRIM_INC \
+ BIT(PHY_BITLVL_DLY_WIDTH)
+#define PHY_OP_DQ_DM_DQS_BITWISE_TRIM_OVERRIDE \
+ BIT(PHY_BITLVL_DLY_WIDTH + 1)
+#define PHY_DLL_TRIM_CLK (0x69 << (PHY_REG_SHIFT))
+#define PHY_DLL_TRIM_CLK_MASK GENMASK(PHY_SLV_DLY_WIDTH, 0)
+#define PHY_DLL_TRIM_CLK_INCR BIT(PHY_SLV_DLY_WIDTH + 1)
+#define PHY_DYNAMIC_BIT_LVL (0x6B << (PHY_REG_SHIFT))
+#define PHY_SCL_WINDOW_TRIM (0x6D << (PHY_REG_SHIFT))
+#define PHY_DISABLE_GATING_FOR_SCL (0x6E << (PHY_REG_SHIFT))
+#define PHY_SCL_CONFIG_4 (0x6F << (PHY_REG_SHIFT))
+#define PHY_DYNAMIC_WRITE_BIT_LVL (0x70 << (PHY_REG_SHIFT))
+#define PHY_VREF_TRAINING (0x72 << (PHY_REG_SHIFT))
+#define PHY_SCL_GATE_TIMING (0x78 << (PHY_REG_SHIFT))
+
+#endif /* _DDRUQPHY_REGS_H */
#include <asm/processor.h>
#include "../init.h"
+#include "ddrphy-regs.h"
#include "umc64-regs.h"
-#define CONFIG_DDR_FREQ 1866
+#define DDR_FREQ 1600
#define DRAM_CH_NR 2
+#define RANK_BLOCKS_TR 2
enum dram_freq {
DRAM_FREQ_1600M,
DRAM_SZ_NR,
};
-/* umc */
-static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x060D0D20};
-static u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x2D211C08};
-static u32 umc_cmdctlc[DRAM_FREQ_NR] = {0x00150C04};
-static u32 umc_cmdctle[DRAM_FREQ_NR] = {0x0078071D};
-static u32 umc_cmdctlf[DRAM_FREQ_NR] = {0x02000200};
-static u32 umc_cmdctlg[DRAM_FREQ_NR] = {0x08080808};
-
-static u32 umc_rdatactl_d0[DRAM_FREQ_NR] = {0x00000810};
-static u32 umc_rdatactl_d1[DRAM_FREQ_NR] = {0x00000810};
-static u32 umc_wdatactl_d0[DRAM_FREQ_NR] = {0x00000004};
-static u32 umc_wdatactl_d1[DRAM_FREQ_NR] = {0x00000004};
-static u32 umc_odtctl_d0[DRAM_FREQ_NR] = {0x02000002};
-static u32 umc_odtctl_d1[DRAM_FREQ_NR] = {0x02000002};
-static u32 umc_acssetb[DRAM_CH_NR] = {0x00000200, 0x00000203};
-static u32 umc_memconfch[DRAM_FREQ_NR] = {0x00023605};
+/* PHY */
+const int rof_pos_shift_pre[RANK_BLOCKS_TR][2] = { {0, 0}, {0, 0} };
+const int rof_neg_shift_pre[RANK_BLOCKS_TR][2] = { {0, 0}, {0, 0} };
+const int rof_pos_shift[RANK_BLOCKS_TR][2] = { {-35, -35}, {-35, -35} };
+const int rof_neg_shift[RANK_BLOCKS_TR][2] = { {-17, -17}, {-17, -17} };
+const int tof_shift[RANK_BLOCKS_TR][2] = { {-50, -50}, {-50, -50} };
+
+/* Register address */
+#define PHY_ZQ0CR1 0x00000184
+#define PHY_ZQ1CR1 0x00000194
+#define PHY_ZQ2CR1 0x000001A4
+#define PHY_DX0GCR 0x000001C0
+#define PHY_DX0GTR 0x000001F0
+#define PHY_DX1GCR 0x00000200
+#define PHY_DX1GTR 0x00000230
+#define PHY_DX2GCR 0x00000240
+#define PHY_DX2GTR 0x00000270
+#define PHY_DX3GCR 0x00000280
+#define PHY_DX3GTR 0x000002B0
+
+#define PHY_DXMDLR(dx) (0x000001EC + 0x40 * (dx))
+#define PHY_DXLCDLR0(dx) (0x000001E0 + 0x40 * (dx))
+#define PHY_DXLCDLR1(dx) (0x000001E4 + 0x40 * (dx))
+#define PHY_DXLCDLR2(dx) (0x000001E8 + 0x40 * (dx))
+#define PHY_DXBDLR1(dx) (0x000001D0 + 0x40 * (dx))
+#define PHY_DXBDLR2(dx) (0x000001D4 + 0x40 * (dx))
+
+/* MASK */
+#define PHY_ACBD_MASK 0x00FC0000
+#define PHY_CK0BD_MASK 0x0000003F
+#define PHY_CK1BD_MASK 0x00000FC0
+#define PHY_IPRD_MASK 0x000000FF
+#define PHY_WLD_MASK(rank) (0xFF << (8 * (rank)))
+#define PHY_DQSGD_MASK(rank) (0xFF << (8 * (rank)))
+#define PHY_DQSGX_MASK BIT(6)
+#define PHY_DSWBD_MASK 0x3F000000 /* bit[29:24] */
+#define PHY_DSDQOE_MASK 0x00000FFF
+
+static void ddrphy_maskwritel(u32 data, u32 mask, void *addr)
+{
+ u32 value;
+
+ value = (readl(addr) & ~(mask)) | (data & mask);
+ writel(value, addr);
+}
+
+static u32 ddrphy_maskreadl(u32 mask, void *addr)
+{
+ return readl(addr) & mask;
+}
+
+/* step of 0.5T for PUB-byte */
+static u8 ddrphy_get_mdl(int dx, void __iomem *phy_base)
+{
+ return ddrphy_maskreadl(PHY_IPRD_MASK, phy_base + PHY_DXMDLR(dx));
+}
+
+/* Calculating step for PUB-byte */
+static int ddrphy_hpstep(int delay, int dx, void __iomem *phy_base)
+{
+ return delay * ddrphy_get_mdl(dx, phy_base) * DDR_FREQ / 1000000;
+}
+
+static void ddrphy_vt_ctrl(void __iomem *phy_base, int enable)
+{
+ u32 tmp;
+
+ tmp = readl(phy_base + PHY_PGCR1);
+
+ if (enable)
+ tmp &= ~PHY_PGCR1_INHVT;
+ else
+ tmp |= PHY_PGCR1_INHVT;
+
+ writel(tmp, phy_base + PHY_PGCR1);
+
+ if (!enable) {
+ while (!(readl(phy_base + PHY_PGSR1) & PHY_PGSR1_VTSTOP))
+ cpu_relax();
+ }
+}
+
+static void ddrphy_set_ckoffset_qoffset(int delay_ckoffset0, int delay_ckoffset1,
+ int delay_qoffset, int enable,
+ void __iomem *phy_base)
+{
+ u8 ck_step0, ck_step1; /* ckoffset_step for clock */
+ u8 q_step; /* qoffset_step for clock */
+ int dx;
+
+ dx = 2; /* use dx2 in sLD11 */
+
+ ck_step0 = ddrphy_hpstep(delay_ckoffset0, dx, phy_base); /* CK-Offset */
+ ck_step1 = ddrphy_hpstep(delay_ckoffset1, dx, phy_base); /* CK-Offset */
+ q_step = ddrphy_hpstep(delay_qoffset, dx, phy_base); /* Q-Offset */
+
+ ddrphy_vt_ctrl(phy_base, 0);
+
+ /* Q->[23:18], CK1->[11:6], CK0->bit[5:0] */
+ if (enable == 1)
+ ddrphy_maskwritel((q_step << 18) + (ck_step1 << 6) + ck_step0,
+ PHY_ACBD_MASK | PHY_CK1BD_MASK | PHY_CK0BD_MASK,
+ phy_base + PHY_ACBDLR);
+
+ ddrphy_vt_ctrl(phy_base, 1);
+}
+
+static void ddrphy_set_wl_delay_dx(int dx, int r0_delay, int r1_delay,
+ int enable, void __iomem *phy_base)
+{
+ int rank;
+ int delay_wl[4];
+ u32 wl_mask = 0; /* WriteLeveling's Mask */
+ u32 wl_value = 0; /* WriteLeveling's Value */
+
+ delay_wl[0] = r0_delay & 0xfff;
+ delay_wl[1] = r1_delay & 0xfff;
+ delay_wl[2] = 0;
+ delay_wl[3] = 0;
+
+ ddrphy_vt_ctrl(phy_base, 0);
+
+ for (rank = 0; rank < 4; rank++) {
+ wl_mask |= PHY_WLD_MASK(rank);
+ /* WriteLeveling's delay */
+ wl_value |= ddrphy_hpstep(delay_wl[rank], dx, phy_base) << (8 * rank);
+ }
+
+ if (enable == 1)
+ ddrphy_maskwritel(wl_value, wl_mask, phy_base + PHY_DXLCDLR0(dx));
+
+ ddrphy_vt_ctrl(phy_base, 1);
+}
+
+static void ddrphy_set_dqsg_delay_dx(int dx, int r0_delay, int r1_delay,
+ int enable, void __iomem *phy_base)
+{
+ int rank;
+ int delay_dqsg[4];
+ u32 dqsg_mask = 0; /* DQSGating_LCDL_delay's Mask */
+ u32 dqsg_value = 0; /* DQSGating_LCDL_delay's Value */
+
+ delay_dqsg[0] = r0_delay;
+ delay_dqsg[1] = r1_delay;
+ delay_dqsg[2] = 0;
+ delay_dqsg[3] = 0;
+
+ ddrphy_vt_ctrl(phy_base, 0);
+
+ for (rank = 0; rank < 4; rank++) {
+ dqsg_mask |= PHY_DQSGD_MASK(rank);
+ /* DQSGating's delay */
+ dqsg_value |= ddrphy_hpstep(delay_dqsg[rank], dx, phy_base) << (8 * rank);
+ }
+
+ if (enable == 1)
+ ddrphy_maskwritel(dqsg_value, dqsg_mask, phy_base + PHY_DXLCDLR2(dx));
+
+ ddrphy_vt_ctrl(phy_base, 1);
+}
+
+static void ddrphy_set_dswb_delay_dx(int dx, int delay, int enable, void __iomem *phy_base)
+{
+ u8 dswb_step;
+
+ ddrphy_vt_ctrl(phy_base, 0);
+
+ dswb_step = ddrphy_hpstep(delay, dx, phy_base); /* DQS-BDL's delay */
+
+ if (enable == 1)
+ ddrphy_maskwritel(dswb_step << 24, PHY_DSWBD_MASK, phy_base + PHY_DXBDLR1(dx));
+
+ ddrphy_vt_ctrl(phy_base, 1);
+}
+
+static void ddrphy_set_oe_delay_dx(int dx, int dqs_delay, int dq_delay,
+ int enable, void __iomem *phy_base)
+{
+ u8 dqs_oe_step, dq_oe_step;
+ u32 wdata;
+
+ ddrphy_vt_ctrl(phy_base, 0);
+
+ /* OE(DQS,DQ) */
+ dqs_oe_step = ddrphy_hpstep(dqs_delay, dx, phy_base); /* DQS-oe's delay */
+ dq_oe_step = ddrphy_hpstep(dq_delay, dx, phy_base); /* DQ-oe's delay */
+ wdata = ((dq_oe_step<<6) + dqs_oe_step) & 0xFFF;
+
+ if (enable == 1)
+ ddrphy_maskwritel(wdata, PHY_DSDQOE_MASK, phy_base + PHY_DXBDLR2(dx));
+
+ ddrphy_vt_ctrl(phy_base, 1);
+}
+
+static void ddrphy_ext_dqsgt(void __iomem *phy_base)
+{
+ /* Extend DQSGating_window min:+1T max:+1T */
+ ddrphy_maskwritel(PHY_DQSGX_MASK, PHY_DQSGX_MASK, phy_base + PHY_DSGCR);
+}
+
+static void ddrphy_shift_tof_hws(void __iomem *phy_base, const int shift[][2])
+{
+ int dx, block, byte;
+ u32 lcdlr1, wdqd;
+
+ ddrphy_vt_ctrl(phy_base, 0);
+
+ for (block = 0; block < RANK_BLOCKS_TR; block++) {
+ for (byte = 0; byte < 2; byte++) {
+ dx = block * 2 + byte;
+ lcdlr1 = readl(phy_base + PHY_DXLCDLR1(dx));
+ wdqd = lcdlr1 & 0xff;
+ wdqd = clamp(wdqd + ddrphy_hpstep(shift[block][byte], dx, phy_base),
+ 0U, 0xffU);
+ lcdlr1 = (lcdlr1 & ~0xff) | wdqd;
+ writel(lcdlr1, phy_base + PHY_DXLCDLR1(dx));
+ readl(phy_base + PHY_DXLCDLR1(dx)); /* relax */
+ }
+ }
+
+ ddrphy_vt_ctrl(phy_base, 1);
+}
+
+static void ddrphy_shift_rof_hws(void __iomem *phy_base, const int pos_shift[][2],
+ const int neg_shift[][2])
+{
+ int dx, block, byte;
+ u32 lcdlr1, rdqsd, rdqnsd;
+
+ ddrphy_vt_ctrl(phy_base, 0);
+
+ for (block = 0; block < RANK_BLOCKS_TR; block++) {
+ for (byte = 0; byte < 2; byte++) {
+ dx = block * 2 + byte;
+ lcdlr1 = readl(phy_base + PHY_DXLCDLR1(dx));
+
+ /* DQS LCDL RDQNSD->[23:16] RDQSD->[15:8] */
+ rdqsd = (lcdlr1 >> 8) & 0xff;
+ rdqnsd = (lcdlr1 >> 16) & 0xff;
+ rdqsd = clamp(rdqsd + ddrphy_hpstep(pos_shift[block][byte], dx, phy_base),
+ 0U, 0xffU);
+ rdqnsd = clamp(rdqnsd + ddrphy_hpstep(neg_shift[block][byte], dx, phy_base),
+ 0U, 0xffU);
+ lcdlr1 = (lcdlr1 & ~(0xffff << 8)) | (rdqsd << 8) | (rdqnsd << 16);
+ readl(phy_base + PHY_DXLCDLR1(dx)); /* relax */
+ }
+ }
+
+ ddrphy_vt_ctrl(phy_base, 1);
+}
+
+static void ddrphy_boot_run_hws(void __iomem *phy_base)
+{
+ /* Hard Training for DIO */
+ writel(0x0000f401, phy_base + PHY_PIR);
+ while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE))
+ cpu_relax();
+}
+
+static void ddrphy_training(void __iomem *phy_base)
+{
+ /* DIO roffset shift before hard training */
+ ddrphy_shift_rof_hws(phy_base, rof_pos_shift_pre, rof_neg_shift_pre);
+
+ /* Hard Training for each CH */
+ ddrphy_boot_run_hws(phy_base);
+
+ /* DIO toffset shift after training */
+ ddrphy_shift_tof_hws(phy_base, tof_shift);
+
+ /* DIO roffset shift after training */
+ ddrphy_shift_rof_hws(phy_base, rof_pos_shift, rof_neg_shift);
+
+ /* Extend DQSGating window min:+1T max:+1T */
+ ddrphy_ext_dqsgt(phy_base);
+}
+
+static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq)
+{
+ writel(0x40000000, phy_base + PHY_PIR);
+ writel(0x0300C4F1, phy_base + PHY_PGCR1);
+ writel(0x0C807D04, phy_base + PHY_PTR0);
+ writel(0x27100578, phy_base + PHY_PTR1);
+ writel(0x00083DEF, phy_base + PHY_PTR2);
+ writel(0x12061A80, phy_base + PHY_PTR3);
+ writel(0x08027100, phy_base + PHY_PTR4);
+ writel(0x9D9CBB66, phy_base + PHY_DTPR0);
+ writel(0x1a878400, phy_base + PHY_DTPR1);
+ writel(0x50025200, phy_base + PHY_DTPR2);
+ writel(0xF004641A, phy_base + PHY_DSGCR);
+ writel(0x0000040B, phy_base + PHY_DCR);
+ writel(0x00000d71, phy_base + PHY_MR0);
+ writel(0x00000006, phy_base + PHY_MR1);
+ writel(0x00000098, phy_base + PHY_MR2);
+ writel(0x00000000, phy_base + PHY_MR3);
+
+ while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE))
+ cpu_relax();
+
+ writel(0x00000059, phy_base + PHY_ZQ0CR1);
+ writel(0x00000019, phy_base + PHY_ZQ1CR1);
+ writel(0x00000019, phy_base + PHY_ZQ2CR1);
+ writel(0x30FC6C20, phy_base + PHY_PGCR2);
+
+ ddrphy_set_ckoffset_qoffset(119, 0, 0, 1, phy_base);
+ ddrphy_set_wl_delay_dx(0, 220, 220, 1, phy_base);
+ ddrphy_set_wl_delay_dx(1, 160, 160, 1, phy_base);
+ ddrphy_set_wl_delay_dx(2, 190, 190, 1, phy_base);
+ ddrphy_set_wl_delay_dx(3, 150, 150, 1, phy_base);
+ ddrphy_set_dqsg_delay_dx(0, 750, 750, 1, phy_base);
+ ddrphy_set_dqsg_delay_dx(1, 750, 750, 1, phy_base);
+ ddrphy_set_dqsg_delay_dx(2, 750, 750, 1, phy_base);
+ ddrphy_set_dqsg_delay_dx(3, 750, 750, 1, phy_base);
+ ddrphy_set_dswb_delay_dx(0, 0, 1, phy_base);
+ ddrphy_set_dswb_delay_dx(1, 0, 1, phy_base);
+ ddrphy_set_dswb_delay_dx(2, 0, 1, phy_base);
+ ddrphy_set_dswb_delay_dx(3, 0, 1, phy_base);
+ ddrphy_set_oe_delay_dx(0, 0, 0, 1, phy_base);
+ ddrphy_set_oe_delay_dx(1, 0, 0, 1, phy_base);
+ ddrphy_set_oe_delay_dx(2, 0, 0, 1, phy_base);
+ ddrphy_set_oe_delay_dx(3, 0, 0, 1, phy_base);
+
+ writel(0x44000E81, phy_base + PHY_DX0GCR);
+ writel(0x44000E81, phy_base + PHY_DX1GCR);
+ writel(0x44000E81, phy_base + PHY_DX2GCR);
+ writel(0x44000E81, phy_base + PHY_DX3GCR);
+ writel(0x00055002, phy_base + PHY_DX0GTR);
+ writel(0x00055002, phy_base + PHY_DX1GTR);
+ writel(0x00055010, phy_base + PHY_DX2GTR);
+ writel(0x00055010, phy_base + PHY_DX3GTR);
+ writel(0x930035C7, phy_base + PHY_DTCR);
+ writel(0x00000003, phy_base + PHY_PIR);
+ readl(phy_base + PHY_PIR);
+ while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE))
+ cpu_relax();
+
+ writel(0x00000181, phy_base + PHY_PIR);
+ readl(phy_base + PHY_PIR);
+ while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE))
+ cpu_relax();
+
+ writel(0x44181884, phy_base + PHY_DXCCR);
+ writel(0x00000001, phy_base + PHY_GPR1);
+}
+
+/* UMC */
+static const u32 umc_cmdctla[DRAM_FREQ_NR] = {0x060B0B1C};
+static const u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x27201806};
+static const u32 umc_cmdctlc[DRAM_FREQ_NR] = {0x00120B04};
+static const u32 umc_cmdctle[DRAM_FREQ_NR] = {0x00680607};
+static const u32 umc_cmdctlf[DRAM_FREQ_NR] = {0x02000200};
+static const u32 umc_cmdctlg[DRAM_FREQ_NR] = {0x08080808};
+
+static const u32 umc_rdatactl[DRAM_FREQ_NR] = {0x00000810};
+static const u32 umc_wdatactl[DRAM_FREQ_NR] = {0x00000004};
+static const u32 umc_odtctl[DRAM_FREQ_NR] = {0x02000002};
+static const u32 umc_acssetb[DRAM_CH_NR] = {0x00000200, 0x00000203};
+
+static const u32 umc_memconfch[DRAM_FREQ_NR] = {0x00023605};
static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq,
unsigned long size, int ch)
{
+ /* Wait for PHY Init Complete */
writel(umc_cmdctla[freq], dc_base + UMC_CMDCTLA);
writel(umc_cmdctlb[freq], dc_base + UMC_CMDCTLB);
writel(umc_cmdctlc[freq], dc_base + UMC_CMDCTLC);
writel(umc_cmdctlf[freq], dc_base + UMC_CMDCTLF);
writel(umc_cmdctlg[freq], dc_base + UMC_CMDCTLG);
- writel(umc_rdatactl_d0[freq], dc_base + UMC_RDATACTL_D0);
- writel(umc_rdatactl_d1[freq], dc_base + UMC_RDATACTL_D1);
+ writel(umc_rdatactl[freq], dc_base + UMC_RDATACTL_D0);
+ writel(umc_rdatactl[freq], dc_base + UMC_RDATACTL_D1);
- writel(umc_wdatactl_d0[freq], dc_base + UMC_WDATACTL_D0);
- writel(umc_wdatactl_d1[freq], dc_base + UMC_WDATACTL_D1);
+ writel(umc_wdatactl[freq], dc_base + UMC_WDATACTL_D0);
+ writel(umc_wdatactl[freq], dc_base + UMC_WDATACTL_D1);
- writel(umc_odtctl_d0[freq], dc_base + UMC_ODTCTL_D0);
- writel(umc_odtctl_d1[freq], dc_base + UMC_ODTCTL_D1);
+ writel(umc_odtctl[freq], dc_base + UMC_ODTCTL_D0);
+ writel(umc_odtctl[freq], dc_base + UMC_ODTCTL_D1);
writel(0x00000003, dc_base + UMC_ACSSETA);
writel(0x00000103, dc_base + UMC_FLOWCTLG);
{
void __iomem *um_base = (void __iomem *)0x5B800000;
void __iomem *umc_ch_base = (void __iomem *)0x5BC00000;
+ void __iomem *phy_base = (void __iomem *)0x5BC01000;
enum dram_freq freq;
int ch, ret;
return -EINVAL;
}
+ writel(0x00000101, umc_ch_base + UMC_DIOCTLA);
+ while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE))
+ cpu_relax();
+
+ writel(0x00000000, umc_ch_base + UMC_DIOCTLA);
+ writel(0x00000001, umc_ch_base + UMC_DEBUGC);
+ writel(0x00000101, umc_ch_base + UMC_DIOCTLA);
+
+ writel(0x00000100, umc_ch_base + UMC_INITSET);
+ while (readl(umc_ch_base + UMC_INITSTAT) & BIT(8))
+ cpu_relax();
+
+ writel(0x00000100, umc_ch_base + 0x00200000 + UMC_INITSET);
+ while (readl(umc_ch_base + 0x00200000 + UMC_INITSTAT) & BIT(8))
+ cpu_relax();
+
+ ddrphy_init(phy_base, freq);
+
for (ch = 0; ch < bd->dram_nr_ch; ch++) {
unsigned long size = bd->dram_ch[ch].size;
unsigned int width = bd->dram_ch[ch].width;
umc_ch_base += 0x00200000;
}
+ ddrphy_training(phy_base);
um_init(um_base);
/*
* Copyright (C) 2016 Socionext Inc.
*
- * based on commit 9073035a9860f892f8d1345dfb0ea862b5021145 of Diag
+ * based on commit a7a36122aa072fe1bb06e02b73b3634b7a6c555a of Diag
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/processor.h>
#include "../init.h"
-#include "ddrphy-ld20-regs.h"
+#include "ddruqphy-regs.h"
#include "umc64-regs.h"
#define DRAM_CH_NR 3
enum dram_board { /* board type */
DRAM_BOARD_LD20_REF, /* LD20 reference */
DRAM_BOARD_LD20_GLOBAL, /* LD20 TV */
+ DRAM_BOARD_LD20_C1, /* LD20 TV C1 */
DRAM_BOARD_LD21_REF, /* LD21 reference */
DRAM_BOARD_LD21_GLOBAL, /* LD21 TV */
DRAM_BOARD_NR,
static const int ddrphy_adrctrl[DRAM_BOARD_NR][DRAM_CH_NR] = {
{268 - 262, 268 - 263, 268 - 378}, /* LD20 reference */
{268 - 262, 268 - 263, 268 - 378}, /* LD20 TV */
+ {268 - 262, 268 - 263, 268 - 378}, /* LD20 TV C1 */
{268 - 212, 268 - 268, /* No CH2 */}, /* LD21 reference */
{268 - 212, 268 - 268, /* No CH2 */}, /* LD21 TV */
};
static const int ddrphy_dlltrimclk[DRAM_BOARD_NR][DRAM_CH_NR] = {
{268, 268, 268}, /* LD20 reference */
{268, 268, 268}, /* LD20 TV */
+ {189, 189, 189}, /* LD20 TV C1 */
{268, 268 + 252, /* No CH2 */}, /* LD21 reference */
{268, 268 + 202, /* No CH2 */}, /* LD21 TV */
};
static const int ddrphy_dllrecalib[DRAM_BOARD_NR][DRAM_CH_NR] = {
{268 - 378, 268 - 263, 268 - 378}, /* LD20 reference */
{268 - 378, 268 - 263, 268 - 378}, /* LD20 TV */
+ {268 - 378, 268 - 263, 268 - 378}, /* LD20 TV C1 */
{268 - 212, 268 - 536, /* No CH2 */}, /* LD21 reference */
{268 - 212, 268 - 536, /* No CH2 */}, /* LD21 TV */
};
static const u32 ddrphy_phy_pad_ctrl[DRAM_BOARD_NR][DRAM_CH_NR] = {
{0x50B840B1, 0x50B840B1, 0x50B840B1}, /* LD20 reference */
{0x50BB40B1, 0x50BB40B1, 0x50BB40B1}, /* LD20 TV */
+ {0x50BB40B1, 0x50BB40B1, 0x50BB40B1}, /* LD20 TV C1 */
{0x50BB40B4, 0x50B840B1, /* No CH2 */}, /* LD21 reference */
{0x50BB40B4, 0x50B840B1, /* No CH2 */}, /* LD21 TV */
};
1, 1, 1, 0, 2, 2, 1, 2,
},
},
+ { /* LD20 TV C1 */
+ {
+ 2, 1, 0, 1, 2, 1, 1, 1,
+ 2, 1, 1, 2, 1, 1, 1, 1,
+ 1, 2, 1, 1, 1, 2, 1, 1,
+ 2, 2, 0, 1, 1, 2, 2, 1,
+ },
+ {
+ 1, 1, 0, 1, 2, 2, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 0, 0, 1, 1, 0, 0,
+ 0, 1, 1, 1, 2, 1, 2, 1,
+ },
+ {
+ 2, 2, 0, 2, 1, 1, 2, 1,
+ 1, 1, 0, 1, 1, -1, 1, 1,
+ 2, 2, 2, 2, 1, 1, 1, 1,
+ 1, 1, 1, 0, 2, 2, 1, 2,
+ },
+ },
{ /* LD21 reference */
{
1, 1, 0, 1, 1, 1, 1, 1,
2, 2, 2, 2, 1, 2, 2, 1,
},
},
+ { /* LD20 TV C1 */
+ {
+ 3, 3, 3, 2, 3, 2, 0, 2,
+ 2, 3, 3, 1, 2, 2, 2, 2,
+ 2, 2, 2, 2, 0, 1, 1, 1,
+ 2, 2, 2, 2, 3, 0, 2, 2,
+ },
+ {
+ 2, 2, 1, 1, -1, 1, 1, 1,
+ 2, 0, 2, 2, 2, 1, 0, 2,
+ 2, 1, 2, 1, 0, 1, 1, 1,
+ 2, 2, 2, 2, 2, 2, 2, 2,
+ },
+ {
+ 2, 2, 3, 2, 1, 2, 2, 2,
+ 2, 3, 4, 2, 3, 4, 3, 3,
+ 2, 2, 1, 2, 1, 1, 1, 1,
+ 2, 2, 2, 2, 1, 2, 2, 1,
+ },
+ },
{ /* LD21 reference */
{
2, 2, 2, 2, 1, 2, 2, 2,
writel(0x00010000, phy_base + PHY_DLL_TRIM_2);
writel(0x50000000, phy_base + PHY_SCL_START);
- while (readl(phy_base + PHY_SCL_START) & BIT(28))
+ while (readl(phy_base + PHY_SCL_START) & PHY_SCL_START_GO_DONE)
cpu_relax();
writel(0x00000000, phy_base + PHY_DISABLE_GATING_FOR_SCL);
writel(0xFBF8FFFF, phy_base + PHY_SCL_START_ADDR);
writel(0x11000000, phy_base + PHY_SCL_START);
- while (readl(phy_base + PHY_SCL_START) & BIT(28))
+ while (readl(phy_base + PHY_SCL_START) & PHY_SCL_START_GO_DONE)
cpu_relax();
writel(0xFBF0FFFF, phy_base + PHY_SCL_START_ADDR);
writel(0x30500000, phy_base + PHY_SCL_START);
- while (readl(phy_base + PHY_SCL_START) & BIT(28))
+ while (readl(phy_base + PHY_SCL_START) & PHY_SCL_START_GO_DONE)
cpu_relax();
writel(0x00000001, phy_base + PHY_DISABLE_GATING_FOR_SCL);
writel(0xf10e4a56, phy_base + PHY_SCL_DATA_1);
writel(0x11000000, phy_base + PHY_SCL_START);
- while (readl(phy_base + PHY_SCL_START) & BIT(28))
+ while (readl(phy_base + PHY_SCL_START) & PHY_SCL_START_GO_DONE)
cpu_relax();
writel(0x34000000, phy_base + PHY_SCL_START);
- while (readl(phy_base + PHY_SCL_START) & BIT(28))
+ while (readl(phy_base + PHY_SCL_START) & PHY_SCL_START_GO_DONE)
cpu_relax();
writel(0x00000003, phy_base + PHY_DISABLE_GATING_FOR_SCL);
}
/* UMC */
-static u32 umc_initctla[DRAM_FREQ_NR] = {0x71016D11};
-static u32 umc_initctlb[DRAM_FREQ_NR] = {0x07E390AC};
-static u32 umc_initctlc[DRAM_FREQ_NR] = {0x00FF00FF};
-static u32 umc_drmmr0[DRAM_FREQ_NR] = {0x00000114};
-static u32 umc_drmmr2[DRAM_FREQ_NR] = {0x000002a0};
+static const u32 umc_initctla[DRAM_FREQ_NR] = {0x71016D11};
+static const u32 umc_initctlb[DRAM_FREQ_NR] = {0x07E390AC};
+static const u32 umc_initctlc[DRAM_FREQ_NR] = {0x00FF00FF};
+static const u32 umc_drmmr0[DRAM_FREQ_NR] = {0x00000114};
+static const u32 umc_drmmr2[DRAM_FREQ_NR] = {0x000002a0};
-static u32 umc_memconf0a[DRAM_FREQ_NR][DRAM_SZ_NR] = {
+static const u32 umc_memconf0a[DRAM_FREQ_NR][DRAM_SZ_NR] = {
/* 256MB 512MB */
{0x00000601, 0x00000801}, /* 1866 MHz */
};
-static u32 umc_memconf0b[DRAM_FREQ_NR][DRAM_SZ_NR] = {
+static const u32 umc_memconf0b[DRAM_FREQ_NR][DRAM_SZ_NR] = {
/* 256MB 512MB */
{0x00000120, 0x00000130}, /* 1866 MHz */
};
-static u32 umc_memconfch[DRAM_FREQ_NR][DRAM_SZ_NR] = {
+static const u32 umc_memconfch[DRAM_FREQ_NR][DRAM_SZ_NR] = {
/* 256MB 512MB */
{0x00033603, 0x00033803}, /* 1866 MHz */
};
-static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x060D0D20};
-static u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x2D211C08};
-static u32 umc_cmdctlc[DRAM_FREQ_NR] = {0x00150C04};
-static u32 umc_cmdctle[DRAM_FREQ_NR][DRAM_SZ_NR] = {
+static const u32 umc_cmdctla[DRAM_FREQ_NR] = {0x060D0D20};
+static const u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x2D211C08};
+static const u32 umc_cmdctlc[DRAM_FREQ_NR] = {0x00150C04};
+static const u32 umc_cmdctle[DRAM_FREQ_NR][DRAM_SZ_NR] = {
/* 256MB 512MB */
{0x0049071D, 0x0078071D}, /* 1866 MHz */
};
-static u32 umc_rdatactl_d0[DRAM_FREQ_NR] = {0x00000610};
-static u32 umc_rdatactl_d1[DRAM_FREQ_NR] = {0x00000610};
-static u32 umc_wdatactl_d0[DRAM_FREQ_NR] = {0x00000204};
-static u32 umc_wdatactl_d1[DRAM_FREQ_NR] = {0x00000204};
-static u32 umc_odtctl_d0[DRAM_FREQ_NR] = {0x02000002};
-static u32 umc_odtctl_d1[DRAM_FREQ_NR] = {0x02000002};
-static u32 umc_dataset[DRAM_FREQ_NR] = {0x04000000};
+static const u32 umc_rdatactl[DRAM_FREQ_NR] = {0x00000610};
+static const u32 umc_wdatactl[DRAM_FREQ_NR] = {0x00000204};
+static const u32 umc_odtctl[DRAM_FREQ_NR] = {0x02000002};
+static const u32 umc_dataset[DRAM_FREQ_NR] = {0x04000000};
-static u32 umc_flowctla[DRAM_FREQ_NR] = {0x0081E01E};
-static u32 umc_directbusctrla[DRAM_CH_NR] = {
+static const u32 umc_flowctla[DRAM_FREQ_NR] = {0x0081E01E};
+static const u32 umc_directbusctrla[DRAM_CH_NR] = {
0x00000000, 0x00000001, 0x00000001
};
writel(umc_cmdctlc[freq_e], dc_base + UMC_CMDCTLC);
writel(umc_cmdctle[freq_e][size_e], dc_base + UMC_CMDCTLE);
- writel(umc_rdatactl_d0[freq_e], dc_base + UMC_RDATACTL_D0);
- writel(umc_rdatactl_d1[freq_e], dc_base + UMC_RDATACTL_D1);
+ writel(umc_rdatactl[freq_e], dc_base + UMC_RDATACTL_D0);
+ writel(umc_rdatactl[freq_e], dc_base + UMC_RDATACTL_D1);
- writel(umc_wdatactl_d0[freq_e], dc_base + UMC_WDATACTL_D0);
- writel(umc_wdatactl_d1[freq_e], dc_base + UMC_WDATACTL_D1);
- writel(umc_odtctl_d0[freq_e], dc_base + UMC_ODTCTL_D0);
- writel(umc_odtctl_d1[freq_e], dc_base + UMC_ODTCTL_D1);
+ writel(umc_wdatactl[freq_e], dc_base + UMC_WDATACTL_D0);
+ writel(umc_wdatactl[freq_e], dc_base + UMC_WDATACTL_D1);
+ writel(umc_odtctl[freq_e], dc_base + UMC_ODTCTL_D0);
+ writel(umc_odtctl[freq_e], dc_base + UMC_ODTCTL_D1);
writel(umc_dataset[freq_e], dc_base + UMC_DATASET);
writel(0x00400020, dc_base + UMC_DCCGCTL);
case UNIPHIER_BD_BOARD_LD20_GLOBAL:
board = DRAM_BOARD_LD20_GLOBAL;
break;
+ case UNIPHIER_BD_BOARD_LD20_C1:
+ board = DRAM_BOARD_LD20_C1;
+ break;
case UNIPHIER_BD_BOARD_LD21_REF:
board = DRAM_BOARD_LD21_REF;
break;
#include <asm/processor.h>
#include "../init.h"
-#include "ddrphy-regs.h"
+#include "ddrphy-init.h"
#include "umc-regs.h"
#define DRAM_CH_NR 2
int ret;
writel(UMC_INITSET_INIT1EN, dc_base + UMC_INITSET);
- while (readl(dc_base + UMC_INITSET) & UMC_INITSTAT_INIT1ST)
+ while (readl(dc_base + UMC_INITSTAT) & UMC_INITSTAT_INIT1ST)
cpu_relax();
writel(0x00000101, dc_base + UMC_DIOCTLA);
#include <asm/processor.h>
#include "../init.h"
-#include "ddrphy-regs.h"
+#include "ddrphy-init.h"
#include "umc-regs.h"
#define DRAM_CH_NR 2
int phy, ret;
writel(UMC_INITSET_INIT1EN, dc_base + UMC_INITSET);
- while (readl(dc_base + UMC_INITSET) & UMC_INITSTAT_INIT1ST)
+ while (readl(dc_base + UMC_INITSTAT) & UMC_INITSTAT_INIT1ST)
cpu_relax();
for (phy = 0; phy < nr_phy; phy++) {
#include <asm/processor.h>
#include "../init.h"
-#include "ddrphy-regs.h"
+#include "ddrphy-init.h"
#include "umc-regs.h"
#define DRAM_CH_NR 2
int ret;
writel(UMC_INITSET_INIT1EN, dc_base + UMC_INITSET);
- while (readl(dc_base + UMC_INITSET) & UMC_INITSTAT_INIT1ST)
+ while (readl(dc_base + UMC_INITSTAT) & UMC_INITSTAT_INIT1ST)
cpu_relax();
writel(0x00000101, dc_base + UMC_DIOCTLA);
struct uniphier_dram_ch dram_ch[UNIPHIER_MAX_NR_DRAM_CH];
unsigned int flags;
-#define UNIPHIER_BD_DPLL_SSC_GET_RATE(f) (((f) >> 8) & 0x3)
-#define UNIPHIER_BD_DPLL_SSC_RATE(r) (((r) & 0x3) << 8)
-
#define UNIPHIER_BD_DDR3PLUS BIT(2)
-#define UNIPHIER_BD_BOARD_GET_TYPE(f) ((f) & 0x3)
+#define UNIPHIER_BD_BOARD_GET_TYPE(f) ((f) & 0x7)
#define UNIPHIER_BD_BOARD_LD20_REF 0 /* LD20 reference */
#define UNIPHIER_BD_BOARD_LD20_GLOBAL 1 /* LD20 TV Set */
-#define UNIPHIER_BD_BOARD_LD21_REF 2 /* LD21 reference */
-#define UNIPHIER_BD_BOARD_LD21_GLOBAL 3 /* LD21 TV Set */
+#define UNIPHIER_BD_BOARD_LD20_C1 2 /* LD20 TV Set C1 */
+#define UNIPHIER_BD_BOARD_LD21_REF 3 /* LD21 reference */
+#define UNIPHIER_BD_BOARD_LD21_GLOBAL 4 /* LD21 TV Set */
};
const struct uniphier_board_data *uniphier_get_board_param(void);
#define SC_CLKCTRL (SC_BASE_ADDR | 0x2100)
#define SC_CLKCTRL3 (SC_BASE_ADDR | 0x2108)
#define SC_CLKCTRL4 (SC_BASE_ADDR | 0x210c)
+#define SC_CLKCTRL4_MIO (1 << 10)
+#define SC_CLKCTRL4_STDMAC (1 << 8)
#define SC_CLKCTRL4_PERI (1 << 7)
#define SC_CLKCTRL4_ETHER (1 << 6)
#define SC_CLKCTRL4_NAND (1 << 0)
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x777
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 6
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 200
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x330
#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32
#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8
#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3
#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2
#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0
+#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0
#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x1FF
debug("Configuring DRAMODT\n");
writel(cfg->dram_odt, &sdr_ctrl->dram_odt);
+
+ debug("Configuring EXTRATIME1\n");
+ writel(cfg->extratime1, &sdr_ctrl->extratime1);
}
/**
return ehci_register(dev, hccr, hcor, &vf_ehci_ops, 0, priv->init_type);
}
-static int ehci_usb_remove(struct udevice *dev)
-{
- int ret;
-
- ret = ehci_deregister(dev);
- if (ret)
- return ret;
-
- return 0;
-}
-
static const struct udevice_id vf_usb_ids[] = {
{ .compatible = "fsl,vf610-usb" },
{ }
.of_match = vf_usb_ids,
.bind = vf_usb_bind,
.probe = ehci_usb_probe,
- .remove = ehci_usb_remove,
+ .remove = ehci_deregister,
.ops = &ehci_usb_ops,
.ofdata_to_platdata = vf_usb_ofdata_to_platdata,
.platdata_auto_alloc_size = sizeof(struct usb_platdata),
ed->hwNextED = 0;
flush_dcache_ed(ed);
if (ohci->ed_controltail == NULL)
- ohci_writel(ed, &ohci->regs->ed_controlhead);
+ ohci_writel((uintptr_t)ed, &ohci->regs->ed_controlhead);
else
ohci->ed_controltail->hwNextED =
m32_swap((unsigned long)ed);
ed->hwNextED = 0;
flush_dcache_ed(ed);
if (ohci->ed_bulktail == NULL)
- ohci_writel(ed, &ohci->regs->ed_bulkhead);
+ ohci_writel((uintptr_t)ed, &ohci->regs->ed_bulkhead);
else
ohci->ed_bulktail->hwNextED =
m32_swap((unsigned long)ed);
/* ED might have been unlinked through another path */
while (*ed_p != 0) {
- if (((struct ed *)
+ if (((struct ed *)(uintptr_t)
m32_swap((unsigned long)ed_p)) == ed) {
*ed_p = ed->hwNextED;
aligned_ed_p = (unsigned long)ed_p;
aligned_ed_p + ARCH_DMA_MINALIGN);
break;
}
- ed_p = &(((struct ed *)
+ ed_p = &(((struct ed *)(uintptr_t)
m32_swap((unsigned long)ed_p))->hwNextED);
}
}
if (ohci->ed_controltail == ed) {
ohci->ed_controltail = ed->ed_prev;
} else {
- ((ed_t *)m32_swap(
+ ((ed_t *)(uintptr_t)m32_swap(
*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
}
break;
if (ohci->ed_bulktail == ed) {
ohci->ed_bulktail = ed->ed_prev;
} else {
- ((ed_t *)m32_swap(
+ ((ed_t *)(uintptr_t)m32_swap(
*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
}
break;
/* fill the old dummy TD */
td = urb_priv->td [index] =
- (td_t *)(m32_swap(urb_priv->ed->hwTailP) & ~0xf);
+ (td_t *)(uintptr_t)
+ (m32_swap(urb_priv->ed->hwTailP) & ~0xf);
td->ed = urb_priv->ed;
td->next_dl_td = NULL;
td->index = index;
- td->data = (__u32)data;
+ td->data = (uintptr_t)data;
#ifdef OHCI_FILL_TRACE
if (usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe)) {
for (i = 0; i < len; i++)
* we reverse the reversed done-list */
static td_t *dl_reverse_done_list(ohci_t *ohci)
{
- __u32 td_list_hc;
+ uintptr_t td_list_hc;
td_t *td_rev = NULL;
td_t *td_list = NULL;
ohci_writel(0, &ohci->regs->ed_controlhead);
ohci_writel(0, &ohci->regs->ed_bulkhead);
- ohci_writel((__u32)ohci->hcca,
+ ohci_writel((uintptr_t)ohci->hcca,
&ohci->regs->hcca); /* reset clears this */
fminterval = 0x2edf;
extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0;
#endif
priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;
- priv->phy_index = ((u32)regs - (SUNXI_USB1_BASE + 0x400)) / BASE_DIST;
+ priv->phy_index = ((uintptr_t)regs - (SUNXI_USB1_BASE + 0x400)) / BASE_DIST;
priv->ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST;
extra_ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST;
priv->usb_gate_mask <<= priv->phy_index;
/*
* e.g. PCI controllers need this
*/
+
+#include <asm/io.h>
+
#ifdef CONFIG_SYS_OHCI_SWAP_REG_ACCESS
-# define ohci_readl(a) __swap_32(*((volatile u32 *)(a)))
-# define ohci_writel(a, b) (*((volatile u32 *)(b)) = __swap_32((volatile u32)a))
+# define ohci_readl(a) __swap_32(readl(a))
+# define ohci_writel(v, a) writel(__swap_32(v), a)
#else
-# define ohci_readl(a) (*((volatile u32 *)(a)))
-# define ohci_writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a))
+# define ohci_readl(a) readl(a)
+# define ohci_writel(v, a) writel(v, a)
#endif /* CONFIG_SYS_OHCI_SWAP_REG_ACCESS */
#if ARCH_DMA_MINALIGN > 16
return xhci_register(dev, ctx->hcd, hcor);
}
-static int xhci_usb_remove(struct udevice *dev)
-{
- return xhci_deregister(dev);
-}
-
static int xhci_usb_ofdata_to_platdata(struct udevice *dev)
{
struct mvebu_xhci_platdata *plat = dev_get_platdata(dev);
.of_match = xhci_usb_ids,
.ofdata_to_platdata = xhci_usb_ofdata_to_platdata,
.probe = xhci_usb_probe,
- .remove = xhci_usb_remove,
+ .remove = xhci_deregister,
.ops = &xhci_usb_ops,
.platdata_auto_alloc_size = sizeof(struct mvebu_xhci_platdata),
.priv_auto_alloc_size = sizeof(struct mvebu_xhci),
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