#include <common.h>
#include <netdev.h>
-#include <s3c2410.h>
+#include <asm/arch/s3c2410.h>
#include <stdio_dev.h>
#include <i2c.h>
* Global routines used for VCMA9
*****************************************************************************/
-#include <s3c2410.h>
+#include <asm/arch/s3c2410.h>
extern int mem_test(unsigned long start, unsigned long ramsize,int mode);
#include <common.h>
#include <netdev.h>
-#include <s3c2400.h>
+#include <asm/arch/s3c2400.h>
DECLARE_GLOBAL_DATA_PTR;
#include <common.h>
#include <netdev.h>
-#include <s3c2410.h>
+#include <asm/arch/s3c2410.h>
DECLARE_GLOBAL_DATA_PTR;
#include <common.h>
#include <netdev.h>
-#include <s3c2410.h>
+#include <asm/arch/s3c2410.h>
#if defined(CONFIG_CMD_NAND)
#include <linux/mtd/nand.h>
#include <common.h>
#include <command.h>
-#include <s3c2400.h>
+#include <asm/arch/s3c2400.h>
#include <rtc.h>
/*
*/
#include <common.h>
-#include <s3c2400.h>
+#include <asm/arch/s3c2400.h>
#include "rs485.h"
static void rs485_setbrg (void);
#ifndef _RS485_H_
#define _RS485_H_
-#include <s3c2400.h>
+#include <asm/arch/s3c2400.h>
int rs485_init (void);
int rs485_getc (void);
#include <common.h>
#include <netdev.h>
#include <malloc.h>
-#include <s3c2400.h>
+#include <asm/arch/s3c2400.h>
#include <command.h>
DECLARE_GLOBAL_DATA_PTR;
#include <common.h>
#include <exports.h>
#include <timestamp.h>
-#include <s3c2400.h>
+#include <asm/arch/s3c2400.h>
#include "tsc2000.h"
#include "rs485.h"
*/
#include <common.h>
-#include <s3c2400.h>
+#include <asm/arch/s3c2400.h>
#include <asm/io.h>
#include <div64.h>
#include "tsc2000.h"
#include <stdarg.h>
#include <linux/types.h>
#include <stdio_dev.h>
-#include <s3c2400.h>
+#include <asm/arch/s3c2400.h>
DECLARE_GLOBAL_DATA_PTR;
#include <common.h>
#if defined(CONFIG_S3C2400)
-#include <s3c2400.h>
+#include <asm/arch/s3c2400.h>
#elif defined(CONFIG_S3C2410)
-#include <s3c2410.h>
+#include <asm/arch/s3c2410.h>
#endif
#include <asm/proc-armv/ptrace.h>
#include <asm/io.h>
#if defined(CONFIG_S3C2400)
-#include <s3c2400.h>
+#include <asm/arch/s3c2400.h>
#elif defined(CONFIG_S3C2410)
-#include <s3c2410.h>
+#include <asm/arch/s3c2410.h>
#endif
#define MPLL 0
#include <asm/io.h>
#if defined(CONFIG_S3C2400)
-#include <s3c2400.h>
+#include <asm/arch/s3c2400.h>
#elif defined(CONFIG_S3C2410)
-#include <s3c2410.h>
+#include <asm/arch/s3c2410.h>
#endif
int timer_load_val = 0;
# if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)
#if defined(CONFIG_S3C2400)
-# include <s3c2400.h>
+# include <asm/arch/s3c2400.h>
#elif defined(CONFIG_S3C2410)
-# include <s3c2410.h>
+# include <asm/arch/s3c2410.h>
#endif
#include <asm/io.h>
#ifdef CONFIG_USB_OHCI
#if defined(CONFIG_S3C2400)
-#include <s3c2400.h>
+#include <asm/arch/s3c2400.h>
#elif defined(CONFIG_S3C2410)
-#include <s3c2410.h>
+#include <asm/arch/s3c2410.h>
#endif
#include <asm/io.h>
#include <common.h>
#if defined(CONFIG_S3C2400)
-#include <s3c2400.h>
+#include <asm/arch/s3c2400.h>
#elif defined(CONFIG_S3C2410)
-#include <s3c2410.h>
+#include <asm/arch/s3c2410.h>
#endif
#include <asm/io.h>
#include <common.h>
#include <nand.h>
-#include <s3c2410.h>
+#include <asm/arch/s3c2410.h>
#include <asm/io.h>
#define S3C2410_NFCONF_EN (1<<15)
#if (defined(CONFIG_CMD_DATE))
#if defined(CONFIG_S3C2400)
-#include <s3c2400.h>
+#include <asm/arch/s3c2400.h>
#elif defined(CONFIG_S3C2410)
-#include <s3c2410.h>
+#include <asm/arch/s3c2410.h>
#endif
#include <rtc.h>
#include <common.h>
#if defined(CONFIG_S3C2400) || defined(CONFIG_TRAB)
-#include <s3c2400.h>
+#include <asm/arch/s3c2400.h>
#elif defined(CONFIG_S3C2410)
-#include <s3c2410.h>
+#include <asm/arch/s3c2410.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************
+ * NAME : s3c2400.h
+ * Version : 31.3.2003
+ *
+ * Based on S3C2400X User's manual Rev 1.1
+ ************************************************/
+
+#ifndef __S3C2400_H__
+#define __S3C2400_H__
+
+#define S3C24X0_UART_CHANNELS 2
+#define S3C24X0_SPI_CHANNELS 1
+#define PALETTE (0x14A00400) /* SJS */
+
+enum s3c24x0_uarts_nr {
+ S3C24X0_UART0,
+ S3C24X0_UART1,
+};
+
+/*S3C2400 device base addresses */
+#define S3C24X0_MEMCTL_BASE 0x14000000
+#define S3C24X0_USB_HOST_BASE 0x14200000
+#define S3C24X0_INTERRUPT_BASE 0x14400000
+#define S3C24X0_DMA_BASE 0x14600000
+#define S3C24X0_CLOCK_POWER_BASE 0x14800000
+#define S3C24X0_LCD_BASE 0x14A00000
+#define S3C24X0_UART_BASE 0x15000000
+#define S3C24X0_TIMER_BASE 0x15100000
+#define S3C24X0_USB_DEVICE_BASE 0x15200140
+#define S3C24X0_WATCHDOG_BASE 0x15300000
+#define S3C24X0_I2C_BASE 0x15400000
+#define S3C24X0_I2S_BASE 0x15508000
+#define S3C24X0_GPIO_BASE 0x15600000
+#define S3C24X0_RTC_BASE 0x15700000
+#define S3C24X0_ADC_BASE 0x15800000
+#define S3C24X0_SPI_BASE 0x15900000
+#define S3C2400_MMC_BASE 0x15A00000
+
+/* include common stuff */
+#include <asm/arch/s3c24x0.h>
+
+
+static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void)
+{
+ return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE;
+}
+static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void)
+{
+ return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE;
+}
+static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void)
+{
+ return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE;
+}
+static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void)
+{
+ return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE;
+}
+static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void)
+{
+ return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE;
+}
+static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void)
+{
+ return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE;
+}
+static inline struct s3c24x0_uart
+ *s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n)
+{
+ return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000));
+}
+static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void)
+{
+ return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE;
+}
+static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void)
+{
+ return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE;
+}
+static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void)
+{
+ return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE;
+}
+static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void)
+{
+ return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE;
+}
+static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void)
+{
+ return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE;
+}
+static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void)
+{
+ return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE;
+}
+static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void)
+{
+ return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE;
+}
+static inline struct s3c2400_adc *s3c2400_get_base_adc(void)
+{
+ return (struct s3c2400_adc *)S3C24X0_ADC_BASE;
+}
+static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void)
+{
+ return (struct s3c24x0_spi *)S3C24X0_SPI_BASE;
+}
+static inline struct s3c2400_mmc *s3c2400_get_base_mmc(void)
+{
+ return (struct s3c2400_mmc *)S3C2400_MMC_BASE;
+}
+
+#endif /*__S3C2400_H__*/
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************
+ * NAME : s3c2410.h
+ * Version : 31.3.2003
+ *
+ * Based on S3C2410X User's manual Rev 1.1
+ ************************************************/
+
+#ifndef __S3C2410_H__
+#define __S3C2410_H__
+
+#define S3C24X0_UART_CHANNELS 3
+#define S3C24X0_SPI_CHANNELS 2
+
+/* S3C2410 only supports 512 Byte HW ECC */
+#define S3C2410_ECCSIZE 512
+#define S3C2410_ECCBYTES 3
+
+enum s3c24x0_uarts_nr {
+ S3C24X0_UART0,
+ S3C24X0_UART1,
+ S3C24X0_UART2
+};
+
+/* S3C2410 device base addresses */
+#define S3C24X0_MEMCTL_BASE 0x48000000
+#define S3C24X0_USB_HOST_BASE 0x49000000
+#define S3C24X0_INTERRUPT_BASE 0x4A000000
+#define S3C24X0_DMA_BASE 0x4B000000
+#define S3C24X0_CLOCK_POWER_BASE 0x4C000000
+#define S3C24X0_LCD_BASE 0x4D000000
+#define S3C2410_NAND_BASE 0x4E000000
+#define S3C24X0_UART_BASE 0x50000000
+#define S3C24X0_TIMER_BASE 0x51000000
+#define S3C24X0_USB_DEVICE_BASE 0x52000140
+#define S3C24X0_WATCHDOG_BASE 0x53000000
+#define S3C24X0_I2C_BASE 0x54000000
+#define S3C24X0_I2S_BASE 0x55000000
+#define S3C24X0_GPIO_BASE 0x56000000
+#define S3C24X0_RTC_BASE 0x57000000
+#define S3C2410_ADC_BASE 0x58000000
+#define S3C24X0_SPI_BASE 0x59000000
+#define S3C2410_SDI_BASE 0x5A000000
+
+
+/* include common stuff */
+#include <asm/arch/s3c24x0.h>
+
+
+static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void)
+{
+ return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE;
+}
+static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void)
+{
+ return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE;
+}
+static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void)
+{
+ return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE;
+}
+static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void)
+{
+ return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE;
+}
+static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void)
+{
+ return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE;
+}
+static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void)
+{
+ return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE;
+}
+static inline struct s3c2410_nand *s3c2410_get_base_nand(void)
+{
+ return (struct s3c2410_nand *)S3C2410_NAND_BASE;
+}
+static inline struct s3c24x0_uart
+ *s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n)
+{
+ return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000));
+}
+static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void)
+{
+ return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE;
+}
+static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void)
+{
+ return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE;
+}
+static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void)
+{
+ return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE;
+}
+static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void)
+{
+ return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE;
+}
+static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void)
+{
+ return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE;
+}
+static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void)
+{
+ return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE;
+}
+static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void)
+{
+ return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE;
+}
+static inline struct s3c2410_adc *s3c2410_get_base_adc(void)
+{
+ return (struct s3c2410_adc *)S3C2410_ADC_BASE;
+}
+static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void)
+{
+ return (struct s3c24x0_spi *)S3C24X0_SPI_BASE;
+}
+static inline struct s3c2410_sdi *s3c2410_get_base_sdi(void)
+{
+ return (struct s3c2410_sdi *)S3C2410_SDI_BASE;
+}
+
+#endif /*__S3C2410_H__*/
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************
+ * NAME : s3c24x0.h
+ * Version : 31.3.2003
+ *
+ * common stuff for SAMSUNG S3C24X0 SoC
+ ************************************************/
+
+#ifndef __S3C24X0_H__
+#define __S3C24X0_H__
+
+typedef volatile u8 S3C24X0_REG8;
+typedef volatile u16 S3C24X0_REG16;
+typedef volatile u32 S3C24X0_REG32;
+
+/* Memory controller (see manual chapter 5) */
+struct s3c24x0_memctl {
+ S3C24X0_REG32 BWSCON;
+ S3C24X0_REG32 BANKCON[8];
+ S3C24X0_REG32 REFRESH;
+ S3C24X0_REG32 BANKSIZE;
+ S3C24X0_REG32 MRSRB6;
+ S3C24X0_REG32 MRSRB7;
+};
+
+
+/* USB HOST (see manual chapter 12) */
+struct s3c24x0_usb_host {
+ S3C24X0_REG32 HcRevision;
+ S3C24X0_REG32 HcControl;
+ S3C24X0_REG32 HcCommonStatus;
+ S3C24X0_REG32 HcInterruptStatus;
+ S3C24X0_REG32 HcInterruptEnable;
+ S3C24X0_REG32 HcInterruptDisable;
+ S3C24X0_REG32 HcHCCA;
+ S3C24X0_REG32 HcPeriodCuttendED;
+ S3C24X0_REG32 HcControlHeadED;
+ S3C24X0_REG32 HcControlCurrentED;
+ S3C24X0_REG32 HcBulkHeadED;
+ S3C24X0_REG32 HcBuldCurrentED;
+ S3C24X0_REG32 HcDoneHead;
+ S3C24X0_REG32 HcRmInterval;
+ S3C24X0_REG32 HcFmRemaining;
+ S3C24X0_REG32 HcFmNumber;
+ S3C24X0_REG32 HcPeriodicStart;
+ S3C24X0_REG32 HcLSThreshold;
+ S3C24X0_REG32 HcRhDescriptorA;
+ S3C24X0_REG32 HcRhDescriptorB;
+ S3C24X0_REG32 HcRhStatus;
+ S3C24X0_REG32 HcRhPortStatus1;
+ S3C24X0_REG32 HcRhPortStatus2;
+};
+
+
+/* INTERRUPT (see manual chapter 14) */
+struct s3c24x0_interrupt {
+ S3C24X0_REG32 SRCPND;
+ S3C24X0_REG32 INTMOD;
+ S3C24X0_REG32 INTMSK;
+ S3C24X0_REG32 PRIORITY;
+ S3C24X0_REG32 INTPND;
+ S3C24X0_REG32 INTOFFSET;
+#ifdef CONFIG_S3C2410
+ S3C24X0_REG32 SUBSRCPND;
+ S3C24X0_REG32 INTSUBMSK;
+#endif
+};
+
+
+/* DMAS (see manual chapter 8) */
+struct s3c24x0_dma {
+ S3C24X0_REG32 DISRC;
+#ifdef CONFIG_S3C2410
+ S3C24X0_REG32 DISRCC;
+#endif
+ S3C24X0_REG32 DIDST;
+#ifdef CONFIG_S3C2410
+ S3C24X0_REG32 DIDSTC;
+#endif
+ S3C24X0_REG32 DCON;
+ S3C24X0_REG32 DSTAT;
+ S3C24X0_REG32 DCSRC;
+ S3C24X0_REG32 DCDST;
+ S3C24X0_REG32 DMASKTRIG;
+#ifdef CONFIG_S3C2400
+ S3C24X0_REG32 res[1];
+#endif
+#ifdef CONFIG_S3C2410
+ S3C24X0_REG32 res[7];
+#endif
+};
+
+struct s3c24x0_dmas {
+ struct s3c24x0_dma dma[4];
+};
+
+
+/* CLOCK & POWER MANAGEMENT (see S3C2400 manual chapter 6) */
+/* (see S3C2410 manual chapter 7) */
+struct s3c24x0_clock_power {
+ S3C24X0_REG32 LOCKTIME;
+ S3C24X0_REG32 MPLLCON;
+ S3C24X0_REG32 UPLLCON;
+ S3C24X0_REG32 CLKCON;
+ S3C24X0_REG32 CLKSLOW;
+ S3C24X0_REG32 CLKDIVN;
+};
+
+
+/* LCD CONTROLLER (see manual chapter 15) */
+struct s3c24x0_lcd {
+ S3C24X0_REG32 LCDCON1;
+ S3C24X0_REG32 LCDCON2;
+ S3C24X0_REG32 LCDCON3;
+ S3C24X0_REG32 LCDCON4;
+ S3C24X0_REG32 LCDCON5;
+ S3C24X0_REG32 LCDSADDR1;
+ S3C24X0_REG32 LCDSADDR2;
+ S3C24X0_REG32 LCDSADDR3;
+ S3C24X0_REG32 REDLUT;
+ S3C24X0_REG32 GREENLUT;
+ S3C24X0_REG32 BLUELUT;
+ S3C24X0_REG32 res[8];
+ S3C24X0_REG32 DITHMODE;
+ S3C24X0_REG32 TPAL;
+#ifdef CONFIG_S3C2410
+ S3C24X0_REG32 LCDINTPND;
+ S3C24X0_REG32 LCDSRCPND;
+ S3C24X0_REG32 LCDINTMSK;
+ S3C24X0_REG32 LPCSEL;
+#endif
+};
+
+
+/* NAND FLASH (see S3C2410 manual chapter 6) */
+struct s3c2410_nand {
+ S3C24X0_REG32 NFCONF;
+ S3C24X0_REG32 NFCMD;
+ S3C24X0_REG32 NFADDR;
+ S3C24X0_REG32 NFDATA;
+ S3C24X0_REG32 NFSTAT;
+ S3C24X0_REG32 NFECC;
+};
+
+
+/* UART (see manual chapter 11) */
+struct s3c24x0_uart {
+ S3C24X0_REG32 ULCON;
+ S3C24X0_REG32 UCON;
+ S3C24X0_REG32 UFCON;
+ S3C24X0_REG32 UMCON;
+ S3C24X0_REG32 UTRSTAT;
+ S3C24X0_REG32 UERSTAT;
+ S3C24X0_REG32 UFSTAT;
+ S3C24X0_REG32 UMSTAT;
+#ifdef __BIG_ENDIAN
+ S3C24X0_REG8 res1[3];
+ S3C24X0_REG8 UTXH;
+ S3C24X0_REG8 res2[3];
+ S3C24X0_REG8 URXH;
+#else /* Little Endian */
+ S3C24X0_REG8 UTXH;
+ S3C24X0_REG8 res1[3];
+ S3C24X0_REG8 URXH;
+ S3C24X0_REG8 res2[3];
+#endif
+ S3C24X0_REG32 UBRDIV;
+};
+
+
+/* PWM TIMER (see manual chapter 10) */
+struct s3c24x0_timer {
+ S3C24X0_REG32 TCNTB;
+ S3C24X0_REG32 TCMPB;
+ S3C24X0_REG32 TCNTO;
+};
+
+struct s3c24x0_timers {
+ S3C24X0_REG32 TCFG0;
+ S3C24X0_REG32 TCFG1;
+ S3C24X0_REG32 TCON;
+ struct s3c24x0_timer ch[4];
+ S3C24X0_REG32 TCNTB4;
+ S3C24X0_REG32 TCNTO4;
+};
+
+
+/* USB DEVICE (see manual chapter 13) */
+struct s3c24x0_usb_dev_fifos {
+#ifdef __BIG_ENDIAN
+ S3C24X0_REG8 res[3];
+ S3C24X0_REG8 EP_FIFO_REG;
+#else /* little endian */
+ S3C24X0_REG8 EP_FIFO_REG;
+ S3C24X0_REG8 res[3];
+#endif
+};
+
+struct s3c24x0_usb_dev_dmas {
+#ifdef __BIG_ENDIAN
+ S3C24X0_REG8 res1[3];
+ S3C24X0_REG8 EP_DMA_CON;
+ S3C24X0_REG8 res2[3];
+ S3C24X0_REG8 EP_DMA_UNIT;
+ S3C24X0_REG8 res3[3];
+ S3C24X0_REG8 EP_DMA_FIFO;
+ S3C24X0_REG8 res4[3];
+ S3C24X0_REG8 EP_DMA_TTC_L;
+ S3C24X0_REG8 res5[3];
+ S3C24X0_REG8 EP_DMA_TTC_M;
+ S3C24X0_REG8 res6[3];
+ S3C24X0_REG8 EP_DMA_TTC_H;
+#else /* little endian */
+ S3C24X0_REG8 EP_DMA_CON;
+ S3C24X0_REG8 res1[3];
+ S3C24X0_REG8 EP_DMA_UNIT;
+ S3C24X0_REG8 res2[3];
+ S3C24X0_REG8 EP_DMA_FIFO;
+ S3C24X0_REG8 res3[3];
+ S3C24X0_REG8 EP_DMA_TTC_L;
+ S3C24X0_REG8 res4[3];
+ S3C24X0_REG8 EP_DMA_TTC_M;
+ S3C24X0_REG8 res5[3];
+ S3C24X0_REG8 EP_DMA_TTC_H;
+ S3C24X0_REG8 res6[3];
+#endif
+};
+
+struct s3c24x0_usb_device {
+#ifdef __BIG_ENDIAN
+ S3C24X0_REG8 res1[3];
+ S3C24X0_REG8 FUNC_ADDR_REG;
+ S3C24X0_REG8 res2[3];
+ S3C24X0_REG8 PWR_REG;
+ S3C24X0_REG8 res3[3];
+ S3C24X0_REG8 EP_INT_REG;
+ S3C24X0_REG8 res4[15];
+ S3C24X0_REG8 USB_INT_REG;
+ S3C24X0_REG8 res5[3];
+ S3C24X0_REG8 EP_INT_EN_REG;
+ S3C24X0_REG8 res6[15];
+ S3C24X0_REG8 USB_INT_EN_REG;
+ S3C24X0_REG8 res7[3];
+ S3C24X0_REG8 FRAME_NUM1_REG;
+ S3C24X0_REG8 res8[3];
+ S3C24X0_REG8 FRAME_NUM2_REG;
+ S3C24X0_REG8 res9[3];
+ S3C24X0_REG8 INDEX_REG;
+ S3C24X0_REG8 res10[7];
+ S3C24X0_REG8 MAXP_REG;
+ S3C24X0_REG8 res11[3];
+ S3C24X0_REG8 EP0_CSR_IN_CSR1_REG;
+ S3C24X0_REG8 res12[3];
+ S3C24X0_REG8 IN_CSR2_REG;
+ S3C24X0_REG8 res13[7];
+ S3C24X0_REG8 OUT_CSR1_REG;
+ S3C24X0_REG8 res14[3];
+ S3C24X0_REG8 OUT_CSR2_REG;
+ S3C24X0_REG8 res15[3];
+ S3C24X0_REG8 OUT_FIFO_CNT1_REG;
+ S3C24X0_REG8 res16[3];
+ S3C24X0_REG8 OUT_FIFO_CNT2_REG;
+#else /* little endian */
+ S3C24X0_REG8 FUNC_ADDR_REG;
+ S3C24X0_REG8 res1[3];
+ S3C24X0_REG8 PWR_REG;
+ S3C24X0_REG8 res2[3];
+ S3C24X0_REG8 EP_INT_REG;
+ S3C24X0_REG8 res3[15];
+ S3C24X0_REG8 USB_INT_REG;
+ S3C24X0_REG8 res4[3];
+ S3C24X0_REG8 EP_INT_EN_REG;
+ S3C24X0_REG8 res5[15];
+ S3C24X0_REG8 USB_INT_EN_REG;
+ S3C24X0_REG8 res6[3];
+ S3C24X0_REG8 FRAME_NUM1_REG;
+ S3C24X0_REG8 res7[3];
+ S3C24X0_REG8 FRAME_NUM2_REG;
+ S3C24X0_REG8 res8[3];
+ S3C24X0_REG8 INDEX_REG;
+ S3C24X0_REG8 res9[7];
+ S3C24X0_REG8 MAXP_REG;
+ S3C24X0_REG8 res10[7];
+ S3C24X0_REG8 EP0_CSR_IN_CSR1_REG;
+ S3C24X0_REG8 res11[3];
+ S3C24X0_REG8 IN_CSR2_REG;
+ S3C24X0_REG8 res12[3];
+ S3C24X0_REG8 OUT_CSR1_REG;
+ S3C24X0_REG8 res13[7];
+ S3C24X0_REG8 OUT_CSR2_REG;
+ S3C24X0_REG8 res14[3];
+ S3C24X0_REG8 OUT_FIFO_CNT1_REG;
+ S3C24X0_REG8 res15[3];
+ S3C24X0_REG8 OUT_FIFO_CNT2_REG;
+ S3C24X0_REG8 res16[3];
+#endif /* __BIG_ENDIAN */
+ struct s3c24x0_usb_dev_fifos fifo[5];
+ struct s3c24x0_usb_dev_dmas dma[5];
+};
+
+
+/* WATCH DOG TIMER (see manual chapter 18) */
+struct s3c24x0_watchdog {
+ S3C24X0_REG32 WTCON;
+ S3C24X0_REG32 WTDAT;
+ S3C24X0_REG32 WTCNT;
+};
+
+
+/* IIC (see manual chapter 20) */
+struct s3c24x0_i2c {
+ S3C24X0_REG32 IICCON;
+ S3C24X0_REG32 IICSTAT;
+ S3C24X0_REG32 IICADD;
+ S3C24X0_REG32 IICDS;
+};
+
+
+/* IIS (see manual chapter 21) */
+struct s3c24x0_i2s {
+#ifdef __BIG_ENDIAN
+ S3C24X0_REG16 res1;
+ S3C24X0_REG16 IISCON;
+ S3C24X0_REG16 res2;
+ S3C24X0_REG16 IISMOD;
+ S3C24X0_REG16 res3;
+ S3C24X0_REG16 IISPSR;
+ S3C24X0_REG16 res4;
+ S3C24X0_REG16 IISFCON;
+ S3C24X0_REG16 res5;
+ S3C24X0_REG16 IISFIFO;
+#else /* little endian */
+ S3C24X0_REG16 IISCON;
+ S3C24X0_REG16 res1;
+ S3C24X0_REG16 IISMOD;
+ S3C24X0_REG16 res2;
+ S3C24X0_REG16 IISPSR;
+ S3C24X0_REG16 res3;
+ S3C24X0_REG16 IISFCON;
+ S3C24X0_REG16 res4;
+ S3C24X0_REG16 IISFIFO;
+ S3C24X0_REG16 res5;
+#endif
+};
+
+
+/* I/O PORT (see manual chapter 9) */
+struct s3c24x0_gpio {
+#ifdef CONFIG_S3C2400
+ S3C24X0_REG32 PACON;
+ S3C24X0_REG32 PADAT;
+
+ S3C24X0_REG32 PBCON;
+ S3C24X0_REG32 PBDAT;
+ S3C24X0_REG32 PBUP;
+
+ S3C24X0_REG32 PCCON;
+ S3C24X0_REG32 PCDAT;
+ S3C24X0_REG32 PCUP;
+
+ S3C24X0_REG32 PDCON;
+ S3C24X0_REG32 PDDAT;
+ S3C24X0_REG32 PDUP;
+
+ S3C24X0_REG32 PECON;
+ S3C24X0_REG32 PEDAT;
+ S3C24X0_REG32 PEUP;
+
+ S3C24X0_REG32 PFCON;
+ S3C24X0_REG32 PFDAT;
+ S3C24X0_REG32 PFUP;
+
+ S3C24X0_REG32 PGCON;
+ S3C24X0_REG32 PGDAT;
+ S3C24X0_REG32 PGUP;
+
+ S3C24X0_REG32 OPENCR;
+
+ S3C24X0_REG32 MISCCR;
+ S3C24X0_REG32 EXTINT;
+#endif
+#ifdef CONFIG_S3C2410
+ S3C24X0_REG32 GPACON;
+ S3C24X0_REG32 GPADAT;
+ S3C24X0_REG32 res1[2];
+ S3C24X0_REG32 GPBCON;
+ S3C24X0_REG32 GPBDAT;
+ S3C24X0_REG32 GPBUP;
+ S3C24X0_REG32 res2;
+ S3C24X0_REG32 GPCCON;
+ S3C24X0_REG32 GPCDAT;
+ S3C24X0_REG32 GPCUP;
+ S3C24X0_REG32 res3;
+ S3C24X0_REG32 GPDCON;
+ S3C24X0_REG32 GPDDAT;
+ S3C24X0_REG32 GPDUP;
+ S3C24X0_REG32 res4;
+ S3C24X0_REG32 GPECON;
+ S3C24X0_REG32 GPEDAT;
+ S3C24X0_REG32 GPEUP;
+ S3C24X0_REG32 res5;
+ S3C24X0_REG32 GPFCON;
+ S3C24X0_REG32 GPFDAT;
+ S3C24X0_REG32 GPFUP;
+ S3C24X0_REG32 res6;
+ S3C24X0_REG32 GPGCON;
+ S3C24X0_REG32 GPGDAT;
+ S3C24X0_REG32 GPGUP;
+ S3C24X0_REG32 res7;
+ S3C24X0_REG32 GPHCON;
+ S3C24X0_REG32 GPHDAT;
+ S3C24X0_REG32 GPHUP;
+ S3C24X0_REG32 res8;
+
+ S3C24X0_REG32 MISCCR;
+ S3C24X0_REG32 DCLKCON;
+ S3C24X0_REG32 EXTINT0;
+ S3C24X0_REG32 EXTINT1;
+ S3C24X0_REG32 EXTINT2;
+ S3C24X0_REG32 EINTFLT0;
+ S3C24X0_REG32 EINTFLT1;
+ S3C24X0_REG32 EINTFLT2;
+ S3C24X0_REG32 EINTFLT3;
+ S3C24X0_REG32 EINTMASK;
+ S3C24X0_REG32 EINTPEND;
+ S3C24X0_REG32 GSTATUS0;
+ S3C24X0_REG32 GSTATUS1;
+ S3C24X0_REG32 GSTATUS2;
+ S3C24X0_REG32 GSTATUS3;
+ S3C24X0_REG32 GSTATUS4;
+#endif
+};
+
+
+/* RTC (see manual chapter 17) */
+struct s3c24x0_rtc {
+#ifdef __BIG_ENDIAN
+ S3C24X0_REG8 res1[67];
+ S3C24X0_REG8 RTCCON;
+ S3C24X0_REG8 res2[3];
+ S3C24X0_REG8 TICNT;
+ S3C24X0_REG8 res3[11];
+ S3C24X0_REG8 RTCALM;
+ S3C24X0_REG8 res4[3];
+ S3C24X0_REG8 ALMSEC;
+ S3C24X0_REG8 res5[3];
+ S3C24X0_REG8 ALMMIN;
+ S3C24X0_REG8 res6[3];
+ S3C24X0_REG8 ALMHOUR;
+ S3C24X0_REG8 res7[3];
+ S3C24X0_REG8 ALMDATE;
+ S3C24X0_REG8 res8[3];
+ S3C24X0_REG8 ALMMON;
+ S3C24X0_REG8 res9[3];
+ S3C24X0_REG8 ALMYEAR;
+ S3C24X0_REG8 res10[3];
+ S3C24X0_REG8 RTCRST;
+ S3C24X0_REG8 res11[3];
+ S3C24X0_REG8 BCDSEC;
+ S3C24X0_REG8 res12[3];
+ S3C24X0_REG8 BCDMIN;
+ S3C24X0_REG8 res13[3];
+ S3C24X0_REG8 BCDHOUR;
+ S3C24X0_REG8 res14[3];
+ S3C24X0_REG8 BCDDATE;
+ S3C24X0_REG8 res15[3];
+ S3C24X0_REG8 BCDDAY;
+ S3C24X0_REG8 res16[3];
+ S3C24X0_REG8 BCDMON;
+ S3C24X0_REG8 res17[3];
+ S3C24X0_REG8 BCDYEAR;
+#else /* little endian */
+ S3C24X0_REG8 res0[64];
+ S3C24X0_REG8 RTCCON;
+ S3C24X0_REG8 res1[3];
+ S3C24X0_REG8 TICNT;
+ S3C24X0_REG8 res2[11];
+ S3C24X0_REG8 RTCALM;
+ S3C24X0_REG8 res3[3];
+ S3C24X0_REG8 ALMSEC;
+ S3C24X0_REG8 res4[3];
+ S3C24X0_REG8 ALMMIN;
+ S3C24X0_REG8 res5[3];
+ S3C24X0_REG8 ALMHOUR;
+ S3C24X0_REG8 res6[3];
+ S3C24X0_REG8 ALMDATE;
+ S3C24X0_REG8 res7[3];
+ S3C24X0_REG8 ALMMON;
+ S3C24X0_REG8 res8[3];
+ S3C24X0_REG8 ALMYEAR;
+ S3C24X0_REG8 res9[3];
+ S3C24X0_REG8 RTCRST;
+ S3C24X0_REG8 res10[3];
+ S3C24X0_REG8 BCDSEC;
+ S3C24X0_REG8 res11[3];
+ S3C24X0_REG8 BCDMIN;
+ S3C24X0_REG8 res12[3];
+ S3C24X0_REG8 BCDHOUR;
+ S3C24X0_REG8 res13[3];
+ S3C24X0_REG8 BCDDATE;
+ S3C24X0_REG8 res14[3];
+ S3C24X0_REG8 BCDDAY;
+ S3C24X0_REG8 res15[3];
+ S3C24X0_REG8 BCDMON;
+ S3C24X0_REG8 res16[3];
+ S3C24X0_REG8 BCDYEAR;
+ S3C24X0_REG8 res17[3];
+#endif
+};
+
+
+/* ADC (see manual chapter 16) */
+struct s3c2400_adc {
+ S3C24X0_REG32 ADCCON;
+ S3C24X0_REG32 ADCDAT;
+};
+
+
+/* ADC (see manual chapter 16) */
+struct s3c2410_adc {
+ S3C24X0_REG32 ADCCON;
+ S3C24X0_REG32 ADCTSC;
+ S3C24X0_REG32 ADCDLY;
+ S3C24X0_REG32 ADCDAT0;
+ S3C24X0_REG32 ADCDAT1;
+};
+
+
+/* SPI (see manual chapter 22) */
+struct s3c24x0_spi_channel {
+ S3C24X0_REG8 SPCON;
+ S3C24X0_REG8 res1[3];
+ S3C24X0_REG8 SPSTA;
+ S3C24X0_REG8 res2[3];
+ S3C24X0_REG8 SPPIN;
+ S3C24X0_REG8 res3[3];
+ S3C24X0_REG8 SPPRE;
+ S3C24X0_REG8 res4[3];
+ S3C24X0_REG8 SPTDAT;
+ S3C24X0_REG8 res5[3];
+ S3C24X0_REG8 SPRDAT;
+ S3C24X0_REG8 res6[3];
+ S3C24X0_REG8 res7[16];
+};
+
+struct s3c24x0_spi {
+ struct s3c24x0_spi_channel ch[S3C24X0_SPI_CHANNELS];
+};
+
+
+/* MMC INTERFACE (see S3C2400 manual chapter 19) */
+struct s3c2400_mmc {
+#ifdef __BIG_ENDIAN
+ S3C24X0_REG8 res1[3];
+ S3C24X0_REG8 MMCON;
+ S3C24X0_REG8 res2[3];
+ S3C24X0_REG8 MMCRR;
+ S3C24X0_REG8 res3[3];
+ S3C24X0_REG8 MMFCON;
+ S3C24X0_REG8 res4[3];
+ S3C24X0_REG8 MMSTA;
+ S3C24X0_REG16 res5;
+ S3C24X0_REG16 MMFSTA;
+ S3C24X0_REG8 res6[3];
+ S3C24X0_REG8 MMPRE;
+ S3C24X0_REG16 res7;
+ S3C24X0_REG16 MMLEN;
+ S3C24X0_REG8 res8[3];
+ S3C24X0_REG8 MMCR7;
+ S3C24X0_REG32 MMRSP[4];
+ S3C24X0_REG8 res9[3];
+ S3C24X0_REG8 MMCMD0;
+ S3C24X0_REG32 MMCMD1;
+ S3C24X0_REG16 res10;
+ S3C24X0_REG16 MMCR16;
+ S3C24X0_REG8 res11[3];
+ S3C24X0_REG8 MMDAT;
+#else
+ S3C24X0_REG8 MMCON;
+ S3C24X0_REG8 res1[3];
+ S3C24X0_REG8 MMCRR;
+ S3C24X0_REG8 res2[3];
+ S3C24X0_REG8 MMFCON;
+ S3C24X0_REG8 res3[3];
+ S3C24X0_REG8 MMSTA;
+ S3C24X0_REG8 res4[3];
+ S3C24X0_REG16 MMFSTA;
+ S3C24X0_REG16 res5;
+ S3C24X0_REG8 MMPRE;
+ S3C24X0_REG8 res6[3];
+ S3C24X0_REG16 MMLEN;
+ S3C24X0_REG16 res7;
+ S3C24X0_REG8 MMCR7;
+ S3C24X0_REG8 res8[3];
+ S3C24X0_REG32 MMRSP[4];
+ S3C24X0_REG8 MMCMD0;
+ S3C24X0_REG8 res9[3];
+ S3C24X0_REG32 MMCMD1;
+ S3C24X0_REG16 MMCR16;
+ S3C24X0_REG16 res10;
+ S3C24X0_REG8 MMDAT;
+ S3C24X0_REG8 res11[3];
+#endif
+};
+
+
+/* SD INTERFACE (see S3C2410 manual chapter 19) */
+struct s3c2410_sdi {
+ S3C24X0_REG32 SDICON;
+ S3C24X0_REG32 SDIPRE;
+ S3C24X0_REG32 SDICARG;
+ S3C24X0_REG32 SDICCON;
+ S3C24X0_REG32 SDICSTA;
+ S3C24X0_REG32 SDIRSP0;
+ S3C24X0_REG32 SDIRSP1;
+ S3C24X0_REG32 SDIRSP2;
+ S3C24X0_REG32 SDIRSP3;
+ S3C24X0_REG32 SDIDTIMER;
+ S3C24X0_REG32 SDIBSIZE;
+ S3C24X0_REG32 SDIDCON;
+ S3C24X0_REG32 SDIDCNT;
+ S3C24X0_REG32 SDIDSTA;
+ S3C24X0_REG32 SDIFSTA;
+#ifdef __BIG_ENDIAN
+ S3C24X0_REG8 res[3];
+ S3C24X0_REG8 SDIDAT;
+#else
+ S3C24X0_REG8 SDIDAT;
+ S3C24X0_REG8 res[3];
+#endif
+ S3C24X0_REG32 SDIIMSK;
+};
+
+#endif /*__S3C24X0_H__*/
+++ /dev/null
-/*
- * (C) Copyright 2003
- * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/************************************************
- * NAME : s3c2400.h
- * Version : 31.3.2003
- *
- * Based on S3C2400X User's manual Rev 1.1
- ************************************************/
-
-#ifndef __S3C2400_H__
-#define __S3C2400_H__
-
-#define S3C24X0_UART_CHANNELS 2
-#define S3C24X0_SPI_CHANNELS 1
-#define PALETTE (0x14A00400) /* SJS */
-
-enum s3c24x0_uarts_nr {
- S3C24X0_UART0,
- S3C24X0_UART1,
-};
-
-/*S3C2400 device base addresses */
-#define S3C24X0_MEMCTL_BASE 0x14000000
-#define S3C24X0_USB_HOST_BASE 0x14200000
-#define S3C24X0_INTERRUPT_BASE 0x14400000
-#define S3C24X0_DMA_BASE 0x14600000
-#define S3C24X0_CLOCK_POWER_BASE 0x14800000
-#define S3C24X0_LCD_BASE 0x14A00000
-#define S3C24X0_UART_BASE 0x15000000
-#define S3C24X0_TIMER_BASE 0x15100000
-#define S3C24X0_USB_DEVICE_BASE 0x15200140
-#define S3C24X0_WATCHDOG_BASE 0x15300000
-#define S3C24X0_I2C_BASE 0x15400000
-#define S3C24X0_I2S_BASE 0x15508000
-#define S3C24X0_GPIO_BASE 0x15600000
-#define S3C24X0_RTC_BASE 0x15700000
-#define S3C24X0_ADC_BASE 0x15800000
-#define S3C24X0_SPI_BASE 0x15900000
-#define S3C2400_MMC_BASE 0x15A00000
-
-/* include common stuff */
-#include <s3c24x0.h>
-
-
-static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void)
-{
- return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE;
-}
-static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void)
-{
- return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE;
-}
-static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void)
-{
- return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE;
-}
-static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void)
-{
- return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE;
-}
-static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void)
-{
- return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE;
-}
-static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void)
-{
- return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE;
-}
-static inline struct s3c24x0_uart
- *s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n)
-{
- return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000));
-}
-static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void)
-{
- return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE;
-}
-static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void)
-{
- return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE;
-}
-static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void)
-{
- return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE;
-}
-static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void)
-{
- return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE;
-}
-static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void)
-{
- return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE;
-}
-static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void)
-{
- return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE;
-}
-static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void)
-{
- return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE;
-}
-static inline struct s3c2400_adc *s3c2400_get_base_adc(void)
-{
- return (struct s3c2400_adc *)S3C24X0_ADC_BASE;
-}
-static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void)
-{
- return (struct s3c24x0_spi *)S3C24X0_SPI_BASE;
-}
-static inline struct s3c2400_mmc *s3c2400_get_base_mmc(void)
-{
- return (struct s3c2400_mmc *)S3C2400_MMC_BASE;
-}
-
-#endif /*__S3C2400_H__*/
+++ /dev/null
-/*
- * (C) Copyright 2003
- * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/************************************************
- * NAME : s3c2410.h
- * Version : 31.3.2003
- *
- * Based on S3C2410X User's manual Rev 1.1
- ************************************************/
-
-#ifndef __S3C2410_H__
-#define __S3C2410_H__
-
-#define S3C24X0_UART_CHANNELS 3
-#define S3C24X0_SPI_CHANNELS 2
-
-/* S3C2410 only supports 512 Byte HW ECC */
-#define S3C2410_ECCSIZE 512
-#define S3C2410_ECCBYTES 3
-
-enum s3c24x0_uarts_nr {
- S3C24X0_UART0,
- S3C24X0_UART1,
- S3C24X0_UART2
-};
-
-/* S3C2410 device base addresses */
-#define S3C24X0_MEMCTL_BASE 0x48000000
-#define S3C24X0_USB_HOST_BASE 0x49000000
-#define S3C24X0_INTERRUPT_BASE 0x4A000000
-#define S3C24X0_DMA_BASE 0x4B000000
-#define S3C24X0_CLOCK_POWER_BASE 0x4C000000
-#define S3C24X0_LCD_BASE 0x4D000000
-#define S3C2410_NAND_BASE 0x4E000000
-#define S3C24X0_UART_BASE 0x50000000
-#define S3C24X0_TIMER_BASE 0x51000000
-#define S3C24X0_USB_DEVICE_BASE 0x52000140
-#define S3C24X0_WATCHDOG_BASE 0x53000000
-#define S3C24X0_I2C_BASE 0x54000000
-#define S3C24X0_I2S_BASE 0x55000000
-#define S3C24X0_GPIO_BASE 0x56000000
-#define S3C24X0_RTC_BASE 0x57000000
-#define S3C2410_ADC_BASE 0x58000000
-#define S3C24X0_SPI_BASE 0x59000000
-#define S3C2410_SDI_BASE 0x5A000000
-
-
-/* include common stuff */
-#include <s3c24x0.h>
-
-
-static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void)
-{
- return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE;
-}
-static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void)
-{
- return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE;
-}
-static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void)
-{
- return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE;
-}
-static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void)
-{
- return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE;
-}
-static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void)
-{
- return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE;
-}
-static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void)
-{
- return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE;
-}
-static inline struct s3c2410_nand *s3c2410_get_base_nand(void)
-{
- return (struct s3c2410_nand *)S3C2410_NAND_BASE;
-}
-static inline struct s3c24x0_uart
- *s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n)
-{
- return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000));
-}
-static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void)
-{
- return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE;
-}
-static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void)
-{
- return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE;
-}
-static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void)
-{
- return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE;
-}
-static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void)
-{
- return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE;
-}
-static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void)
-{
- return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE;
-}
-static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void)
-{
- return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE;
-}
-static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void)
-{
- return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE;
-}
-static inline struct s3c2410_adc *s3c2410_get_base_adc(void)
-{
- return (struct s3c2410_adc *)S3C2410_ADC_BASE;
-}
-static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void)
-{
- return (struct s3c24x0_spi *)S3C24X0_SPI_BASE;
-}
-static inline struct s3c2410_sdi *s3c2410_get_base_sdi(void)
-{
- return (struct s3c2410_sdi *)S3C2410_SDI_BASE;
-}
-
-#endif /*__S3C2410_H__*/
+++ /dev/null
-/*
- * (C) Copyright 2003
- * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/************************************************
- * NAME : s3c24x0.h
- * Version : 31.3.2003
- *
- * common stuff for SAMSUNG S3C24X0 SoC
- ************************************************/
-
-#ifndef __S3C24X0_H__
-#define __S3C24X0_H__
-
-typedef volatile u8 S3C24X0_REG8;
-typedef volatile u16 S3C24X0_REG16;
-typedef volatile u32 S3C24X0_REG32;
-
-/* Memory controller (see manual chapter 5) */
-struct s3c24x0_memctl {
- S3C24X0_REG32 BWSCON;
- S3C24X0_REG32 BANKCON[8];
- S3C24X0_REG32 REFRESH;
- S3C24X0_REG32 BANKSIZE;
- S3C24X0_REG32 MRSRB6;
- S3C24X0_REG32 MRSRB7;
-};
-
-
-/* USB HOST (see manual chapter 12) */
-struct s3c24x0_usb_host {
- S3C24X0_REG32 HcRevision;
- S3C24X0_REG32 HcControl;
- S3C24X0_REG32 HcCommonStatus;
- S3C24X0_REG32 HcInterruptStatus;
- S3C24X0_REG32 HcInterruptEnable;
- S3C24X0_REG32 HcInterruptDisable;
- S3C24X0_REG32 HcHCCA;
- S3C24X0_REG32 HcPeriodCuttendED;
- S3C24X0_REG32 HcControlHeadED;
- S3C24X0_REG32 HcControlCurrentED;
- S3C24X0_REG32 HcBulkHeadED;
- S3C24X0_REG32 HcBuldCurrentED;
- S3C24X0_REG32 HcDoneHead;
- S3C24X0_REG32 HcRmInterval;
- S3C24X0_REG32 HcFmRemaining;
- S3C24X0_REG32 HcFmNumber;
- S3C24X0_REG32 HcPeriodicStart;
- S3C24X0_REG32 HcLSThreshold;
- S3C24X0_REG32 HcRhDescriptorA;
- S3C24X0_REG32 HcRhDescriptorB;
- S3C24X0_REG32 HcRhStatus;
- S3C24X0_REG32 HcRhPortStatus1;
- S3C24X0_REG32 HcRhPortStatus2;
-};
-
-
-/* INTERRUPT (see manual chapter 14) */
-struct s3c24x0_interrupt {
- S3C24X0_REG32 SRCPND;
- S3C24X0_REG32 INTMOD;
- S3C24X0_REG32 INTMSK;
- S3C24X0_REG32 PRIORITY;
- S3C24X0_REG32 INTPND;
- S3C24X0_REG32 INTOFFSET;
-#ifdef CONFIG_S3C2410
- S3C24X0_REG32 SUBSRCPND;
- S3C24X0_REG32 INTSUBMSK;
-#endif
-};
-
-
-/* DMAS (see manual chapter 8) */
-struct s3c24x0_dma {
- S3C24X0_REG32 DISRC;
-#ifdef CONFIG_S3C2410
- S3C24X0_REG32 DISRCC;
-#endif
- S3C24X0_REG32 DIDST;
-#ifdef CONFIG_S3C2410
- S3C24X0_REG32 DIDSTC;
-#endif
- S3C24X0_REG32 DCON;
- S3C24X0_REG32 DSTAT;
- S3C24X0_REG32 DCSRC;
- S3C24X0_REG32 DCDST;
- S3C24X0_REG32 DMASKTRIG;
-#ifdef CONFIG_S3C2400
- S3C24X0_REG32 res[1];
-#endif
-#ifdef CONFIG_S3C2410
- S3C24X0_REG32 res[7];
-#endif
-};
-
-struct s3c24x0_dmas {
- struct s3c24x0_dma dma[4];
-};
-
-
-/* CLOCK & POWER MANAGEMENT (see S3C2400 manual chapter 6) */
-/* (see S3C2410 manual chapter 7) */
-struct s3c24x0_clock_power {
- S3C24X0_REG32 LOCKTIME;
- S3C24X0_REG32 MPLLCON;
- S3C24X0_REG32 UPLLCON;
- S3C24X0_REG32 CLKCON;
- S3C24X0_REG32 CLKSLOW;
- S3C24X0_REG32 CLKDIVN;
-};
-
-
-/* LCD CONTROLLER (see manual chapter 15) */
-struct s3c24x0_lcd {
- S3C24X0_REG32 LCDCON1;
- S3C24X0_REG32 LCDCON2;
- S3C24X0_REG32 LCDCON3;
- S3C24X0_REG32 LCDCON4;
- S3C24X0_REG32 LCDCON5;
- S3C24X0_REG32 LCDSADDR1;
- S3C24X0_REG32 LCDSADDR2;
- S3C24X0_REG32 LCDSADDR3;
- S3C24X0_REG32 REDLUT;
- S3C24X0_REG32 GREENLUT;
- S3C24X0_REG32 BLUELUT;
- S3C24X0_REG32 res[8];
- S3C24X0_REG32 DITHMODE;
- S3C24X0_REG32 TPAL;
-#ifdef CONFIG_S3C2410
- S3C24X0_REG32 LCDINTPND;
- S3C24X0_REG32 LCDSRCPND;
- S3C24X0_REG32 LCDINTMSK;
- S3C24X0_REG32 LPCSEL;
-#endif
-};
-
-
-/* NAND FLASH (see S3C2410 manual chapter 6) */
-struct s3c2410_nand {
- S3C24X0_REG32 NFCONF;
- S3C24X0_REG32 NFCMD;
- S3C24X0_REG32 NFADDR;
- S3C24X0_REG32 NFDATA;
- S3C24X0_REG32 NFSTAT;
- S3C24X0_REG32 NFECC;
-};
-
-
-/* UART (see manual chapter 11) */
-struct s3c24x0_uart {
- S3C24X0_REG32 ULCON;
- S3C24X0_REG32 UCON;
- S3C24X0_REG32 UFCON;
- S3C24X0_REG32 UMCON;
- S3C24X0_REG32 UTRSTAT;
- S3C24X0_REG32 UERSTAT;
- S3C24X0_REG32 UFSTAT;
- S3C24X0_REG32 UMSTAT;
-#ifdef __BIG_ENDIAN
- S3C24X0_REG8 res1[3];
- S3C24X0_REG8 UTXH;
- S3C24X0_REG8 res2[3];
- S3C24X0_REG8 URXH;
-#else /* Little Endian */
- S3C24X0_REG8 UTXH;
- S3C24X0_REG8 res1[3];
- S3C24X0_REG8 URXH;
- S3C24X0_REG8 res2[3];
-#endif
- S3C24X0_REG32 UBRDIV;
-};
-
-
-/* PWM TIMER (see manual chapter 10) */
-struct s3c24x0_timer {
- S3C24X0_REG32 TCNTB;
- S3C24X0_REG32 TCMPB;
- S3C24X0_REG32 TCNTO;
-};
-
-struct s3c24x0_timers {
- S3C24X0_REG32 TCFG0;
- S3C24X0_REG32 TCFG1;
- S3C24X0_REG32 TCON;
- struct s3c24x0_timer ch[4];
- S3C24X0_REG32 TCNTB4;
- S3C24X0_REG32 TCNTO4;
-};
-
-
-/* USB DEVICE (see manual chapter 13) */
-struct s3c24x0_usb_dev_fifos {
-#ifdef __BIG_ENDIAN
- S3C24X0_REG8 res[3];
- S3C24X0_REG8 EP_FIFO_REG;
-#else /* little endian */
- S3C24X0_REG8 EP_FIFO_REG;
- S3C24X0_REG8 res[3];
-#endif
-};
-
-struct s3c24x0_usb_dev_dmas {
-#ifdef __BIG_ENDIAN
- S3C24X0_REG8 res1[3];
- S3C24X0_REG8 EP_DMA_CON;
- S3C24X0_REG8 res2[3];
- S3C24X0_REG8 EP_DMA_UNIT;
- S3C24X0_REG8 res3[3];
- S3C24X0_REG8 EP_DMA_FIFO;
- S3C24X0_REG8 res4[3];
- S3C24X0_REG8 EP_DMA_TTC_L;
- S3C24X0_REG8 res5[3];
- S3C24X0_REG8 EP_DMA_TTC_M;
- S3C24X0_REG8 res6[3];
- S3C24X0_REG8 EP_DMA_TTC_H;
-#else /* little endian */
- S3C24X0_REG8 EP_DMA_CON;
- S3C24X0_REG8 res1[3];
- S3C24X0_REG8 EP_DMA_UNIT;
- S3C24X0_REG8 res2[3];
- S3C24X0_REG8 EP_DMA_FIFO;
- S3C24X0_REG8 res3[3];
- S3C24X0_REG8 EP_DMA_TTC_L;
- S3C24X0_REG8 res4[3];
- S3C24X0_REG8 EP_DMA_TTC_M;
- S3C24X0_REG8 res5[3];
- S3C24X0_REG8 EP_DMA_TTC_H;
- S3C24X0_REG8 res6[3];
-#endif
-};
-
-struct s3c24x0_usb_device {
-#ifdef __BIG_ENDIAN
- S3C24X0_REG8 res1[3];
- S3C24X0_REG8 FUNC_ADDR_REG;
- S3C24X0_REG8 res2[3];
- S3C24X0_REG8 PWR_REG;
- S3C24X0_REG8 res3[3];
- S3C24X0_REG8 EP_INT_REG;
- S3C24X0_REG8 res4[15];
- S3C24X0_REG8 USB_INT_REG;
- S3C24X0_REG8 res5[3];
- S3C24X0_REG8 EP_INT_EN_REG;
- S3C24X0_REG8 res6[15];
- S3C24X0_REG8 USB_INT_EN_REG;
- S3C24X0_REG8 res7[3];
- S3C24X0_REG8 FRAME_NUM1_REG;
- S3C24X0_REG8 res8[3];
- S3C24X0_REG8 FRAME_NUM2_REG;
- S3C24X0_REG8 res9[3];
- S3C24X0_REG8 INDEX_REG;
- S3C24X0_REG8 res10[7];
- S3C24X0_REG8 MAXP_REG;
- S3C24X0_REG8 res11[3];
- S3C24X0_REG8 EP0_CSR_IN_CSR1_REG;
- S3C24X0_REG8 res12[3];
- S3C24X0_REG8 IN_CSR2_REG;
- S3C24X0_REG8 res13[7];
- S3C24X0_REG8 OUT_CSR1_REG;
- S3C24X0_REG8 res14[3];
- S3C24X0_REG8 OUT_CSR2_REG;
- S3C24X0_REG8 res15[3];
- S3C24X0_REG8 OUT_FIFO_CNT1_REG;
- S3C24X0_REG8 res16[3];
- S3C24X0_REG8 OUT_FIFO_CNT2_REG;
-#else /* little endian */
- S3C24X0_REG8 FUNC_ADDR_REG;
- S3C24X0_REG8 res1[3];
- S3C24X0_REG8 PWR_REG;
- S3C24X0_REG8 res2[3];
- S3C24X0_REG8 EP_INT_REG;
- S3C24X0_REG8 res3[15];
- S3C24X0_REG8 USB_INT_REG;
- S3C24X0_REG8 res4[3];
- S3C24X0_REG8 EP_INT_EN_REG;
- S3C24X0_REG8 res5[15];
- S3C24X0_REG8 USB_INT_EN_REG;
- S3C24X0_REG8 res6[3];
- S3C24X0_REG8 FRAME_NUM1_REG;
- S3C24X0_REG8 res7[3];
- S3C24X0_REG8 FRAME_NUM2_REG;
- S3C24X0_REG8 res8[3];
- S3C24X0_REG8 INDEX_REG;
- S3C24X0_REG8 res9[7];
- S3C24X0_REG8 MAXP_REG;
- S3C24X0_REG8 res10[7];
- S3C24X0_REG8 EP0_CSR_IN_CSR1_REG;
- S3C24X0_REG8 res11[3];
- S3C24X0_REG8 IN_CSR2_REG;
- S3C24X0_REG8 res12[3];
- S3C24X0_REG8 OUT_CSR1_REG;
- S3C24X0_REG8 res13[7];
- S3C24X0_REG8 OUT_CSR2_REG;
- S3C24X0_REG8 res14[3];
- S3C24X0_REG8 OUT_FIFO_CNT1_REG;
- S3C24X0_REG8 res15[3];
- S3C24X0_REG8 OUT_FIFO_CNT2_REG;
- S3C24X0_REG8 res16[3];
-#endif /* __BIG_ENDIAN */
- struct s3c24x0_usb_dev_fifos fifo[5];
- struct s3c24x0_usb_dev_dmas dma[5];
-};
-
-
-/* WATCH DOG TIMER (see manual chapter 18) */
-struct s3c24x0_watchdog {
- S3C24X0_REG32 WTCON;
- S3C24X0_REG32 WTDAT;
- S3C24X0_REG32 WTCNT;
-};
-
-
-/* IIC (see manual chapter 20) */
-struct s3c24x0_i2c {
- S3C24X0_REG32 IICCON;
- S3C24X0_REG32 IICSTAT;
- S3C24X0_REG32 IICADD;
- S3C24X0_REG32 IICDS;
-};
-
-
-/* IIS (see manual chapter 21) */
-struct s3c24x0_i2s {
-#ifdef __BIG_ENDIAN
- S3C24X0_REG16 res1;
- S3C24X0_REG16 IISCON;
- S3C24X0_REG16 res2;
- S3C24X0_REG16 IISMOD;
- S3C24X0_REG16 res3;
- S3C24X0_REG16 IISPSR;
- S3C24X0_REG16 res4;
- S3C24X0_REG16 IISFCON;
- S3C24X0_REG16 res5;
- S3C24X0_REG16 IISFIFO;
-#else /* little endian */
- S3C24X0_REG16 IISCON;
- S3C24X0_REG16 res1;
- S3C24X0_REG16 IISMOD;
- S3C24X0_REG16 res2;
- S3C24X0_REG16 IISPSR;
- S3C24X0_REG16 res3;
- S3C24X0_REG16 IISFCON;
- S3C24X0_REG16 res4;
- S3C24X0_REG16 IISFIFO;
- S3C24X0_REG16 res5;
-#endif
-};
-
-
-/* I/O PORT (see manual chapter 9) */
-struct s3c24x0_gpio {
-#ifdef CONFIG_S3C2400
- S3C24X0_REG32 PACON;
- S3C24X0_REG32 PADAT;
-
- S3C24X0_REG32 PBCON;
- S3C24X0_REG32 PBDAT;
- S3C24X0_REG32 PBUP;
-
- S3C24X0_REG32 PCCON;
- S3C24X0_REG32 PCDAT;
- S3C24X0_REG32 PCUP;
-
- S3C24X0_REG32 PDCON;
- S3C24X0_REG32 PDDAT;
- S3C24X0_REG32 PDUP;
-
- S3C24X0_REG32 PECON;
- S3C24X0_REG32 PEDAT;
- S3C24X0_REG32 PEUP;
-
- S3C24X0_REG32 PFCON;
- S3C24X0_REG32 PFDAT;
- S3C24X0_REG32 PFUP;
-
- S3C24X0_REG32 PGCON;
- S3C24X0_REG32 PGDAT;
- S3C24X0_REG32 PGUP;
-
- S3C24X0_REG32 OPENCR;
-
- S3C24X0_REG32 MISCCR;
- S3C24X0_REG32 EXTINT;
-#endif
-#ifdef CONFIG_S3C2410
- S3C24X0_REG32 GPACON;
- S3C24X0_REG32 GPADAT;
- S3C24X0_REG32 res1[2];
- S3C24X0_REG32 GPBCON;
- S3C24X0_REG32 GPBDAT;
- S3C24X0_REG32 GPBUP;
- S3C24X0_REG32 res2;
- S3C24X0_REG32 GPCCON;
- S3C24X0_REG32 GPCDAT;
- S3C24X0_REG32 GPCUP;
- S3C24X0_REG32 res3;
- S3C24X0_REG32 GPDCON;
- S3C24X0_REG32 GPDDAT;
- S3C24X0_REG32 GPDUP;
- S3C24X0_REG32 res4;
- S3C24X0_REG32 GPECON;
- S3C24X0_REG32 GPEDAT;
- S3C24X0_REG32 GPEUP;
- S3C24X0_REG32 res5;
- S3C24X0_REG32 GPFCON;
- S3C24X0_REG32 GPFDAT;
- S3C24X0_REG32 GPFUP;
- S3C24X0_REG32 res6;
- S3C24X0_REG32 GPGCON;
- S3C24X0_REG32 GPGDAT;
- S3C24X0_REG32 GPGUP;
- S3C24X0_REG32 res7;
- S3C24X0_REG32 GPHCON;
- S3C24X0_REG32 GPHDAT;
- S3C24X0_REG32 GPHUP;
- S3C24X0_REG32 res8;
-
- S3C24X0_REG32 MISCCR;
- S3C24X0_REG32 DCLKCON;
- S3C24X0_REG32 EXTINT0;
- S3C24X0_REG32 EXTINT1;
- S3C24X0_REG32 EXTINT2;
- S3C24X0_REG32 EINTFLT0;
- S3C24X0_REG32 EINTFLT1;
- S3C24X0_REG32 EINTFLT2;
- S3C24X0_REG32 EINTFLT3;
- S3C24X0_REG32 EINTMASK;
- S3C24X0_REG32 EINTPEND;
- S3C24X0_REG32 GSTATUS0;
- S3C24X0_REG32 GSTATUS1;
- S3C24X0_REG32 GSTATUS2;
- S3C24X0_REG32 GSTATUS3;
- S3C24X0_REG32 GSTATUS4;
-#endif
-};
-
-
-/* RTC (see manual chapter 17) */
-struct s3c24x0_rtc {
-#ifdef __BIG_ENDIAN
- S3C24X0_REG8 res1[67];
- S3C24X0_REG8 RTCCON;
- S3C24X0_REG8 res2[3];
- S3C24X0_REG8 TICNT;
- S3C24X0_REG8 res3[11];
- S3C24X0_REG8 RTCALM;
- S3C24X0_REG8 res4[3];
- S3C24X0_REG8 ALMSEC;
- S3C24X0_REG8 res5[3];
- S3C24X0_REG8 ALMMIN;
- S3C24X0_REG8 res6[3];
- S3C24X0_REG8 ALMHOUR;
- S3C24X0_REG8 res7[3];
- S3C24X0_REG8 ALMDATE;
- S3C24X0_REG8 res8[3];
- S3C24X0_REG8 ALMMON;
- S3C24X0_REG8 res9[3];
- S3C24X0_REG8 ALMYEAR;
- S3C24X0_REG8 res10[3];
- S3C24X0_REG8 RTCRST;
- S3C24X0_REG8 res11[3];
- S3C24X0_REG8 BCDSEC;
- S3C24X0_REG8 res12[3];
- S3C24X0_REG8 BCDMIN;
- S3C24X0_REG8 res13[3];
- S3C24X0_REG8 BCDHOUR;
- S3C24X0_REG8 res14[3];
- S3C24X0_REG8 BCDDATE;
- S3C24X0_REG8 res15[3];
- S3C24X0_REG8 BCDDAY;
- S3C24X0_REG8 res16[3];
- S3C24X0_REG8 BCDMON;
- S3C24X0_REG8 res17[3];
- S3C24X0_REG8 BCDYEAR;
-#else /* little endian */
- S3C24X0_REG8 res0[64];
- S3C24X0_REG8 RTCCON;
- S3C24X0_REG8 res1[3];
- S3C24X0_REG8 TICNT;
- S3C24X0_REG8 res2[11];
- S3C24X0_REG8 RTCALM;
- S3C24X0_REG8 res3[3];
- S3C24X0_REG8 ALMSEC;
- S3C24X0_REG8 res4[3];
- S3C24X0_REG8 ALMMIN;
- S3C24X0_REG8 res5[3];
- S3C24X0_REG8 ALMHOUR;
- S3C24X0_REG8 res6[3];
- S3C24X0_REG8 ALMDATE;
- S3C24X0_REG8 res7[3];
- S3C24X0_REG8 ALMMON;
- S3C24X0_REG8 res8[3];
- S3C24X0_REG8 ALMYEAR;
- S3C24X0_REG8 res9[3];
- S3C24X0_REG8 RTCRST;
- S3C24X0_REG8 res10[3];
- S3C24X0_REG8 BCDSEC;
- S3C24X0_REG8 res11[3];
- S3C24X0_REG8 BCDMIN;
- S3C24X0_REG8 res12[3];
- S3C24X0_REG8 BCDHOUR;
- S3C24X0_REG8 res13[3];
- S3C24X0_REG8 BCDDATE;
- S3C24X0_REG8 res14[3];
- S3C24X0_REG8 BCDDAY;
- S3C24X0_REG8 res15[3];
- S3C24X0_REG8 BCDMON;
- S3C24X0_REG8 res16[3];
- S3C24X0_REG8 BCDYEAR;
- S3C24X0_REG8 res17[3];
-#endif
-};
-
-
-/* ADC (see manual chapter 16) */
-struct s3c2400_adc {
- S3C24X0_REG32 ADCCON;
- S3C24X0_REG32 ADCDAT;
-};
-
-
-/* ADC (see manual chapter 16) */
-struct s3c2410_adc {
- S3C24X0_REG32 ADCCON;
- S3C24X0_REG32 ADCTSC;
- S3C24X0_REG32 ADCDLY;
- S3C24X0_REG32 ADCDAT0;
- S3C24X0_REG32 ADCDAT1;
-};
-
-
-/* SPI (see manual chapter 22) */
-struct s3c24x0_spi_channel {
- S3C24X0_REG8 SPCON;
- S3C24X0_REG8 res1[3];
- S3C24X0_REG8 SPSTA;
- S3C24X0_REG8 res2[3];
- S3C24X0_REG8 SPPIN;
- S3C24X0_REG8 res3[3];
- S3C24X0_REG8 SPPRE;
- S3C24X0_REG8 res4[3];
- S3C24X0_REG8 SPTDAT;
- S3C24X0_REG8 res5[3];
- S3C24X0_REG8 SPRDAT;
- S3C24X0_REG8 res6[3];
- S3C24X0_REG8 res7[16];
-};
-
-struct s3c24x0_spi {
- struct s3c24x0_spi_channel ch[S3C24X0_SPI_CHANNELS];
-};
-
-
-/* MMC INTERFACE (see S3C2400 manual chapter 19) */
-struct s3c2400_mmc {
-#ifdef __BIG_ENDIAN
- S3C24X0_REG8 res1[3];
- S3C24X0_REG8 MMCON;
- S3C24X0_REG8 res2[3];
- S3C24X0_REG8 MMCRR;
- S3C24X0_REG8 res3[3];
- S3C24X0_REG8 MMFCON;
- S3C24X0_REG8 res4[3];
- S3C24X0_REG8 MMSTA;
- S3C24X0_REG16 res5;
- S3C24X0_REG16 MMFSTA;
- S3C24X0_REG8 res6[3];
- S3C24X0_REG8 MMPRE;
- S3C24X0_REG16 res7;
- S3C24X0_REG16 MMLEN;
- S3C24X0_REG8 res8[3];
- S3C24X0_REG8 MMCR7;
- S3C24X0_REG32 MMRSP[4];
- S3C24X0_REG8 res9[3];
- S3C24X0_REG8 MMCMD0;
- S3C24X0_REG32 MMCMD1;
- S3C24X0_REG16 res10;
- S3C24X0_REG16 MMCR16;
- S3C24X0_REG8 res11[3];
- S3C24X0_REG8 MMDAT;
-#else
- S3C24X0_REG8 MMCON;
- S3C24X0_REG8 res1[3];
- S3C24X0_REG8 MMCRR;
- S3C24X0_REG8 res2[3];
- S3C24X0_REG8 MMFCON;
- S3C24X0_REG8 res3[3];
- S3C24X0_REG8 MMSTA;
- S3C24X0_REG8 res4[3];
- S3C24X0_REG16 MMFSTA;
- S3C24X0_REG16 res5;
- S3C24X0_REG8 MMPRE;
- S3C24X0_REG8 res6[3];
- S3C24X0_REG16 MMLEN;
- S3C24X0_REG16 res7;
- S3C24X0_REG8 MMCR7;
- S3C24X0_REG8 res8[3];
- S3C24X0_REG32 MMRSP[4];
- S3C24X0_REG8 MMCMD0;
- S3C24X0_REG8 res9[3];
- S3C24X0_REG32 MMCMD1;
- S3C24X0_REG16 MMCR16;
- S3C24X0_REG16 res10;
- S3C24X0_REG8 MMDAT;
- S3C24X0_REG8 res11[3];
-#endif
-};
-
-
-/* SD INTERFACE (see S3C2410 manual chapter 19) */
-struct s3c2410_sdi {
- S3C24X0_REG32 SDICON;
- S3C24X0_REG32 SDIPRE;
- S3C24X0_REG32 SDICARG;
- S3C24X0_REG32 SDICCON;
- S3C24X0_REG32 SDICSTA;
- S3C24X0_REG32 SDIRSP0;
- S3C24X0_REG32 SDIRSP1;
- S3C24X0_REG32 SDIRSP2;
- S3C24X0_REG32 SDIRSP3;
- S3C24X0_REG32 SDIDTIMER;
- S3C24X0_REG32 SDIBSIZE;
- S3C24X0_REG32 SDIDCON;
- S3C24X0_REG32 SDIDCNT;
- S3C24X0_REG32 SDIDSTA;
- S3C24X0_REG32 SDIFSTA;
-#ifdef __BIG_ENDIAN
- S3C24X0_REG8 res[3];
- S3C24X0_REG8 SDIDAT;
-#else
- S3C24X0_REG8 SDIDAT;
- S3C24X0_REG8 res[3];
-#endif
- S3C24X0_REG32 SDIIMSK;
-};
-
-#endif /*__S3C24X0_H__*/
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