port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP;
/* Restart the transmitter if disabled */
- if (!(inl(EDTRR(port)) & EDTRR_TRNS))
- outl(EDTRR_TRNS, EDTRR(port));
+ if (!(sh_eth_read(eth, EDTRR) & EDTRR_TRNS))
+ sh_eth_write(eth, EDTRR_TRNS, EDTRR);
/* Wait until packet is transmitted */
timeout = TIMEOUT_CNT;
}
/* Restart the receiver if disabled */
- if (!(inl(EDRRR(port)) & EDRRR_R))
- outl(EDRRR_R, EDRRR(port));
+ if (!(sh_eth_read(eth, EDRRR) & EDRRR_R))
+ sh_eth_write(eth, EDRRR_R, EDRRR);
return len;
}
static int sh_eth_reset(struct sh_eth_dev *eth)
{
- int port = eth->port;
#if defined(SH_ETH_TYPE_GETHER)
int ret = 0, i;
/* Start e-dmac transmitter and receiver */
- outl(EDSR_ENALL, EDSR(port));
+ sh_eth_write(eth, EDSR_ENALL, EDSR);
/* Perform a software reset and wait for it to complete */
- outl(EDMR_SRST, EDMR(port));
+ sh_eth_write(eth, EDMR_SRST, EDMR);
for (i = 0; i < TIMEOUT_CNT ; i++) {
- if (!(inl(EDMR(port)) & EDMR_SRST))
+ if (!(sh_eth_read(eth, EDMR) & EDMR_SRST))
break;
udelay(1000);
}
return ret;
#else
- outl(inl(EDMR(port)) | EDMR_SRST, EDMR(port));
+ sh_eth_write(eth, sh_eth_read(eth, EDMR) | EDMR_SRST, EDMR);
udelay(3000);
- outl(inl(EDMR(port)) & ~EDMR_SRST, EDMR(port));
+ sh_eth_write(eth, sh_eth_read(eth, EDMR) & ~EDMR_SRST, EDMR);
return 0;
#endif
/* Point the controller to the tx descriptor list. Must use physical
addresses */
- outl(ADDR_TO_PHY(port_info->tx_desc_base), TDLAR(port));
+ sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR);
#if defined(SH_ETH_TYPE_GETHER)
- outl(ADDR_TO_PHY(port_info->tx_desc_base), TDFAR(port));
- outl(ADDR_TO_PHY(cur_tx_desc), TDFXR(port));
- outl(0x01, TDFFR(port));/* Last discriptor bit */
+ sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR);
+ sh_eth_write(eth, ADDR_TO_PHY(cur_tx_desc), TDFXR);
+ sh_eth_write(eth, 0x01, TDFFR);/* Last discriptor bit */
#endif
err:
cur_rx_desc->rd0 |= RD_RDLE;
/* Point the controller to the rx descriptor list */
- outl(ADDR_TO_PHY(port_info->rx_desc_base), RDLAR(port));
+ sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR);
#if defined(SH_ETH_TYPE_GETHER)
- outl(ADDR_TO_PHY(port_info->rx_desc_base), RDFAR(port));
- outl(ADDR_TO_PHY(cur_rx_desc), RDFXR(port));
- outl(RDFFR_RDLF, RDFFR(port));
+ sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR);
+ sh_eth_write(eth, ADDR_TO_PHY(cur_rx_desc), RDFXR);
+ sh_eth_write(eth, RDFFR_RDLF, RDFFR);
#endif
return ret;
struct phy_device *phy;
/* Configure e-dmac registers */
- outl((inl(EDMR(port)) & ~EMDR_DESC_R) | EDMR_EL, EDMR(port));
- outl(0, EESIPR(port));
- outl(0, TRSCER(port));
- outl(0, TFTR(port));
- outl((FIFO_SIZE_T | FIFO_SIZE_R), FDR(port));
- outl(RMCR_RST, RMCR(port));
+ sh_eth_write(eth, (sh_eth_read(eth, EDMR) & ~EMDR_DESC_R) | EDMR_EL,
+ EDMR);
+ sh_eth_write(eth, 0, EESIPR);
+ sh_eth_write(eth, 0, TRSCER);
+ sh_eth_write(eth, 0, TFTR);
+ sh_eth_write(eth, (FIFO_SIZE_T | FIFO_SIZE_R), FDR);
+ sh_eth_write(eth, RMCR_RST, RMCR);
#if defined(SH_ETH_TYPE_GETHER)
- outl(0, RPADIR(port));
+ sh_eth_write(eth, 0, RPADIR);
#endif
- outl((FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR(port));
+ sh_eth_write(eth, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR);
/* Configure e-mac registers */
- outl(0, ECSIPR(port));
+ sh_eth_write(eth, 0, ECSIPR);
/* Set Mac address */
val = dev->enetaddr[0] << 24 | dev->enetaddr[1] << 16 |
dev->enetaddr[2] << 8 | dev->enetaddr[3];
- outl(val, MAHR(port));
+ sh_eth_write(eth, val, MAHR);
val = dev->enetaddr[4] << 8 | dev->enetaddr[5];
- outl(val, MALR(port));
+ sh_eth_write(eth, val, MALR);
- outl(RFLR_RFL_MIN, RFLR(port));
+ sh_eth_write(eth, RFLR_RFL_MIN, RFLR);
#if defined(SH_ETH_TYPE_GETHER)
- outl(0, PIPR(port));
- outl(APR_AP, APR(port));
- outl(MPR_MP, MPR(port));
- outl(TPAUSER_TPAUSE, TPAUSER(port));
+ sh_eth_write(eth, 0, PIPR);
+ sh_eth_write(eth, APR_AP, APR);
+ sh_eth_write(eth, MPR_MP, MPR);
+ sh_eth_write(eth, TPAUSER_TPAUSE, TPAUSER);
#endif
#if defined(CONFIG_CPU_SH7734)
- outl(CONFIG_SH_ETHER_SH7734_MII, RMII_MII(port));
+ sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
#endif
/* Configure phy */
ret = sh_eth_phy_config(eth);
if (phy->speed == 100) {
printf(SHETHER_NAME ": 100Base/");
#if defined(SH_ETH_TYPE_GETHER)
- outl(GECMR_100B, GECMR(port));
+ sh_eth_write(eth, GECMR_100B, GECMR);
#elif defined(CONFIG_CPU_SH7757)
- outl(1, RTRATE(port));
+ sh_eth_write(eth, 1, RTRATE);
#elif defined(CONFIG_CPU_SH7724)
val = ECMR_RTM;
#endif
} else if (phy->speed == 10) {
printf(SHETHER_NAME ": 10Base/");
#if defined(SH_ETH_TYPE_GETHER)
- outl(GECMR_10B, GECMR(port));
+ sh_eth_write(eth, GECMR_10B, GECMR);
#elif defined(CONFIG_CPU_SH7757)
- outl(0, RTRATE(port));
+ sh_eth_write(eth, 0, RTRATE);
#endif
}
#if defined(SH_ETH_TYPE_GETHER)
else if (phy->speed == 1000) {
printf(SHETHER_NAME ": 1000Base/");
- outl(GECMR_1000B, GECMR(port));
+ sh_eth_write(eth, GECMR_1000B, GECMR);
}
#endif
/* Check if full duplex mode is supported by the phy */
if (phy->duplex) {
printf("Full\n");
- outl(val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM), ECMR(port));
+ sh_eth_write(eth, val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM),
+ ECMR);
} else {
printf("Half\n");
- outl(val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR(port));
+ sh_eth_write(eth, val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR);
}
return ret;
* Enable the e-dmac receiver only. The transmitter will be enabled when
* we have something to transmit
*/
- outl(EDRRR_R, EDRRR(eth->port));
+ sh_eth_write(eth, EDRRR_R, EDRRR);
}
static void sh_eth_stop(struct sh_eth_dev *eth)
{
- outl(~EDRRR_R, EDRRR(eth->port));
+ sh_eth_write(eth, ~EDRRR_R, EDRRR);
}
int sh_eth_init(struct eth_device *dev, bd_t *bd)
static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
{
struct sh_eth_dev *eth = bus->priv;
- int port = eth->port;
- outl(inl(PIR(port)) | PIR_MMD, PIR(port));
+ sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MMD, PIR);
return 0;
}
static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
{
struct sh_eth_dev *eth = bus->priv;
- int port = eth->port;
- outl(inl(PIR(port)) & ~PIR_MMD, PIR(port));
+ sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MMD, PIR);
return 0;
}
static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
{
struct sh_eth_dev *eth = bus->priv;
- int port = eth->port;
if (v)
- outl(inl(PIR(port)) | PIR_MDO, PIR(port));
+ sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MDO, PIR);
else
- outl(inl(PIR(port)) & ~PIR_MDO, PIR(port));
+ sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDO, PIR);
return 0;
}
static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
{
struct sh_eth_dev *eth = bus->priv;
- int port = eth->port;
- *v = (inl(PIR(port)) & PIR_MDI) >> 3;
+ *v = (sh_eth_read(eth, PIR) & PIR_MDI) >> 3;
return 0;
}
static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
{
struct sh_eth_dev *eth = bus->priv;
- int port = eth->port;
if (v)
- outl(inl(PIR(port)) | PIR_MDC, PIR(port));
+ sh_eth_write(eth, sh_eth_read(eth, PIR) | PIR_MDC, PIR);
else
- outl(inl(PIR(port)) & ~PIR_MDC, PIR(port));
+ sh_eth_write(eth, sh_eth_read(eth, PIR) & ~PIR_MDC, PIR);
return 0;
}
struct sh_eth_info port_info[MAX_PORT_NUM];
};
+/* from linux/drivers/net/ethernet/renesas/sh_eth.h */
+enum {
+ /* E-DMAC registers */
+ EDSR = 0,
+ EDMR,
+ EDTRR,
+ EDRRR,
+ EESR,
+ EESIPR,
+ TDLAR,
+ TDFAR,
+ TDFXR,
+ TDFFR,
+ RDLAR,
+ RDFAR,
+ RDFXR,
+ RDFFR,
+ TRSCER,
+ RMFCR,
+ TFTR,
+ FDR,
+ RMCR,
+ EDOCR,
+ TFUCR,
+ RFOCR,
+ FCFTR,
+ RPADIR,
+ TRIMD,
+ RBWAR,
+ TBRAR,
+
+ /* Ether registers */
+ ECMR,
+ ECSR,
+ ECSIPR,
+ PIR,
+ PSR,
+ RDMLR,
+ PIPR,
+ RFLR,
+ IPGR,
+ APR,
+ MPR,
+ PFTCR,
+ PFRCR,
+ RFCR,
+ RFCF,
+ TPAUSER,
+ TPAUSECR,
+ BCFR,
+ BCFRR,
+ GECMR,
+ BCULR,
+ MAHR,
+ MALR,
+ TROCR,
+ CDCR,
+ LCCR,
+ CNDCR,
+ CEFCR,
+ FRECR,
+ TSFRCR,
+ TLFRCR,
+ CERCR,
+ CEECR,
+ MAFCR,
+ RTRATE,
+ CSMR,
+ RMII_MII,
+
+ /* This value must be written at last. */
+ SH_ETH_MAX_REGISTER_OFFSET,
+};
+
+static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
+ [EDSR] = 0x0000,
+ [EDMR] = 0x0400,
+ [EDTRR] = 0x0408,
+ [EDRRR] = 0x0410,
+ [EESR] = 0x0428,
+ [EESIPR] = 0x0430,
+ [TDLAR] = 0x0010,
+ [TDFAR] = 0x0014,
+ [TDFXR] = 0x0018,
+ [TDFFR] = 0x001c,
+ [RDLAR] = 0x0030,
+ [RDFAR] = 0x0034,
+ [RDFXR] = 0x0038,
+ [RDFFR] = 0x003c,
+ [TRSCER] = 0x0438,
+ [RMFCR] = 0x0440,
+ [TFTR] = 0x0448,
+ [FDR] = 0x0450,
+ [RMCR] = 0x0458,
+ [RPADIR] = 0x0460,
+ [FCFTR] = 0x0468,
+ [CSMR] = 0x04E4,
+
+ [ECMR] = 0x0500,
+ [ECSR] = 0x0510,
+ [ECSIPR] = 0x0518,
+ [PIR] = 0x0520,
+ [PSR] = 0x0528,
+ [PIPR] = 0x052c,
+ [RFLR] = 0x0508,
+ [APR] = 0x0554,
+ [MPR] = 0x0558,
+ [PFTCR] = 0x055c,
+ [PFRCR] = 0x0560,
+ [TPAUSER] = 0x0564,
+ [GECMR] = 0x05b0,
+ [BCULR] = 0x05b4,
+ [MAHR] = 0x05c0,
+ [MALR] = 0x05c8,
+ [TROCR] = 0x0700,
+ [CDCR] = 0x0708,
+ [LCCR] = 0x0710,
+ [CEFCR] = 0x0740,
+ [FRECR] = 0x0748,
+ [TSFRCR] = 0x0750,
+ [TLFRCR] = 0x0758,
+ [RFCR] = 0x0760,
+ [CERCR] = 0x0768,
+ [CEECR] = 0x0770,
+ [MAFCR] = 0x0778,
+ [RMII_MII] = 0x0790,
+};
+
+static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
+ [ECMR] = 0x0100,
+ [RFLR] = 0x0108,
+ [ECSR] = 0x0110,
+ [ECSIPR] = 0x0118,
+ [PIR] = 0x0120,
+ [PSR] = 0x0128,
+ [RDMLR] = 0x0140,
+ [IPGR] = 0x0150,
+ [APR] = 0x0154,
+ [MPR] = 0x0158,
+ [TPAUSER] = 0x0164,
+ [RFCF] = 0x0160,
+ [TPAUSECR] = 0x0168,
+ [BCFRR] = 0x016c,
+ [MAHR] = 0x01c0,
+ [MALR] = 0x01c8,
+ [TROCR] = 0x01d0,
+ [CDCR] = 0x01d4,
+ [LCCR] = 0x01d8,
+ [CNDCR] = 0x01dc,
+ [CEFCR] = 0x01e4,
+ [FRECR] = 0x01e8,
+ [TSFRCR] = 0x01ec,
+ [TLFRCR] = 0x01f0,
+ [RFCR] = 0x01f4,
+ [MAFCR] = 0x01f8,
+ [RTRATE] = 0x01fc,
+
+ [EDMR] = 0x0000,
+ [EDTRR] = 0x0008,
+ [EDRRR] = 0x0010,
+ [TDLAR] = 0x0018,
+ [RDLAR] = 0x0020,
+ [EESR] = 0x0028,
+ [EESIPR] = 0x0030,
+ [TRSCER] = 0x0038,
+ [RMFCR] = 0x0040,
+ [TFTR] = 0x0048,
+ [FDR] = 0x0050,
+ [RMCR] = 0x0058,
+ [TFUCR] = 0x0064,
+ [RFOCR] = 0x0068,
+ [FCFTR] = 0x0070,
+ [RPADIR] = 0x0078,
+ [TRIMD] = 0x007c,
+ [RBWAR] = 0x00c8,
+ [RDFAR] = 0x00cc,
+ [TBRAR] = 0x00d4,
+ [TDFAR] = 0x00d8,
+};
+
/* Register Address */
-#ifdef CONFIG_CPU_SH7763
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
#define SH_ETH_TYPE_GETHER
#define BASE_IO_ADDR 0xfee00000
-
-#define EDSR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0000)
-
-#define TDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0010)
-#define TDFAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0014)
-#define TDFXR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0018)
-#define TDFFR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x001c)
-
-#define RDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0030)
-#define RDFAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0034)
-#define RDFXR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0038)
-#define RDFFR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x003c)
-
-#define EDMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0400)
-#define EDTRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0408)
-#define EDRRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0410)
-#define EESR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0428)
-#define EESIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0430)
-#define TRSCER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0438)
-#define TFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0448)
-#define FDR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0450)
-#define RMCR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0458)
-#define RPADIR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0460)
-#define FCFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0468)
-#define ECMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0500)
-#define RFLR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0508)
-#define ECSIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0518)
-#define PIR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0520)
-#define PIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x052c)
-#define APR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0554)
-#define MPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0558)
-#define TPAUSER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0564)
-#define GECMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x05b0)
-#define MALR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x05c8)
-#define MAHR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x05c0)
-
#elif defined(CONFIG_CPU_SH7757)
#define SH_ETH_TYPE_ETHER
#define BASE_IO_ADDR 0xfef00000
-
-#define TDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0018)
-#define RDLAR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0020)
-
-#define EDMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0000)
-#define EDTRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0008)
-#define EDRRR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0010)
-#define EESR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0028)
-#define EESIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0030)
-#define TRSCER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0038)
-#define TFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0048)
-#define FDR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0050)
-#define RMCR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0058)
-#define FCFTR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0070)
-#define ECMR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0100)
-#define RFLR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0108)
-#define ECSIPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0118)
-#define PIR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0120)
-#define APR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0154)
-#define MPR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0158)
-#define TPAUSER(port) (BASE_IO_ADDR + 0x800 * (port) + 0x0164)
-#define MAHR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x01c0)
-#define MALR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x01c8)
-#define RTRATE(port) (BASE_IO_ADDR + 0x800 * (port) + 0x01fc)
-
#elif defined(CONFIG_CPU_SH7724)
#define SH_ETH_TYPE_ETHER
#define BASE_IO_ADDR 0xA4600000
-
-#define TDLAR(port) (BASE_IO_ADDR + 0x0018)
-#define RDLAR(port) (BASE_IO_ADDR + 0x0020)
-
-#define EDMR(port) (BASE_IO_ADDR + 0x0000)
-#define EDTRR(port) (BASE_IO_ADDR + 0x0008)
-#define EDRRR(port) (BASE_IO_ADDR + 0x0010)
-#define EESR(port) (BASE_IO_ADDR + 0x0028)
-#define EESIPR(port) (BASE_IO_ADDR + 0x0030)
-#define TRSCER(port) (BASE_IO_ADDR + 0x0038)
-#define TFTR(port) (BASE_IO_ADDR + 0x0048)
-#define FDR(port) (BASE_IO_ADDR + 0x0050)
-#define RMCR(port) (BASE_IO_ADDR + 0x0058)
-#define FCFTR(port) (BASE_IO_ADDR + 0x0070)
-#define ECMR(port) (BASE_IO_ADDR + 0x0100)
-#define RFLR(port) (BASE_IO_ADDR + 0x0108)
-#define ECSIPR(port) (BASE_IO_ADDR + 0x0118)
-#define PIR(port) (BASE_IO_ADDR + 0x0120)
-#define APR(port) (BASE_IO_ADDR + 0x0154)
-#define MPR(port) (BASE_IO_ADDR + 0x0158)
-#define TPAUSER(port) (BASE_IO_ADDR + 0x0164)
-#define MAHR(port) (BASE_IO_ADDR + 0x01c0)
-#define MALR(port) (BASE_IO_ADDR + 0x01c8)
-
-#elif defined(CONFIG_CPU_SH7734)
-#define SH_ETH_TYPE_GETHER
-#define BASE_IO_ADDR 0xFEE00000
-
-#define EDSR(port) (BASE_IO_ADDR)
-
-#define TDLAR(port) (BASE_IO_ADDR + 0x0010)
-#define TDFAR(port) (BASE_IO_ADDR + 0x0014)
-#define TDFXR(port) (BASE_IO_ADDR + 0x0018)
-#define TDFFR(port) (BASE_IO_ADDR + 0x001c)
-#define RDLAR(port) (BASE_IO_ADDR + 0x0030)
-#define RDFAR(port) (BASE_IO_ADDR + 0x0034)
-#define RDFXR(port) (BASE_IO_ADDR + 0x0038)
-#define RDFFR(port) (BASE_IO_ADDR + 0x003c)
-
-#define EDMR(port) (BASE_IO_ADDR + 0x0400)
-#define EDTRR(port) (BASE_IO_ADDR + 0x0408)
-#define EDRRR(port) (BASE_IO_ADDR + 0x0410)
-#define EESR(port) (BASE_IO_ADDR + 0x0428)
-#define EESIPR(port) (BASE_IO_ADDR + 0x0430)
-#define TRSCER(port) (BASE_IO_ADDR + 0x0438)
-#define TFTR(port) (BASE_IO_ADDR + 0x0448)
-#define FDR(port) (BASE_IO_ADDR + 0x0450)
-#define RMCR(port) (BASE_IO_ADDR + 0x0458)
-#define RPADIR(port) (BASE_IO_ADDR + 0x0460)
-#define FCFTR(port) (BASE_IO_ADDR + 0x0468)
-#define ECMR(port) (BASE_IO_ADDR + 0x0500)
-#define RFLR(port) (BASE_IO_ADDR + 0x0508)
-#define ECSIPR(port) (BASE_IO_ADDR + 0x0518)
-#define PIR(port) (BASE_IO_ADDR + 0x0520)
-#define PIPR(port) (BASE_IO_ADDR + 0x052c)
-#define APR(port) (BASE_IO_ADDR + 0x0554)
-#define MPR(port) (BASE_IO_ADDR + 0x0558)
-#define TPAUSER(port) (BASE_IO_ADDR + 0x0564)
-#define GECMR(port) (BASE_IO_ADDR + 0x05b0)
-#define MAHR(port) (BASE_IO_ADDR + 0x05C0)
-#define MALR(port) (BASE_IO_ADDR + 0x05C8)
-#define RMII_MII(port) (BASE_IO_ADDR + 0x0790)
-
#endif
/*
enum FIFO_SIZE_BIT {
FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007,
};
+
+static inline unsigned long sh_eth_reg_addr(struct sh_eth_dev *eth,
+ int enum_index)
+{
+#if defined(SH_ETH_TYPE_GETHER)
+ const u16 *reg_offset = sh_eth_offset_gigabit;
+#elif defined(SH_ETH_TYPE_ETHER)
+ const u16 *reg_offset = sh_eth_offset_fast_sh4;
+#else
+#error
+#endif
+ return BASE_IO_ADDR + reg_offset[enum_index] + 0x800 * eth->port;
+}
+
+static inline void sh_eth_write(struct sh_eth_dev *eth, unsigned long data,
+ int enum_index)
+{
+ outl(data, sh_eth_reg_addr(eth, enum_index));
+}
+
+static inline unsigned long sh_eth_read(struct sh_eth_dev *eth,
+ int enum_index)
+{
+ return inl(sh_eth_reg_addr(eth, enum_index));
+}
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