u32 svr = gur_in32(&gur->svr);
/* LS2085A has DP_DDR */
- if (SVR_SOC_VER(svr) == SVR_LS2085)
+ if (SVR_SOC_VER(svr) == SVR_LS2085A)
return true;
return false;
u32 svr = gur_in32(&gur->svr);
/* LS2085A has AIOP */
- if (SVR_SOC_VER(svr) == SVR_LS2085)
+ if (SVR_SOC_VER(svr) == SVR_LS2085A)
return true;
return false;
#define _FSL_LAYERSCAPE_CPU_H
static struct cpu_type cpu_type_list[] = {
- CPU_TYPE_ENTRY(LS2080, LS2080, 8),
- CPU_TYPE_ENTRY(LS2085, LS2085, 8),
- CPU_TYPE_ENTRY(LS2045, LS2045, 4),
- CPU_TYPE_ENTRY(LS1043, LS1043, 4),
- CPU_TYPE_ENTRY(LS1023, LS1023, 2),
- CPU_TYPE_ENTRY(LS2040, LS2040, 4),
- CPU_TYPE_ENTRY(LS1012, LS1012, 1),
+ CPU_TYPE_ENTRY(LS2080A, LS2080A, 8),
+ CPU_TYPE_ENTRY(LS2085A, LS2085A, 8),
+ CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
+ CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
+ CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
+ CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
+ CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
};
#ifndef CONFIG_SYS_DCACHE_OFF
{ .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
#define SVR_WO_E 0xFFFFFE
-#define SVR_LS1012 0x870400
-#define SVR_LS1043 0x879200
-#define SVR_LS1023 0x879208
-#define SVR_LS2045 0x870120
-#define SVR_LS2080 0x870110
-#define SVR_LS2085 0x870100
-#define SVR_LS2040 0x870130
+#define SVR_LS1012A 0x870400
+#define SVR_LS1043A 0x879200
+#define SVR_LS1023A 0x879208
+#define SVR_LS2045A 0x870120
+#define SVR_LS2080A 0x870110
+#define SVR_LS2085A 0x870100
+#define SVR_LS2040A 0x870130
#define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
#define SVR_MIN(svr) (((svr) >> 0) & 0xf)