drivers/ddr/fsl: update workaround for erratum A-008511

Per the latest erratum document, update step 4 and step 8, only
DEBUG_29[21] is changed, all other bits should not be changed.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
index 608810d4e29cb09be3193869101d956293f48464..7cdb7008b46dd850eab107981663cd0a9caa093d 100644 (file)
--- a/drivers/ddr/fsl/fsl_ddr_gen4.c
+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
@@ -240,8 +240,10 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
                /* Disable DRAM VRef training */
                ddr_out32(&ddr->ddr_cdr2,
                          regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
-               /* Disable deskew */
-               ddr_out32(&ddr->debug[28], 0x400);
+               /* disable transmit bit deskew */
+               temp32 = ddr_in32(&ddr->debug[28]);
+               temp32 |= DDR_TX_BD_DIS;
+               ddr_out32(&ddr->debug[28], temp32);
                /* Disable D_INIT */
                ddr_out32(&ddr->sdram_cfg_2,
                          regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
@@ -358,7 +360,9 @@ step2:
                        debug("MR6 = 0x%08x\n", temp32);
                }
                ddr_out32(&ddr->sdram_md_cntl, 0);
-               ddr_out32(&ddr->debug[28], 0);          /* Enable deskew */
+               temp32 = ddr_in32(&ddr->debug[28]);
+               temp32 &= ~DDR_TX_BD_DIS; /* Enable deskew */
+               ddr_out32(&ddr->debug[28], temp32);
                ddr_out32(&ddr->debug[1], 0x400);       /* restart deskew */
                /* wait for idle */
                timeout = 40;

diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h
index 44ae7fbb9cede2a17c90a95499c29e0bf6df9517..acddf14a3f5f6affa8e8f82b3256e531d366e49b 100644 (file)
--- a/include/fsl_ddr_sdram.h
+++ b/include/fsl_ddr_sdram.h
@@ -189,6 +189,9 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
 #define DDR_MR5_CA_PARITY_LAT_4_CLK    0x1 /* for DDR4-1600/1866/2133 */
 #define DDR_MR5_CA_PARITY_LAT_5_CLK    0x2 /* for DDR4-2400 */
 
+/* DEBUG_29 register */
+#define DDR_TX_BD_DIS  (1 << 10) /* Transmit Bit Deskew Disable */
+
 
 #if (defined(CONFIG_SYS_FSL_DDR_VER) && \
        (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7))